Semiconductor structure and method of forming the same

Abstract

The embodiments of the present disclosure provide a semiconductor structure and a forming method thereof. The semiconductor structure comprises: a semiconductor substrate comprising a plurality of active regions and a first isolation structure arranged at intervals along a first direction; a gate structure located in the active region and the first isolation structure, and a top surface of the active region is higher than a top surface of the gate structure; a second isolation structure with a preset height is located on a surface of the gate structure, and a top surface of the second isolation structure is flush with a top surface of the active region.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and to, but is not limited to, a semiconductor structure and a method for forming the same. Background Technology

[0002] With the continuous development of semiconductor technology, the requirements for the process precision of semiconductor devices are becoming increasingly stringent. In the fabrication process of Dynamic Random Access Memory (DRAM), the contact window (overlap area) between the storage node contact (SNC) and the active region is becoming smaller and smaller. Furthermore, the storage node contact fence in DRAM employs a self-aligned quadruple patterning (SAQP) process. Even small deviations can lead to a reduction in the contact area between the storage node contact and the active region, increasing the contact resistance and causing many memory cells to fail to meet read / write speed requirements. Additionally, in related technologies, adjacent SNCs are prone to contact, forming short circuits. Summary of the Invention

[0003] In view of this, embodiments of the present disclosure provide a semiconductor structure and a method for forming the same.

[0004] In a first aspect, embodiments of this disclosure provide a semiconductor structure, including:

[0005] A semiconductor substrate, the semiconductor substrate including a plurality of active regions and a first isolation structure arranged at intervals along a first direction;

[0006] A gate structure is located in the active region and the first isolation structure, and the top surface of the active region extends beyond the top surface of the gate structure;

[0007] A second isolation structure with a preset height is located on the surface of the gate structure, and the top surface of the second isolation structure is flush with the top surface of the active region.

[0008] In some embodiments, the semiconductor structure further includes: an epitaxial structure;

[0009] The extension structure is located between any two adjacent second isolation structures in the first direction; the sidewall of the extension structure is in contact with the second isolation structure, and the top surface of the extension structure extends beyond the top surface of the second isolation structure.

[0010] In some embodiments, the first isolation structure includes an isolation trench, a first etched isolation layer, and a second etched isolation layer;

[0011] The first etched isolation layer is located on the inner wall of the isolation trench, and the top surface of the first etched isolation layer is flush with the top surface of the gate structure;

[0012] The second etched isolation layer is located between the bottom of the gate structure and the isolation trench.

[0013] In some embodiments, the preset height includes 5 nanometers to 20 nanometers.

[0014] In a second aspect, embodiments of this disclosure provide a method for forming a semiconductor structure, the method comprising:

[0015] A semiconductor substrate is provided; the provided semiconductor substrate includes a plurality of active regions spaced apart along a first direction and a first initial isolation structure;

[0016] An initial gate structure is formed in the first initial isolation structure;

[0017] The initial first isolation structure and the initial gate structure are etched to form a first isolation structure, a gate structure, and a second isolation structure with a preset height.

[0018] In some embodiments, after forming the first isolation structure, the gate structure, and the second isolation structure, the method further includes: forming an epitaxial structure of the active region between any two adjacent second isolation structures in the first direction.

[0019] In some embodiments, the first initial isolation structure is formed by the following steps:

[0020] The semiconductor substrate is etched to form a plurality of isolation trenches spaced apart along the first direction;

[0021] A first isolation layer and a second isolation layer are sequentially formed on the inner wall of the isolation trench to form the first initial isolation structure; wherein the second isolation layer fills the isolation trench.

[0022] In some embodiments, the first isolation layer is also attached to the surface of the active region; the first isolation layer is formed by the following steps:

[0023] Sacrificial material is deposited on the inner wall of the isolation trench and on the surface of the active region to form a sacrificial layer;

[0024] The sacrificial layer is oxidized in situ to form the first isolation layer.

[0025] In some embodiments, the second isolation layer is formed by the following steps:

[0026] A second isolation material is deposited on the surface of the first isolation layer to form the second initial isolation layer;

[0027] The second initial isolation layer is processed to form the second isolation layer.

[0028] In some embodiments, processing the second initial isolation layer to form the second isolation layer includes:

[0029] The second initial isolation layer is planarized or etched until the first isolation layer on the surface of the active region is exposed, thus forming the second isolation layer.

[0030] In some embodiments, forming an initial gate structure in the first initial isolation structure includes:

[0031] Along a second direction, a portion of the second isolation layer is etched to form a first gate trench and a second etched isolation layer; wherein, the second direction is the thickness direction of the semiconductor substrate, and the second direction is perpendicular to the first direction;

[0032] A first gate dielectric layer is formed on the inner wall of the first gate trench;

[0033] A first gate metal layer is formed at the bottom of the first gate trench where the first gate dielectric layer is formed;

[0034] A first gate insulating layer is formed on the surface of the first gate metal layer.

[0035] In some embodiments, the initial gate structure is further formed in the active region;

[0036] The initial gate structure located in the active region is formed by the following steps:

[0037] Along the second direction, the first isolation layer and the active region are etched sequentially to form a second gate trench;

[0038] A second gate dielectric layer is formed on the inner wall of the second gate trench;

[0039] A second gate metal layer is formed in a second gate trench in which the second gate dielectric layer is formed;

[0040] A second gate insulating layer is formed on the surface of the second gate metal layer;

[0041] Wherein, the dimension of the second gate trench in the second direction is smaller than the dimension of the first gate trench in the second direction, and the dimension of the second gate metal layer in the second direction is smaller than the dimension of the first gate metal layer in the second direction.

[0042] In some embodiments, after forming the initial gate structure, the method further includes:

[0043] The first isolation layer on the surface of the active region is planarized or etched until the surface of the active region is exposed.

[0044] In some embodiments, the second isolation structure is formed in the following manner:

[0045] Along the second direction, the first isolation layer, the first gate dielectric layer and the second gate dielectric layer with a preset height are simultaneously etched away to expose the first gate insulating layer and the second gate insulating layer with the preset height, forming the second isolation structure and the first etched isolation layer.

[0046] The preset height is less than the initial height of the first gate insulating layer in the second direction, and the preset height includes 5 nanometers to 20 nanometers.

[0047] In some embodiments, the first isolation layer and the first gate dielectric layer are made of the same material, or the first isolation layer and the first gate dielectric layer have the same etch selectivity.

[0048] In some embodiments, the epitaxial structure forming the active region between any two adjacent second isolation structures in the first direction includes:

[0049] The epitaxial structure is formed by using a preset reaction gas and taking the surface of the active region between any two second isolation structures in the first direction as the reaction substrate.

[0050] In some embodiments, the active region is doped with a first predetermined concentration of ions of a specific type; after forming the epitaxial structure, the method further includes:

[0051] The epitaxial structure is doped with the ions at a second preset concentration to form a doped epitaxial structure;

[0052] Wherein, the first preset concentration is less than the second preset concentration.

[0053] The semiconductor structure and its formation method provided in this disclosure include a semiconductor substrate comprising a plurality of active regions and a first isolation structure spaced apart along a first direction; a gate structure located within the first isolation structure, wherein the top surface of the active regions extends beyond the top surface of the gate structure; and a second isolation structure having a predetermined height located on the surface of the gate structure, wherein the top surface of the second isolation structure is flush with the top surface of the active regions. Because the semiconductor structure provided in this disclosure includes the second isolation structure, which can be used to isolate adjacent SNCs, short circuits between the formed SNCs are prevented, thus improving the electrical performance of the fabricated semiconductor structure. Attached Figure Description

[0054] In the accompanying drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The drawings illustrate, by way of example and not limitation, the various embodiments discussed herein.

[0055] Figure 1 This is a schematic diagram of the semiconductor structure in the related technology;

[0056] Figure 2a A three-dimensional structural schematic diagram of a semiconductor structure provided in an embodiment of this disclosure;

[0057] Figure 2b A cross-sectional view of a semiconductor structure provided in an embodiment of this disclosure along the word line direction;

[0058] Figure 2c A cross-sectional view of a semiconductor structure provided in an embodiment of this disclosure along the extension direction of the active region;

[0059] Figure 2d This is another three-dimensional structural schematic diagram of the semiconductor structure provided in the embodiments of this disclosure;

[0060] Figure 2e A cross-sectional view of a semiconductor structure provided in an embodiment of this disclosure along the word line direction;

[0061] Figure 2f A cross-sectional view of a semiconductor structure provided in an embodiment of this disclosure along the extension direction of the active region;

[0062] Figure 3 A schematic flowchart illustrating a method for forming a semiconductor structure according to an embodiment of this disclosure;

[0063] Figures 4a-4j 5a to 5q are schematic diagrams of the semiconductor structure formation process provided in the embodiments of this disclosure;

[0064] Explanation of reference numerals in the attached figures:

[0065] 10 / 30 - Semiconductor structure; 101 / 201 / 3011 - Active region; 102 - Word line; 103 - Bit line; 104 / 212 - Memory node contact; 202 - Isolation trench; 203 - Sacrificial layer; 204 - First isolation layer; 205a - Second initial isolation layer; 205 - Second isolation layer; 206 - First gate trench; 206a - First gate dielectric layer; 206b - First gate metal layer; 206c - First gate insulating layer; 206' / 206” / 207' / 207” - Metal layer; 207 - Second gate trench; 20 7a - Second gate dielectric layer; 207b - Second gate metal layer; 207c - Second gate insulating layer; 208 / 303 - Second isolation structure; 209 / 304 - Epitaxial structure; 210 - Gate structure; 211 - Bit line structure; 211a - Bit line contact layer; 211b - Bit line metal layer; 211c - Bit line insulating layer; 301 - Semiconductor substrate; 302 - Gate structure; 302a - Gate insulating layer; 302b - Gate dielectric layer; 305 / 204a - First etched isolation layer; 306 - Second etched isolation layer; A / B - Contact window. Detailed Implementation

[0066] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0067] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0068] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0069] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0070] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0071] Figure 1 This is a schematic diagram of a semiconductor structure in the related art. Before describing in detail the semiconductor structure and its formation method provided in the embodiments of this disclosure, we will first combine... Figure 1 The semiconductor structure in the relevant technology is explained.

[0072] like Figure 1 As shown, the semiconductor structure 10 in the related technology includes multiple active regions 101, multiple word lines 102 (which can serve as buried gate structures), multiple bit lines 103, and memory node contacts 104 that contact each active region. It can be seen that the contact window A between the memory node contact 104 and the active region 101 in the related technology is relatively small. This increases the contact resistance between the memory node contact 104 and the active region 101, thereby reducing the read / write speed of the memory cell. Furthermore, in the related technology, adjacent memory node contacts are prone to contact, forming short circuits.

[0073] Based on the problems existing in related technologies, the semiconductor structure and its formation method provided in this disclosure include a semiconductor substrate, which includes a plurality of active regions and a first isolation structure spaced apart along a first direction; a gate structure located in the first isolation structure, wherein the top surface of the active regions extends beyond the top surface of the gate structure; and a second isolation structure with a preset height located on the surface of the gate structure, wherein the top surface of the second isolation structure is flush with the top surface of the active regions. Since the semiconductor structure provided in this disclosure includes the second isolation structure, the second isolation structure can be used to isolate adjacent SNCs, thus preventing short circuits between the formed SNCs and improving the electrical performance of the fabricated semiconductor structure. Furthermore, the second isolation structure is self-aligned during the fabrication process, reducing the complexity of the semiconductor structure fabrication process.

[0074] This disclosure provides a semiconductor structure. Figure 2a This is a three-dimensional structural diagram of a semiconductor structure provided in an embodiment of this disclosure. Figure 2b This is a cross-sectional view of the semiconductor structure along the word line extension direction (a-a' direction). Figure 2c This is a cross-sectional view of the semiconductor structure along the extension direction (b-b' direction) of the active region, as shown below. Figures 2a-2c As shown, the semiconductor structure 30 includes: a semiconductor substrate 301, a gate structure 302, and a second isolation structure 303 having a preset height.

[0075] In this embodiment of the disclosure, the semiconductor substrate 301 may be a silicon substrate, and the semiconductor substrate may also include other semiconductor elements, such as germanium (Ge), or include semiconductor compounds, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs) or indium antimonide (InSb), or include other semiconductor alloys, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP) or combinations thereof.

[0076] The semiconductor substrate may include a top surface on the front side and a bottom surface on the back side opposite to the front side. Ignoring the flatness of the top and bottom surfaces, a direction perpendicular to the top and bottom surfaces of the semiconductor substrate is defined as a second direction. In the direction of the top and bottom surfaces of the semiconductor substrate (i.e., the plane in which the semiconductor substrate lies), two intersecting directions, a first direction and a third direction, are defined. For example, the extension direction of word lines can be defined as the first direction, and the extension direction of the active region can be defined as the third direction. Here, the first direction and the third direction form an angle, and the angle is not 90°. The plane of the semiconductor substrate can be determined based on the first direction and the third direction. In this embodiment of the disclosure, as... Figures 2a-2c As shown, the first direction is defined as the X-axis direction, the second direction is defined as the Z-axis direction, and the third direction is defined as the Y-axis direction.

[0077] The semiconductor substrate 301 includes a plurality of active regions 3011 spaced apart along the X-axis and a first isolation structure. A gate structure 302 is located between the first isolation structure and the active regions 3011, with the top surface of the active regions 3011 extending beyond the top surface of the gate structure 302. A second isolation structure 303 with a predetermined height is located on the surface of the gate structure 302, and the top surface of the second isolation structure 303 is flush with the top surface of the active regions 3011.

[0078] In this embodiment of the application, the preset height can be from 5 nanometers (nm) to 20 nm.

[0079] In some embodiments, the gate structure 302 includes at least a gate insulating layer 302a and a gate dielectric layer 302b disposed on the sidewall of the gate insulating layer 302a, wherein the top surface of the gate insulating layer 302a is the top surface of the gate structure 302.

[0080] In other embodiments, the gate structure 302 further includes a gate metal layer located below the gate insulating layer. The gate metal layer may consist of one metal layer or two metal layers, without any additional limitation.

[0081] In some embodiments, the first isolation structure includes an isolation trench, a first etched isolation layer 305, and a second etched isolation layer 306; the first etched isolation layer 305 is located on the inner wall of the isolation trench, and the top surface of the first etched isolation layer 305 is flush with the top surface of the gate structure 302; the second etched isolation layer 306 is located between the bottom of the gate structure 302 and the isolation trench.

[0082] Figure 2d This is another three-dimensional structural view of the semiconductor structure provided in this embodiment of the disclosure. Figure 2eThis is a cross-sectional view of the semiconductor structure along the extension direction of the word line (a-a' direction). Figure 2f This is a cross-sectional view of the semiconductor structure along the extension direction (b-b' direction) of the active region, as shown below. Figures 2d to 2f As shown, the semiconductor structure 30 includes a semiconductor substrate 301, a gate structure 302, a second isolation structure 303 with a preset height, and an epitaxial structure 304.

[0083] The extension structure 304 is located between any two adjacent second isolation structures 303 in the X-axis direction; the sidewall of the extension structure 304 is in contact with the second isolation structure 303, and the top surface of the extension structure 304 extends beyond the top surface of the second isolation structure 303.

[0084] Combination Figure 2a and 2d It can be seen that before the epitaxial structure 304 is formed, the top surface of the second isolation structure 303 is flush with the top surface of the active region 3011.

[0085] In some embodiments, the semiconductor structure further includes a bit line structure (not shown in the figure); the bit line structure is located on the surface of the active region between two adjacent gate structures in the active region; the extension direction of the bit line structure is perpendicular to the extension direction of the gate structure, and the bit line structure includes at least a bit line contact layer, a bit line metal layer and a bit line insulating layer stacked sequentially from bottom to top along the Z-axis direction.

[0086] In some embodiments, the semiconductor structure further includes a memory node contact (not shown); the memory node contact is located on the sidewall of the bit line structure and is in contact with the top surface of the epitaxial structure.

[0087] In this embodiment of the disclosure, the epitaxial structure can increase the contact area between the active region and the storage node, which is beneficial for the alignment between the active region and the storage node.

[0088] The semiconductor structure provided in this embodiment has a second isolation structure, which can be used to isolate adjacent memory node contacts, thus preventing short circuits between the formed memory node contacts and improving the electrical performance of the semiconductor structure.

[0089] This disclosure also provides a method for forming a semiconductor structure. Figure 3 This is a schematic flowchart of a method for forming a semiconductor structure according to an embodiment of the present disclosure, as shown below. Figure 3 As shown, the method for forming the semiconductor structure includes the following steps:

[0090] Step S301: Provide a semiconductor substrate; the provided semiconductor substrate includes a plurality of active regions arranged at intervals along a first direction and a first initial isolation structure.

[0091] The first initial isolation structure is used to isolate adjacent active regions.

[0092] Step S302: Form an initial gate structure in the first initial isolation structure.

[0093] Step S303: Etch the first initial isolation structure and the initial gate structure to form the first isolation structure, the gate structure and the second isolation structure with a preset height.

[0094] Figures 4a-4j 5a to 5q are schematic diagrams of the semiconductor structure formation process provided in the embodiments of this disclosure. Please refer to the following... Figures 4a-4j The method for forming a semiconductor structure provided in the embodiments of this disclosure is further described in detail in sections 5a to 5q.

[0095] First, step S301 is performed to provide a semiconductor substrate; the provided semiconductor substrate includes a plurality of active regions arranged at intervals along a first direction and a first initial isolation structure.

[0096] In some embodiments, the first initial isolation structure can be formed through the following steps:

[0097] The semiconductor substrate is etched to form a plurality of isolation trenches spaced apart along the first direction.

[0098] Figure 4a This is a top view of a semiconductor substrate provided in an embodiment of this disclosure. Figure 4b This is a cross-sectional view of a semiconductor substrate along the X-axis and Y-axis, such as... Figure 4a and 4b As shown, the semiconductor substrate is etched to form multiple active regions 201 and isolation trenches 202 arranged at intervals along the X-axis.

[0099] A first isolation layer and a second isolation layer are sequentially formed on the inner wall of the isolation trench to form the first initial isolation structure; wherein the second isolation layer fills the isolation trench.

[0100] In some embodiments, the first isolation layer is also attached to the surface of the active region, and the first isolation layer can be formed in the following three ways:

[0101] The first method involves depositing a first isolation material on the inner wall of the isolation trench and on the surface of the active area to form the first isolation layer.

[0102] The first insulating material can be any insulating material, such as silicon dioxide, silicon nitride, or silicon oxynitride. In this embodiment, the first insulating material can be deposited using any suitable deposition process to form the first insulating layer, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin coating, or coating process.

[0103] The second method involves depositing sacrificial material on the inner wall of the isolation trench and on the surface of the active area to form a sacrificial layer.

[0104] In this embodiment of the disclosure, the sacrificial material may be monocrystalline silicon or polycrystalline silicon.

[0105] Figure 4c This is a top view of the deposition sacrificial material provided in an embodiment of this disclosure. Figure 4d This is a sectional view along the X-axis and Y-axis, such as... Figure 4c and 4d As shown, a sacrificial material is deposited on the surface of the isolation trench 202 and the active region 201 to form a sacrificial layer 203.

[0106] The sacrificial layer is oxidized in situ to form the first isolation layer.

[0107] Figure 4e This is a top view of the formation of the first isolation layer provided in an embodiment of this disclosure. Figure 4f This is a sectional view along the X-axis and Y-axis, such as... Figure 4e and 4f As shown, the sacrificial layer 203 is oxidized in situ to form the first isolation layer 204.

[0108] The third method involves thermally oxidizing the inner wall of the isolation trench and the surface of the active region to form a first isolation layer.

[0109] It should be noted that the third method of forming the first isolation layer between the inner wall of the thermal oxidation isolation trench and the surface of the active region will cause some damage to the surface of the isolation trench and the active region, resulting in an increase in the size of the isolation trench and a decrease in the size of the active region.

[0110] In some embodiments, the second isolation layer may be formed in the following manner:

[0111] A second isolation material is deposited on the surface of the first isolation layer to form the second initial isolation layer.

[0112] In this embodiment of the disclosure, the second insulating material can be any kind of insulating material, such as silicon dioxide, silicon nitride, or silicon oxynitride.

[0113] Figure 4g This is a top view of the formation of the second initial isolation layer provided in an embodiment of this disclosure. Figure 4h This is a sectional view along the X-axis and Y-axis, such as... Figure 4g and 4h As shown, a second isolation material is deposited on the surface of the first isolation layer 204 using any suitable deposition process to form a second initial isolation layer 205a.

[0114] The second initial isolation layer is processed to form the second isolation layer.

[0115] In some embodiments, the process of forming the second initial isolation layer includes: planarizing or etching the second initial isolation layer until the first isolation layer on the surface of the active region is exposed, thereby forming the second isolation layer.

[0116] In this embodiment of the disclosure, the etching process of the second initial isolation layer can be carried out using a dry etching process, such as plasma etching, reactive ion etching, or ion milling, or it can be carried out using a wet etching process.

[0117] Figure 4i This is a top view of the formation of the second isolation layer provided in an embodiment of this disclosure. Figure 4j This is a sectional view along the X-axis and Y-axis, such as... Figure 4i and 4j As shown, the second initial isolation layer 205a is etched or chemically mechanically polished (CMP) until the first isolation layer 204 on the surface of the active region is exposed, forming the second isolation layer 205 located in the isolation trench.

[0118] Next, step S302 is performed to form an initial gate structure in the first initial isolation structure.

[0119] In some embodiments, forming an initial gate structure in the first initial isolation structure can be achieved through the following steps:

[0120] Along the second direction, a portion of the second isolation layer is etched to form a first gate trench and a second etched isolation layer.

[0121] Here, etching part of the second isolation layer to form the first gate trench means etching part of the second isolation layer in the second direction. That is, after forming the first gate trench, part of the second isolation layer is still retained at the bottom of the first gate trench. The retained second isolation layer forms the second etched isolation layer.

[0122] Figure 5a This is a top view of the formation of the first gate trench provided in an embodiment of this disclosure. Figure 5b This is a sectional view along the X-axis and Y-axis, such as... Figure 5a and 5b As shown, along the Z-axis direction, a portion of the second isolation layer 205 is etched to form the first gate trench 206 and the second etched isolation layer 206-1.

[0123] It should be noted that, due to the sectional view along the X-axis (corresponding to...) Figure 5b The left image in the middle is not cut off from the word line, therefore, Figure 5b The first gate trench formed cannot be seen in the left image.

[0124] A first gate dielectric layer is formed on the inner wall of the first gate trench.

[0125] Figure 5c This is a top view of the formation of the first gate dielectric layer provided in an embodiment of the present disclosure. Figure 5d This is a sectional view along the X-axis and Y-axis, such as... Figure 5c and 5d As shown, a first gate dielectric layer 206a is formed on the inner wall of the first gate trench 206. In this embodiment of the present disclosure, the first gate dielectric layer 206a can be formed by any suitable deposition process, and the first gate dielectric layer can be an oxide layer, such as a silicon oxide layer.

[0126] In this embodiment of the disclosure, the first isolation layer and the first gate dielectric layer are made of the same material, or the first isolation layer and the first gate dielectric layer have the same etching selectivity, that is, the first isolation layer and the first gate dielectric layer can be removed simultaneously under the same etching conditions.

[0127] A first gate metal layer is formed at the bottom of a first gate trench where the first gate dielectric layer is formed.

[0128] In this embodiment of the disclosure, the first gate metal layer may consist of one metal layer, two metal layers, or multiple metal layers, and the material of the metal layer includes tungsten, cobalt, copper, aluminum, polycrystalline silicon, doped silicon, silicide, titanium nitride, or any combination thereof.

[0129] The first gate insulating layer is formed on the surface of the first gate metal layer.

[0130] Figure 5e This is a top view showing the formation of the first gate metal layer and the first gate insulation according to an embodiment of the present disclosure. Figure 5f and 5g These are sectional views along the X-axis and Y-axis, respectively, as shown below. Figures 5e-5g As shown, a metal material is filled into the first gate trench where the first gate dielectric layer 206a is formed, and the filled metal material is etched back to form a first gate metal layer 206b at the bottom of the first gate trench. A first gate insulating layer 206c is formed on the surface of the first gate metal layer 206b, and the top surface of the first gate insulating layer 206c is flush with the top surface of the first isolation layer 204. In this embodiment, the first gate metal layer 206b consists of two metal layers, namely metal layer 206' and metal layer 206'". In this embodiment, metal layer 206' can be polysilicon or titanium nitride, and metal layer 206' can be tungsten. The work function of metal layer 206' is lower than that of metal layer 206', thus reducing gate-induced leakage current (GIDL).

[0131] In this embodiment, the first gate insulating layer and the first gate dielectric layer are made of different materials, and the first gate insulating layer has a larger etching selectivity than the first gate dielectric layer. For example, the first gate insulating layer may be a silicon nitride layer, and the first gate dielectric layer may be a silicon oxide layer.

[0132] In some embodiments, the initial gate structure is further formed in the active region; and the initial gate structure located in the active region and the initial gate structure located in the first initial isolation structure are formed simultaneously in the same process step.

[0133] In some embodiments, the initial gate structure located in the active region is formed by the following steps:

[0134] Along the second direction, the first isolation layer and the active region are etched sequentially to form a second gate trench.

[0135] Please continue reading Figure 5a and 5b The first isolation layer 204 and the active region are etched sequentially along the Z-axis to form the second gate trench 207.

[0136] It should be noted that, due to the sectional view along the X-axis (corresponding to...) Figure 5b The left image in the middle is not cut off from the word line, therefore, Figure 5b The second gate trench formed cannot be seen in the left image.

[0137] In this embodiment, because the active region and the second isolation layer are made of different materials, and the etching selectivity of the second isolation layer is greater than that of the active region, the depths of the first gate trench and the second gate trench formed during the simultaneous etching of the second isolation layer and the active region are different. Figure 5a As shown, the dimension h2 of the second gate trench 207 in the Z-axis direction is smaller than the dimension h1 of the first gate trench 206 in the Z-axis direction.

[0138] A second gate dielectric layer is formed on the inner wall of the second gate trench.

[0139] Please continue reading Figure 5c and 5d A second gate dielectric layer 207a is formed on the inner wall of the second gate trench 207. In this embodiment of the present disclosure, the second gate dielectric layer 207a can be formed by any suitable deposition process, and the second gate dielectric layer can be an oxide layer, such as a silicon oxide layer.

[0140] In this embodiment of the disclosure, the first isolation layer and the second gate dielectric layer are made of the same material, or the first isolation layer and the second gate dielectric layer have the same etching selectivity, that is, the first isolation layer and the second gate dielectric layer can be removed simultaneously under the same etching conditions.

[0141] A second gate metal layer is formed in a second gate trench in which the second gate dielectric layer is formed.

[0142] In this embodiment of the disclosure, the second gate metal layer may also be composed of one metal layer, two metal layers or multiple metal layers, and the material of the metal layer includes tungsten, cobalt, copper, aluminum, polycrystalline silicon, doped silicon, silicide, titanium nitride or any combination thereof.

[0143] A second gate insulating layer is formed on the surface of the second gate metal layer.

[0144] Please continue reading Figures 5e-5g A metal material is filled into the second gate trench where the second gate dielectric layer 207a is formed, and the filled metal material is etched back to form a second gate metal layer 207b at the bottom of the second gate trench. A second gate insulating layer 207c is formed on the surface of the second gate metal layer 207b, and the top surface of the second gate insulating layer 207c is flush with the top surface of the first isolation layer 204. In this embodiment, the second gate metal layer 207b consists of two metal layers, namely metal layer 207' and metal layer 207'", and the dimension h4 of the second gate metal layer 207b in the Z-axis direction is smaller than the dimension h3 of the first gate metal layer 206b in the Z-axis direction.

[0145] In this embodiment of the disclosure, the metal layer 207” can be polycrystalline silicon or titanium nitride, and the metal layer 207' can be tungsten. The work function of the metal layer 207” is lower than that of the metal layer 207', thus reducing the GIDL.

[0146] It should be noted that since the initial gate structure located in the active region and the initial gate structure located in the second isolation layer are formed simultaneously in the same process step, the first gate dielectric layer and the second gate dielectric layer are made of the same material, the first gate metal layer and the second gate metal layer are made of the same material, and the first gate insulating layer and the second gate insulating layer are also made of the same material.

[0147] In some embodiments, after forming the initial gate structure, the method for forming the semiconductor structure further includes the following steps:

[0148] The first isolation layer on the surface of the active region is planarized or etched until the surface of the active region is exposed.

[0149] Figure 5h This is a top view of the surface of the active region after removing the first isolation layer, as provided in an embodiment of this disclosure. Figure 5i and 5j These are sectional views along the X-axis and Y-axis, respectively, as shown below. Figures 5h-5j As shown, in this embodiment of the present disclosure, an etching process or a chemical mechanical polishing process can be used to etch away the first isolation layer 204 on the surface of the active region until the surface of the active region 201 is exposed.

[0150] It should be noted that, in this embodiment of the present disclosure, while removing the first isolation layer 204 on the surface of the active region, a portion of the initial gate structure in the active region and a portion of the initial gate structure in the first isolation structure are also removed, so that the top surfaces of the initial gate structure in the active region and the initial gate structure in the first isolation structure are flush with the surface of the active region.

[0151] Next, step S303 is performed to etch the initial first isolation structure and the initial gate structure to form the first isolation structure, the gate structure, and the second isolation structure with a preset height.

[0152] In some embodiments, step S303 may include the following steps:

[0153] Along the second direction, a first isolation layer with a preset height and a first gate dielectric layer with the preset height are etched away to expose a first gate insulating layer and a second isolation layer with the preset height, forming a first etched isolation layer and a second isolation structure with the preset height.

[0154] Figure 5kThis is a top view of the formation of the second isolation structure provided in an embodiment of this disclosure. Figure 5l This is a sectional view along the X-axis and Y-axis, such as... Figure 5k and 5l As shown, along the Z-axis direction, a first isolation layer, a first gate dielectric layer, and a second gate dielectric layer with a preset height h5 are simultaneously etched away, exposing a first gate insulating layer and a second gate insulating layer with a preset height h5, forming a second isolation structure 208 and a first etched isolation layer 204a. Furthermore, the preset height h5 is less than the initial height h6 of the first or second gate insulating layer in the Z-axis direction.

[0155] In this embodiment of the application, the preset height can be from 5nm to 20nm.

[0156] It should be noted that the first isolation structure and the gate structure 210 are formed simultaneously with the formation of the second isolation structure 208. In this embodiment, the first isolation structure includes an isolation trench and a first etched isolation layer 204a and a second etched isolation layer 206-1 located in the isolation trench.

[0157] In some embodiments, after forming the first isolation structure, the gate structure, and the second isolation structure, the method for forming the semiconductor structure further includes: forming an epitaxial structure of the active region between any two adjacent second isolation structures in the first direction.

[0158] Here, the epitaxial structure includes epitaxial silicon or doped epitaxial silicon.

[0159] In some embodiments, forming the epitaxial structure of the active region between any two adjacent second isolation structures in the first direction may include the following steps:

[0160] The epitaxial structure is formed by using a preset reaction gas and taking the surface of the active region between any two second isolation structures in the first direction as the reaction substrate.

[0161] In this embodiment of the disclosure, the preset reaction gas includes any one of silicon tetrachloride (SiCl4), trichlorosilane (SiHCl3), dichlorosilane (SiH2Cl2) or silane (SiH4) and hydrogen (H2).

[0162] Figure 5m This is a top view of the formation of the epitaxial structure provided in an embodiment of the present disclosure. Figure 5n This is a sectional view along the X-axis and Y-axis, such as... Figure 5m and 5nAs shown, using the surface of the active region between any two adjacent second isolation structures 208 in the X-axis direction as the reaction substrate, an epitaxial structure 209 is formed by a vapor phase epitaxial growth process. In this embodiment, the sidewall of the epitaxial structure 209 is in contact with the second isolation structure 208, and the top surface of the epitaxial structure 209 extends beyond the top surface of the second isolation structure 208.

[0163] In some embodiments, the active region is doped with a first predetermined concentration of a specific type of ions; after forming the epitaxial structure, the method for forming the semiconductor structure further includes:

[0164] The epitaxial structure is doped with the ions at a second preset concentration to form a doped epitaxial structure; wherein the first preset concentration is less than the second preset concentration.

[0165] In this embodiment of the disclosure, the ions used to dope the active region can be group VI element ions or group III element ions.

[0166] It should be noted that, in the embodiments of this disclosure, the ion types used to dope the epitaxial structure are the same as those used to dope the active region.

[0167] In this embodiment of the disclosure, high-concentration ion doping of the epitaxial structure can reduce the contact resistance between the epitaxial structure and the active region, thereby further improving the electrical performance of the formed semiconductor structure.

[0168] In some embodiments, after forming the epitaxial structure, the method for forming the semiconductor structure further includes the following steps:

[0169] A bit line structure is formed on the surface of the active region located between two adjacent gate structures in the active region.

[0170] Figure 5o This is a top view of the bitline structure provided in an embodiment of the present disclosure. Figure 5p This is a sectional view along the Y-axis, such as... Figure 5o and 5p As shown, a bit line structure 211 is formed on the surface of the active region located between two adjacent gate structures 210 in the active region 201. The extension direction of the bit line structure 211 is perpendicular to the extension direction of the gate structure 210. The bit line structure 211 includes at least a bit line contact layer 211a, a bit line metal layer 211b, and a bit line insulating layer 211c stacked sequentially from bottom to top along the Z-axis direction.

[0171] A storage node contact is formed on the sidewall of the bitline structure; wherein the storage node contact is in contact with the top surface of the epitaxial structure.

[0172] Please continue reading Figure 5p A storage node contact 212 is formed on the sidewall of the bit line structure 211, and the storage node contact 212 is in contact with the top surface of the epitaxial structure 209.

[0173] Figure 5q A top view of the semiconductor structure provided in the embodiments of this disclosure, such as Figure 5q As shown, the contact window B between the storage node contact and the active region in the semiconductor structure provided in this embodiment is relatively large. This can improve the alignment between the active region and the storage node contact, thereby reducing the contact resistance between the storage node contact and the active region, improving the read / write speed of the storage cell, and thus improving the fabrication yield of the semiconductor device.

[0174] The method for forming a semiconductor structure provided in this disclosure is similar to the semiconductor structure in the above embodiments. For technical features not disclosed in detail in this disclosure, please refer to the above embodiments for understanding. Here, they will not be repeated.

[0175] The semiconductor structure formed by the semiconductor structure formation method provided in this embodiment includes a second isolation structure, which can be used to isolate adjacent SNCs. This prevents short circuits between the formed SNCs and improves the electrical performance of the prepared semiconductor structure.

[0176] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in a non-target manner. The device embodiments described above are merely illustrative; for example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. Furthermore, the various components shown or discussed may be coupled or directly coupled to each other.

[0177] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0178] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0179] The above descriptions are merely some embodiments of this disclosure, but the protection scope of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this disclosure should be included within the protection scope of this disclosure. Therefore, the protection scope of this disclosure should be determined by the scope of the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, The method includes; A semiconductor substrate is provided; the provided semiconductor substrate includes a plurality of active regions spaced apart along a first direction and a first initial isolation structure; An initial gate structure is formed in the first initial isolation structure; Etch the first initial isolation structure and the initial gate structure to form a first isolation structure, a gate structure and a second isolation structure with a preset height; After forming the first isolation structure, the gate structure, and the second isolation structure, the method further includes: An extensional structure of the active region is formed between any two adjacent second isolation structures in the first direction; The first initial isolation structure is formed through the following steps: The semiconductor substrate is etched to form a plurality of isolation trenches spaced apart along the first direction; A first isolation layer and a second isolation layer are sequentially formed on the inner wall of the isolation trench to form the first initial isolation structure; wherein the second isolation layer fills the isolation trench. The step of forming an initial gate structure in the first initial isolation structure includes: Along a second direction, a portion of the second isolation layer is etched to form a first gate trench and a second etched isolation layer; wherein, the second direction is the thickness direction of the semiconductor substrate, and the second direction is perpendicular to the first direction; A first gate dielectric layer is formed on the inner wall of the first gate trench; A first gate metal layer is formed at the bottom of the first gate trench where the first gate dielectric layer is formed; A first gate insulating layer is formed on the surface of the first gate metal layer; The initial gate structure is also formed in the active region; The initial gate structure located in the active region is formed by the following steps: Along the second direction, the first isolation layer and the active region are etched sequentially to form a second gate trench; A second gate dielectric layer is formed on the inner wall of the second gate trench; A second gate metal layer is formed in a second gate trench in which the second gate dielectric layer is formed; A second gate insulating layer is formed on the surface of the second gate metal layer; Wherein, the dimension of the second gate trench in the second direction is smaller than the dimension of the first gate trench in the second direction, and the dimension of the second gate metal layer in the second direction is smaller than the dimension of the first gate metal layer in the second direction; The second isolation structure is formed in the following way: Along the second direction, the first isolation layer, the first gate dielectric layer and the second gate dielectric layer with a preset height are simultaneously etched away to expose the first gate insulating layer and the second gate insulating layer with the preset height, forming the second isolation structure and the first etched isolation layer. The preset height is less than the initial height of the first gate insulating layer in the second direction, and the preset height includes 5 nanometers to 20 nanometers.

2. The method according to claim 1, characterized in that, The first isolation layer is also attached to the surface of the active region; the first isolation layer is formed by the following steps: Sacrificial material is deposited on the inner wall of the isolation trench and on the surface of the active region to form a sacrificial layer; The sacrificial layer is oxidized in situ to form the first isolation layer.

3. The method according to claim 2, characterized in that, The second isolation layer is formed by the following steps: A second isolation material is deposited on the surface of the first isolation layer to form a second initial isolation layer; The second initial isolation layer is processed to form the second isolation layer.

4. The method according to claim 3, characterized in that, The process of forming the second isolation layer includes: The second initial isolation layer is planarized or etched until the first isolation layer on the surface of the active region is exposed, thus forming the second isolation layer.

5. The method according to claim 1, characterized in that, After forming the initial gate structure, the method further includes: The first isolation layer on the surface of the active region is planarized or etched until the surface of the active region is exposed.

6. The method according to claim 1, characterized in that, The first isolation layer and the first gate dielectric layer are made of the same material, or the first isolation layer and the first gate dielectric layer have the same etching selectivity.

7. The method according to claim 1, characterized in that, The epitaxial structure forming the active region between any two adjacent second isolation structures in the first direction includes: The epitaxial structure is formed by using a preset reaction gas and taking the surface of the active region between any two second isolation structures in the first direction as the reaction substrate.

8. The method according to claim 7, characterized in that, The active region is doped with a first preset concentration of a specific type of ion; after forming the epitaxial structure, the method further includes: The epitaxial structure is doped with the ions at a second preset concentration to form a doped epitaxial structure; Wherein, the first preset concentration is less than the second preset concentration.

9. A semiconductor structure, fabricated based on the method described in claim 1, characterized in that, include: A semiconductor substrate, the semiconductor substrate including a plurality of active regions and a first isolation structure arranged at intervals along a first direction; A gate structure is located in the active region and the first isolation structure, and the top surface of the active region extends beyond the top surface of the gate structure; A second isolation structure with a preset height is located on the surface of the gate structure, and the top surface of the second isolation structure is flush with the top surface of the active region; The semiconductor structure further includes: an epitaxial structure; The extensional structure is located between any two adjacent second isolation structures in the first direction; the sidewall of the extensional structure is in contact with the second isolation structure, and the top surface of the extensional structure extends beyond the top surface of the second isolation structure; The first isolation structure includes an isolation trench, a first etched isolation layer, and a second etched isolation layer; The first etched isolation layer is located on the inner wall of the isolation trench, and the top surface of the first etched isolation layer is flush with the top surface of the gate structure; The second etched isolation layer is located between the bottom of the gate structure and the isolation trench; The preset height ranges from 5 nanometers to 20 nanometers.

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