Fluid ejection device including first and second memories

Abstract

A fluid ejection apparatus including a first memory and a second memory is provided. An integrated circuit for driving a plurality of fluid actuation apparatuses includes a plurality of first data lines, a second data line, first memory elements, and second memory elements. The first memory elements are enabled in response to first data on the plurality of first data lines. The second memory elements are enabled in response to second data on the second data line.

Description

[0001] This application is a divisional application of the application patent application with the application date of April 19, 2019, the application number of 201980091629.2, and the invention name of “Fluid Ejection Apparatus Including First and Second Memories”. TECHNICAL FIELD

[0002] The present disclosure relates generally to fluid ejection apparatuses. BACKGROUND

[0003] An inkjet printing system, as one example of a fluid ejection system, can include a printhead, an ink supply that supplies liquid ink to the printhead, and an electronic controller that controls the printhead. The printhead, as one example of a fluid ejection apparatus, ejects drops of ink through a plurality of nozzles or orifices and onto a print medium, such as a sheet of paper, to print on the print medium. In some examples, the orifices are arranged in at least one column or array, such that when the printhead and the print medium are moved relative to each other, the appropriate sequential ejection of ink from the orifices causes characters or other images to be printed on the print medium. SUMMARY

[0004] According to an aspect of the present disclosure, an integrated circuit is provided that includes a first plurality of data lines, a second data line, an ID line, a first select line, a second select line, a first memory element enabled in response to first data on the first plurality of data lines and in response to a first logic level on the first select line, and a second memory element enabled in response to second data on the second data line and in response to a first logic level on the second select line and a first logic level on the ID line.

[0005] According to an aspect of the present disclosure, a method for accessing a first memory element and a second memory element of an integrated circuit is provided that includes sequentially generating a first select signal and a second select signal, enabling the first memory element in response to the first select signal and first data on a first plurality of data lines, and enabling the second memory element in response to the second select signal and second data on a second data line. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figure 1 is a block diagram illustrating one example of a fluid ejection system.

[0007] Figure 2 is a schematic diagram illustrating one example of a fluid ejection apparatus.

[0008] Figure 3 is a block diagram illustrating one example of a circuit including a first memory and a second memory of a fluid ejection apparatus.

[0009] Figure 4 is a block diagram illustrating another example of a circuit including a first memory and a second memory of a fluid ejection device.

[0010] Figure 5 is a schematic diagram illustrating one example of a circuit including a memory element of a fluid ejection device.

[0011] Figure 6 is a schematic diagram illustrating another example of a circuit including a memory element of a fluid ejection device.

[0012] Figure 7A is a schematic diagram illustrating one example of a circuit including a plurality of memory elements of a fluid ejection device.

[0013] Figure 7B is a schematic diagram illustrating another example of a circuit including a plurality of memory elements of a fluid ejection device.

[0014] Figures 8A-8B is a schematic diagram illustrating one example of a circuit including a plurality of memory elements and a plurality of fluid actuation devices of a fluid ejection device.

[0015] Figure 9A is a schematic diagram illustrating one example of a circuit including a first memory, a second memory, and a fluid actuation device.

[0016] Figure 9B is a schematic diagram illustrating another example of a circuit including a first memory, a second memory, and a fluid actuation device.

[0017] Figure 10A and Figure 10B is a timing diagram illustrating one example of operation of a circuit of Figure 9B

[0018] Figure 11A and Figure 11B is a timing diagram illustrating another example of operation of a circuit of Figure 9B

[0019] Figure 12 is a block diagram illustrating one example of a fluid ejection system.

[0020] Figures 13A-13D is a flow diagram illustrating one example of a method for accessing a first memory and a second memory of a fluid ejection device.

[0021] Figures 14A-14B is a flow diagram illustrating one example of a method for accessing a memory of a fluid ejection device. ​​

[0022] Figures 15A-15B is a flowchart illustrating another example of a method for accessing a memory of a fluid ejection device. DETAILED DESCRIPTION

[0023] In the following detailed description, references are made to the accompanying drawings, which form a part hereof, and in which are shown by way of illustration specific examples in which a disclosure can be practiced. It is to be understood that other examples can be utilized and that structural or logical changes can be made without departing from the scope of the present disclosure. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present disclosure is defined by the appended claims. It is to be understood that features of the various examples described herein can be combined, in part or whole, with each other, unless otherwise specifically noted.

[0024] As used herein, a "logic high" signal is a logic "1" or "on" signal or a signal having a voltage about equal to a logic power supplied to an integrated circuit (e.g., between about 1.8 V and 15 V, such as 5.6 V). As used herein, a "logic low" signal is a logic "0" or "off' signal or a signal having a voltage about equal to a logic power ground return of a logic power supplied to an integrated circuit (e.g., about 0 V).

[0025] A printhead used in a printing system can include nozzles that are activated to cause ejection of a print fluid droplet from a corresponding nozzle. Each nozzle includes a fluid actuation device. The fluid actuation device, when activated, causes a print fluid droplet to be ejected from the corresponding nozzle. In one example, each fluid actuation device includes a heating element (e.g., a thermistor) that, when activated, generates heat to cause vaporization of a print fluid in a firing chamber of the nozzle. The vaporization of the print fluid causes a droplet of the print fluid to be expelled from the nozzle. In other examples, each fluid actuation device includes a piezoelectric element. When activated, the piezoelectric element applies a force to cause a print fluid droplet to be ejected from the nozzle. In other examples, other types of fluid actuation devices can be used to eject fluid from a nozzle.

[0026] A printing system can be a two-dimensional (2D) printing system or a three- dimensional (3D) printing system. A 2D printing system dispenses a print fluid, such as ink, to form an image on a print medium, such as a paper medium or other type of print medium. A 3D printing system forms a 3D object by depositing successive layers of build material. A print fluid dispensed from a 3D printing system can include ink as well as a powder for fusing a layer of build material, an agent to detail a layer of build material (such as by defining an edge or shape of the layer of build material), and the like.

[0027] As used herein, the term “printhead” generally refers to a printhead die or an assembly comprising multiple dies mounted on a support structure. A die (also referred to as an “integrated circuit die”) comprises a substrate on which various layers of control circuitry for forming nozzles and / or for controlling fluid ejection by the nozzles are disposed.

[0028] While reference is made in some examples to printheads used in printing systems, it is noted that the techniques or mechanisms of the present disclosure are applicable to other types of fluid ejection devices used in non-printing applications capable of dispensing fluid through nozzles. Examples of such other types of fluid ejection devices include those used in fluid sensing systems, medical systems, vehicles, fluid flow control systems, etc.

[0029] As the size of devices comprising printhead dies or other types of fluid ejection dies continues to shrink, the number of signal lines used to control the circuitry of the devices can impact the overall size of the devices. A large number of signal lines can result in the use of a large number of signal pads (referred to as “bond pads”) to electrically connect the signal lines to external lines. Adding features to fluid ejection devices can result in the use of an increasing number of signal lines (and corresponding bond pads), which can occupy valuable die space. Examples of additional features that can be added to fluid ejection devices include memory devices.

[0030] Accordingly, various example circuits of fluid ejection devices (which comprise one die or multiple dies) are disclosed herein that can share control lines and data lines to allow for a reduction in the number of signal lines of the fluid ejection devices. As used herein, the term “line” refers to an electrical conductor (or alternatively, multiple electrical conductors) that can be used to carry a signal (or multiple signals).

[0031] Figure 1 is a block diagram illustrating one example of a fluid ejection system 100. The fluid ejection system 100 comprises a fluid ejection controller 102 and a fluid ejection device 106. The fluid ejection controller 102 is communicatively coupled to the fluid ejection device 106 by a plurality of control lines 104. The fluid ejection device 106 can comprise a control circuit 108, a fluid actuation device 110, a first memory 112, and a second memory 114. The control circuit 108 is electrically coupled to the fluid actuation device 110, the first memory 112, and the second memory 114.

[0032] The fluid ejection controller 102 is separate from the fluid ejection device 106. The fluid ejection controller 102 can include a processor, an application specific integrated circuit (ASIC), or other suitable logic circuitry for controlling the fluid ejection device 106 through the control lines 104. For example, in a printing system, the fluid ejection controller 102 can be a print head drive controller that is part of the printing system, and the fluid ejection device 106 can be a print head integrated circuit die that is part of a print cartridge (containing ink or another agent) or another structure.

[0033] The fluid actuation device 110 of the fluid ejection device 106 can include an array of nozzles that can be selectively controlled to dispense fluid. The first memory 112 can include an ID memory for storing identification data and / or other information about the fluid ejection device 106, such as for uniquely identifying the fluid ejection device 106. The second memory 114 can include a firing memory for storing data related to the fluid actuation device 110, where the data can include any or some combination of the following, such as examples: die position, zone information, drop weight encoding information, authentication information, data for enabling or disabling selected fluid actuation devices, and so forth.

[0034] The first memory 112 and the second memory 114 can be implemented with different types of memory to form a hybrid memory arrangement. The first memory 112 can be implemented with non-volatile memory, such as electrically programmable read-only memory (EPROM). The second memory 114 can be implemented with non-volatile memory, such as a fuse memory, where the fuse memory includes an array of fuses that can be selectively blown (or not blown) to program data into the second memory 114. Although specific examples of types of memory are listed above, it should be noted that in other examples, the first memory 112 and the second memory 114 can be implemented with other types of memory. In some examples, the first memory 112 and the second memory 114 can be implemented with the same type of memory.

[0035] In one example, the fluid actuation devices 110, the first memory 112, and the second memory 114 of the fluid ejection device 106 can be formed on a common die (i.e., a fluid ejection die). In another example, the fluid actuation devices 110 can be implemented on one die (i.e., a fluid ejection die), while the first memory 112 and the second memory 114 can be implemented on separate dies (or respective separate dies). For example, the first memory 112 and the second memory 114 can be formed on a second die separate from the fluid ejection die, or alternatively, the first memory 112 and the second memory 114 can be formed on respective different dies separate from the fluid ejection die. In other examples, a portion of the first memory 112 can be on one die, and another portion of the first memory 112 can be on another die. Likewise, a portion of the second memory 114 can be on one die, and another portion of the second memory 114 can be on another die.

[0036] The control circuit 108 controls the operation of the fluid actuation devices 110, the first memory 112, and the second memory 114 based on control signals received over the control lines 104. The control lines 104 include a fire line, a CSYNC line, a select line, address data lines, an ID line, a clock line, and other lines. In other examples, there can be multiple fire lines and / or multiple select lines and / or multiple address data lines. The control circuit 108 can select the fluid actuation devices 110 or the second memory 114 based on an ID signal on the ID line. The ID line can also be used to access the first memory 112 for read and / or write operations. Memory elements of the first memory 112 can be addressed based on selection signals and data signals on the select line and the address data lines.

[0037] The fire line is used to control activation of the fluid actuation devices 110 when the fluid actuation devices 110 are selected by the control circuit 108 in response to a first logic level on the ID line. If such fluid actuation device (or fluid actuation devices) is addressed based on selection signals and data signals on the select line and the address data lines, a fire signal on the fire line causes the corresponding fluid actuation device (or fluid actuation devices) to be activated when set to the first logic level. If the fire signal is set to a second logic level different from the first logic level, the fluid actuation device (or fluid actuation devices) is not activated. The fire line can also be used to access the second memory 114 for read and / or write operations when the second memory 114 is selected by the control circuit 108 in response to a second logic level on the ID line. Memory elements of the second memory 114 can be addressed based on selection signals and data signals on the select line and the address data lines.

[0038] The CSYNC signal is used to initiate an address (referred to as Ax and Ay) in the fluid ejection device 106. The select line can be used to select certain fluid actuation devices or memory elements. The address data line can be used to carry address bits (or multiple address bits) to address a particular fluid actuation device or memory element (or a particular group of fluid actuation devices or memory elements). The clock line can be used to carry a clock signal for the control circuit 108.

[0039] According to some embodiments of the present disclosure, to improve the flexibility and reduce the number of input / output (I / O) pads that must be provided on the fluid ejection device 106, each firing line and ID line performs both a primary task and a secondary task. As described above, the primary task of the firing line is to activate the selected fluid actuation device(s) 110. The secondary task of the firing line is to transfer data for the second memory 114. In this way, a data path can be provided between the fluid ejection controller 102 and the second memory 114 (through the firing line) without the need for a separate data line between the fluid ejection controller 102 and the fluid ejection device 106.

[0040] The primary task of the ID line is to transfer data for the first memory 112. The secondary task of the ID line is to cause the control circuit 108 to enable the fluid actuation device 110 or the second memory 114. In this way, a common firing line can be used to control the activation of the fluid actuation device 110 and to transfer data for the second memory 114, where the ID line can be used to select when the fluid actuation device 110 is controlled by the firing line and when the firing line can be used to transfer data for the second memory 114.

[0041] Figure 2 is shown in more detail Figure 1 A schematic diagram of one example of the fluid ejection device 106 of Figure 1 The latches 130 and 132, the shift register decoder 134, the address generator 136, and the switches 144, 146, 148, and 150 can be part of the control circuit 108 of Figure 1

[0042] ​The ID line 142 is electrically coupled to an input of the latch 130, an input of the latch 132, and the first memory 112. The fire line 140 is electrically coupled to one side of a switch 146 and to the fluid actuation device 110. An output of the latch 130 is electrically coupled to a control input of the switch 146. The other side of the switch 146 is electrically coupled to the second memory 114. An output of the latch 132 is electrically coupled to a control input of a switch 148. The switch 148 is electrically coupled between the second memory 114 and a common or ground node 152. A switch 150 is electrically coupled between the fluid actuation device 110 and the common or ground node 152. An output of the address generator 136 is electrically coupled to a control input of the switch 148 and to a control input of the switch 150. An output of the shift register 134 is electrically coupled to a control input of the switch 144. The switch 144 is electrically coupled between the first memory 112 and the common or ground node 152.

[0043] The first memory 112 can include a plurality of memory elements. The switch 144 can include a plurality of switches, where each switch corresponds to one of the memory elements of the first memory 112. The shift register decoder 134 selects a memory element of the first memory 112 for read and / or write access by closing the switch 144 corresponding to the selected memory element. The shift register decoder 134 disables a memory element of the first memory 112 by opening the switch 144 corresponding to the disabled memory element. Where a memory element of the first memory 112 is selected by the shift register decoder 134, the memory element can be accessed for read and / or write operations by the ID line 142.

[0044] The latch 130 receives an ID signal on the ID line 142, latches the logic level of the ID signal, and controls the switch 146 based on the latched value. In response to a first logic level (e.g., logic high) of the latched value, the latch 130 turns on the switch 146. In response to a second logic level (e.g., logic low) of the latched value, the latch 130 turns off the switch 146. With the switch 146 closed, the second memory 114 is enabled for read and / or write access by the fire line 140. With the switch 146 open, the second memory 114 is disabled.

[0045] The second memory 114 can include a plurality of memory elements. The switch 148 can include a plurality of switches, where each switch corresponds to one of the memory elements of the second memory 114. The switch 150 can include a plurality of switches, where each switch corresponds to one of the fluid actuation devices 110. The latch 132 receives an ID signal on the ID line 142, latches the inverse logic level of the ID signal, and controls the switch 148 based on the latched value. In response to a first logic level (e.g., logic high) of the latched value, the latch 132 disables the switch 148 (i.e., prevents the switch 148 from conducting). In response to a second logic level (e.g., logic low) of the latched value, the latch 132 enables the switch 148 (i.e., allows the switch 148 to conduct).

[0046] The address generator 136 generates address signals Ax and Ay for selecting a memory element of the second memory 114 or a fluid actuation device 110. The selection of a memory element of the second memory 114 or a fluid actuation device 110 can also be based on a data signal (D2) on a data line. Thus, as shown and described in more detail below, the switch 148 can be controlled based on ID x D2 x Ax Ay, and the switch 150 can be controlled based on ID' x D2 x Ax Ay. With the switch 150 open, the switch 146 closed, and the switch 148 closed, the second memory 114 can be accessed for read and / or write operations by the fire line 140. With the switch 146 open, the switch 148 open, and the switch 150 closed, the fluid actuation device 110 can be activated by the fire line 140. Figure 2

[0047] Figure 3 is a block diagram illustrating one example of a circuit 200 including a first memory and a second memory of a fluid ejection device. In one example, the circuit 200 is part of an integrated circuit for driving a plurality of fluid actuation devices. The circuit 200 includes a first memory 112 and a second memory 114. The first memory 112 includes a plurality of first memory elements 2121to 212 M where "M" is any suitable number of memory elements. The second memory 114 includes a plurality of second memory elements 2141to 214 N where "N" is any suitable number of memory elements. The first memory 112 and the second memory 114 can include the same number of memory elements or a different number of memory elements.

[0048] ​Circuit 200 also includes a plurality of first data (Dl 1-D13) lines 2161-2163 and a second data (D2) line 218. First data lines 2161-2163 are electrically coupled to first memory 112, and second data line 218 is electrically coupled to second memory 114. In one example, first data lines 2161-2163 and second data line 218 are part of address data lines of control lines 104. In this example, memory elements 212 of first memory 112 are enabled in response to first data on a plurality of first data lines 2161-2163, and memory elements 214 of second memory 114 are enabled in response to second data on second data line 218. Figure 1

[0049] Figure 4 is a block diagram illustrating another example of a circuit 230 including a first memory and a second memory of a fluid ejection device. In one example, circuit 230 is part of an integrated circuit for driving a plurality of fluid actuation devices. Circuit 230 includes first memory 112 and second memory 114 as previously described and illustrated with respect to Figure 3 In this example, memory elements 212 of first memory 112 are enabled in response to a first logic level on first select line 236, and memory elements 214 of second memory 114 are enabled in response to a first logic level on second select line 238 and a first logic level on ID line.

[0050] In one example, Figure 3 Circuit 200 of Figure 4 may be combined with circuit 230 of Figure 1 Thus, first memory 112 can be accessed based on an address generated by first data Dl 1, D12, and D13 (e.g., via shift register decoder 134 of Figure 1 ), while second memory 114 can be accessed based on an address generated by second data D2. First data and second data can be completely independent of each other. Additionally, first memory 112 can be enabled in response to an S4 select signal, while second memory 114 can be enabled in response to an S5 select signal. S4 select signal and S5 select signal can be interleaved. In this way, ID signal corruption due to a shift register (e.g., shift register decoder 134 of

[0051] Figure 5 ​is a schematic diagram illustrating one example of a circuit 250 including a memory element of a fluid ejection device. In one example, the circuit 250 is part of an integrated circuit for driving a plurality of fluid actuation devices. The circuit 250 includes a firing line 140, an ID line 142, a memory element 252, a latch 254, and a discharge path 256. The firing line 140 is electrically coupled to the memory element 252. The ID line 142 is electrically coupled to an input of the latch 254. An output of the latch 254 is electrically coupled to an input of the discharge path 256. The discharge path 256 is electrically coupled between the memory element 252 and a common or ground node 152.

[0052] The discharge path 256 prevents the memory element 252 from floating when the memory element 252 is not enabled for read and / or write access. In this example, the latch 254 disables the discharge path in response to a first logic level (e.g., logic high) on the ID line 142 and enables the discharge path in response to a second logic level (e.g., logic low) on the ID line. When the memory element 252 is enabled, the discharge path 256 is disabled and the memory element 252 can be accessed for read and / or write operations via the firing line 140. In one example, the latch 254 provides a high impedance to the discharge path 256 when the latch 254 is enabled. Figure 2 The latch 132 of FIG. 1, the discharge path 256 is part of the control input to the switch 148, and the memory element 252 is the memory element of the second memory 114 of FIG. 1. Figure 2 The latch 132 of FIG. 1, the discharge path 256 is part of the control input to the switch 148, and the memory element 252 is the memory element of the second memory 114 of FIG. 1.

[0053] Figure 6 is a schematic diagram illustrating another example of a circuit 270 including a memory element of a fluid ejection device. In one example, the circuit 270 is part of an integrated circuit for driving a plurality of fluid actuation devices. The circuit 270 includes a firing line 140, an ID line 142, a memory element 252, a latch 272, and a switch 274. The switch 274 is electrically coupled between the firing line 140 and the memory element 252. An input of the latch 272 is electrically coupled to the ID line 142. An output of the latch 272 is electrically coupled to a control input of the switch 274. The memory element 252 is electrically coupled to a common or ground node 152.

[0054] In this example, latch 272 enables (i.e., turns on) switch 274 in response to a first logic level (e.g., logic high) on ID line 142, and disables (i.e., turns off) switch 274 in response to a second logic level (e.g., logic low) on ID line 142. When switch 274 is enabled, trigger line 140 is electrically connected to memory element 252. When switch 274 is disabled, trigger line 140 is electrically disconnected from memory element 252. When switch 274 is enabled, memory element 252 can be accessed via trigger line 140 for read and / or write operations. In one example, latch 272 provides... Figure 2 The latch 130 and switch 274 provide Figure 2 The switch 146, and the memory element 252 provides Figure 2 The memory element of the second memory 114.

[0055] Figure 7A This is a schematic diagram illustrating an example of a circuit 300 including multiple memory elements of a fluid jetting device. In one example, circuit 300 is part of an integrated circuit for driving multiple fluid actuation devices. Circuit 300 includes an excitation line 140 and multiple memory elements 2141 to 2142. N First switch 304 and multiple second switches 3081 to 308 N Switch 304 is electrically coupled to excitation line 140 and each memory element 2141 to 214. N Between the first side. The control input of switch 304 is electrically coupled to control (Vy) signal line 302. Each second switch 3081 to 308 N One side is electrically coupled to the corresponding memory element 2141 to 214. N The second side. Each second switch 3081 to 308 N The other side is electrically coupled to a common or grounded node 152. Each second switch 3081 to 308 N The control inputs are electrically coupled to the control (X1 to X...) N Signal lines 3061 to 306 N .

[0056] The Vy control signal can be based on the ID signal (e.g., on ID line 142). Control signals X1 to X N This can be based on the ID signal (e.g., on ID line 142), the D2 data signal (e.g., on D2 data line 218), and the Ax and Ay address signals (e.g., from address generator 136). In this example, switch 304 can be turned on in response to the Vy signal and in response to the corresponding X1 to X... N The signal activates at least one corresponding second switch 3081 to 308.N memory elements 2141-214 N In the event that a memory element 2141-214 N is enabled, the enabled memory element can be accessed for read and / or write operations via the firing line 140. In one example, the first switch 304 provides Figure 2 switch 146, and each second switch 3081-308 N provides Figure 2 switch 148.

[0057] Figure 7B is a schematic diagram illustrating another example of a circuit 320 including a plurality of memory elements of a fluid ejection device. In one example, the circuit 320 is part of an integrated circuit for driving a plurality of fluid actuation devices. The circuit 320 is similar to the circuit 300 previously described and illustrated with reference to Figure 7A , except that in the circuit 320 a first transistor 324 is used in place of the first switch 304 and a plurality of second transistors 3281-328 N are used in place of the second switches 3081-308 N . The first transistor 324 has a source-drain path electrically coupled between the firing line 140 and a first side of each memory element 2141-214 N . Each second transistor 3281-328 N has a source-drain path electrically coupled between the respective memory element 2141-214 N and a common or ground node 152. The gate of each second transistor 3281-328 N is electrically coupled to the control signal line 3061-306 N , respectively.

[0058] In this example, a memory element 2141-214 N may be enabled by turning on the first transistor 324 in response to a logic high Vy signal and turning on at least one respective second transistor 3281-328 N in response to a respective logic high X1-X N signal. In the event that a memory element 2141-214 N is enabled, the enabled memory element can be accessed for read and / or write operations via the firing line 140. In one example, the first transistor 324 provides Figure 2 switch 146, and each second transistor 3281-328 N provides Figure 2 switch 148.

[0059] Figures 8A-8BThis is a schematic diagram illustrating an example of circuitry 350, which includes multiple memory elements of a fluid jetting device and multiple fluid actuation devices. In one example, circuitry 350 is part of an integrated circuit for driving multiple fluid actuation devices. Circuitry 350 includes elements from previous references. Figure 7B The circuit 320 described and illustrated. Additionally, as... Figure 8A As illustrated, circuit 350 includes a plurality of fluid actuation devices 3521 to 352. N and multiple third switches (e.g., third transistors) 3581 to 358 N Each fluid actuation device 3521 to 352 N Electrically coupled to the excitation line 140 and the corresponding third transistors 3581 to 358 N Between one side of the source-drain path. Each third transistor 3581 to 358 N The other side of the source-drain path is electrically coupled to a common or ground node 152. Each third transistor 3581 to 358... N The gates are electrically coupled to the control (Y1 to Y). N Signal lines 3561 to 356 N .

[0060] like Figure 8B As illustrated, circuit 350 also includes address generator 136 and decoder 360. The output of address generator 136 is electrically coupled to the input of decoder 360 via Ax address signal line 362 and Ay address signal line 364. Other inputs of decoder 360 are electrically coupled to ID line 142 and second data line 218. The first output of decoder 360 is transmitted via control signal lines 3061 to 306... N Electrically coupled to the second transistor 3281 to 328 N The gate of the decoder 360. The second output of the decoder 360 is respectively controlled by signal lines 3561 to 356. N Electrically coupled to the third transistor 3581 to 358 N The gate.

[0061] Ax and Ay are output by address generator 136, such as in response to the select signal on the select line and the CSYNC signal on the CSYNC line. In one example, decoder 360 receives an address (e.g., D2, Ax, Ay) to turn on the corresponding second transistors 3281 to 328 in response to that address. N Or the corresponding third transistor 3581 to 358 N In another example, in response to a first logic level (e.g., logic high) on ID line 142, decoder 360 turns on the corresponding second transistors 3281 to 328 in response to the address. NIn response to a second logic level (e.g., logic low) on ID line 142, decoder 360 turns on the corresponding third transistors 3581 to 358 in response to the address. N To activate the corresponding fluid actuation devices 3521 to 352 N In fluid actuation devices 3521 to 352 N When enabled, the activated fluid actuation device can be activated via excitation line 140. In one example, each third transistor 3581 to 358 N supply Figure 2 Switch 150.

[0062] Figure 9A This is a schematic diagram showing in more detail an example of a circuit 400 including a first memory 112, a second memory 114, and a fluid actuation device 110. In one example, circuit 400 is part of an integrated circuit for driving multiple fluid actuation devices. Although the first memory 112 includes multiple memory elements, Figure 9A Only one memory element 212 is shown. Similarly, although the second memory 114 includes multiple memory elements, Figure 9A Only one memory element 214 is shown, and although the fluid actuation device 110 includes multiple fluid actuation devices, Figure 9A Only one fluid actuation device 352 is shown in the figure.

[0063] Circuit 400 includes a trigger line 140, an ID line 142, first data lines 2161 to 2163, a second data line 218, select lines 236 and 238, an Ax address signal line 362, an Ay address signal line 364, a shift register decoder 134, and transistors 324, 328, and 358, as previously described. Additionally, circuit 400 includes a buffer 408, an inverter 410, and transistors 402, 404, 406, 412, 414, 416, 418, 420, 422, 432, 434, 436, 438, 440, and 442. In one example, transistors 402, 404, and 406 may provide... Figure 2 Switch 144. Buffer 408 can provide Figure 2 latch 130 or Figure 6 The latch 272. The inverter 410 can provide... Figure 2 latch 132 or Figure 5 The latch 254. Transistor 416 can provide the first memory 114 with... Figure 5part of the discharge path 256. The transistor 436 can provide the discharge path for the fluid actuation device 110. The transistors 412, 414, 418, 420, 422, 432, 434, 438, 440, and 442 can provide Figure 8B part of the decoder 360.

[0064] A first input of the shift register decoder 134 is electrically coupled to the first data lines 2161-2163. A second input of the shift register decoder 134 is electrically coupled to the first select (S4) line 236. An output of the shift register decoder 134 is electrically coupled to the gates of the transistors 402, 404, and 406. The transistors 402, 404, and 406 are electrically coupled in series between the memory element 212 and the common or ground node 152. When the transistors 402, 404, and 406 are turned on, the memory element 212 is addressed such that the data of the memory element 212 can be accessed via the ID line 142.

[0065] The shift register decoder 134 includes a shift register connected to each of the first data lines 2161-2163 to input address data bits to the shift register decoder 134. Each shift register includes a string of shift register cells, which can be implemented as flip-flops, other storage elements, or any sample-and-hold circuitry that can maintain its value until the next time the storage element is selected (such as circuitry for pre-charging and evaluating the address data bits). The output of one shift register cell in the string can be provided to the input of the next shift register cell to perform a data shift through the shift register. The address data bits provided through each shift register are connected to the gates of the corresponding ones of the transistors 402, 404, and 406.

[0066] By using the shift registers in the shift register decoder 134, a small number of data lines 2161-2163 can be used to select a large address space. For example, each shift register can include eight (or any other number of) shift register cells. In the case of a shift register decoder 134 including three shift registers (each eight in length) into which three address data bits (D11, D12, and D13) are input, the address space that can be addressed by the shift register decoder 134 is 512 bits (instead of just eight bits if the three address bits were used without the shift registers of the shift register decoder 134). The output of the shift register decoder 134 can be enabled in response to a first logic level on the first select (S4) line 236 and disabled in response to a second logic level on the first select (S4) line 236.

[0067] The buffer 408 is electrically coupled between the ID line 142 and the gate of the transistor 324 by a Vy node 409. The inverter 410 is electrically coupled between the ID line 142 and the gate of the transistor 416 by a Vx node 411. One side of the source-drain path of the transistor 416 is electrically coupled to the common or ground node 152. The other side of the source-drain path of the transistor 416 is electrically coupled to one side of the source-drain path of the transistor 414, one side of the source-drain path of the transistor 418, one side of the source-drain path of the transistor 420, and one side of the source-drain path of the transistor 422. The other side of the source-drain path of each of the transistors 418, 420, and 422 is electrically coupled to the common or ground node 152. The gate of the transistor 418 is electrically coupled to the second data line 218. The gate of the transistor 420 is electrically coupled to the Ax address signal line 362. The gate of the transistor 422 is electrically coupled to the Ay address signal line 364. The gate of the transistor 414 is electrically coupled to the second select (S5) line 238. The other side of the source-drain path of the transistor 414 is electrically coupled to one side of the source-drain path of the transistor 412 and the gate of the transistor 328. The other side and the gate of the source-drain path of the transistor 412 are electrically coupled to the first select (S4) line 236.

[0068] The gate of the transistor 436 is electrically coupled to the ID line 142. One side of the source-drain path of the transistor 436 is electrically coupled to the common or ground node 152. The other side of the source-drain path of the transistor 436 is electrically coupled to one side of the source-drain path of the transistor 434, one side of the source-drain path of the transistor 438, one side of the source-drain path of the transistor 440, and one side of the source-drain path of the transistor 442. The other side of the source-drain path of each of the transistors 438, 440, and 442 is electrically coupled to the common or ground node 152. The gate of the transistor 438 is electrically coupled to the second data line 218. The gate of the transistor 440 is electrically coupled to the Ax address signal line 362. The gate of the transistor 442 is electrically coupled to the Ay address signal line 364. The gate of the transistor 434 is electrically coupled to the second select (S5) line 238. The other side of the source-drain path of the transistor 434 is electrically coupled to one side of the source-drain path of the transistor 432 and the gate of the transistor 358. The other side and the gate of the source-drain path of the transistor 432 are electrically coupled to the first select (S4) line 236.

[0069] Two separate decoders are used to individually control the respective transistors 328 and 358 connected to the memory element 214 and the fluid actuating device 352. The gate of the transistor 328 is connected to a first decoder including transistors 412, 414, 418, 420, and 422. The gate of the transistor 358 is connected to a second decoder including transistors 432, 434, 438, 440, and 442. The S4 select signal can be activated earlier in time than the S5 select signal. The combination of Ax, Ay, D2, S4, and S5 form the address input to the first and second decoders.

[0070] When the ID signal on the ID line 142 is at the first logic level (e.g., logic high), the transistor 436 is on and keeps the gate of the transistor 358 discharged (i.e., disables the gate of the transistor 358) so that the fluid actuating device 352 remains deactivated. In addition, when the ID signal is at the first logic level (e.g., logic high), the transistor 324 is turned on by the buffer 408 and the transistor 416 is turned off by the inverter 410 so that when the transistor 328 is turned on based on the address input to the first decoder, the memory element 214 can be accessed for read and / or write operations through the fire line 140.

[0071] When the ID signal on the ID line 142 is at the second logic level (e.g., logic low), the transistor 436 is off so that when the transistor 358 is turned on based on the address input to the second decoder, the fluid actuating device 352 can be activated through the fire line 140. In addition, when the ID signal is at the second logic level (e.g., logic low), the transistor 324 is turned off by the buffer 408 and the transistor 416 is turned on by the inverter 410. With the transistor 416 on, the gate of the transistor 328 remains discharged (i.e., the gate of the transistor 328 is disabled) so that the memory element 214 remains deselected.

[0072] Figure 9B FIG. 4B is a schematic diagram illustrating another example of a circuit 450 including a first memory 112, a second memory 114, and a fluid actuating device 110. In one example, the circuit 450 is part of an integrated circuit for driving a plurality of fluid actuating devices. The circuit 450 is similar to the circuit 400 previously described and illustrated with respect to FIG. 4A, except in the circuit 450, the buffer 408 is replaced with transistors 452, 454, 456, 458, 460, and 462; and the inverter 410 is replaced with transistors 468, 470, and 472. Figure 9A

[0073] ​Transistors 460 and 462 are electrically coupled in series between node 459 and a common or ground node 152. The gate of transistor 462 is electrically coupled to the ID line 142, and the gate of transistor 460 is electrically coupled to the S4 select line 236. Transistor 458 has a source-drain path electrically coupled between the S3 select line 234 and node 459. The gate of transistor 458 is electrically coupled to the S3 select line 234. Transistor 454 and transistor 456 are electrically coupled in series between the gate of transistor 324 and the common or ground node 152. The gate of transistor 456 is electrically coupled to node 459. The gate of transistor 454 is electrically coupled to the S5 select line 238. Transistor 452 has a source-drain path electrically coupled between the S4 select line 236 and the gate of transistor 324. The gate of transistor 452 is electrically coupled to the S4 select line 236.

[0074] Transistors 470 and 472 are electrically coupled in series between the gate of transistor 416 and the common or ground node 152. The gate of transistor 472 is electrically coupled to the ID line 142. The gate of transistor 470 is electrically coupled to the S4 select line 236. Transistor 468 has a source-drain path electrically coupled between the S3 select line 234 and the gate of transistor 416. The gate of transistor 468 is electrically coupled to the S3 select line 234.

[0075] The S3 select signal can be activated earlier in time than the S4 select signal. The S4 select signal can be activated earlier in time than the S5 select signal. In the case that the ID signal on the ID line 142 is at a first logic level (e.g., logic high), a second logic level (e.g., logic low) is latched on the Vx node 411 in response to the S3 select signal and the S4 select signal. In the case that the ID signal is at a second logic level (e.g., logic low), a first logic level (e.g., logic high) is latched on the Vx node 411 in response to the S3 select signal and the S4 select signal.

[0076] In the case that the ID signal on the ID line 142 is at the first logic level (e.g., logic high), the second logic level (e.g., logic low) is latched on the node 459 in response to the S3 select signal and the S4 select signal. In the case that the ID signal is at the second logic level (e.g., logic low), the first logic level (e.g., logic high) is latched on the node 459 in response to the S3 select signal and the S4 select signal. In the case that the first logic level (e.g., logic high) on the node 459, the second logic level (e.g., logic low) is latched on the Vy node 409 in response to the S4 select signal and the S5 select signal. In the case that the second logic level (e.g., logic low) on the node 459, the first logic level (e.g., logic high) is latched on the Vy node 409 in response to the S4 select signal and the S5 select signal. Thus, in the case that the ID signal on the ID line 142 is at the first logic level (e.g., logic high), the first logic level (e.g., logic high) is latched on the Vy node 409 in response to the S3 select signal, the S4 select signal, and the S5 select signal. In the case that the ID signal is at the second logic level (e.g., logic low), the second logic level (e.g., logic low) is latched on the Vy node 409 in response to the S3 select signal, the S4 select signal, and the S5 select signal.

[0077] Figure 10A and Figure 10B is a timing diagram illustrating one example of operation of the circuit 450 of Figure 9B Figure 10A Timing diagram 500a is shown when the memory element 214 is enabled, and Figure 10B Timing diagram 500b is shown when the fluid actuation device 352 is enabled. Timing diagrams 500a and 500b include the CSYNC signal, the S1 select signal, the S2 select signal, the S3 select signal on the S3 select line 234, the S4 select signal on the S4 select line 236, the S5 select signal on the S5 select line 238, the clock signal, the D11 data signal on the D11 data line 2161, the D12 data signal on the D12 data line 2162, the D2 data signal on the D2 data line 218, the ID signal on the ID line 142, the Vx signal on the Vx node 411, and the fire signal on the fire line 140.

[0078] The S1 to S5 select signals are activated in sequence. The S1 and S2 select signals can be used by the first memory 112, such as for controlling the shift register decoder 134. As Figure 10A ​As shown, at 502, when the S4 signal is logic high and the ID signal is logic high, Vx is logic low. Therefore, when the S5 signal is logic high, the discharge path of memory element 214 is broken and memory element 214 is enabled for read and / or write access via the trigger signal, as indicated at 504. Figure 10B As shown, at 506, when the S4 signal is logic high and the ID signal is logic low, Vx is logic high. Therefore, when the S5 signal is logic high, the discharge path of memory element 214 is connected and memory element 214 is disabled. With memory element 214 disabled, fluid actuator 352 can be enabled and activated via an excitation signal, as indicated at 508.

[0079] In one example, such as Figure 10A and Figure 10B As shown, the ID signal and the excitation signal can not be turned on simultaneously (i.e., logic high). Therefore, when the S4 signal is logic high, the ID signal is latched to provide Vx in preparation for the excitation signal when S5 is logic high. This also ensures that the gate of the transistor 328 for memory element 214 or the gate of the transistor 358 for fluid actuation device 352 has a discharge path to avoid a floating condition when not selected. Floating conditions should be avoided to prevent data corruption stored in the second memory 114.

[0080] Figure 11A and Figure 11B It shows Figure 9B A timing diagram of another example of the operation of the circuit. Figure 11A Timing diagram 550a is shown when memory element 214 is enabled, and Figure 11B Timing diagram 550b is shown when the fluid actuation device 352 is enabled. Timing diagrams 550a and 550b include the CSYNC signal, S1 select signal, S2 select signal, S3 select signal on S3 select line 234, S4 select signal on S4 select line 236, S5 select signal on S5 select line 238, clock signal, D11 data signal on D11 data line 2161, D12 data signal on D12 data line 2162, D2 data signal on D2 data line 218, ID signal on ID line 142, Vy signal on Vy node 409, and excitation signal on excitation line 140.

[0081] like Figure 11A As shown, at 552, when the S4 signal is logic high and the ID signal is logic high, Vy is logic high when the S5 signal is logic high. When Vy is logic high, memory element 214 is enabled for read and / or write access via the trigger signal, as indicated at 554. Figure 11BAs shown, at 556, when the S4 signal is logic high and the ID signal is logic low, Vy is logic low when the S5 signal is logic high. When Vy is logic low, memory element 214 is disabled and isolated from the excitation signal. With memory element 214 disabled, fluid actuator 352 can be enabled and activated via the excitation signal, as indicated at 558.

[0082] In one example, such as Figure 11A and Figure 11B As shown, the ID signal and the excitation signal can not be turned on simultaneously (i.e., logic high). Therefore, when the S4 signal is logic high, the ID signal is latched to provide Vy in preparation for the excitation signal when S5 is logic high. When the fluid actuation device 352 is activated, the transistor 324 also acts as an isolator between the excitation signal and the memory element 214. This prevents the memory element 214 from being subjected to high voltage at high frequencies, which improves the reliability of the memory element 214.

[0083] Figure 12 This is a block diagram illustrating an example of a fluid jetting system 600. The fluid jetting system 600 includes fluid jetting components (such as a printhead assembly 602) and fluid supply components (such as an ink supply assembly 610). In the example shown, the fluid jetting system 600 also includes a service station assembly 604, a carriage assembly 616, a print media transport assembly 618, and an electronic controller 620. Although the following description provides examples of systems and components for fluid handling with respect to ink, the disclosed systems and components are also suitable for handling fluids other than ink.

[0084] Printhead assembly 602 includes at least one printhead or fluid jet mold 606 (e.g. Figure 1 The fluid jetting apparatus 106 ejects ink droplets or liquid droplets through a plurality of orifices or nozzles 608. In one example, the droplets are directed toward a medium, such as printing medium 624, to be printed onto the printing medium 624. In one example, printing medium 624 comprises any type of suitable sheet material, such as paper, cardstock, transparent film, polyester film, fabric, etc. In another example, printing medium 624 comprises a medium for three-dimensional (3D) printing, such as a powder bed, or a medium for bioprinting and / or drug discovery testing, such as a reservoir or container. In one example, the nozzles 608 are arranged in at least one column or array such that, as the printhead assembly 602 and the printing medium 624 move relative to each other, the properly ordered ejection of ink from the nozzles 608 results in characters, symbols, and / or other graphics or images being printed onto the printing medium 624.

[0085] The ink supply assembly 610 supplies ink to the printhead assembly 602 and includes a reservoir 612 for storing ink. Thus, in one example, ink flows from the reservoir 612 to the printhead assembly 602. In one example, the printhead assembly 602 and the ink supply assembly 610 are housed together in an inkjet or fluid ejection printing cartridge or pen. In another example, the ink supply assembly 610 is separate from the printhead assembly 602 and supplies ink to the printhead assembly 602 through an interface connection 613, such as a supply tube and / or valve.

[0086] The carriage assembly 616 positions the printhead assembly 602 relative to the print media transport assembly 618, and the print media transport assembly 618 positions the print media 624 relative to the printhead assembly 602. Thus, a print zone 626 is defined as the area adjacent the nozzles 608 in the region between the printhead assembly 602 and the print media 624. In one example, the printhead assembly 602 is a scanning printhead assembly such that the carriage assembly 616 moves the printhead assembly 602 relative to the print media transport assembly 618. In another example, the printhead assembly 602 is a non-scanning printhead assembly such that the carriage assembly 616 fixes the printhead assembly 602 at a prescribed position relative to the print media transport assembly 618.

[0087] The service station assembly 604 provides for ejection, wiping, capping, and / or priming of the printhead assembly 602 to maintain the functionality of the printhead assembly 602, and more specifically the nozzles 608. For example, the service station assembly 604 can include a rubber blade or wiper that periodically passes over the printhead assembly 602 to wipe and clean excess ink from the nozzles 608. Additionally, the service station assembly 604 can include a cap that covers the printhead assembly 602 to protect the nozzles 608 from drying out during periods of non-use. Additionally, the service station assembly 604 can include a spittoon into which the printhead assembly 602 ejects ink during spitting to ensure that the reservoir 612 maintains an appropriate level of pressure and fluidity, and to ensure that the nozzles 608 do not clog or leak. The functionality of the service station assembly 604 can include relative motion between the service station assembly 604 and the printhead assembly 602.

[0088] The electronic controller 620 communicates with the printhead assembly 602 over a communication path 603, with the service station assembly 604 over a communication path 605, with the carriage assembly 616 over a communication path 617, and with the print media transport assembly 618 over a communication path 619. In one example, the electronic controller 620 and the printhead assembly 602 can communicate via the carriage assembly 616 over a communication path 601 when the printhead assembly 602 is installed in the carriage assembly 616. The electronic controller 620 can also communicate with the ink supply assembly 610 so that, in one implementation, a new (or used) ink supply can be detected.

[0089] The electronic controller 620 receives data 628 from a host system (e.g., a computer) and can include memory for temporarily storing the data 628. The data 628 can be transmitted to the fluid ejection system 600 along an electronic, infrared, optical, or other information transfer path. The data 628 represents, for example, a document and / or file to be printed. Thus, the data 628 forms a print job for the fluid ejection system 600 and includes at least one print job command and / or command parameter.

[0090] In one example, the electronic controller 620 provides control of the printhead assembly 602, including timing control for ejection of drops of ink from the nozzles 608. Thus, the electronic controller 620 defines a pattern of ejected drops of ink that form characters, symbols, and / or other graphics or images on the print media 624. The timing control, and thus the pattern of ejected drops of ink, is determined by the print job command and / or command parameter. In one example, logic and drive circuitry forming part of the electronic controller 620 is located on the printhead assembly 602. In another example, logic and drive circuitry forming part of the electronic controller 620 is located off the printhead assembly 602.

[0091] Figures 13A-13D is a flowchart illustrating one example of a method 700 for accessing a first memory and a second memory of a fluid ejection device. In one example, the method 700 can be implemented by Figure 1 the fluid ejection system 100 of Figure 13A As illustrated, at 702, the method 700 includes sequentially generating a first select signal and a second select signal. At 704, the method 700 includes enabling a first memory element in response to the first select signal and first data on a plurality of first data lines. At 706, the method 700 includes enabling a second memory element in response to the second select signal and second data on a second data line.

[0092] As illustrated, at 702, the method 700 includes sequentially generating a first select signal and a second select signal. At 704, the method 700 includes enabling a first memory element in response to the first select signal and first data on a plurality of first data lines. At 706, the method 700 includes enabling a second memory element in response to the second select signal and second data on a second data line. Figure 13BAs illustrated, at 708, the method 700 can further include generating an address signal. In this case, enabling the second memory element can include enabling the second memory element in response to the second select signal, the second data on the second data line, and the address signal.

[0093] As Figure 13C illustrated, at 710, the method 700 can further include generating a signal on an ID line. At 712, the method 700 can further include enabling the fluid actuation device in response to the second select signal and a first logic level on the ID line. In this case, enabling the second memory element can include enabling the second memory element in response to the second select signal and a second logic level on the ID line.

[0094] As Figure 13D illustrated, at 714, the method 700 can further include accessing the first memory element via the ID line if the first memory element is enabled. At 716, the method 700 can further include accessing the second memory element via the fire line if the second memory element is enabled.

[0095] Figures 14A-14B is a flow diagram illustrating one example of a method 800 for accessing memory of a fluid ejection device. In one example, the method 800 can be implemented by a fluid ejection system 100 of Figure 1 FIG. 1. As Figure 14A illustrated, at 802, the method 800 includes electrically connecting, via a first switch, a first side of each memory element of a plurality of memory elements to a fire line in response to a first logic level on an ID line, and electrically disconnecting, via the first switch, the first side of each memory element of the plurality of memory elements from the fire line in response to a second logic level on the ID line. At 804, the method 800 includes electrically connecting, via a respective second switch of a plurality of second switches, a second side of a respective memory element of the plurality of memory elements to a common node in response to an address signal.

[0096] In one example, the first switch includes a first transistor and the plurality of second switches includes a plurality of second transistors. As Figure 14B illustrated, at 806, the method 800 can further include accessing the respective memory element of the plurality of memory elements via the fire line if the respective memory element is electrically connected between the fire line and the common node.

[0097] Figures 15A-15B is a flow diagram illustrating another example of a method 900 for accessing memory of a fluid ejection device. In one example, the method 900 can be implemented by a fluid ejection system 100 of Figure 1 FIG. 1. AsFigure 15A As illustrated, at 902, the method 900 includes generating an ID signal on an ID line. At 904, the method 900 includes sequentially generating a first select signal and a second select signal. At 906, the method 900 includes latching the ID signal in response to the first select signal. At 908, the method 900 includes enabling a memory element in response to the latched ID signal having a first logic level. At 910, the method 900 includes, with the memory element enabled, accessing the memory element via a fire line in response to the second select signal.

[0098] In one example, enabling the memory element includes electrically connecting the memory element to the fire line in response to the latched ID signal having the first logic level. In another example, latching the ID signal includes inverting the ID signal and, in response to the first select signal, latching the inverted ID signal; and enabling the memory element includes turning off a discharge path coupled to the memory element in response to the latched inverted ID signal having a second logic level.

[0099] As Figure 15B As illustrated, at 912, the method 900 can further include enabling a fluid actuation device in response to the ID signal having a second logic level. At 914, the method 900 can further include, with the fluid actuation device enabled, activating the fluid actuation device via the fire line in response to the second select signal.

[0100] Although specific examples have been shown and described herein, a wide variety of alternatives and / or equivalents exist, which can be substituted for the specific examples shown and described herein without departing from the scope of the disclosure. This application is intended to cover any alternatives or variations of the specific examples discussed herein. Therefore, the disclosure is intended to be limited only by the claims and their equivalents.

Claims

1. An integrated circuit, the integrated circuit comprising: a first plurality of data lines; a second data line; an ID line; a first select line; a second select line; a first latch having an input coupled to the ID line; a second latch having an input coupled to the ID line and an output coupled to a plurality of transistors, wherein a first transistor of the plurality of transistors is coupled to the second data line; a first memory element enabled in response to first data on the first plurality of data lines and in response to a first logic level on the first select line; and a second memory element enabled in response to second data on the second data line and in response to the first logic level on the second select line and the first logic level on the ID line.

2. The integrated circuit of claim 1, wherein, The first memory element and the second memory element are separate from a fluid ejection die comprising a fluid actuation device.

3. The integrated circuit of claim 1, further comprising: a shift register decoder to enable the first memory element in response to the first data on the first plurality of data lines.

4. The integrated circuit of claim 1, wherein, The first transistor is configured to enable the second memory element in response to the second data on the second data line.

5. The integrated circuit of claim 4, further comprising: a second transistor to enable the second memory element in response to the first logic level on the ID line, wherein the first transistor is on a first side of the second memory element and the second transistor is on a second side of the second memory element, the second side being opposite the first side of the second memory element.

6. The integrated circuit of claim 1, wherein, The first memory element is accessed via the ID line with the first memory element enabled.

7. The integrated circuit of claim 6, further comprising: a control line electrically coupled to the second memory element; wherein the second memory element is accessed via the control line with the second memory element enabled.

8. The integrated circuit of claim 1, further comprising: an address generator to generate an address signal, wherein the second memory element is enabled in response to the address signal.

9. The integrated circuit of claim 1, further comprising: a second plurality of transistors to enable the first memory element in response to the first data on the first plurality of data lines.

10. The integrated circuit of claim 1, further comprising: a discharge path electrically coupled between the second memory element and a common or ground node, wherein the discharge path is disabled in response to the first logic level on the ID line and enabled in response to a second logic level on the ID line.

11. The integrated circuit of claim 10, further comprising: a third transistor coupled between the second select line and the discharge path, the third transistor to enable and disable the discharge path in response to different logic levels on the second select line.

12. The integrated circuit of claim 1, wherein, The first memory element comprises a non-volatile memory element and the second memory element comprises a non-volatile memory element.

13. A method for accessing a first memory element and a second memory element of an integrated circuit, the method comprising: generating a first select signal via a first latch having an input coupled to an ID line; generating a second select signal via a second latch under sequential control of the first select signal, the second latch having an input coupled to the ID line and an output coupled to a plurality of transistors, wherein a first transistor of the plurality of transistors is coupled to a second data line; enabling the first memory element in response to the first select signal and first data on a first data line; and enabling the second memory element in response to the second select signal and second data on the second data line.

14. The method of claim 13, wherein, The first memory element and the second memory element are separate from a fluid ejection die comprising a fluid actuation device.

15. The method of claim 13, further comprising: generating an address signal, wherein enabling the second memory element comprises enabling the second memory element in response to the second select signal, second data on the second data line, and the address signal.

16. The method of claim 13, further comprising: accessing the first memory element via an ID line with the first memory element enabled; and accessing the second memory element via a control line with the second memory element enabled.

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