Method for extracting degradation results of transistors, reliability analysis method

Abstract

The application discloses a transistor degradation result extraction method and a reliability analysis method. The transistor degradation result extraction method of the circuit design comprises the following steps: analyzing the net list file of the selected standard cell of the standard cell library to obtain the detailed information of the transistor of the standard cell and deduce the logical relationship of the signal of the standard cell and the relationship between the level of the three ports of the transistor and the transistor degradation; then deducing the degradation logical relationship formula of each transistor; solving the signal level combination condition when the degradation logical relationship formula of all transistors is true; simulating the circuit design according to the input working excitation to obtain the statistical information of the signal; finally, calculating the degradation time of each transistor; and substituting the degradation time of the transistor into the reliability model to obtain the degradation result of the transistor. The extraction accuracy of the degradation stress can be more close to the SPICE level simulation.

Description

Technical Field

[0001] This invention relates to the technical field of reliability analysis of digital circuits, and more particularly to a method for extracting the degradation results of transistors. Background Technology

[0002] With the rapid shrinking of CMOS integrated circuit device dimensions, the impact of device degradation on circuit performance is becoming increasingly apparent, especially on timing. Therefore, a fast and accurate reliability and timing evaluation method is needed during the circuit design phase. Furthermore, the closer a circuit design is to the underlying physical implementation, the more concrete it becomes; the closer it is to the functional description, the more abstract it becomes. Since the circuit hierarchy is a higher level of abstraction than the transistor hierarchy, how to perceive the degradation state of transistors in all standard cells at the circuit hierarchy is a key factor directly determining the accuracy of this method. Standard cells include various basic units such as inverters, AND gates, registers, selectors, and full adders.

[0003] Existing techniques typically employ logic simulation to acquire signal characteristics and then analyze the serial-parallel structure of digital standard cells to obtain the degradation state of each transistor. However, due to the logical correlation between signals within the standard cells, traditional methods cannot detect this correlation when calculating the degradation state, leading to additional errors.

[0004] Therefore, finding a method to extract transistor degradation results and obtain this logic correlation is key to improving the accuracy of circuit reliability analysis. Summary of the Invention

[0005] To address the technical problem of additional errors in calculating degradation results in existing technologies, this invention proposes a method for extracting transistor degradation results and a reliability analysis method.

[0006] This invention proposes a method for extracting the degradation results of transistors in circuit design, comprising:

[0007] The netlist file of the standard cells in the selected standard cell library is parsed to obtain detailed information about the transistors of the standard cells;

[0008] Based on the detailed information of the transistor, the logical relationship of the signal of the standard unit and the relationship between the level of the three ports of the transistor and the transistor degradation are derived.

[0009] Based on the logical relationship of the signals of the standard unit and the relationship between the voltage levels of the three ports of the transistor and the transistor degradation, the degradation logic formula of each transistor is derived.

[0010] Solve to obtain the signal level combinations when the degenerate logic relation of all transistors is true;

[0011] Based on the input operating stimuli, the circuit design whose reliability needs to be verified is simulated to obtain statistical information of the signal;

[0012] The degradation time of each transistor is calculated based on the statistical information of the signal and the obtained combination of signal levels.

[0013] Substituting the transistor's degradation time into the reliability model yields the transistor's degradation results.

[0014] Furthermore, the detailed information of the transistor includes: the transistor type of the standard unit, the connection relationship between the transistors, and all signals within the standard unit.

[0015] Furthermore, the logical relationship of the signals in the standard unit is obtained through the following steps:

[0016] All signals within the standard cell in the transistor details are treated as nodes, including power nodes, ground nodes, and intermediate signal nodes.

[0017] Transistors are converted into lines, and the nodes at the source and drain ends of the transistors are connected according to the transistor type and the connection relationship between the transistors to form an undirected loop graph.

[0018] Traverse all paths between intermediate signal nodes and power signal nodes in the undirected cyclic graph, and / or traverse all paths between intermediate signal nodes and ground nodes, while filtering out loop paths, to obtain the path relationship of intermediate signals and record the transistor information passed through these paths.

[0019] The logical expression of the signal of the standard unit is obtained based on the path relationship of the intermediate signal.

[0020] Furthermore, when traversing the undirected cyclic graph, the connection relationship between the transistors is divided into pull-up networks and pull-down networks. The pull-up networks and pull-down networks are traversed respectively to obtain the path relationship of the intermediate signal.

[0021] Furthermore, the process of determining the signal level combinations when the degenerate logic relation for all transistors is true includes the following steps:

[0022] Convert the degradation logic of all transistors into a binary decision graph;

[0023] Solve the binary decision graph to find all signal level combinations that satisfy a given Boolean expression as true.

[0024] Furthermore, the statistical information of the signal includes the probability of high and low levels of the signal waveform during the simulation time and the number of flips per unit time for the circuit design whose reliability is to be verified.

[0025] The reliability analysis method for circuit design proposed in this invention includes:

[0026] At least one degenerate timing library is pre-built based on the standard cell library;

[0027] The circuit design whose reliability needs to be verified is logic synthesized to obtain a synthesized circuit netlist that does not include degradation information;

[0028] Traverse the standard cells of the circuit design whose reliability is to be verified, and extract the transistor degradation results of the synthesized circuit netlist corresponding to the standard cells using the transistor degradation result extraction method of the circuit design described in the above technical solution.

[0029] Based on the degradation timing library and the standard cell netlist file, the degradation results of the transistors and the synthesized circuit netlist are used to obtain the degradation timing analysis results of the circuit functional design.

[0030] Furthermore, establishing at least one degenerate time series library based on the standard cell library includes:

[0031] It analyzes the types of all standard cells in the standard cell library and the device models corresponding to the transistors inside the standard cells.

[0032] Different degradation amounts were selected under the same environmental conditions;

[0033] Based on different combinations of degradation conditions and the device model, the degradation results of each standard cell under all combinations of degradation conditions corresponding to different degradation amounts are calculated. The degradation results are the timing changes of the standard cell corresponding to the degradation amount of the transistor.

[0034] Based on all degradation results corresponding to different degradation levels, the parameters of all standard units and device models corresponding to different degradation levels are back-inscribed to obtain the degradation units corresponding to different degradation levels.

[0035] Then, a characteristic simulation process is performed on all degradation units corresponding to different degradation levels, and the temporal characteristic values ​​of the degradation units are refreshed to obtain degradation time series libraries corresponding to different degradation levels.

[0036] Furthermore, the degradation conditions include at least one of the following: the power supply voltage of the system in which the circuit operates, the operating temperature, and the degradation time during its life cycle.

[0037] Furthermore, based on the degradation timing library and the standard cell netlist file, the degradation results of the transistors and the synthesized circuit netlist are used to obtain the degradation timing analysis results, which include the following steps:

[0038] Based on the degradation results of the transistors in the synthesized circuit netlist, the cell types of the standard cells in the synthesized circuit netlist are remapped to the degradation cell types that take into account the degradation effects.

[0039] Update the information in the synthesized circuit netlist;

[0040] Back-annotate the synthesized circuit netlist, select all used degraded timing libraries, and import them into the reverse static timing analysis tool;

[0041] Extract the degradation critical path from the static time series analysis report output by the static time series analysis tool;

[0042] Analyze the overall impact of degradation on the circuit.

[0043] Compared with the prior art, the present invention has the following advantages:

[0044] 1. Using the stress extraction method of this patent, additional errors caused by logic conflicts or repetitions can be avoided, and the accuracy can be made closer to SPICE-level simulation while ensuring efficiency requirements at the circuit level.

[0045] 2. This patent proposes a general method that can analyze the degenerate logic relationships of all logic standard units and can also be directly applied to the analysis of small-scale module circuits.

[0046] 3. It is fully compatible with standard digital circuit design flow, mainly by incorporating reliability considerations in some intermediate steps, so implementing this flow does not require significant secondary development. Attached Figure Description

[0047] The present invention will now be described in detail with reference to the embodiments and accompanying drawings, wherein:

[0048] Figure 1 This is an overall flowchart of the circuit reliability analysis of the present invention.

[0049] Figure 2 This is a schematic diagram of a transition signal that leads to degradation according to an embodiment of the present invention.

[0050] Figure 3 This is a flowchart of a method for extracting the degradation results of transistors in a circuit design according to an embodiment of the present invention.

[0051] Figure 4 This is a flowchart of establishing a degradation time series library according to an embodiment of the present invention.

[0052] Figure 5 This is a flowchart of circuit reliability analysis according to an embodiment of the present invention. Detailed Implementation

[0053] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0054] Therefore, a feature pointed out in this specification is used to describe one feature of one embodiment of the invention, and does not imply that every embodiment of the invention must have the described feature. Furthermore, it should be noted that this specification describes many features. Although certain features may be combined to illustrate possible system designs, these features may also be used in other combinations not explicitly stated. Therefore, unless otherwise stated, the described combinations are not intended to be limiting.

[0055] Transistor degradation is an inherent phenomenon. It begins to occur under specific stress conditions (e.g., under a certain voltage stress) throughout its lifespan, leading to changes in a series of transistor parameters. For example, a degradation in the transistor threshold voltage necessitates a larger reverse bias voltage to turn the transistor on, resulting in a decrease in the saturation current across the source and drain terminals. Since standard units in digital circuits are composed of a series of transistors connected in a specific manner, transistor degradation leads to a decline in the performance of these standard units, particularly affecting timing performance. However, extracting this fine-grained degradation information at the circuit level makes it difficult to guarantee accuracy. Therefore, the transistor degradation extraction method of this invention extracts degradation information from the signal level, which is the inventive point of this invention. The transistor degradation extraction method of this invention will be described in detail below.

[0056] like Figure 1 As shown, the reliability analysis of a circuit typically includes three main stages: establishing a degradation timing library, extracting and calculating degradation stress, and performing degradation timing analysis on the circuit.

[0057] A degradation timing library refers to a standard cell library that considers the degradation results of transistors under a series of degradation conditions, based on the existing digital design standard cell library. The timing information in the original digital design standard cell library is then updated accordingly to obtain a standard cell library that takes into account the effects of degradation. The degradation conditions include the power supply voltage, operating temperature, and degradation time within the circuit's lifespan. Other inputs required at this stage include a device reliability model and a cell netlist. The device reliability model refers to the mathematical model relationship describing the degradation behavior of transistors. The transistor threshold voltage offset is calculated based on the actual degradation condition parameters. The cell netlist is a SPICE design file describing the transistor connections and internal parasitic parameters within a standard cell, used for low-level SPICE simulation.

[0058] Degradation stress refers to the alternating nature of signals in digital circuits during actual operation, causing the electrical signals connected to internal transistors to also change abruptly. This abrupt signal change only leads to transistor degradation under specific conditions; therefore, it is necessary to characterize the time occupied by these degradation states to calculate the degradation results under arbitrary input excitation conditions in conjunction with a degradation model. Figure 2 For example, the two transition signals in the diagram cause transistor degradation. The purpose of this invention is to determine the duration of these transition signals. Other inputs required at this stage include circuit functional design and degradation stimuli. The circuit functional design refers to the design object requiring reliability analysis. Subsequently, through a synthesis and implementation process, all logic functions are mapped into combinations of standard cells and hard-core modules, connected by a series of physical connections. The degradation stimuli refer to the main-level input signal vectors during circuit operation. The circuit under these stimuli input conditions is considered to be degrading while operating, and the output results after logic simulation serve as the basis for subsequent degradation stress analysis.

[0059] The degradation timing analysis phase refers to the process of analyzing the circuit delays before and after degradation by comparing the circuit's delays under various degrees of degradation caused by a series of degradation stimuli. Other inputs required at this stage include a degradation cell library (i.e., a degradation timing library), circuit degradation results, and a synthesized netlist. The degradation cell library refers to a series of library files generated during the degradation timing library creation phase, representing different degradation scenarios, used to update the timing values ​​of the degraded circuit. The circuit degradation results refer to the overall degradation analysis results of the circuit under specific stimuli obtained during the degradation stress extraction and calculation phase, used to guide the mapping to the corresponding degradation timing library. The synthesized netlist refers to the circuit netlist obtained from synthesis mapping without considering degradation, used to remap cell types to the degraded timing library based on the degradation results.

[0060] The method for extracting the degradation results of transistors in the circuit design of this invention mainly occurs during the stage of extracting and calculating degradation stress.

[0061] The method for extracting the degradation results of transistors in the circuit design of the present invention mainly includes the following steps.

[0062] The netlist file of the standard cell in the selected standard cell library is parsed to obtain detailed information about the transistors of the standard cell; the detailed information about the transistors includes, but is not limited to: the transistor type of the standard cell, the connection relationship between the transistors, and all signals inside the standard cell.

[0063] Based on the detailed information of the transistor, the logical relationship of the signal of the standard cell and the relationship between the voltage levels of the three ports of the transistor and the transistor degradation are derived.

[0064] Based on the logical relationship of the signals in the standard unit and the relationship between the voltage levels of the three ports of the transistor and the transistor degradation, the degradation logic formula of each transistor is derived.

[0065] Solve to obtain the signal level combinations when the degenerate logic relation of all transistors is true;

[0066] Based on the input operating stimuli, the circuit design whose reliability needs to be verified is simulated to obtain statistical information of the signal;

[0067] The degradation time of each transistor is calculated based on the statistical information of the signal and the obtained combination of signal levels.

[0068] Substituting the transistor's degradation time into the reliability model yields the transistor's degradation results.

[0069] The degradation result referred to here specifically refers to the change in the values ​​of the corresponding parameters of the transistor before and after degradation. For example, if the threshold voltage of the transistor parameter is 'a' before degradation and 'b' after degradation, then 'ba' is the degradation result of the transistor or one of the degradation results of the transistor.

[0070] In the above technical solution, the logical relationship of the signals of the standard unit is obtained through the following steps.

[0071] All signals within the standard cell in the transistor details are treated as nodes, including power nodes, ground nodes, and intermediate signal nodes.

[0072] Transistors are converted into lines, and the nodes at the source and drain ends of the transistors are connected according to the transistor type and the connection relationship between the transistors to form an undirected loop graph.

[0073] Traverse all paths between intermediate signal nodes and power signal nodes in an undirected cyclic graph, and / or traverse all paths between intermediate signal nodes and ground nodes, while filtering out loop paths, to obtain the path relationships of intermediate signals and record the transistor information traversed by these paths.

[0074] The logical expression of the standard unit signal is obtained based on the path relationship of the intermediate signal.

[0075] like Figure 3 As shown, in one embodiment, a process for extracting all transistor degradation results in a circuit design under a given input operating stimulus is implemented, including the following steps.

[0076] Step 301: Obtain the netlist file corresponding to the standard cells of the selected standard cell library. Foundry provides a variety of standard cell libraries, and developers can select the appropriate standard cell library based on the specific functional design of the circuit.

[0077] Step 302: Parse the netlist file of the input standard cell. The parsing content mainly includes the transistor types described in the circuit netlist, the connection relationships between transistors, and all signals inside the standard cell.

[0078] Step 303: Based on the analytically obtained connection relationships between transistors and the correspondence between signals and transistor pins, signals are treated as nodes, including power and ground signals. Then, transistors are converted into lines, connecting the node pairs corresponding to the source and drain signals. Finally, the connection relationships and signal paths represented by the netlist file of the standard cell can be converted into an undirected cyclic graph. Since this invention is aimed at digital circuit design, which uses CMOS circuit cells, there are no analog circuit devices such as transistors; all transistors can be converted into lines.

[0079] Step 304: Based on the undirected cyclic graph obtained in step 303, a breadth-first search or other search method is used to traverse all paths between intermediate signal nodes and power or ground signal nodes, filtering out path loops to avoid their occurrence. Simultaneously, the transistor information traversed by these paths is recorded. For example, for PMOS transistors in the pull-up network of a cell, this involves searching for all paths between their source and drain signal nodes and the power node, while for the pull-down network, it involves finding all paths with the ground node. In one embodiment, the signal connection relationship of the standard cell can be first divided into pull-up and pull-down networks, and then traversed separately to obtain all paths corresponding to the signals in the pull-up network and the pull-down network. The pull-up network consists entirely of PMOS transistors, and the pull-down network consists entirely of NMOS transistors. Transistor information refers to the transistor numbers and signal names (defined in the standard cell SPICE netlist) traversed by these paths.

[0080] Step 305: Derive the logical expression corresponding to the signal based on the path connection relationship. That is, after traversing to obtain the path relationship of the intermediate signal, obtain the logical expression corresponding to the signal based on the path of the pull-up network and the pull-down network respectively. For example, the logical relationship corresponding to the pull-up network signal is to invert the gate signal of the transistor passed through the same path and then perform a logical AND, and perform a logical OR between different paths.

[0081] Step 306: Based on the signal logic relationships obtained through reasoning, and the gate / source / drain three-terminal level relationships of the transistors under degradation conditions, such as degradation occurring when the transistor is in reverse bias, further derive the degradation logic relationships for each transistor within the unit.

[0082] Assuming the source signal of a transistor is represented by S, the gate signal by G, and the drain signal by D, and the logical relationship is represented by BF, according to the transistor degradation relationship, taking PMOS as an example, degradation occurs when it is in reverse bias, and the corresponding logical relationship of transistor degradation is not(BF(G))and(BF(S)or BF(D)).

[0083] Step 307: After obtaining all the transistor degradation logic expressions, it is necessary to solve for the signal level combinations when these logic expressions are true, thus converting all the transistor degradation logic expressions into a binary decision graph.

[0084] Step 308: Based on the binary decision graph obtained from the transformation, solve for all possible combinations of input logic that satisfy a given logical Boolean expression.

[0085] Step 310 provides statistical information about the signal for calculating the degradation time. This involves simulating the circuit design whose reliability is to be verified using the input operating stimulus. This allows us to obtain the changes in signal high and low levels during the simulation time and the number of signal flips per unit time. Therefore, the signal statistical information mainly includes the probability of high and low signal levels during the simulation time and the number of flips per unit time. This invention primarily focuses on predictive evaluation, so it assumes that the circuit will receive the same operating stimulus as during the simulation time for the next 10 years of operation.

[0086] Step 309: Based on all the input logic combinations solved in step 308, and combined with the statistical information of the signals, enumerate and directly calculate the degradation time of each transistor.

[0087] After obtaining all input logic combinations, the probability results of these logic combinations can be calculated based on the high and low level probabilities of these input signals obtained in step 310. Then, these probabilities are added together to obtain the final probability value of degradation, which is multiplied by the degradation time (10 years by default in one embodiment) to obtain the degradation time of the transistor.

[0088] Step 311: After obtaining the degradation time result, the degradation amount is directly calculated by substituting it into the reliability model. The degradation result of the transistor includes the degradation value of the transistor parameters caused by the degradation effect, mainly the degradation of the threshold voltage (ΔVth).

[0089] The reliability analysis method for the circuit of the present invention includes the following steps.

[0090] At least one degraded timing library is pre-built based on a standard cell library. In a preferred embodiment, multiple degraded timing libraries can be built.

[0091] It analyzes the types of all standard cells in the standard cell library and the device models corresponding to the transistors inside the standard cells.

[0092] Different degradation amounts were selected under the same environmental conditions;

[0093] Based on different combinations of degradation conditions and device models, the degradation results of each standard cell under all combinations of degradation conditions corresponding to different degradation amounts are calculated. The degradation results are the timing changes of the standard cell corresponding to the degradation amount of the transistor.

[0094] Based on all degradation results corresponding to different degradation levels, the parameters of all standard units and device models corresponding to different degradation levels are back-inscribed to obtain the degradation units corresponding to different degradation levels.

[0095] Then, a characteristic simulation process is performed on all degenerate units corresponding to different degradation levels, and the temporal characteristic values ​​of the degenerate units are refreshed to obtain the degradation time series library corresponding to different degradation levels.

[0096] Figure 4 A flowchart illustrating an embodiment of pre-establishing a series of degradation time series libraries as input for degradation time series analysis is shown, specifically including the following steps.

[0097] Step 201: First, based on the selected process and the corresponding original standard cell library (undegraded), analyze the types of all standard cells in the original standard cell library and the device models corresponding to the transistors inside the standard cells.

[0098] Step 202: In this embodiment, taking circuit degradation over a 10-year operating period as an example, three different degradation rates of 10%, 50%, and 100% are selected under the same operating temperature and voltage. These three different degradation rates represent 10%, 50%, and 100% of the 10-year operating time being in a state of degradation, respectively. The corresponding combination of degradation conditions is selected, including the power supply voltage and operating temperature of the system in which the circuit operates, as well as the degradation time within its lifespan.

[0099] The combination of these degradation conditions is used to calculate the time-dependent degradation of each transistor within the cell.

[0100] Step 203: Based on the device model corresponding to the selected process and different combinations of degradation conditions, calculate the degradation results of the standard cell under each combination of degradation conditions for different degradation amounts.

[0101] Step 204: Because device degradation affects some parameters of standard cells and transistors, based on the transistor degradation results calculated in step 203, parameter back-annotation is performed on the device models of all the analyzed standard cells and corresponding transistors. This step completes the back-annotation of parameter offset values ​​under the selected degradation conditions to the device model and the cell netlist (the file containing transistor connection relationships). All standard cells are back-annotated once to obtain a degraded cell library corresponding to different degradation levels. That is, in this embodiment, there are three degraded cell libraries: one for 10% degradation, one for 50% degradation, and one for 100% degradation. Each degraded cell library has the same format as the original standard cell library; the difference is that the degraded cells in the library update the timing information of the standard cells to reflect the degradation of transistor parameters (i.e., the values ​​change).

[0102] Step 205 involves performing a characterization simulation process on the degraded cell library obtained after degradation back-annotation. While maintaining the library format, the timing characteristic values ​​of the degraded cells are refreshed. This step maps the impact of device degradation to its effect on the cell timing level and characterizes it in a standard format. After this step, three different degradation levels corresponding to the degradation timing libraries are obtained.

[0103] Step 206: Since multiple characterization operations are required for units with the same function and structure (one for 10% degradation, one for 50% degradation, and one for 100% degradation), subsequent circuit synthesis mapping and static timing analysis will require differentiation based on unit type. Therefore, the naming rules for the degraded units in the three degradation timing libraries need to be expanded for easier distinction. This is to differentiate the obtained degradation timing libraries from the timing libraries provided by the vendor.

[0104] The present invention obtains the degradation timing analysis results based on the degradation timing library and the standard cell netlist file of the transistors and the synthesized circuit netlist, including the following steps.

[0105] Based on the degradation results of the transistors in the synthesized circuit netlist, the cell types of the standard cells in the synthesized circuit netlist are remapped to degraded cell types that take into account the degradation effects; this mapping can be understood as selection.

[0106] Update the information in the synthesized circuit netlist, that is, reselect the cell type of the standard cells in the circuit to the degenerate cell type, i.e., the type of degenerate cells.

[0107] Back-annotate the synthesized circuit netlist, select all used degraded timing libraries, and import them into the reverse static timing analysis tool;

[0108] Extract the degradation critical path from the static time series analysis report output by the static time series analysis tool;

[0109] Analyze the overall impact of degradation on the circuit.

[0110] like Figure 5 As shown, circuit degradation timing analysis based on a degradation timing library includes the following steps:

[0111] Step 401: After the original circuit functional design (i.e. the circuit design whose reliability is to be verified) is implemented by logic synthesis, a circuit netlist without degradation information is obtained and used as the object of reliability analysis.

[0112] Step 402: Traverse the standard cells of the circuit design whose reliability needs to be verified, and extract the transistor degradation results of the synthesized circuit netlist corresponding to the standard cell using the transistor degradation result extraction method of the circuit design described above.

[0113] Step 403: Based on the degradation results of each standard cell, remap the cell type of the standard cell to the type of the degradation cell that takes into account the degradation effect. The selection criteria are to choose the degradation time series library with the closest degradation conditions and the type of the corresponding degradation cell in the degradation time series library from a series of pre-prepared degradation time series libraries.

[0114] Step 404: After remapping the cell types in the netlist, update the circuit netlist information as input for subsequent static timing analysis.

[0115] Step 405: After completing the degenerate cell type back-annotation for the entire circuit, select all the degenerate cell libraries used and import them into the static timing analysis tool.

[0116] Step 406: Based on the input degraded back-annotation netlist and degraded cell library, perform static timing analysis on the entire circuit considering degradation information.

[0117] Step 407: Extract the critical degradation path based on the static time series analysis report.

[0118] Step 408: Finally, analyze the overall impact of degradation on the circuit.

[0119] This invention addresses this problem from a logical topology level by combining the structural logic characteristics of circuit units, ensuring rapid analysis of circuit degradation while maintaining accuracy close to transistor-level simulation. This invention solves the problem of circuit-level degradation stress extraction at the logical level and, combined with a degradation-aware unit characterization process, enables rapid and accurate reliability assessment of large-scale circuits.

[0120] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for extracting the degradation results of transistors in a circuit design, characterized in that, include: The netlist file of the standard cells in the selected standard cell library is parsed to obtain detailed information about the transistors of the standard cells; Based on the detailed information of the transistor, the logical relationship of the signal of the standard unit and the relationship between the level of the three ports of the transistor and the transistor degradation are derived. Based on the logical relationship of the signals of the standard unit and the relationship between the voltage levels of the three ports of the transistor and the transistor degradation, the degradation logic formula of each transistor is derived. Solve to obtain the signal level combinations when the degenerate logic relation of all transistors is true; Based on the input operating stimuli, the circuit design whose reliability needs to be verified is simulated to obtain statistical information of the signal; The degradation time of each transistor is calculated based on the statistical information of the signal and the obtained combination of signal levels. Substituting the transistor's degradation time into the reliability model yields the transistor's degradation results; The logical relationship of the signals of the standard unit is derived based on the detailed information of the transistor, including: Treat all signals within the standard unit as nodes; Transistors are converted into lines, and the nodes at the source and drain ends of the transistors are connected according to the transistor type and the connection relationship between the transistors to form an undirected loop graph. Traverse all paths between intermediate signal nodes and power nodes in the undirected cyclic graph, and / or traverse all paths between intermediate signal nodes and ground nodes, while filtering out loop paths, to obtain the path relationships of intermediate signals. The logical expression of the signal of the standard unit is obtained based on the path relationship of the intermediate signal.

2. The method for extracting the degradation results of transistors in the circuit design as described in claim 1, characterized in that, The detailed information about the transistors includes: the transistor type of the standard unit, the connection relationships between the transistors, and all signals within the standard unit.

3. The method for extracting the degradation results of transistors in the circuit design as described in claim 2, characterized in that, The nodes include power nodes, ground nodes, and intermediate signal nodes.

4. The method for extracting the degradation results of transistors in the circuit design as described in claim 3, characterized in that, When traversing the undirected cyclic graph, the connection relationship between the transistors is divided into pull-up networks and pull-down networks. The pull-up networks and pull-down networks are traversed respectively to obtain the path relationship of the intermediate signal.

5. The method for extracting the degradation results of transistors in the circuit design as described in claim 1, characterized in that, The steps to determine the signal level combinations when the degenerate logic relation for all transistors is true include: Convert the degradation logic of all transistors into a binary decision graph; Solve the binary decision graph to find all signal level combinations that satisfy a given Boolean expression as true.

6. The method for extracting the degradation results of transistors in the circuit design as described in claim 1, characterized in that, The statistical information of the signal includes the probability of high and low levels of the signal waveform during the simulation time and the number of flips per unit time for the circuit design whose reliability is to be verified.

7. A reliability analysis method for circuit design, characterized in that, include: At least one degenerate timing library is pre-built based on the standard cell library; The circuit design whose reliability needs to be verified is logic synthesized to obtain a synthesized circuit netlist that does not include degradation information; Traverse the standard cells of the circuit design whose reliability is to be verified, and extract the transistor degradation results of the synthesized circuit netlist corresponding to the standard cells using the transistor degradation result extraction method of the circuit design as described in any one of claims 1 to 6. Based on the degradation timing library and the standard cell netlist file, the degradation results of the transistors and the synthesized circuit netlist are used to obtain the degradation timing analysis results of the circuit functional design.

8. The reliability analysis method for circuit design as described in claim 7, characterized in that, At least one degenerate time series library should be built based on the standard cell library, including: It analyzes the types of all standard cells in the standard cell library and the device models corresponding to the transistors inside the standard cells. Different degradation amounts were selected under the same environmental conditions; Based on different combinations of degradation conditions and the device model, the degradation results of each standard cell under all combinations of degradation conditions corresponding to different degradation amounts are calculated. The degradation results are the timing changes of the standard cell corresponding to the degradation amount of the transistor. Based on all degradation results corresponding to different degradation levels, the parameters of all standard units and device models corresponding to different degradation levels are back-inscribed to obtain the degradation units corresponding to different degradation levels. Then, a characteristic simulation process is performed on all degradation units corresponding to different degradation levels, and the temporal characteristic values ​​of the degradation units are refreshed to obtain degradation time series libraries corresponding to different degradation levels.

9. The reliability analysis method for circuit design as described in claim 8, characterized in that, The degradation conditions include at least one of the following: the power supply voltage of the system in which the circuit operates, the operating temperature, and the degradation time during its life cycle.

10. The reliability analysis method for circuit design as described in claim 7, characterized in that, Based on the degradation timing library and the standard cell netlist file, the degradation results of the transistors and the synthesized circuit netlist are used to obtain the degradation timing analysis results, which include the following steps: Based on the degradation results of the transistors in the synthesized circuit netlist, the cell types of the standard cells in the synthesized circuit netlist are remapped to the degradation cell types that take into account the degradation effects. Update the information in the synthesized circuit netlist; Back-annotate the synthesized circuit netlist, select all used degraded timing libraries, and import them into the reverse static timing analysis tool; Extract the degradation critical path from the static time series analysis report output by the static time series analysis tool; Analyze the overall impact of degradation on the circuit.

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