Signal generator circuit, corresponding equipment and methods

Abstract

This disclosure relates to a signal generator circuit, corresponding apparatus, and method. During startup, current is supplied by a current source to the first plate of a first capacitor, while the second capacitor remains at zero charge. In a subsequent first operating phase, current is supplied to the first plate of the second capacitor, and the second plate of the first capacitor is connected to the first plate. At the end of the first operating phase, the first capacitor is discharged. In a subsequent second operating phase, current is supplied to the first plate of the first capacitor, and the second plate of the second capacitor is connected to the first plate. At the end of the second operating phase, the second capacitor is discharged. Steady-state operation of the circuit involves alternation between the first and second operating phases, which are interleaved with the transition phases during the discharge of the first and second capacitors.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Italian Patent Application No. 102021000027083, filed on October 21, 2021, the contents of which are incorporated herein by reference in their entirety to the fullest extent permitted by law. Technical Field

[0003] This specification relates to circuits for generating signals such as clock and ramp signals.

[0004] One or more embodiments can be advantageously applied, for example, in power management integrated circuit (PMIC) DC-DC converters. Active matrix organic light-emitting diode (AMOLED) display devices are examples of devices in which embodiments as discussed herein can be advantageously applied. Background Technology

[0005] Problems that may arise in circuits such as converter circuits involve generating two ramp signals (and their synchronization clock) that are offset by half a cycle in time.

[0006] Current methods for this purpose include using a first master oscillator operating at dual frequencies and two separate slave ramp generators.

[0007] The circuit topology involving three oscillators has high requirements for area and power.

[0008] The above-mentioned problems need to be addressed in this field. Summary of the Invention

[0009] One or more embodiments relate to a circuit.

[0010] One or more embodiments relate to corresponding devices. A DC-DC converter used in an AMOLED display unit may be an example of such a device.

[0011] One or more embodiments relate to methods of the corresponding operations.

[0012] One or more embodiments provide a self-sustaining structure that generates two ramps from a single current.

[0013] In one or more embodiments, a first capacitor (which is not charged when on) is connected to a current source at the start-up phase (phase 0), while a second capacitor is kept at zero charge. In this case, the signal at the first node rises linearly, while the signal at the second node remains at zero.

[0014] In the subsequent phase (phase 1), the first capacitor is disconnected from the source (and is caused to store a voltage a (e.g., 300mV) across its terminals) while the second capacitor is connected to the current source. The base plate of the first capacitor is connected to the second node while the top plate remains floating. The second node rises (e.g., from 0 to 300mV) while the first node completes its swing (e.g., from 300mV to 600mV), which is offset from the second signal held at T / 2.

[0015] In another phase (phase 2, after the first capacitor has discharged), the second capacitor is disconnected from the source (and is caused to store a voltage (e.g., 300mV) on its terminals), and the first capacitor is recharged via the current source, while the base plate of the second capacitor is connected to the first node and the upper plate floats, thus facilitating a reflection of the situation during the earlier phase.

[0016] Then, the operation returns (advantageously, after the second capacitor has been discharged) to phase 1, causing an alternation of two phases (phase 1, phase 2, during which the capacitor is discharged).

[0017] One or more embodiments provide a dual-phase architecture suitable for integration into a converter, wherein there is a fixed time shift between the two phases.

[0018] One or more embodiments may include a single block that drives multiple clocks and ramps.

[0019] As described above, the examples given in this paper include two (additional) transition phases introduced between the two phases (phase 1, phase 2) discussed earlier, in order to adequately reset the capacitor in a controlled manner. This helps to generate a clock signal with a fixed duty cycle (which is adjustable to change the threshold), for example, in a DC-DC converter where a fixed maximum "on" period is used for high-side switching. Attached Figure Description

[0020] One or more embodiments will now be described by way of example only with reference to the accompanying drawings, in which:

[0021] Figure 1A and 1B These are examples of the possible temporal behavior of clock and ramp signals;

[0022] Figure 2 It is used to generate such Figure 1A and 1B The block diagram of the circuit for the clock and ramp signals is shown.

[0023] Figure 3 This is a general representation of the generation of ramp signals;

[0024] Figure 4These are examples of the phases of operation of a circuit according to embodiments of this specification;

[0025] Figure 5 Included Figure 4 Two example diagrams illustrating the possible temporal behavior of the signal generated in the phase of the operation shown;

[0026] Figure 6 This is an example of another operating phase of a circuit according to an embodiment of this specification;

[0027] Figure 7 Included Figure 6 Two example diagrams illustrating the possible temporal behavior of the signal generated in the phase of the operation are shown in the figure.

[0028] Figure 8 This is an example of another operational phase of the circuit according to an embodiment of this specification;

[0029] Figure 9 Included Figure 8 Two example diagrams illustrating the possible temporal behavior of the signal generated in the phase of the operation shown;

[0030] Figure 10 These are examples of possible phases of operation of a circuit according to embodiments of this specification;

[0031] Figure 11A and 11B Included Figure 10 Two example diagrams illustrating the possible temporal behavior of the signal generated in the phase of the operation shown; and

[0032] Figure 12 It is a block diagram of a device including circuitry according to embodiments of this specification. Detailed Implementation

[0033] Unless otherwise specified, corresponding numbers and symbols in different figures usually refer to the corresponding parts.

[0034] The accompanying drawings are provided to clearly illustrate relevant aspects of the embodiments and are not necessarily drawn to scale.

[0035] The edges of features drawn in the accompanying drawings do not necessarily indicate the end of the feature range.

[0036] In the following description, various specific details are shown to provide a thorough understanding of various examples of embodiments according to the description. Embodiments may be obtained without one or more specific details, or by utilizing other methods, components, materials, etc. In other cases, known structures, materials, or operations are not shown or described in detail so that various aspects of the embodiments are not obscured.

[0037] References to "embodiment" or "an embodiment" within the framework of this specification are intended to indicate that a particular configuration, structure, or feature described with respect to that embodiment is included in at least one embodiment. Therefore, phrases such as "in an embodiment," "in one embodiment," etc., that may appear at various points in this specification do not necessarily refer precisely to the same embodiment. Furthermore, specific configurations, structures, or features may be combined in any suitable manner in one or more embodiments.

[0038] The titles / references used herein are provided for convenience only and are not intended to limit the scope of protection or the scope of the embodiments.

[0039] Similarly, for simplicity and ease of explanation, the same reference symbols / markers (e.g., R1, R2) may be used throughout the specification to denote both a circuit node or line and the signal that appears at that node or line.

[0040] Two-phase peak current DC-DC converters are widely used in existing technology applications, such as power management integrated circuit (PMIC) DC-DC converters in AMOLED products.

[0041] This converter can include two different coils operating in parallel; this is advantageous for delivering very high average current.

[0042] Peak current DC-DC converters include a synchronous clock, a finite state machine, and a voltage ramp signal to ensure loop stability. Therefore, two clocks and two ramps offset by half a cycle in time are generated in both phase converters to minimize voltage ripple at the converter output.

[0043] Figure 1A and 1B The figure is an example of possible time behavior, plotted against the common (horizontal axis) time scale t relative to the two such ramp signals R1, R2 and the two corresponding clock signals CLK1, CLK2.

[0044] The generation of ramp and clock signals is expected to exhibit the following characteristics: the two ramps R1 and R2 have the same frequency; the two clocks have the same duty cycle; and the clock frequency is adjustable.

[0045] Controllability of the clock signal's duty cycle is another desirable feature, as it helps, for example, limit the maximum TON value of the associated converter.

[0046] Think back to things like Figure 1BThe square (rectangular) waves of the clock signals CLK1 and CLK2 can be considered pulse width modulation (PWM) signals, which alternate between an "on" time (signal high) of duration TON and an "off" time (signal low) of duration TOFF. The sum TON+TOFF indicates the period of the signal with a frequency of 1 / (TON+TOFF), and the ratio TON / (TON+TOFF) indicates the duty cycle of the signal.

[0047] Signal generation can be highly area- and power-intensive, leading to reduced efficiency and higher manufacturing costs.

[0048] For example, Figure 2 A circuit is shown in which two (out-of-phase) clocks CLK1, CLK2 and two corresponding ramps R1, R2 are generated by a “master” oscillator MO that provides, for example, a square wave of 3 MHz.

[0049] Two clock signals CLK1 and CLK2, for example, 1.5 MHz, are obtained from the square wave. The oscillator MO therefore operates at twice the frequency of the signals CLK1 and CLK2 that may be supplied to the converter (not visible in the figure).

[0050] The ramp generators RG1 and RG2 generate the corresponding ramp signals R1 and R2 from the clock signals CLK1 and CLK2.

[0051] like Figure 3 As shown, each ramp generator RGj (j = 1, 2) may include a current generator CGj that is coupled to a power line or node Vs and injects its current into a parallel connection of a switch Sj (e.g., this may be a MOSFET transistor configured to be turned on / off by a signal CLKj applied to its gate) and a capacitor Cj.

[0052] For example, the duty cycles of clock signals CLK1 and CLK2 are adjusted to, for example, 10%, and when clock signal CLKj is low (where the switch is not turned on) and its voltage is reinitialized to GND, clock signal CLKj (j=1, 2) is used as a current seed injected into capacitor Cj.

[0053] Note that in Figure 2 In the circuit shown, mismatch and process variations can result in two ramps R1 and R2 that do not guarantee the same final voltage value. An automatic fine-tuning process can address this issue, which may include implementing two comparators for each ramp.

[0054] like Figure 2The circuit shown thus exhibits various drawbacks, such as: high power consumption when three different current “seeds” are involved in generating the oscillator and the two ramps respectively; and high area footprint due to the implementation of the master clock MO and four auto-trimming comparators and related logic.

[0055] Power and area specifications for devices such as PMICs are becoming increasingly stringent. Therefore, new solutions are needed that facilitate efficient chip design without compromising performance.

[0056] This article is from Figure 4 The example presented at the beginning addresses the problems discussed above by replacing the existing circuit with an "all-in-one" circuit 10 that provides improved silicon area and bias current (e.g., efficiency) characteristics. Figure 2 The three-part architecture described in the document.

[0057] It should be noted that, unless otherwise specified, corresponding numbers and symbols in different figures generally refer to corresponding parts. For the sake of brevity, detailed descriptions will not be repeated for each figure; similarly, parts or elements similar to those already described in conjunction with Figures 1, 1B, 2, and 3 will be... Figure 4 The same numbers and symbols are used as indicated in the following figures, and the corresponding detailed descriptions will not be repeated. Furthermore, the same reference symbols / markers (e.g., R1, R2) may be used throughout the specification to designate both circuit nodes or lines and the signals present at those nodes or lines.

[0058] Although they may appear similar at first glance, the circuits in the examples presented in this article differ from charge pumps in many fundamental ways: the capacitors in a charge pump are charged at a certain voltage, rather than through a current generator; and the signal in a charge pump is a square wave between voltage VIN and voltage 2*VIN, rather than a linear voltage ramp.

[0059] In fact, the purpose of a charge pump is to double the voltage (or more generally to produce a higher voltage rail) without generating a clock and a ramp.

[0060] In short, such as Figure 4 The circuit 10 shown includes a current generator CG of a (constant) current of intensity I (of a type known to those skilled in the art), which is coupled to a power node of voltage Vs and configured to inject its current (at a current node denoted as A) into a parallel connection of two circuit branches 11 and 12 arranged between node A and ground GND.

[0061] Circuit branch 11 includes a first switch M1 between node A and the first output node R1, where a first output (ramp) signal is collected at the first output node R1. Circuit branch 12 includes a second switch M2 between node A and the second output node R2, where a second output (ramp) signal is collected at the second output node R2. Circuit branch 11 further includes a first capacitor C1 having a first ("top") plate coupled to the output node R1 (i.e., coupled to the first switch M1) and a second ("bottom") plate coupled to a third switch M3 connected to a reference ground GND, such that when the third switch M3 is closed, it couples the bottom plate of the first capacitor C1 to ground GND. Circuit branch 12 further includes a second capacitor C2 (which can be assumed to have the same capacitance value as capacitor C1), the second capacitor C2 having a first ("top") plate coupled to the output node R2 (i.e., coupled to the second switch M2) and a second ("bottom") plate coupled to a fourth switch M4 connected to a reference ground GND, such that when the fourth switch M4 is closed, it couples the bottom plate of the second capacitor C2 to ground GND. Circuit branch 11 also includes a fifth switch M5 between node A and the line coupling the first capacitor C1 and the third switch M3. Circuit branch 12 also includes a sixth switch M6 between node A and the line coupling the second capacitor C2 and the fourth switch M4. Circuit branch 11 further includes a seventh switch M7 between the first output node R1 and ground GND. Circuit branch 12 further includes eight switches M8 between the second output node R2 and ground GND.

[0062] Switches M1 to M8 can be implemented as electronic switches, such as, for example, using MOSFET transistors, which can alternately conduct (closed or "on") and deconduct (open or "off") according to the function of a control signal applied to the control terminal of the switch (gate in the case of a MOSFET transistor) (e.g., high >>> conduct, low >>> deconduct). Other possible implementations of (electronic) switches M1 to M8 are known to those skilled in the art.

[0063] The operation (i.e., turning switches M1 to M8 on ("on") or off ("off") is controlled by a control circuit device 14, which includes a comparator and control logic, and is sensitive to the ramp signals R1 and R2 at the same output node.

[0064] Circuit 14 is configured (in a manner known to those skilled in the art) to turn switches M1 to M8 on / off according to the criteria illustrated below.

[0065] In the starting phase (specified as phase 0 and) Figure 4As shown in the diagram: This is the start-up phase that occurs only when circuit 10 is turned on. In this phase, capacitor C2 (as illustrated herein, capacitors C1 and C2 have the same capacitance, and for simplicity, C1 = C2) is held at zero by switches M4 and M8 (both are on), and it is assumed that capacitor C1, which has no charge on it when the circuit is turned on, is charged by constant current generator CG to a voltage of, for example, 300mV (this is, of course, a purely exemplary value).

[0066] Regarding the corresponding time behavior of ramp signals R1 and R2 Figure 5 The signals are shown in the graphs (signal R1 in the upper graph and signal R2 in the lower graph), which share a common horizontal time scale t.

[0067] The voltage at node R1 therefore rises linearly with a slope proportional to I / C1 (where I represents the current intensity from generator CG and C1 is the capacitance of the first capacitor), while node R2 remains zero.

[0068] In response to the first ramp signal R1 reaching a first (“semi-dynamic”) threshold (e.g., 300mV), the comparator circuit device 14 is triggered, and the system progresses to the next operating phase.

[0069] In this phase (designated as phase 1 and in Figure 6 (As shown in the diagram), the first capacitor C1 is decoupled from the current path (both switches M1 and M3 are disconnected by circuit 14, i.e., not conducting), and in response to switches M2 and M4 being turned on (closed) by circuit device 14, the second capacitor C2 is coupled to the current source CG. The base plate of the first capacitor C1 is connected to the second output node R2 (turned on via switches M2 and M5), while the upper plate of the first capacitor C1 coupled to the first output node R1 remains floating.

[0070] Under these conditions, with no available discharge path, the first capacitor C1 will retain the previously charged voltage (e.g., 300mV) stored at its terminals.

[0071] During phase 1, the voltage at the second output node R2 will rise linearly from zero with a slope proportional to I / C1 = I / C2 (where I is the current intensity from the generator CG, and C1 = C2 are the capacitance values ​​of capacitors C1 and C2), and the voltage at the first output node R1 will increase from its previous value (e.g., 300mV) with the same slope as signal R2.

[0072] Regarding the corresponding time behavior of ramp signals R1 and R2 Figure 7 The signals are shown in the graphs (signal R1 in the upper graph and signal R2 in the lower graph), which share a common horizontal time scale t.

[0073] In response to the first ramp signal R1 reaching the second (“full dynamic”) threshold (e.g., 600mV), the comparator circuit device 14 is triggered again and the system progresses to the next operating phase.

[0074] As shown in the figure, this involves the first capacitor C1 being (completely) discharged, while switches M3 and M7 are turned on (closed) for a short period of time, during which the circuit progresses to another operating phase.

[0075] In this phase (in Figure 8 The phase shown is phase 2, and this phase can be considered relative to... Figure 6 (In phase 1 symmetry), the second capacitor C2 is decoupled from the current path (switches M2 and M4 are open, i.e., not conducting), and the first capacitor C1 (previously discharged via switches M3 and M7) is recoupled to the current source CG in response to the closing (conducting) of switches M1 and M3.

[0076] Then, the bottom plate of the second capacitor C2 is coupled to the first output node R1 (through the conduction of switches M1 and M6, i.e., closed), while the top plate of the second capacitor C2 (coupled to the second output node R2) remains floating.

[0077] In this phase, the voltage at the first output node R1 will rise linearly from zero with a slope proportional to I / C1 = I / C2, where I is the current intensity from the generator CG and C1 = C2 are the capacitance values ​​of capacitors C1 and C2, while the voltage at the second output node R2 will also rise from its previous value (e.g., 300mV) with the same slope as the first output signal R1.

[0078] The corresponding time characteristics of ramp signals R1 and R2 are again discussed in... Figure 9 The signals are shown in the graphs (signal R1 in the upper graph and signal R2 in the lower graph), which share a common horizontal time scale t.

[0079] In response to the second ramp signal R2 reaching the (second) threshold (which can be assumed to be the second "full dynamic" value, e.g., 600mV), the comparator circuit device 14 is triggered again to close (i.e., turn on) switches M4 and M8 for a short time, causing capacitor C2 to discharge (fully) and the circuit to advance to PHASE1 again. Figure 6 ).

[0080] As mentioned above, Figure 4 Phase 0 shown is the startup phase that occurs only when the circuit is turned on.

[0081] In a steady state, the circuit will cycle between phase 1 and phase 2 (with interleaving transitions T1 and T2), such as Figure 10 As shown in the "cycle" diagram.

[0082] In short, the circuit 10 shown is an example of a circuit that includes a power node Vs, a (constant) current generator CG between the power node Vs and the current node A, and a first circuit branch 11 and a second circuit branch 12 arranged in parallel between the current node A and ground GND.

[0083] As shown in the figure, the first circuit branch 11 includes a first output node R1 and a first capacitor C1 having a first ("top") plate and a second ("bottom") plate, and the second circuit branch 12 includes a second output node R2 and a second capacitor C2 having a first ("top") plate and a second ("bottom") plate. The first plate of the first capacitor C1 is coupled to the first output node R1 and the first plate of the second capacitor C2 is coupled to the second output node R2.

[0084] As shown in the figure, the first circuit branch 11 includes a first set of switches, such as switches M1, M3 and M5, which are configured to alternately turn on and off to couple and decouple the first (top) plate of the first capacitor C1 relative to the current node A (switch M1), and to couple and decouple the first capacitor C1 relative to the current node A (switch M5) and relative to ground GND (switch M3) to the second (bottom) plate of the first capacitor C1.

[0085] Furthermore, the second circuit branch 12 includes a second set of switches, such as switches M2, M4, and M6, which are configured to alternately turn on and off to couple and decouple the first (top) plate of the second capacitor C2 relative to current node A (switch M2), and to couple and decouple the second (bottom) plate of the second capacitor C2 relative to current node A (switch M6) and relative to ground GND (switch M4).

[0086] As shown in the figure, the switches in the first group of switches (i.e., M1, M3, M5) and the second group of switches (i.e., M2, M4, M6) are selectively switchable to:

[0087] Startup Configuration ( Figure 4 and 5 Phase 0), wherein the first plate and the second plate of the first capacitor C1 are coupled to the current node A and ground GND respectively, and the first plate and the second plate of the second capacitor C2 are decoupled from the current node A (and connected to ground GND).

[0088] First operation configuration ( Figure 6 and 7Phase 1), wherein the first plate of the first capacitor C1 is decoupled from the current node A, and the second plate of the first capacitor C1 is decoupled from ground GND and coupled to the second output node R2 via the current node A, and the first plate and the second plate of the second capacitor C2 are coupled to the current node A and ground GND respectively; and

[0089] Second operation configuration ( Figure 8 and 9 Phase 2), wherein the first plate and the second plate of the first capacitor C1 are coupled to the current node A and the ground GND respectively, the first plate of the second capacitor C2 is decoupled from the current node A, and the second plate of the second capacitor C2 is decoupled from the ground GND and coupled to the first output node R1 via the current node A.

[0090] As shown in the figure, circuit 10 includes a control circuit device 14, which is coupled to a first set of switches (i.e., M1, M3, M5) in a first circuit branch 11 and a second set of switches (i.e., M2, M4, M6) in a second circuit branch 12, and is configured to switch the first set of switches M1, M3, M5 in the first circuit branch 11 and the second set of switches M2, M4, M6 in the second circuit branch 12. Figure 4 and 5 In the startup configuration, during the startup phase (phase 0) when the circuit is turned on; and alternatively, during Figure 6 and 7 In the first operation configuration and in Figure 8 and 9 In the second operating configuration, after the start phase (phase 0), there is an alternation between the first operating phase and the second operating phase (i.e., phase 1, phase 2, with the transitions described below).

[0091] As shown in the figure, the control circuit device includes a comparator circuit device 14 coupled to the first output node and the second output nodes R1 and R2. Thus, the comparator circuit device 14 is sensitive to the voltage at the first output node and the second output nodes R1 and R2.

[0092] As shown in the figure, the comparator circuit device 14 has a first threshold (e.g., 300mV) and a second threshold (e.g., 600mV), with the first threshold located between zero and the second threshold.

[0093] As shown in the figure, the comparator circuit device 14 is configured to switch the first set of switches M1, M3, M5 in the first circuit branch 11 and the second set of switches M2, M4, M6 in the second circuit branch (12):

[0094] In response to the voltage at the first output node R1 changing from zero to a first threshold, from the startup configuration ( Figure 4 and 5Phase 0) to the first operation configuration ( Figure 6 and 7 Phase 1);

[0095] In response to the voltage at the first output node R1 changing from a first threshold to a second threshold, from the first operating configuration ( Figure 6 and 7 Phase 1) to the second operation configuration ( Figure 8 and 9 Phase 2); and

[0096] In response to the voltage at the second output node R2 changing from the first threshold to the second threshold, from the second operating configuration ( Figure 8 and 9 Phase 2) Return to the first operation configuration ( Figure 6 and 7 Phase 1).

[0097] In the circuit 10 shown, the ramp signals R1 and R2 will have the same period T, which is proportional to the "full dynamic" voltage (e.g., 600mV) multiplied by the ratio C / I (where I is the current intensity from the generator CG, and C is the capacitance values ​​of capacitors C1 and C2, C1 = C2). CK And will be shifted by half a period T CK / 2.

[0098] In the example considered in this paper, the frequency is 1 / T CK Therefore, it can be set, for example, via a dedicated fine-tuning of the bias current I and / or by adjusting the capacitance of capacitors C1, C2 (e.g., digitally), which can be performed in a manner known to those skilled in the art.

[0099] The circuit described above can be used in a DC-DC converter to generate, in addition to two (compensated) ramps such as ramp signals R1 and R2, clock signals corresponding to the two phases (e.g., see CLK1 and CLK2 in Figure 1).

[0100] A clock can be directly generated in response to ramp signals R1 and R2 reaching their final values ​​(i.e., the limit threshold, such as 600mV). This facilitates achieving the desired final value without the need for dedicated autotrimming.

[0101] For example, in a buck-boost converter, the on-time of (multiple) clock signals plays a role in limiting the maximum "on" time of the high-side switch.

[0102] For this effect, the lower threshold in the comparator circuit device 14) can be shifted, for example, from the previously indicated "semi-dynamic" value (e.g., 300mV) to 360mV (still for example), in order to facilitate a 10% duty cycle for (multiple) clock signals. Thus, the duty cycle can be selected to modify the lower threshold accordingly.

[0103] For example, circuit device 14 can be configured to "rise" one of clock signals CLK1 and CLK2 in response to the rising edge of the corresponding ramp signal R1resp.R2 reaching a "full dynamic" threshold (e.g., 600mV), and to "fall" one of the clock signals CLK1 and CLK2 in response to the falling edge of the other ramp signal R2vsR1 reaching a "half dynamic" threshold (e.g., 360mV).

[0104] The corresponding ramp can be held at 0 until the clock signal goes low. This operation can be implemented symmetrically for another ramp / clock pair.

[0105] To achieve this effect, as previously described, two additional intermediate transition phases T1 and T2 are introduced between phase 1 and phase 2, such as... Figure 10 As shown (phase 1>>T1>>phase 2 and phase 2>>T2>>phase 1).

[0106] During the transition phase T1, for example, the first capacitor C1 is discharged (completely) by the short-term closing (conduction) of switches M3 and M7, such that both plates of capacitor C1 are coupled to ground GND.

[0107] During the transition phase T2, for example, the second capacitor C2 is (completely) discharged, while switches M4 and M8 are closed (i.e., turned on) for a short time, so that both plates of capacitor C2 are coupled to ground GND.

[0108] These transition phases are beneficial for properly resetting capacitors C1 and C2.

[0109] Figure 11A and 11B The diagram illustrates possible temporal behavior, plotted against a common (horizontal) time scale relative to the two ramp signals R1, R2 and the two corresponding clock signals CLK1, CLK2 generated in a circuit as illustrated in this article. The startup phase (PHASE0) is... Figure 11B The left side of the image is identifiable.

[0110] The embodiments presented herein offer many advantages.

[0111] As described above, the two phase converters include two clocks and two ramps that are shifted by half a cycle in time to minimize voltage ripple at the converter output. Traditional solutions are high in power and area because they may require three different current seeds and auto-trimming structures.

[0112] The examples presented in this article help to integrate the generation of two ramps and a clock into a single, independent structure.

[0113] The first advantage of the example presented in this article is the reduced footprint: no "master" clock is implemented to time the two ramp generators. Furthermore, by designing to ensure the final ramp voltage value, the associated costs of an auto-trimming structure in terms of footprint, current consumption, and design effort are avoided.

[0114] Another advantage is reduced power consumption, because the switching activity and interconnection between the two capacitors C1 and C2 facilitate the generation of two ramps using a single current seed. Power consumption is correspondingly reduced.

[0115] As mentioned above, automatic trimming becomes unnecessary: ​​the clock is directly generated by the ramp that reaches its final value, thus ensuring the correct final value without dedicated automatic fine-tuning.

[0116] The reduced area results in fewer comparators (e.g., lower bias and lower area).

[0117] The ease of tunability allows for easy fine-tuning of the structure (duty cycle and frequency) by simply changing the lower comparator threshold and current seed (and / or capacitor C1 = C2).

[0118] Figure 12 This is an example of a possible use of circuit 10, which is illustrated herein as a dual clock and ramp generator suitable for use as a power management IC (PMIC) 1000, for example, for power supply of an AMOLED device AD.

[0119] It should also be noted that the circuit 10 described herein can be used in various multi-phase (e.g., two-phase) DC-DC regulator topologies that benefit from the availability of fine shift (compensation) ramps and clocks.

[0120] In addition to circuit 10 Figure 12 The architecture shown is conventional in the field: this makes it unnecessary to provide a more detailed description in this paper.

[0121] The following specifications apply to Figure 12 The block shown is in the power management IC (PMIC).

[0122] Vin: Power supply pin

[0123] 100: Finite state machine (FSM) with enable and test inputs EN and TEST to control a DC-DC converter.

[0124] 101A, 101B: Discontinuous Mode Detectors (Zero Current Comparators) DMD-A and DMD-B

[0125] 102A, 102B: SKIP comparators A and B

[0126] 103: Overcurrent protection OCP and associated pins

[0127] 104: Oscillation Elimination

[0128] 105A, 105B: High-side (HS) and low-side (LS) drivers

[0129] 106: Dual-phase manager with clock and ramp inputs from circuit 10

[0130] 107A, 107B: Main comparators A and B

[0131] 108:HS Current Sensing A / B

[0132] 109: Error amplifier with reference pin REF

[0133] 110: Feedback (FB) distributor with VOUT sensing pin.

[0134] Furthermore, it should be understood that the switch groups M1, M3, M5, and M7 in the first circuit branch 11 and the switch groups M2, M4, M6, and M8 in the second circuit branch 12 are merely examples of switch arrangements suitable for implementing the connection configuration of capacitors C1 and C2 described herein; those skilled in the art can design other switch arrangements for the same purpose.

[0135] Furthermore, the circuit 10 illustrated herein is adapted to be implemented with the opposite polarity to the example presented (e.g., with a negative supply voltage Vs and a current generator CG drawing current from current node A).

[0136] Without departing from the basic principles, details and embodiments may vary significantly from the content described by way of example only, without departing from the scope of the embodiments.

[0137] The claims form the entirety of the technical teachings provided herein regarding the embodiments.

[0138] The scope of protection is determined by the appended claims.

Claims

1. A circuit comprising: A current generator is configured to supply current to a current node; A first switch is located between the current node and the first output node; A second switch is located between the current node and the second output node; A first capacitor has a first plate coupled to the first output node and a second plate coupled to the first intermediate node; The second capacitor has a first plate coupled to the second output node and a second plate coupled to the second intermediate node; The third switch is located between the first intermediate node and the ground; The fourth switch is located between the second intermediate node and the ground. The fifth switch is located between the current node and the first intermediate node; The sixth switch is located between the current node and the second intermediate node; as well as A control circuit is configured to selectively actuate the first switch to the sixth switch to couple and decouple the first plate of the first capacitor and the first plate of the second capacitor relative to the current node, and to couple and decouple the second plate of the first capacitor and the second plate of the second capacitor relative to the current node and relative to ground, respectively, thereby generating a first current ramp signal at the first output node and a second current ramp signal at the second output node, wherein the first current ramp signal and the second current ramp signal have the same period and differ from each other by half of the same period.

2. The circuit of claim 1, wherein the current generator is a variable current generator, and the current is a variable current controlled to change the frequency of the first current ramp signal and the second current ramp signal.

3. The circuit of claim 1, wherein the first capacitor and the second capacitor are variable capacitors, and the capacitance of the first capacitor and the second capacitor is controlled to change the frequency of the first current ramp signal and the second current ramp signal.

4. The circuit of claim 1, wherein the control circuit includes a comparator circuit arrangement coupled to the first output node and the second output node and sensitive to voltages at the first output node and the second output node, the comparator circuit arrangement having a first threshold and a second threshold, the first threshold being between zero and the second threshold.

5. The circuit of claim 4, wherein the first threshold in the comparator circuit device is changeable to change the duty cycle of the first clock signal and the second clock signal generated from the first current ramp signal and the second current ramp signal.

6. The circuit of claim 1, wherein the control circuit is configured to operate in a startup configuration in which the first switch and the third switch are closed to connect the first plate and the second plate of the first capacitor to the current node and ground, respectively, and in the startup configuration the second switch and the sixth switch are open to decouple the first plate and the second plate of the second capacitor from the current node.

7. The circuit of claim 1, wherein the control circuit is configured to operate alternately in a first operating configuration and a second operating configuration, wherein: In the first operating configuration, the second switch, the fourth switch, and the fifth switch are closed, and the first switch, the third switch, and the sixth switch are open; as well as In the second operating configuration, the second switch, the fourth switch, and the fifth switch are open, and the first switch, the third switch, and the sixth switch are closed.

8. The circuit of claim 7, further comprising a seventh switch between the first output node and ground, wherein the control circuit selectively actuates the seventh switch to discharge the first capacitor between the first operating configuration and the second operating configuration.

9. The circuit of claim 8, wherein the control circuit selectively actuates the third switch using the seventh switch to discharge the first capacitor.

10. The circuit of claim 7, further comprising an eighth switch between the second output node and ground, wherein the control circuit selectively actuates the eighth switch to discharge the second capacitor between the second operating configuration and the first operating configuration.

11. The circuit of claim 10, wherein the control circuit selectively actuates the fourth switch with the eighth switch to discharge the second capacitor.

12. A circuit comprising: Power node; A current generator is arranged between the power node and the current node; A first circuit branch and a second circuit branch are arranged in parallel between the current node and ground. The first circuit branch includes a first output node and a first capacitor having a first plate and a second plate, wherein the first plate of the first capacitor is coupled to the first output node. The second circuit branch includes a second output node and a second capacitor having a first plate and a second plate, wherein the first plate of the second capacitor is coupled to the second output node. The first set of switches in the first circuit branch includes switches configured to alternately turn on and off to couple and decouple the first plate of the first capacitor relative to the current node, and to couple and decouple the second plate of the first capacitor relative to the current node and relative to ground. The second set of switches in the second circuit branch includes switches configured to alternately turn on and off to couple and decouple the first plate of the second capacitor relative to the current node, and to couple and decouple the second plate of the second capacitor relative to the current node and relative to ground. The switches in the first group of switches and the switches in the second group of switches can be switched alternately between the following: In a first operating configuration, the first plate of the first capacitor is decoupled from the current node, and the second plate of the first capacitor is decoupled from ground and coupled to the second output node via the current node, and the first plate and the second plate of the second capacitor are respectively coupled to the current node and ground; as well as In the second operating configuration, the first plate and the second plate of the first capacitor are respectively coupled to the current node and ground, and the first plate of the second capacitor is decoupled from the current node, and the second plate of the second capacitor is decoupled from ground and coupled to the first output node via the current node.

13. The circuit of claim 12, further comprising a control circuit means coupled to the first set of switches in the first circuit branch and the second set of switches in the second circuit branch, and configured to alternately switch the first set of switches in the first circuit branch and the second set of switches in the second circuit branch in alternation of a first operating phase and a second operating phase in the first operating configuration and the second operating configuration.

14. The circuit of claim 13, wherein the control circuit means includes a comparator circuit means coupled to the first output node and the second output node and sensitive to voltages at the first output node and the second output node, the comparator circuit means having a first threshold and a second threshold, the first threshold being between zero and the second threshold, wherein the comparator circuit means is configured to switch the first set of switches in the first circuit branch and the second set of switches in the second circuit branch as follows: In response to the voltage at the first output node rising from the first threshold to the second threshold, the operation configuration changes from the first operation configuration to the second operation configuration; and The system returns from the second operating configuration to the first operating configuration in response to the voltage at the second output node rising from the first threshold to the second threshold.

15. The circuit of claim 14, wherein the first threshold in the comparator circuit device is selectively changeable.

16. The circuit of claim 13, further comprising a discharge switch for the first capacitor and the second capacitor, wherein the control circuitry is configured to activate the discharge switch to: In response to the control circuit device switching the first set of switches and the second set of switches from the first operating configuration to the second operating configuration, the first capacitor is discharged; and The second capacitor is discharged in response to the control circuit device switching the first set of switches and the second set of switches from the second operating configuration back to the first operating configuration.

17. The circuit of claim 12, wherein the current generator generates a selective variable current.

18. The circuit of claim 12, wherein the capacitance value of each of the first capacitor and the second capacitor is selectively changeable.

19. A circuit comprising: Power node; A current generator is arranged between the power node and the current node; A first circuit branch and a second circuit branch are arranged in parallel between the current node and ground. The first circuit branch includes a first output node and a first capacitor having a first plate and a second plate, wherein the first plate of the first capacitor is coupled to the first output node. The second circuit branch includes a second output node and a second capacitor having a first plate and a second plate, wherein the first plate of the second capacitor is coupled to the second output node. The first set of switches in the first circuit branch includes switches configured to alternately turn on and off to couple and decouple the first plate of the first capacitor relative to the current node, and to couple and decouple the second plate of the first capacitor relative to the current node and relative to ground. The second set of switches in the second circuit branch includes switches configured to alternately turn on and off to couple and decouple the first plate of the second capacitor relative to the current node, and to couple and decouple the second plate of the second capacitor relative to the current node and relative to ground. The switches in the first group of switches and the switches in the second group of switches can be selectively switched to: The configuration is initiated, wherein the first plate and the second plate of the first capacitor are respectively coupled to the current node and ground, and the first plate and the second plate of the second capacitor are decoupled from the current node; In a first operating configuration, the first plate of the first capacitor is decoupled from the current node, and the second plate of the first capacitor is decoupled from ground and coupled to the second output node via the current node, and the first plate and the second plate of the second capacitor are respectively coupled to the current node and ground; as well as A second operating configuration wherein the first plate and the second plate of the first capacitor are respectively coupled to the current node and ground, and the first plate of the second capacitor is decoupled from the current node, and the second plate of the second capacitor is decoupled from ground and coupled to the first output node via the current node; as well as The circuit includes a control circuit device coupled to a first set of switches in the first circuit branch and a second set of switches in the second circuit branch, and configured to switch the first set of switches in the first circuit branch and the second set of switches in the second circuit branch. In the startup configuration, the circuit is on during the startup phase; as well as After the start phase, the operation is alternately switched between the first operation phase and the second operation phase in the first operation configuration and the second operation configuration.

20. The circuit of claim 19, wherein the control circuit means includes a comparator circuit means coupled to the first output node and the second output node and sensitive to voltages at the first output node and the second output node, the comparator circuit means having a first threshold and a second threshold, the first threshold being between zero and the second threshold, wherein the comparator circuit means is configured to switch the first set of switches in the first circuit branch and the second set of switches in the second circuit branch: The startup configuration is switched to the first operation configuration in response to the voltage at the first output node rising to the first threshold. In response to the voltage at the first output node rising from the first threshold to the second threshold, the operation configuration changes from the first operation configuration to the second operation configuration; and The system returns from the second operating configuration to the first operating configuration in response to the voltage at the second output node rising from the first threshold to the second threshold.

21. The circuit of claim 20, wherein the first threshold in the comparator circuit device is selectively changeable.

22. The circuit of claim 19, wherein the current generator generates a selective variable current.

23. The circuit of claim 19, wherein the capacitance value of each of the first capacitor and the second capacitor is selectively changeable.

24. The circuit of claim 19, further comprising a discharge switch for the first capacitor and the second capacitor, wherein the control circuitry is configured to activate the discharge switch to: In response to the control circuit device switching the first set of switches and the second set of switches from the first operating configuration to the second operating configuration, the first capacitor is discharged; and The second capacitor is discharged in response to the control circuit device switching the first set of switches and the second set of switches from the second operating configuration back to the first operating configuration.

25. The circuit according to claim 19: The first group of switches includes: A first switch is located between the current node and the first output node in the first circuit branch; The third switch is located between the second plate of the first capacitor in the first circuit branch and ground. as well as The fifth switch is located between the second plate of the first capacitor in the current node and the first circuit branch; as well as The second group of switches includes: A second switch is located between the current node and the second output node in the second circuit branch; A fourth switch is located between the second plate of the second capacitor in the second circuit branch and ground; and A sixth switch is located between the second plate of the second capacitor in the current node and the second circuit branch.

26. The circuit of claim 25, further comprising: A seventh switch between the first output node and ground in the first circuit branch, wherein the third switch and the seventh switch provide a discharge switch for the first capacitor in the first circuit branch, and An eighth switch between the second output node and ground in the second circuit branch, wherein the fourth switch and the eighth switch provide a discharge switch for the second capacitor in the second circuit branch.

27. An apparatus comprising: The circuit according to claim 19; as well as A multi-phase circuit block is coupled to the first output node and the second output node to collect a first ramp signal and a second ramp signal from the first output node and the second output node, respectively. The first ramp signal and the second ramp signal have the same frequency and the same period, and the first ramp signal and the second ramp signal are offset from each other by half of the same period. The multi-phase circuit block is coupled to the control circuit device to collect a first clock signal and a second clock signal having the same frequency of the first ramp signal and the second ramp signal from the control circuit device at the alternation of the first operating phase and the second operating phase after the start phase.

28. A method of operating the circuit according to claim 19, the method comprising: The circuit is switched on, wherein the circuit enters the startup phase, followed by the alternation of the first operating phase and the second operating phase after the startup phase; as well as During the alternation of the first operating phase and the second operating phase: A first ramp signal and a second ramp signal are collected from the first output node and the second output node, respectively. The first ramp signal and the second ramp signal have the same frequency and the same period, and the first ramp signal and the second ramp signal are offset from each other by half of the same period. as well as At the alternation between the first operating phase and the second operating phase following the start phase, a first clock signal and a second clock signal having the same frequency as the first ramp signal and the second ramp signal are collected from the control circuit device.

29. The method of claim 28, wherein the control circuitry includes a comparator circuitry coupled to the first output node and the second output node and sensitive to voltages at the first output node and the second output node, the comparator circuitry having a first threshold and a second threshold, the first threshold being between zero and the second threshold, the method further comprising changing the first threshold in the comparator circuitry to change the duty cycle of the first clock signal and the second clock signal.

30. The method of claim 28, further comprising changing the intensity of the current generated by the current generator to change the same frequency of the first clock signal and the second clock signal, and the same frequency of the first ramp signal and the second ramp signal.

31. The method of claim 28, further comprising changing the capacitance values ​​of the first capacitor and the second capacitor to change the same frequency of the first clock signal and the second clock signal, and the same frequency of the first ramp signal and the second ramp signal.

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