A solid state drive injection error testing method, device, equipment and medium

Abstract

The present invention proposes a solid-state hard drive error injection testing method, which is applied to a flash memory controller in a solid-state hard drive, including: obtaining data to be written into the flash memory; after triggering the error injection test according to a preset error injection triggering method, performing multiple error injection tests on the data to be written into the flash memory during the verification and error correction process; obtaining test results of the multiple error injection tests. The present invention also proposes a solid-state hard drive error injection testing device, equipment and medium, which realizes active verification testing of the error correction and recovery functions of the solid-state hard drive, can effectively verify the completeness of all error correction and recovery functions of the solid-state hard drive, can effectively eliminate unknown bugs in the software code, and effectively improve the qualification rate of solid-state hard drive products.

Description

Technical Field

[0001] The present invention relates to the field of replica configuration, and in particular to a solid-state hard disk injection error testing method, device, equipment and medium. Background Art

[0002] A solid-state drive (SSD), also known as a solid-state drive (SSD), is a hard drive made from an array of solid-state electronic memory chips. The SSD backend primarily includes two functional modules: NFC (NAND flash controller) and ECC (Error Correcting Code): a method that enables "error checking and correction." The ECC module is a data encoding and decoding unit. Because flash memory storage inherently has a bit error rate, ECC checksum protection must be added to the original data during data write operations to ensure data accuracy. This is an encoding process. When reading data, decoding is also required for error detection and correction. If the number of erroneous bits exceeds the ECC error correction capability, the data will be uploaded to the host as "uncorrectable."

[0003] Currently, the error correction and recovery function of solid-state drives only has an error handling process, and can only passively wait until an error occurs before entering the error handling process. It is unable to actively check whether the data error correction and recovery function of the solid-state drive's internal software code is available, which is not conducive to active verification testing of the error correction and recovery (check and error correction) function of the solid-state drive. Summary of the Invention

[0004] In order to solve the problems existing in the prior art, the present invention innovatively proposes a solid-state hard drive error injection testing method, device, equipment and medium, which effectively solves the problem that the prior art cannot actively verify whether the data error correction and recovery function of the solid-state hard drive is normally available, and realizes the active verification test of the error correction and recovery (check and error correction) function of the solid-state hard drive.

[0005] A first aspect of the present invention provides a solid-state drive injection error testing method, which is applied to a flash memory controller in a solid-state drive, comprising:

[0006] Obtaining data to be written into the flash memory;

[0007] After the error injection test is triggered according to the preset error injection triggering mode, the data to be written into the flash memory is subjected to multiple error injection tests during the error correction process;

[0008] Get the test results of multiple injection errors test.

[0009] Optionally, the check and error correction process includes hard decision decoding, soft decision decoding, and XOR check and error correction.

[0010] Furthermore, after the error injection test is triggered according to the preset error injection triggering mode, multiple error injection tests are performed on the data to be written into the flash memory during the error correction process, including:

[0011] After the error injection test is triggered by the preset error injection trigger mode, the first error injection is performed when reading the data written in the flash memory;

[0012] During the decoding process of the data after the first error injection by hard decision decoding, a second error injection is performed to force the hard decision decoding to fail;

[0013] A third error injection is performed when rereading the data written to the flash memory;

[0014] During the decoding process of the data after the third error injection by hard decision decoding, a fourth error injection is performed to force the hard decision decoding to fail;

[0015] A fifth error is made when rereading data written to the flash memory;

[0016] During the soft decision decoding process of the data after the fifth error injection, the sixth error injection is performed to force the soft decision decoding to fail;

[0017] The seventh error is made when rereading the data written to the flash memory;

[0018] During the XOR error correction process, the data after the seventh error is corrected and restored.

[0019] Furthermore, obtaining the test results of multiple injection errors tests specifically includes:

[0020] If decoding fails during any hard decision decoding or soft decision decoding process, the subsequent error injection test will not be continued, the error injection test ends, and the check and error correction function of the solid state drive is abnormal.

[0021] Furthermore, if the decoding is successful during any hard decision decoding or soft decision decoding process, the subsequent error injection test will continue.

[0022] Optionally, if error recovery fails during the XOR check and error correction process, the subsequent error injection test will not be continued, the error injection test ends, and the check and error correction function of the solid-state drive is abnormal.

[0023] Optionally, during the error injection test, if each hard decision decoding is successful, the soft decision decoding is successful, and the XOR check error correction recovery is successful, the error injection test ends and the check error correction function of the solid state drive is normal.

[0024] A second aspect of the present invention provides a solid-state drive injection error testing device, which is applied to a flash memory controller in a solid-state drive, comprising:

[0025] A first acquisition module acquires data to be written into the flash memory;

[0026] A test module, after triggering an error injection test according to a preset error injection triggering mode, performs multiple error injection tests on the data to be written into the flash memory during the error correction process;

[0027] The second acquisition module obtains the test results of multiple injection error tests.

[0028] The third aspect of the present invention provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of a solid-state hard disk injection error testing method as described in the first aspect of the present invention when executing the computer program.

[0029] A fourth aspect of the present invention provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the steps of a solid-state hard drive injection error testing method as described in the first aspect of the present invention are implemented.

[0030] The technical solution adopted by the present invention includes the following technical effects:

[0031] 1. After the error injection test is triggered according to a preset error injection triggering method, the present invention performs an error injection test on the data to be written into the flash memory during the verification and error correction process, effectively solving the problem that the existing technology cannot actively verify whether the data error correction and recovery function of the solid-state hard disk is normally available, and realizes the active verification test of the error correction and recovery (verification and error correction) function of the solid-state hard disk.

[0032] 2. In the technical solution of the present invention, multiple error injection tests are performed on the data to be written into the flash memory during the error correction process, and the error correction and recovery function of the solid-state hard disk is fully verified, thereby improving the accuracy and reliability of the error injection test.

[0033] 3. In the technical solution of the present invention, if the decoding fails during any hard decision decoding or soft decision decoding process, the subsequent error injection test will not be continued, the error injection test will end, and the check and error correction function of the solid-state drive will be abnormal; if the decoding is successful during any hard decision decoding or soft decision decoding process, the subsequent error injection test will be continued, thereby improving the efficiency of the error injection test.

[0034] 4. In the technical solution of the present invention, during the error injection test, if each hard decision decoding is successful, the soft decision decoding is successful, and the XOR check and error correction recovery is successful, the error injection test is completed, and the check and error correction function of the solid-state drive is normal, further improving the accuracy and reliability of the error injection test, and ensuring the normal availability of the solid-state drive's data check and error correction recovery function.

[0035] It should be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0037] Figure 1 Schematic diagram of the process of the method of Example 1 in the scheme of the present invention;

[0038] Figure 2 Schematic diagram of the process of step S2 in the method of Example 1 of the present invention;

[0039] Figure 3 Schematic diagram of error correction decoding and error annotation timing in the method of Example 1 of the present invention;

[0040] Figure 4 1 is a flow chart of step S3 in the method of embodiment 1 of the present invention;

[0041] Figure 5 This is another flow chart of step S3 in the method of Example 1 of the present invention;

[0042] Figure 6 This is a schematic structural diagram of a device in Example 2 of the present invention;

[0043] Figure 7 This is a structural diagram of the device in Example 3 of the present invention. DETAILED DESCRIPTION

[0044] In order to clearly illustrate the technical features of this solution, the present invention is described in detail below through specific implementation methods and in conjunction with the accompanying drawings. The disclosure below provides many different embodiments or examples for realizing different structures of the present invention. In order to simplify the disclosure of the present invention, the components and settings of specific examples are described below. In addition, the present invention may repeat reference numbers and / or letters in different examples. This repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or settings discussed. It should be noted that the components illustrated in the accompanying drawings are not necessarily drawn to scale. The present invention omits descriptions of well-known components and processing technologies and processes to avoid unnecessary limitations on the present invention.

[0045] Example 1

[0046] like Figure 1 As shown, the present invention provides a solid state drive injection error testing method, which is applied to a flash memory controller in a solid state drive, comprising:

[0047] S1, obtaining data to be written into the flash memory;

[0048] S2, after triggering the error injection test according to the preset error injection triggering mode, performing multiple error injection tests on the data to be written into the flash memory during the error correction process;

[0049] S3, obtaining test results of multiple injection error tests.

[0050] Wherein, in step S1, the flash memory controller reads data to be written into the flash memory (NAND FLASH).

[0051] In step S2, a back-end error injection function is developed in the SSD through software code. This function can be turned on or off via serial port commands, and error injection can be performed using serial port commands or the NVME_CLI tool (a tool for managing NVME drives). The error injection trigger can be used to set the error injection method. The default is probabilistic injection. If scheduled injection is required, a command to switch the method must be actively input.

[0052] Specifically, the probabilistic triggering method is as follows: by setting the probability value, each time the operation is executed, it is determined whether the data reading operation is incorrect by checking whether the random number output value falls within the probability interval.

[0053] The timing trigger is specifically achieved by setting the number of triggers per second. The program will calculate the time interval for triggering the error injection based on the input value. Each time it is executed, it will judge the difference between the last trigger time and this time. If it is greater than the error injection time interval, an error injection will be performed.

[0054] SSDs perform error checking and correction on data written to flash memory, including hard decoding, soft decoding, and XOR (Exclusive Or) error correction. Error checking and correction for data written to flash memory in SSDs primarily uses ECC algorithms, including BCH decoding (abbreviation for Bose Ray-Chaudhuri Hocquenghem, a widely studied encoding method for error-correcting codes), LDPC decoding (Low Density Parity Check Code), and XOR decoding.

[0055] The LDPC decoding method involves multiplying the received codeword by a parity check matrix. If the result is a zero matrix, it indicates the codeword was correct; otherwise, it is incorrect. Further error correction decoding is then performed based on the multiplication result. The LDPC decoding process includes hard-decision decoding and soft-decision decoding. Hard-decision decoding passes information between parity check nodes and variable nodes, iterating until all parity checks return to 0, indicating successful decoding. Soft-decision decoding adjusts read levels and, based on the read results, determines the probability of a bit (binary digit, the smallest unit of information) being 1 or 0. Soft-decision decoding is then performed based on this probability. The data parity and error correction process in solid-state drives typically involves first reading and writing data to the flash memory through a NAND flash controller, then performing LDPC hard-decision decoding. If hard-decision decoding fails, the data is reread and hard-decision decoding is repeated. If hard-decision decoding still fails, LDPC soft-decision decoding is performed. If soft-decision decoding also fails, XOR error correction or other error correction methods are used.

[0056] like Figure 2-Figure 3 As shown, step S2 includes:

[0057] S201, after the error injection test is triggered by a preset error injection triggering mode, performing the first error injection when reading data written into the flash memory;

[0058] S202, during the hard decision decoding process of the data after the first error injection, a second error injection is performed to force the hard decision decoding to fail;

[0059] S203, performing a third error annotation when re-reading the data written into the flash memory;

[0060] S204, during the hard decision decoding process of the data after the third error injection, a fourth error injection is performed to force the hard decision decoding to fail;

[0061] S205, performing a fifth error annotation when re-reading the data written into the flash memory;

[0062] S206, during the soft decision decoding process for decoding the data after the fifth error injection, a sixth error injection is performed to force the soft decision decoding to fail;

[0063] S207, performing a seventh error annotation when re-reading the data written into the flash memory;

[0064] S208, performing error correction and recovery on the data after the seventh error injection in the XOR check error correction process.

[0065] The first, third, fifth, and seventh injection errors are identical in terms of both the injection method and the injection type. The second and fourth injection errors are identical in terms of both the injection method and the injection type, changing the hard decision decoding success flag to a failure flag, forcing the hard decision decoding to fail. The sixth injection error changes the soft decision decoding success flag to a failure flag, forcing the soft decision decoding to fail.

[0066] Among them, Figure 4 As shown, in step S3, the test results of multiple injection errors are obtained as follows:

[0067] S301, in the multiple error injection test, determine whether any hard decision decoding or soft decision decoding fails. If the result is yes, execute step S302; if not, execute step S303;

[0068] S302 , the subsequent error injection test is no longer continued, the error injection test ends, and the check and error correction function of the solid state drive is abnormal.

[0069] S303, continue with subsequent injection error testing.

[0070] Furthermore, if Figure 5 As shown, in step S3, obtaining the test results of multiple injection errors also includes:

[0071] S304, during the XOR error correction process, determining whether error correction recovery has failed. If so, proceed to step S302; if not, proceed to step S305;

[0072] S305, the error injection test is completed, and the error correction function of the solid state drive is normal.

[0073] The corresponding test result in step S305 is that during the error injection test, each hard decision decoding is successful, the soft decision decoding is successful, and the XOR check error correction recovery is successful, then the error injection test ends and the check error correction function of the solid state drive is normal.

[0074] In step S3, the success of hard decision decoding can be determined by whether the data to be written is consistent with the decoded data. If they are consistent, the hard decision decoding is determined to be successful; if they are inconsistent, the hard decision decoding is determined to be unsuccessful. The success of soft decision decoding can be determined by whether the data to be written is consistent with the decoded data. If they are consistent, the soft decision decoding is determined to be successful; if they are inconsistent, the soft decision decoding is determined to be unsuccessful. The data recovery process can also be viewed through serial port printing, and the error correction error count (or injection error count) can be queried by entering a serial port command. If the error correction error count is not 0, and no verification failure is prompted after all injection error tests are completed, the verification and error correction function is available.

[0075] Generally, a flash memory controller will not generate a large number of errors when reading data from NAND flash memory to trigger all subsequent error handling processes. Therefore, the probability of actively triggering the data verification and recovery function during routine testing is very low.

[0076] Through the error injection test method of this embodiment, errors are actively injected multiple times during the process of NFC reading data and verifying it. The software code will automatically enter the data recovery process, which can effectively verify the completeness of all error handling functions of the solid-state drive (error correction function or error correction recovery function), increase the test coverage, effectively eliminate unknown bugs (program errors) in the software code, and effectively improve the qualification rate of solid-state drive products.

[0077] After triggering the error injection test according to a preset error injection triggering method, the present invention performs an error injection test on the data to be written into the flash memory during the verification and error correction process, effectively solving the problem that the existing technology cannot actively verify whether the data error correction and recovery function of the solid-state hard disk is normally available, and realizes the active verification test of the error correction and recovery (verification and error correction) function of the solid-state hard disk.

[0078] In the technical solution of the present invention, multiple error injection tests are performed on the data to be written into the flash memory during the error correction process, and the error correction and recovery function of the solid state drive is fully verified, thereby improving the accuracy and reliability of the error injection test.

[0079] In the technical solution of the present invention, if decoding fails during any hard decision decoding or soft decision decoding process, the subsequent error injection test will not be continued, the error injection test will end, and the check and error correction function of the solid-state drive will be abnormal; if decoding is successful during any hard decision decoding or soft decision decoding process, the subsequent error injection test will be continued, thereby improving the efficiency of the error injection test.

[0080] In the technical solution of the present invention, during the error injection test process, if each hard decision decoding is successful, the soft decision decoding is successful, and the XOR check error correction recovery is successful, the error injection test is completed, and the check error correction function of the solid-state drive is normal, further improving the accuracy and reliability of the error injection test, and ensuring the normal availability of the solid-state drive's data check error correction recovery function.

[0081] Example 2

[0082] like Figure 6 As shown, the technical solution of the present invention also provides a solid state drive injection error test device, which is applied to a flash memory controller in a solid state drive, comprising:

[0083] A first acquisition module 101 acquires data to be written into the flash memory;

[0084] The test module 102 triggers the error injection test according to the preset error injection triggering mode, and performs multiple error injection tests on the data to be written into the flash memory during the error correction process;

[0085] The second acquisition module 103 acquires test results of multiple injection error tests.

[0086] In the first acquisition module 101 , the flash memory controller reads data to be written into the flash memory (NAND FLASH).

[0087] In test module 102, a back-end error injection function is developed in the SSD through software code. This function can be enabled or disabled via serial port commands or the NVME_CLI tool (a tool for managing NVME drives). Error injection triggers can be used to set the error injection method. The default is probabilistic injection. If scheduled injection is required, a command to switch the method is required.

[0088] Specifically, the probabilistic triggering method is as follows: by setting the probability value, each time the operation is executed, it is determined whether the data reading operation is incorrect by checking whether the random number output value falls within the probability interval.

[0089] The timing trigger is specifically achieved by setting the number of triggers per second. The program will calculate the time interval for triggering the error injection based on the input value. Each time it is executed, it will judge the difference between the last trigger time and this time. If it is greater than the error injection time interval, an error injection will be performed.

[0090] SSDs perform error checking and correction on data written to flash memory, including hard decoding, soft decoding, and XOR (Exclusive Or) error correction. Error checking and correction for data written to flash memory in SSDs primarily uses ECC algorithms, including BCH decoding (abbreviation for Bose Ray-Chaudhuri Hocquenghem, a widely studied encoding method for error-correcting codes), LDPC decoding (Low Density Parity Check Code), and XOR decoding.

[0091] The LDPC decoding method involves multiplying the received codeword by a parity check matrix. If the result is a zero matrix, it indicates the codeword was correct; otherwise, it is incorrect. Further error correction decoding is then performed based on the multiplication result. The LDPC decoding process includes hard-decision decoding and soft-decision decoding. Hard-decision decoding passes information between parity check nodes and variable nodes, iterating until all parity checks return to 0, indicating successful decoding. Soft-decision decoding adjusts read levels and, based on the read results, determines the probability of a bit (binary digit, the smallest unit of information) being 1 or 0. Soft-decision decoding is then performed based on this probability. The data parity and error correction process in solid-state drives typically involves first reading and writing data to the flash memory through a NAND flash controller, then performing LDPC hard-decision decoding. If hard-decision decoding fails, the data is reread and hard-decision decoding is repeated. If hard-decision decoding still fails, LDPC soft-decision decoding is performed. If soft-decision decoding also fails, XOR error correction or other error correction methods are used.

[0092] The steps performed by the testing module 102 include:

[0093] After the error injection test is triggered by the preset error injection trigger mode, the first error injection is performed when reading the data written in the flash memory;

[0094] During the decoding process of the data after the first error injection by hard decision decoding, a second error injection is performed to force the hard decision decoding to fail;

[0095] A third error injection is performed when rereading the data written to the flash memory;

[0096] During the decoding process of the data after the third error injection by hard decision decoding, a fourth error injection is performed to force the hard decision decoding to fail;

[0097] A fifth error is made when rereading data written to the flash memory;

[0098] During the soft decision decoding process of the data after the fifth error injection, the sixth error injection is performed to force the soft decision decoding to fail;

[0099] The seventh error is made when rereading the data written to the flash memory;

[0100] During the XOR error correction process, the data after the seventh error is corrected and restored.

[0101] The first, third, fifth, and seventh injection errors are identical in terms of both the injection method and the injection type. The second and fourth injection errors are identical in terms of both the injection method and the injection type, changing the hard decision decoding success flag to a failure flag, forcing the hard decision decoding to fail. The sixth injection error changes the soft decision decoding success flag to a failure flag, forcing the soft decision decoding to fail.

[0102] Among them, in the second acquisition module 103, in multiple error injection tests, it is determined whether any hard decision decoding or soft decision decoding has a decoding failure. If a decoding failure occurs, the subsequent error injection test will not be continued, the error injection test ends, and the verification and error correction function of the solid-state drive is abnormal; if no decoding failure occurs, the subsequent error injection test will be continued.

[0103] During the XOR check and error correction process, determine whether the error correction recovery fails. If the error correction recovery fails, the subsequent error injection test will not continue, the error injection test ends, and the check and error correction function of the solid-state drive is abnormal; if the error correction recovery fails, the error injection test ends, and the check and error correction function of the solid-state drive is normal.

[0104] Furthermore, if during the error injection test, each hard decision decoding is successful, the soft decision decoding is successful, and the XOR check error correction recovery is successful, then the error injection test ends and the check error correction function of the solid state drive is normal.

[0105] The success of hard-decision decoding can be determined by checking whether the data to be written is consistent with the decoded data. If so, the hard-decision decoding is considered successful; if not, the hard-decision decoding is considered unsuccessful. The success of soft-decision decoding can be determined by checking whether the data to be written is consistent with the decoded data. If so, the soft-decision decoding is considered successful; if not, the soft-decision decoding is considered unsuccessful. The data recovery process can also be viewed through serial port printing, and the error correction count (or injection error count) can be queried by entering serial port commands. If the error correction count is not 0 and no verification failure is prompted after all injection error tests are completed, the verification and error correction function is available.

[0106] Generally, a flash memory controller will not generate a large number of errors when reading data from NAND flash memory to trigger all subsequent error handling processes. Therefore, the probability of actively triggering the data verification and recovery function during routine testing is very low.

[0107] Through the error injection test device of this embodiment, errors are actively injected multiple times during the process of NFC reading data and verifying it. The software code will automatically enter the data recovery process, which can effectively verify the completeness of all error handling functions of the solid-state drive (error correction function or error correction recovery function), increase the test coverage, effectively eliminate unknown bugs (program errors) in the software code, and effectively improve the qualification rate of solid-state drive products.

[0108] After triggering the error injection test according to a preset error injection triggering method, the present invention performs an error injection test on the data to be written into the flash memory during the verification and error correction process, effectively solving the problem that the existing technology cannot actively verify whether the data error correction and recovery function of the solid-state hard disk is normally available, and realizes the active verification test of the error correction and recovery (verification and error correction) function of the solid-state hard disk.

[0109] In the technical solution of the present invention, multiple error injection tests are performed on the data to be written into the flash memory during the error correction process, and the error correction and recovery function of the solid state drive is fully verified, thereby improving the accuracy and reliability of the error injection test.

[0110] In the technical solution of the present invention, if decoding fails during any hard decision decoding or soft decision decoding process, the subsequent error injection test will not be continued, the error injection test will end, and the check and error correction function of the solid-state drive will be abnormal; if decoding is successful during any hard decision decoding or soft decision decoding process, the subsequent error injection test will be continued, thereby improving the efficiency of the error injection test.

[0111] In the technical solution of the present invention, during the error injection test process, if each hard decision decoding is successful, the soft decision decoding is successful, and the XOR check error correction recovery is successful, the error injection test is completed, and the check error correction function of the solid-state drive is normal, further improving the accuracy and reliability of the error injection test, and ensuring the normal availability of the solid-state drive's data check error correction recovery function.

[0112] Example 3

[0113] like Figure 7 As shown, the technical solution of the present invention also provides an electronic device, including: a memory 201 for storing a computer program; a processor 202 for implementing the steps of a solid-state hard disk injection error testing method as in Example 1 when executing the computer program.

[0114] The memory 201 in the embodiment of the present application is used to store various types of data to support the operation of the electronic device. Examples of these data include: any computer program for operating on the electronic device. It is understood that the memory 201 can be a volatile memory or a non-volatile memory, and can also include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a magnetic random access memory (FRAM), a flash memory, a magnetic surface memory, an optical disc, or a read-only optical disc (CD-ROM); the magnetic surface memory can be a disk memory or a tape memory. The volatile memory can be a random access memory (RAM), which is used as an external cache.By way of example and not limitation, many forms of RAM are available, such as static random access memory (SRAM), synchronous static random access memory (SSRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), direct RAM bus random access memory (DRRAM). The memory 201 described in the embodiments of the present application is intended to include, but is not limited to, these and any other suitable types of memory.

[0115] The methods disclosed in the above embodiments of the present application can be applied to or implemented by processor 202. Processor 202 may be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method can be completed by hardware integrated logic circuits in processor 202 or by software instructions. The above processor 202 may be a general-purpose processor, a DSP (Digital Signal Processing), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Processor 202 can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of this application. A general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly implemented and executed by a hardware decoding processor, or by a combination of hardware and software modules in the decoding processor. The software module can be located in a storage medium located in memory 201. Processor 202 reads the program in memory 201 and, in conjunction with its hardware, completes the steps of the above method. When the processor 202 executes the program, the corresponding processes in the various methods of the embodiments of the present application are implemented. For the sake of brevity, they are not described here.

[0116] After triggering the error injection test according to a preset error injection triggering method, the present invention performs an error injection test on the data to be written into the flash memory during the verification and error correction process, effectively solving the problem that the existing technology cannot actively verify whether the data error correction and recovery function of the solid-state hard disk is normally available, and realizes the active verification test of the error correction and recovery (verification and error correction) function of the solid-state hard disk.

[0117] In the technical solution of the present invention, multiple error injection tests are performed on the data to be written into the flash memory during the error correction process, and the error correction and recovery function of the solid state drive is fully verified, thereby improving the accuracy and reliability of the error injection test.

[0118] In the technical solution of the present invention, if decoding fails during any hard decision decoding or soft decision decoding process, the subsequent error injection test will not be continued, the error injection test will end, and the check and error correction function of the solid-state drive will be abnormal; if decoding is successful during any hard decision decoding or soft decision decoding process, the subsequent error injection test will be continued, thereby improving the efficiency of the error injection test.

[0119] In the technical solution of the present invention, during the error injection test process, if each hard decision decoding is successful, the soft decision decoding is successful, and the XOR check error correction recovery is successful, the error injection test is completed, and the check error correction function of the solid-state drive is normal, further improving the accuracy and reliability of the error injection test, and ensuring the normal availability of the solid-state drive's data check error correction recovery function.

[0120] Example 4

[0121] The technical solution of the present invention also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of a solid-state hard disk injection error testing method as described in Example 1 are implemented.

[0122] For example, the computer program may be stored in a memory 201, which may be executed by a processor 202 to perform the steps of the method. The computer-readable storage medium may be a memory such as FRAM, ROM, PROM, EPROM, EEPROM, Flash Memory, magnetic surface storage, optical disk, or CD-ROM.

[0123] Those skilled in the art will appreciate that all or part of the steps of the above-mentioned method embodiments can be implemented by hardware related to program instructions, and the aforementioned program can be stored in a computer-readable storage medium. When the program is executed, the steps of the above-mentioned method embodiments are executed; and the aforementioned storage medium includes: various media that can store program codes, such as mobile storage devices, ROM, RAM, magnetic disks or optical disks. Alternatively, if the above-mentioned integrated unit of the present application is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiment of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for enabling an electronic device (which can be a personal computer, server, or network device, etc.) to execute all or part of the methods described in each embodiment of the present application. And the aforementioned storage medium includes: various media that can store program codes, such as mobile storage devices, ROM, RAM, magnetic disks or optical disks.

[0124] After triggering the error injection test according to a preset error injection triggering method, the present invention performs an error injection test on the data to be written into the flash memory during the verification and error correction process, effectively solving the problem that the existing technology cannot actively verify whether the data error correction and recovery function of the solid-state hard disk is normally available, and realizes the active verification test of the error correction and recovery (verification and error correction) function of the solid-state hard disk.

[0125] In the technical solution of the present invention, multiple error injection tests are performed on the data to be written into the flash memory during the error correction process, and the error correction and recovery function of the solid state drive is fully verified, thereby improving the accuracy and reliability of the error injection test.

[0126] In the technical solution of the present invention, if decoding fails during any hard decision decoding or soft decision decoding process, the subsequent error injection test will not be continued, the error injection test will end, and the check and error correction function of the solid-state drive will be abnormal; if decoding is successful during any hard decision decoding or soft decision decoding process, the subsequent error injection test will be continued, thereby improving the efficiency of the error injection test.

[0127] In the technical solution of the present invention, during the error injection test process, if each hard decision decoding is successful, the soft decision decoding is successful, and the XOR check error correction recovery is successful, the error injection test is completed, and the check error correction function of the solid-state drive is normal, further improving the accuracy and reliability of the error injection test, and ensuring the normal availability of the solid-state drive's data check error correction recovery function.

[0128] Although the above describes the specific embodiments of the present invention in conjunction with the accompanying drawings, it is not intended to limit the scope of protection of the present invention. Those skilled in the art should understand that various modifications or variations that can be made by those skilled in the art on the basis of the technical solution of the present invention without any creative work are still within the scope of protection of the present invention.

Claims

1. A method for testing injection errors in solid-state hard drives, characterized by: Flash memory controllers used in solid-state drives include: Obtaining data to be written into the flash memory; After the error injection test is triggered according to a preset error injection trigger mode, multiple error injection tests are performed on the data to be written into the flash memory during the verification and error correction process; wherein the verification and error correction process includes hard decision decoding, soft decision decoding, and XOR verification and error correction; after the error injection test is triggered according to the preset error injection trigger mode, multiple error injection tests are performed on the data to be written into the flash memory during the verification and error correction process, including: After the error injection test is triggered by the preset error injection trigger mode, the first error injection is performed when reading the data written in the flash memory; During the decoding process of the data after the first error injection by hard decision decoding, a second error injection is performed to force the hard decision decoding to fail; wherein forcing the hard decision decoding to fail specifically includes changing the hard decision decoding success flag to a failure flag; A third error injection is performed when rereading the data written to the flash memory; During the decoding process of the data after the third error injection by hard decision decoding, a fourth error injection is performed to force the hard decision decoding to fail; The fifth error is made when rereading the data written to the flash memory; During the soft decision decoding process of data after the fifth error injection, a sixth error injection is performed to force the soft decision decoding to fail; wherein forcing the soft decision decoding to fail specifically includes changing the soft decision decoding success flag to a failure flag; The seventh error is made when rereading the data written to the flash memory; During the XOR error correction process, the data after the seventh error is corrected and restored; Get the test results of multiple injection errors test.

2. The method for testing an injection error of a solid-state hard disk according to claim 1, wherein: The obtaining of the test results of multiple injection errors test specifically includes: If decoding fails during any hard decision decoding or soft decision decoding process, the subsequent error injection test will not be continued, the error injection test will end, and the SSD's check and error correction function will be abnormal; wherein, the decoding failure includes hard decision decoding and soft decision decoding. Hard decision decoding failure is specifically when the data to be written is inconsistent with the data after hard decision decoding; soft decision decoding failure is specifically when the data to be written is inconsistent with the data after soft decision decoding.

3. A solid state drive injection error testing method according to claim 2, characterized in that If the decoding is successful during any hard decision decoding or soft decision decoding process, the subsequent error injection test will continue.

4. A solid state drive injection error testing method according to claim 2, characterized in that If the error recovery fails during the XOR check and correction process, the subsequent error injection test will not continue. The error injection test ends and the check and error correction function of the solid-state drive is abnormal.

5. The method for testing an injection error of a solid-state hard disk according to claim 2, wherein: During the error injection test, if each hard decision decoding is successful, the soft decision decoding is successful, and the XOR check error correction recovery is successful, the error injection test ends and the check error correction function of the solid-state drive is normal.

6. A solid state drive injection error testing device, characterized in that: Flash memory controllers used in solid-state drives include: A first acquisition module acquires data to be written into the flash memory; The test module triggers an error injection test according to a preset error injection trigger mode, and then performs multiple error injection tests on the data to be written into the flash memory during a verification and error correction process; wherein the verification and error correction process includes hard decision decoding, soft decision decoding, and XOR verification and error correction; after the error injection test is triggered according to the preset error injection trigger mode, the test module performs multiple error injection tests on the data to be written into the flash memory during a verification and error correction process, including: After the error injection test is triggered by the preset error injection trigger mode, the first error injection is performed when reading the data written in the flash memory; During the decoding process of the data after the first error injection by hard decision decoding, a second error injection is performed to force the hard decision decoding to fail; A third error injection is performed when rereading the data written to the flash memory; During the decoding process of the data after the third error injection by hard decision decoding, a fourth error injection is performed to force the hard decision decoding to fail; A fifth error is made when rereading data written to the flash memory; During the soft decision decoding process of the data after the fifth error injection, the sixth error injection is performed to force the soft decision decoding to fail; The seventh error is made when rereading the data written to the flash memory; During the XOR error correction process, the data after the seventh error is corrected and restored; The second acquisition module obtains the test results of multiple injection error tests.

7. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of a solid-state drive injection error testing method as claimed in any one of claims 1 to 5 when executing the computer program.

8. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by the processor, the steps of the solid-state hard disk injection error testing method according to any one of claims 1 to 5 are implemented.

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