A multi-stage equalizer for a receiver analog front end of a high-speed serial link

Abstract

The present invention discloses a multi-stage equalizer for a receiver analog front-end of a high-speed serial link, belonging to the field of integrated circuit design. The equalizer of the present invention includes two parts: a linear equalizer and a DFE equalizer. The linear equalizer has a variable amplitude-frequency gain and is used to compensate for channel loss. The DFE equalizer is used to further eliminate residual inter-symbol interference. The linear equalizer adopts an active inductor peaking technology, which improves the peak gain on the premise of saving circuit layout area. At the same time, a negative capacitance structure is used to expand the gain bandwidth. The DFE equalizer adopts a half-rate speculative structure to solve the timing problem in high-speed signal equalization. The present invention can achieve low-bit-error reception of high-speed serial signals, has a small occupied area, is convenient to integrate in an RX receiver, has low power consumption, has good stability, can compensate for large channel losses, and provides a feasible solution for solving the signal equalization problem of a SerDes high-speed serial link.

Description

Technical Field

[0001] The present invention relates to a multi-stage equalizer for a receiver analog front end of a high-speed serial link, and belongs to the field of integrated circuit design. Background Art

[0002] In the rapidly developing information age, the transmission rate of signals continues to increase. However, the bandwidth-limited backplane channel will cause serious high-frequency channel loss, resulting in serious inter-symbol interference (ISI), which poses a challenge to low-bit-error reception. In order to improve the performance of the communication system, it is necessary to apply equalization technology to high-speed links.

[0003] Common equalization techniques in high-speed serial links can be divided into linear equalizers and decision feedback equalizers (DFEs). Linear equalizers use the frequency characteristics of variable gain filters to compensate for channel loss. However, for high-speed signals, especially in high-speed serial links with a signal transmission rate greater than 5 Gb / s, since signal jitter (such as deterministic jitter and random jitter related to ISI) may exceed one symbol interval (UI), using a linear equalizer alone is no longer applicable. On the other hand, linear equalizers amplify both noise and signals, which does not improve the BER performance of the communication system. For the above reasons, DFE equalizers are mainly used together with linear equalizers to eliminate residual ISI. As a non-linear equalizer, DFE only amplifies signals and does not amplify noise, which can effectively improve the signal-to-noise ratio characteristics.

[0004] Generally speaking, FR-4 backplane channels have more serious insertion loss at high frequencies, and the traditional continuous-time linear equalizer (CTLE) structure cannot provide enough gain. Patent CN213461678 U uses inductive peaking technology to expand the bandwidth and increase the peak gain. However, traditional inductors occupy a large area and are difficult to integrate, and the equalizer based on passive inductors does not have variable gain and cannot well adapt to the change of channel loss. Considering that channel loss is affected by non-ideal characteristics such as environment and skin effect, Patent CN 114268522 A proposes an adaptive-structured gain-adjustable CTLE that can better adjust to the change of channel loss under different conditions. However, in the design of channel equalization, compared with obvious high-frequency loss, the channel loss in the low-frequency part is often ignored because its slope is relatively smooth, so that the low-frequency loss cannot be well compensated. Summary of the Invention

[0005] In order to achieve a variable amplitude-frequency gain of the equalizer, effectively compensate for channel loss according to channel characteristics in the high and low frequency bands, improve the circuit integration degree at the same time, and reduce the occupied area of the RX receiver chip, the present invention provides a multi-stage equalizer for the receiver analog front end of a high-speed serial link, including: a three-stage cascaded linear equalizer and a three-tap DFE equalizer, and the output end of the three-stage cascaded linear equalizer is sequentially connected to the input end of the three-tap DFE equalizer;

[0006] The three-stage cascaded linear equalizer includes: a variable gain amplifier, a CTLE equalizer and a buffer connected in sequence. The three-stage cascaded linear equalizer has a variable amplitude-frequency gain and is used to compensate for channel loss;

[0007] The three-tap DFE equalizer adopts a half-rate architecture and is composed of odd and even signal processing branches and a final stage selector. Each branch includes: an adder, a limiting amplifier, a selector and a D flip-flop connected in sequence. A signal feedback path is provided between the corresponding taps of the D flip-flop and the adder. The odd and even signals pass through the final stage selector and are restored into a high-speed serial signal output under the control of the clock signal.

[0008] Optionally, the variable gain amplifier provides a variable low-frequency gain through a source-parallel resistor array, which is used to compensate for the low-frequency loss of the channel and adjust the amplitude of the input signal at the receiving end;

[0009] The variable gain amplifier includes:

[0010] A first load resistor R D 1, the first end of the first load resistor R D 1 is connected to the voltage source at the first end and the drain of the first NMOS transistor N1 at the second end;

[0011] A second load resistor R D 2, the first end of the second load resistor R D 2 is connected to the voltage source at the first end and the drain of the second NMOS transistor N2 at the second end;

[0012] A first NMOS transistor N1, the gate of the first NMOS transistor N1 is connected to the first input signal, the source is connected to the first current source I1, and the drain is connected to the first load resistor R D 1;

[0013] A second NMOS transistor N2, the gate of the second NMOS transistor N2 is connected to the second input signal, the source is connected to the second current source I2, and the drain is connected to the second load resistor R D 2;

[0014] A first current source I1, the first end of the first current source I1 is connected to the source of the first NMOS transistor N1, and the second end is grounded.

[0015] A second current source I2, the first end of the second current source I2 is connected to the source of the second NMOS transistor N2, and the second end is grounded.

[0016] The variable gain amplifier further includes: a source resistance array;

[0017] The source resistance array includes:

[0018] A first NMOS switch, including: a third NMOS transistor N3 and a fourth NMOS transistor N4, the gates of the third NMOS transistor N3 and the fourth NMOS transistor N4 are connected to a first voltage control word b0, the sources are connected to a first resistor R1, and the drains are respectively connected to the first current source I1 and the second current source I2;

[0019] A first resistor R1, with both ends respectively bridging between the sources of the third NMOS transistor N3 and the fourth NMOS transistor N4;

[0020] A second NMOS switch, including: a fifth NMOS transistor N5 and a sixth NMOS transistor N6, the gates of the fifth NMOS transistor N5 and the sixth NMOS transistor N6 are connected to a second voltage control word b1, the sources are connected to a second resistor R2, and the drains are respectively connected to the first current source I1 and the second current source I2;

[0021] A second resistor R2, with both ends respectively bridging between the sources of the fifth NMOS transistor N5 and the sixth NMOS transistor N6;

[0022] A third NMOS switch, including: a seventh NMOS transistor N7 and an eighth NMOS transistor N8, the gates of the seventh NMOS transistor N7 and the eighth NMOS transistor N8 are connected to a third voltage control word b2, the sources are connected to a third resistor R3, and the drains are respectively connected to the first current source I1 and the second current source I2;

[0023] A third resistor R3, with both ends respectively bridging between the sources of the seventh NMOS transistor N7 and the eighth NMOS transistor N8;

[0024] A fourth NMOS switch, including: a ninth NMOS transistor N9 and a tenth NMOS transistor N10, the gates of the ninth NMOS transistor N9 and the tenth NMOS transistor N10 are connected to a fourth voltage control word b3, the sources are connected to a fourth resistor R4, and the drains are respectively connected to the first current source I1 and the second current source I2;

[0025] A fourth resistor R4, with both ends respectively bridging between the sources of the ninth NMOS transistor N9 and the tenth NMOS transistor N10;

[0026] The resistance values of the source resistors are set in a ratio of 1:2:4:8.

[0027] Optionally, the CTLE equalizer includes:

[0028] The eleventh NMOS transistor N11, the gate of the eleventh NMOS transistor N11 is connected to the first input end of the CTLE equalizer, the source is connected to the third current source I3, and the drain is connected to the first PMOS transistor P1;

[0029] The twelfth NMOS transistor N12, the gate of the twelfth NMOS transistor N12 is connected to the second input end of the CTLE equalizer, the source is connected to the fourth current source I4, and the drain is connected to the second PMOS transistor P2;

[0030] The first variable resistor R S 1, the first end of the first variable resistor R S 1 is connected to the source of the eleventh NMOS transistor N11, the second end is connected to the source of the twelfth NMOS transistor N12, and the third end is connected to the control voltage VRctrl;

[0031] The variable capacitor C S 1, the variable resistor C S 1's first end is connected to the source of the eleventh NMOS transistor N11, the second end is connected to the source of the twelfth NMOS transistor N12, and the third end is connected to the control voltage VCctrl;

[0032] The fifth resistor R5, with both ends respectively bridging between the sources of the eleventh NMOS transistor N11 and the twelfth NMOS transistor N12;

[0033] The first load capacitor C L 1, the first end of the first load capacitor C L 1 is connected to the first output end of the CTLE equalizer, and the second end is grounded;

[0034] The second load capacitor C L 2, the first end of the second load capacitor C L 2 is connected to the second output end of the CTLE equalizer, and the second end is grounded;

[0035] The variable capacitor C S 1 and the first variable resistor R S 1 determine the zero and pole of the gain function, and the variable mid - and high - frequency gain is achieved by tuning the zero and pole of the circuit through the capacitance control voltage VRctrl and the resistance control voltage VCctrl. At the same time, the active inductor peaking technology is adopted to improve the peak gain of the equalizer;

[0036] The CTLE equalizer further includes: an active inductor circuit and a negative capacitance circuit; the active inductor circuit is connected to the load end of the CTLE equalizer for expanding the bandwidth of the CTLE equalizer; the negative capacitance circuit is connected to the output end of the CTLE equalizer for introducing an additional zero point to eliminate the negative effect of the first pole of the CTLE equalizer on the gain.

[0037] Optionally, the active inductor circuit includes:

[0038] A first capacitor C1, the first end of the first capacitor C1 is connected to a voltage source, and the second end is connected to the gate of a first PMOS transistor P1;

[0039] A second capacitor C2, the first end of the second capacitor C2 is connected to a voltage source, and the second end is connected to the gate of a second PMOS transistor P2;

[0040] A first PMOS transistor P1, the gate of the first PMOS transistor P1 is connected to the first capacitor C1, the source is connected to a voltage source, and the drain is connected to the drain of an eleventh NMOS transistor N11;

[0041] A second PMOS transistor P2, the gate of the second PMOS transistor P2 is connected to the second capacitor C2, the source is connected to a voltage source, and the drain is connected to the drain of a twelfth NMOS transistor N12;

[0042] A second variable resistor R S 2, the first end of the second variable resistor R S 2 is connected to the gate of the first PMOS transistor P1, the second end is connected to the drain of the first PMOS transistor P1, and the third end is connected to a tuning voltage V b ;

[0043] A third variable resistor R S 3, the first end of the third variable resistor R S 3 is connected to the gate of the second PMOS transistor P2, the second end is connected to the drain of the second PMOS transistor P2, and the third end is connected to a tuning voltage V b .

[0044] Optionally, the negative capacitance circuit includes:

[0045] A thirteenth NMOS transistor N13, the gate of the thirteenth NMOS transistor N13 is connected to the drain of a fourteenth NMOS transistor N14, the source is connected to a fifth current source I5, and the drain is connected to the first output end of the CTLE equalizer;

[0046] The fourteenth NMOS transistor N14, the gate of the fourteenth NMOS transistor N14 is connected to the drain of the thirteenth NMOS transistor N13, the source is connected to the sixth current source I6, and the drain is connected to the second output terminal of the CTLE equalizer;

[0047] The third capacitor C3, the first end of the third capacitor C3 is connected to the source of the thirteenth NMOS transistor N13, and the second end is connected to the source of the fourteenth NMOS transistor N14;

[0048] The fifth current source I5, the first end of the fifth current source I5 is connected to the source of the thirteenth NMOS transistor N13, and the second end is grounded;

[0049] The sixth current source I6, the first end of the sixth current source I6 is connected to the source of the fourteenth NMOS transistor N14, and the second end is grounded.

[0050] Optionally, the buffer adopts a two-stage drive structure, which is used to drive the subsequent DFE circuit and provide a sufficient voltage signal swing;

[0051] Both stages of the two-stage drive adopt a CML circuit structure. The first-stage buffer is used to improve the overall gain of the output buffer and isolate the previous-stage circuit from the second-stage buffer at the same time; the output terminal of the first-stage buffer is sequentially connected to the input terminal of the second-stage buffer.

[0052] Optionally, the adder is designed based on a CML circuit structure and is used to sum the input signal and the tap feedback signal.

[0053] Optionally, the selector is used to select and output two input signals under the control of a clock signal, and the last-stage selector is used to regenerate a high-speed serial signal from the odd and even signals again.

[0054] Optionally, the D flip-flop delays the output signal of the limiting amplifier by 1UI-3UI under the control of a clock signal and feeds it back to the first to third taps corresponding to the adder to eliminate the corresponding backward symbol tails.

[0055] The present invention also provides a high-speed serial signal equalization method, which is implemented based on the multi-stage equalizer of the receiver analog front-end of the above-mentioned high-speed serial link. The three-stage cascaded linear equalizer provides amplitude-frequency gain to achieve channel flattening. The three-tap DFE equalizer cooperates with the three-stage cascaded linear equalizer to further eliminate residual inter-symbol interference without amplifying noise.

[0056] The beneficial effects of the present invention are:

[0057] The present invention uses a combined equalization structure of a linear equalizer and a non - linear equalizer to compensate for channel loss in high - speed transmission, improve the post - symbol tail of the received signal, thereby greatly increasing the eye opening degree, time and voltage margins of the received signal, and achieving high - speed signal reception with a low bit error rate of 10 -12 The high - speed signal reception at a low bit error rate.

[0058] In the present invention, the active inductor peaking technology can be further adopted in the linear equalizer. Compared with the traditional passive inductor load, it greatly improves the circuit integration degree, saves the circuit layout area, and by changing the control voltage, the active inductor can provide variable impedance, improving the adaptability of the equalizer to the channel. The negative capacitance structure cascaded at the output end of the CTLE equalizer can neutralize the original first pole of the circuit by introducing additional zeros, further improving the gain - bandwidth compared with the traditional CTLE structure, thus greatly increasing the transmission rate of the system.

[0059] The non - linear DFE equalizer adopts the first - tap speculative structure, which has a shorter response time compared with the traditional DFE structure. Further, the DFE equalizer adopts a half - rate structure, thereby greatly broadening the timing constraints for high - speed signal equalization.

[0060] The present invention can achieve the equalization at the receiving end of high - speed serial signals, occupies a small area, is convenient for integration in the RX receiver, has low power consumption, has good stability, can compensate for large channel losses, and provides a feasible solution for solving the signal equalization problem of the SerDes high - speed serial link. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following - described drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0062] Figure 1 Schematically shows the upper - layer architecture diagram and circuit structure diagram of the linear equalizer circuit of the SerDes receiver analog front - end in the embodiment of the present invention.

[0063] Figure 2 Schematically shows the circuit structure diagram of a traditional differential amplifier.

[0064] Figure 3 Schematically shows the circuit structure diagram of a traditional CTLE equalizer.

[0065] Figure 4 Schematically shows the circuit structure diagram of a traditional single - stage CML.

[0066] Figure 5 Schematically shows the upper architecture diagram and circuit structure diagram of the decision feedback equalizer of the SerDes receiver analog front end in the embodiment of the present invention.

[0067] Figure 6 Schematically shows the amplitude-frequency gain curve diagram of the variable gain amplifier obtained by adjusting the voltage control word in the embodiment of the present invention.

[0068] Figure 7 Schematically shows the amplitude-frequency gain curve diagram of the linear equalizer obtained by adjusting the system zeros and poles in a certain PVT environment in the embodiment of the present invention.

[0069] Figure 8 Schematically shows the relationship diagram between the number of DFE taps and the eye opening degree at the receiving end in the embodiment of the present invention.

[0070] Figure 9 Schematically shows the post-layout simulation layout diagram of the SerDes receiver analog front end equalizer circuit in the embodiment of the present invention.

[0071] Figure 10 Schematically shows the channel loss curve diagram of the 12-inch FR-4 backplane channel in the embodiment of the present invention.

[0072] Figure 11 Schematically shows the signal eye diagram at the receiving end of the 25Gb / s SerDes high-speed serial link in the embodiment of the present invention, where (a) is the signal eye diagram at the receiving end without equalization, (b) is the signal eye diagram at the receiving end after passing through the linear equalizer, and (c) is the signal eye diagram at the receiving end after passing through the decision feedback equalizer.

[0073] Figure 12 (a) and (b) schematically show the time bathtub curve and voltage bathtub curve of the signal at the receiving end of the 25Gb / s SerDes high-speed serial link in the embodiment of the present invention before and after equalization.

[0074] The description of the reference numerals is as follows:

[0075] 1. Variable gain amplifier circuit, 101. First input terminal of the variable gain amplifier, 102. Second input terminal of the variable gain amplifier, 103. First NMOS switch, 104. Second NMOS switch, 105. Third NMOS switch, 106. Fourth NMOS switch, 107. First output terminal of the variable gain amplifier, 108. Second output terminal of the variable gain amplifier.

[0076] 2. CTLE Equalizer Circuit, 201. First Input Terminal of CTLE Equalizer, 202. Second Input Terminal of CTLE Equalizer, 203. First Input Terminal of Variable Resistor Control Voltage, 204. Input Terminal of Variable Capacitor Control Voltage, 205. Second Input Terminal of Variable Resistor Control Voltage, 206. Third Input Terminal of Variable Resistor Control Voltage, 207. First Output Terminal of CTLE Equalizer Circuit, 208. Second Output Terminal of CTLE Equalizer Circuit.

[0077] 3. Buffer Circuit, 301. First Input Terminal of Buffer, 302. Second Input Terminal of Buffer, 303. First Output Terminal of Buffer, 304. Second Output Terminal of Buffer.

[0078] 4. Source Negative Feedback Resistor.

[0079] 5. Source Degeneration RC Pair.

[0080] 6. DFE Adder.

[0081] 7. DFE Limiting Amplifier.

[0082] 8. DFE D Flip-Flop.

[0083] 9. DFE Selector.

[0084] R D 1. First Load Resistor, R D 2. Second Load Resistor, N1. First NMOS Transistor, N2. Second NMOS Transistor, N3. Third NMOS Transistor, N4. Fourth NMOS Transistor, N5. Fifth NMOS Transistor, N6. Sixth NMOS Transistor, N7. Seventh NMOS Transistor, N8. Eighth NMOS Transistor, N9. Ninth NMOS Transistor, N10. Tenth NMOS Transistor, R1. First Resistor, R2. Second Resistor, R3. Third Resistor, R4. Fourth Resistor, R5. Fifth Resistor, I1. First Current Source, I2. Second Current Source, b0. First Voltage Control Word, b1. Second Voltage Control Word, b2. Third Voltage Control Word, b3. Fourth Voltage Control Word.

[0085] N11. Eleventh NMOS Transistor, N12. Twelfth NMOS Transistor, R S 1. First Variable Resistor, R S 2. Second Variable Resistor, R S 3. Third Variable Resistor, C S1. Variable capacitor, C1, first capacitor, C2, second capacitor, C3, third capacitor, P1, first PMOS transistor, P2, second PMOS transistor, I3, third current source, I4, fourth current source; N13, thirteenth NMOS transistor, N14, fourteenth NMOS transistor, I5, fifth current source, I6, sixth current source, VRctrl, resistor control voltage, VCctrl, capacitor control voltage, V b , tuning voltage. CK, clock signal, T1, DFE first tap coefficient, T2, DFE second tap coefficient, T3, DFE third tap coefficient. Detailed implementation manners

[0086] To make the objectives, technical solutions and advantages of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0087] First, the basic knowledge related to the present invention will be described:

[0088] (1) Fully differential amplifier circuit. The structure of the traditional fully differential amplifier circuit is shown in Figure 2 , and the output power of the signal is increased under the condition that the waveform of the control output signal is consistent with the waveform of the input signal. In the traditional fully differential amplifier circuit, the source feedback resistor plays a role in stabilizing the static operating point, and the traditional fully differential amplifier circuit has a fixed amplitude-frequency gain. In the present invention, the variable gain amplifier is improved based on the traditional fully differential amplifier circuit. In order to achieve variable gain and improve the adaptability of the amplifier to channel loss, the variable gain amplifier uses a source resistor array to replace the source feedback resistor in the traditional fully differential amplifier circuit. The source resistor array has four groups of NMOS switches, and the first to fourth resistors R1 - R4 are respectively connected to the four groups of NMOS switches. The resistance values of the first to fourth resistors R1 - R4 are set in the ratio of 1:2:4:8, and four groups of voltage control words b0 - b3 respectively control the conduction states of the four groups of NMOS switches, further changing the impedance of the source resistor array to achieve the variable amplitude-frequency gain of the variable gain amplifier.

[0089] (2) CTLE equalizer circuit. The structure of the traditional CTLE circuit is shown in Figure 3 , and a source-degenerated RC pair forms a feedback network to achieve a closed-loop high-pass characteristic. The source-degenerated RC pair and the load capacitance resistor introduce two zeros and one pole to the traditional CTLE circuit together, and the gain and bandwidth of the traditional CTLE circuit structure are limited by the zeros and poles. In the present invention, the CTLE equalizer is improved based on the traditional CTLE circuit. The CTLE equalizer consists of a variable capacitor C S 1 and a variable resistor R S1 Replacing the general capacitors and resistors in the traditional CTLE circuit to form a source degeneration RC pair, and an external control voltage VCctrl and VRctrl are used to adjust the variable capacitor C S 1 and the variable resistor R S1 of the capacitive reactance value and impedance value, further adjusting the zero and pole points of the CTLE equalizer. In addition, the present invention designs an active inductor circuit based on the inductance peaking technology, and uses the impedance characteristics of the active inductor circuit to expand the bandwidth of the CTLE equalizer. Further, the CTLE equalizer circuit cascades a negative capacitance circuit at the output end, and introduces an additional zero point through the negative capacitance circuit to reduce the limitation of the first pole point of the CTLE equalizer on the gain.

[0090] (3) CML circuit. The structure of the traditional CML circuit can be seen in Figure 4 , the traditional CML circuit has relatively small switching noise, small signal rise time and fall time, and is suitable for processing high-speed signals. In the present invention, the buffer is improved and designed based on the traditional CML circuit, and is used to drive the subsequent DFE circuit to provide a sufficient voltage signal swing. The buffer circuit adopts a two-stage cascaded CML circuit structure. The first-stage buffer circuit is used to improve the overall gain of the buffer and isolate the previous-stage circuit from the second-stage buffer circuit at the same time. The second-stage buffer uses a PMOS load to replace the resistor load in the traditional CML circuit, and uses the impedance characteristics of the PMOS load to expand the bandwidth of the buffer.

[0091] Embodiment 1:

[0092] This embodiment provides a receiver analog front-end multi-stage equalizer for a high-speed serial link, including: a three-stage cascaded linear equalizer and a three-tap DFE equalizer, and the output end of the three-stage cascaded linear equalizer is sequentially connected to the input end of the three-tap DFE equalizer;

[0093] The three-stage cascaded linear equalizer includes: a variable gain amplifier, a CTLE equalizer and a buffer connected in sequence. The three-stage cascaded linear equalizer has a variable amplitude-frequency gain and is used to compensate for channel loss;

[0094] The three-tap DFE equalizer adopts a half-rate architecture and is composed of odd and even signal processing branches and a final-stage selector. Each branch includes: an adder, a limiting amplifier, a selector and a D flip-flop connected in sequence. A signal feedback path is provided between the D flip-flop and the corresponding tap of the adder. The odd and even signals pass through the final-stage selector and are restored into a high-speed serial signal output under the control of the clock signal.

[0095] Embodiment 2:

[0096] This embodiment provides a multi - stage equalizer for the receiver analog front - end of a high - speed serial link, including a three - stage cascaded linear equalizer and a three - tap DFE equalizer. The structure of the three - stage cascaded linear equalizer in this embodiment is shown in Figure 1 , and includes, connected in sequence: a variable - gain amplifier, a CTLE equalizer, and a buffer.

[0097] The variable - gain amplifier circuit is as shown in Figure 1 . Among them, the source - resistance array has four NMOS switch branches, which are respectively connected across the source of the first NMOS transistor N1 and the source of the second NMOS transistor N2. The first NMOS switch includes the third NMOS transistor N3 and the fourth NMOS transistor N4, which are controlled to conduct by the voltage control word b0, and the first resistor R1 is connected across the third NMOS transistor N3 and the fourth NMOS transistor N4. The second NMOS switch includes the fifth NMOS transistor N5 and the sixth NMOS transistor N6, which are controlled to conduct by the voltage control word b1, and the second resistor R2 is connected across the fifth NMOS transistor N5 and the sixth NMOS transistor N6. The third NMOS switch includes the seventh NMOS transistor N7 and the eighth NMOS transistor N8, which are controlled to conduct by the voltage control word b2, and the third resistor R3 is connected across the seventh NMOS transistor N7 and the eighth NMOS transistor N8. The fourth NMOS switch includes the ninth NMOS transistor N9 and the tenth NMOS transistor N10, which are controlled to conduct by the voltage control word b3, and the fourth resistor R4 is connected across the ninth NMOS transistor N9 and the tenth NMOS transistor N10.

[0098] By adjusting the conduction states of the four NMOS switch branches through four groups of voltage control words b0 - b3, the impedance value of the source - resistance array is further changed to adjust the gain of the variable - gain amplifier, compensate for the low - frequency loss of the FR - 4 channel, and adjust the amplitude of the input signal at the receiving end. The resistance values of R1 - R4 in the source - parallel resistance array are set in the ratio of 1:2:4:8 to provide an approximately linear gain change. The variable - gain amplifier provides a variable gain of - 2.2dB to 6.3dB in the frequency range of 0 - 20GHz. Figure 6 shows the amplitude - frequency gain curve of the variable - gain amplifier obtained by changing the source load.

[0099] The CTLE equalizer circuit is as shown in Figure 1 . Among them, the variable capacitor C S 1 and the first variable resistor R S 1 form a source - degeneration RC pair, and the capacitive reactance and impedance value are respectively adjusted by the externally connected control voltages VRctrl and VCctrl to further adjust the zero - poles of the continuous - time linear equalizer. The active - inductor circuit is as shown in Figure 1 , and includes PMOS transistors P1, P2, capacitors C1, C2 and variable resistors R S2 , R S3. Among them, the transconductance of the PMOS transistor is g m1 , and the equivalent impedance is r0. Capacitors C1 and C2 are respectively connected across the gates and sources of PMOS transistors P1 and P2. When the circuit operates in the low-frequency state, capacitors C1 and C2 can be regarded as open-circuit devices, enabling the active inductor to operate in the low-impedance mode. When the circuit operates in the high-frequency state, capacitors C1 and C2 are short-circuited to increase the impedance of the active inductor. The NMOS variable resistors R S2 , R S3 are respectively connected across the gates and drains of PMOS transistors P1 and P2, and the sources are connected to the tuning voltage V b to tune the impedance value of the PMOS active inductor. The impedance value of the active inductor can be described as:

[0100]

[0101] Among them, S represents the complex frequency variable, and R S2 represents the impedance values of the second and third variable resistors R S2 , R S3 , and C1 represents the capacitive reactance values of capacitors C1 and C2.

[0102] The transfer function of the CTLE equalizer in this embodiment can be described as:

[0103]

[0104] Among them, g m11 represents the transconductance of the eleventh and twelfth NMOS transistors N11 and N12, R5 represents the impedance of the fifth resistor R5, S represents the complex frequency variable, DC Gain represents the DC gain of the CTLE equalizer, C L represents the capacitive reactance of the first and second load capacitors C L1 and C L2 , C S represents the capacitive reactance of the variable capacitor C S1 , and R S represents the impedance of the first variable resistor R S1 .

[0105] The zero point W z1 and poles W P1 , W P2 of the CTLE equalizer in this embodiment can be described as:

[0106]

[0107] The DC gain DC Gain of the CTLE equalizer in this embodiment can be described as:

[0108]

[0109] The output end of the CTLE equalizer of this embodiment is connected to a negative capacitor circuit to introduce an additional zero point to eliminate the negative effect of the first pole of the CTLE equalizer on the gain. The equivalent impedance Z of the negative capacitor circuit is NegC Can be described as:

[0110]

[0111] Wherein, C3 represents the capacitive reactance of the third capacitor C3, C gs13 represents the gate-source capacitance of the thirteenth NMOS tube N13 and the fourteenth NMOS tube N14, S represents the complex frequency variable, g m13 It represents the transconductance of the thirteenth NMOS tube N13 and the fourteenth NMOS tube N14.

[0112] By controlling the voltage to tune the zero pole, the CTLE equalizer of this embodiment can achieve a peak gain of 10dB to 19dB near the Nyquist frequency of 12.5GHz. Figure 7 The amplitude-frequency gain curve of the CTLE equalizer obtained by changing the external control voltage under specific PVT process angle conditions is shown.

[0113] Buffers based on traditional CML structures such as Figure 1 As shown in , the buffer adopts a two-stage CML structure to drive the subsequent DFE circuit and provide sufficient voltage signal swing. The first stage circuit is used to improve the overall gain of the output buffer and isolate the previous stage from the second stage circuit.

[0114] The structure of the three-tap DFE equalizer of this embodiment is as follows: Figure 5 As shown, a half-rate structure is used to improve the signal processing rate, including data of two signal processing branches, wherein the output signal of the upper branch D flip-flop is fed back to the lower branch selector to provide a reference for the output signal of the lower branch selector, and the output signal of the lower branch D flip-flop is fed back to the upper branch selector to provide a reference for the output signal of the upper branch selector. Each branch includes: a current mode adder, a limiting amplifier, a selector and a D flip-flop connected in sequence, a signal feedback path is provided between the D flip-flop and the corresponding tap of the adder, and the odd and even signals are restored to a high-speed serial signal output under the control of the clock signal through the final selector.

[0115] The DFE equalizer is mainly used to eliminate the backward symbol tails and form a combined equalization structure with the linear equalizer to further reduce the impact of residual inter-symbol interference on the signal integrity at the receiving end. To solve the problem of the first-tap timing in high-speed signal equalization by the DFE, the DFE in this embodiment adopts a first-tap speculative structure: the feedback coefficient T1 of the first tap is no longer determined by the feedback signal of the D flip-flop in the current branch, but the limiting amplifier speculatively adds and subtracts the feedback coefficient T1 of the first tap during the sampling phase, and then the selector on the upper branch selects the output through the feedback signal of the D flip-flop on the lower branch. Similarly, the selector on the lower branch selects the output through the feedback signal of the D flip-flop on the upper branch. The said structure solves the timing problem in the signal processing of the DFE equalizer.

[0116] The adder is designed according to the CML structure and is used to sum the input signal and the tap feedback signal. The tap coefficient is controlled by the tail current and is converted into a voltage signal through a resistor. The said tap tail current can be adjusted according to the impulse response of the channel.

[0117] The limiting amplifier is used to quantify the output signal of the adder and is used as a 1-bit analog-to-digital converter. It outputs high and low level signals under the control of the clock signal.

[0118] The selector is used to select and output two input signals under the control of the clock signal, and the last-stage selector is used to regenerate one high-speed serial signal from the odd and even signals again.

[0119] The D flip-flop delays the output signal of the limiting amplifier by 1UI to 3UI under the control of the clock signal and feeds it back to the first to third taps of the adder to eliminate the corresponding backward symbol tails. Figure 8 Shows the influence of adjusting the number of DFE taps on the eye diagram opening of the signal at the receiving end, as Figure 8 shown, the optimization effect of the three-tap DFE on the eye diagram opening is the most significant. Continuing to increase the number of taps has little influence on the eye diagram opening and will increase the additional power consumption.

[0120] The post-layout simulation layout of the circuit in this embodiment is as Figure 9 shown, including the variable gain amplifier circuit, CTLE equalizer circuit, output buffer circuit, adder circuit, limiting amplifier circuit, D flip-flop and selector circuit. The post-layout simulation layout of the circuit includes 145 NMOS transistors, 20 PMOS transistors, 15 capacitors, and 36 resistors. The core circuit layout area of the circuit is 87μm long and 58μm wide, and the area is 0.005mm 2 , with a small occupied area, which is convenient for integration in the receiver chip.

[0121] Apply this embodiment to a SerDes receiver. The signal rate of the SerDes high-speed serial link transmitter is 25 Gb / s, the test signal pattern is PRBS15, and the modulation format is NRZ. The transmission channel is a 12-inch FR-4 backplane channel. Figure 10 Shows the insertion loss and return loss curves of the FR-4 backplane channel. Based on the analysis of the channel loss, adjust the control voltages VCctrl and VRctrl of the linear equalizer and the tuning voltage V b Compensate for the channel loss, and eliminate the residual inter-symbol interference from 1UI to 3UI of the received signal through the DFE equalizer.

[0122] To verify the beneficial effects of the present invention, an experiment was conducted. The parameters of the system in the experiment are shown in Table 1 below:

[0123] Table 1 Experimental parameters

[0124]

[0125]

[0126] The signal eye diagram obtained at the receiver end of the high-speed serial link in this simulation experiment is as Figure 11 shown. When using the linear equalizer of this embodiment for channel equalization alone, the horizontal opening of the received signal eye diagram is 0.46UI (1UI = 40 psec), and the vertical opening is 52 mV. When using the linear equalizer and the DFE equalizer of this embodiment for joint equalization, the horizontal opening of the received signal eye diagram is 0.71UI, and the vertical opening is 184 mV. It can be seen that the multi-stage equalizer of this embodiment can largely eliminate inter-symbol interference and improve the eye diagram opening (signal quality).

[0127] The signal bathtub curve obtained at the receiver end of the high-speed serial link in this simulation experiment is as Figure 12 shown. At a bit error rate of 10 -12 %, when using the linear equalizer and the DFE equalizer of this embodiment for joint equalization, the time margin of the received signal is 0.61UI, and the voltage margin is 171 mV. It can be seen that the multi-stage equalizer of this embodiment can largely improve the time and voltage margins of the received signal at a low bit error rate.

[0128] In summary, the experimental results show that this embodiment can well compensate for the channel loss in high-speed transmission, eliminate the inter-symbol interference caused by the non-ideal characteristics of the channel, and has a small circuit occupied area and high integration. It can compensate for a large channel loss with low power consumption and can be applied to the channel equalization in the SerDes high-speed signal receiver chip.

[0129] Some steps in the embodiments of the present invention can be implemented by software, and the corresponding software program can be stored in a readable storage medium, such as an optical disc or a hard disk, etc.

[0130] The above are only the preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A multi - stage equalizer for a receiver analog front - end of a high - speed serial link, characterized in that, Comprising: A three-stage cascaded linear equalizer and a three-tap DFE equalizer, the output end of the three-stage cascaded linear equalizer is sequentially connected to the input end of the three-tap DFE equalizer; The three-stage cascaded linear equalizer includes: a variable gain amplifier, a CTLE equalizer, and a buffer, which are sequentially connected. The three-stage cascaded linear equalizer has a variable amplitude-frequency gain for compensating channel loss; The three-tap DFE equalizer adopts a half-rate architecture and is composed of odd and even signal processing branches and a final stage selector. Each branch includes: an adder, a limiting amplifier, a selector, and a D flip-flop in sequence. A signal feedback path is provided between the D flip-flop and the corresponding tap of the adder. The odd and even signals pass through the final stage selector and are restored into a high-speed serial signal output under the control of a clock signal; The variable gain amplifier provides a variable low-frequency gain through a source-parallel resistor array for compensating the low-frequency loss of the channel and adjusting the amplitude of the input signal at the receiving end; The CTLE equalizer further includes: an active inductor circuit and a negative capacitance circuit; the active inductor circuit is connected to the load end of the CTLE equalizer for expanding the bandwidth of the CTLE equalizer; the negative capacitance circuit is connected to the output end of the CTLE equalizer for introducing an additional zero point to eliminate the negative effect of the first pole of the CTLE equalizer on the gain.

2. The multi-stage equalizer for a receiver analog front end of a high-speed serial link according to claim 1, wherein: The variable gain amplifier includes: The first load resistor R D 1. The first end of the first load resistor R D 1 is connected to a voltage source at its first end and to the drain of the first NMOS transistor N1 at its second end; The second load resistor R D 2. The first end of the second load resistor R D 2 is connected to a voltage source at its first end and to the drain of a second NMOS transistor N2 at its second end; The first NMOS transistor N1, the gate of the first NMOS transistor N1 is connected to a first input signal, the source is connected to a first current source I1, and the drain is connected to the first load resistor R D 1; The second NMOS transistor N2, the gate of the second NMOS transistor N2 is connected to a second input signal, the source is connected to a second current source I2, and the drain is connected to the second load resistor R D 2; A first current source I1, the first end of the first current source I1 is connected to the source of the first NMOS transistor N1, and the second end is grounded; A second current source I2, the first end of the second current source I2 is connected to the source of the second NMOS transistor N2, and the second end is grounded; The variable gain amplifier further includes: a source resistor array; The source resistor array includes: A first NMOS switch, including: a third NMOS transistor N3 and a fourth NMOS transistor N4. The gates of the third NMOS transistor N3 and the fourth NMOS transistor N4 are connected to a first voltage control word b0, the sources are connected to a first resistor R1, and the drains are respectively connected to the first current source I1 and the second current source I2; A first resistor R1, with both ends respectively bridging between the sources of the third NMOS transistor N3 and the fourth NMOS transistor N4; A second NMOS switch, including: a fifth NMOS transistor N5 and a sixth NMOS transistor N6. The gates of the fifth NMOS transistor N5 and the sixth NMOS transistor N6 are connected to a second voltage control word b1, the sources are connected to a second resistor R2, and the drains are respectively connected to the first current source I1 and the second current source I2; A second resistor R2, with both ends respectively bridging between the sources of the fifth NMOS transistor N5 and the sixth NMOS transistor N6; The third NMOS switch includes: a seventh NMOS transistor N7 and an eighth NMOS transistor N8. The gates of the seventh NMOS transistor N7 and the eighth NMOS transistor N8 are connected to a third voltage control word b2, the sources are connected to a third resistor R3, and the drains are respectively connected to the first current source I1 and the second current source I2; The third resistor R3 has its two ends respectively connected across the sources of the seventh NMOS transistor N7 and the eighth NMOS transistor N8; The fourth NMOS switch includes: a ninth NMOS transistor N9 and a tenth NMOS transistor N10. The gates of the ninth NMOS transistor N9 and the tenth NMOS transistor N10 are connected to a fourth voltage control word b3, the sources are connected to a fourth resistor R4, and the drains are respectively connected to the first current source I1 and the second current source I2; The fourth resistor R4 has its two ends respectively connected across the sources of the ninth NMOS transistor N9 and the tenth NMOS transistor N10; The resistance value of the source resistor is set in a ratio of 1:2:4:

8.

3. The multi-stage equalizer of the receiver analog front-end for a high-speed serial link according to claim 1, wherein The CTLE equalizer includes: An eleventh NMOS transistor N11. The gate of the eleventh NMOS transistor N11 is connected to the first input terminal of the CTLE equalizer, the source is connected to a third current source I3, and the drain is connected to a first PMOS transistor P1; A twelfth NMOS transistor N12. The gate of the twelfth NMOS transistor N12 is connected to the second input terminal of the CTLE equalizer, the source is connected to a fourth current source I4, and the drain is connected to a second PMOS transistor P2; The first variable resistor R S 1. The first terminal of the first variable resistor R S 1 is connected to the source of the eleventh NMOS transistor N11, the second terminal is connected to the source of the twelfth NMOS transistor N12, and the third terminal is connected to the control voltage VRctrl; Variable capacitor C S 1. The variable resistor C S 1. The first terminal of which is connected to the source of the eleventh NMOS transistor N11, the second terminal is connected to the source of the twelfth NMOS transistor N12, and the third terminal is connected to the control voltage VCctrl; A fifth resistor R5 has its two ends respectively connected across the sources of the eleventh NMOS transistor N11 and the twelfth NMOS transistor N12; The first load capacitor C L 1. The first end of the first load capacitor C L 1 is connected to the first output end of the CTLE equalizer, and the second end is grounded; Second load capacitor C L 2, the second load capacitor C L 2 has its first end connected to the second output terminal of the CTLE equalizer and its second end grounded; The variable capacitor C S 1 and the first variable resistor R S 1 determine the zero and pole points of the gain function, and the zero and pole points of the circuit are tuned through the capacitor control voltage VRctrl and the resistor control voltage VCctrl to achieve variable medium and high frequency gains. At the same time, the active inductor peaking technology is adopted to improve the peak gain of the equalizer.

4. The multi-stage equalizer of the receiver analog front end for a high-speed serial link according to claim 3, wherein The active inductor circuit includes: A first capacitor C1. The first end of the first capacitor C1 is connected to a voltage source, and the second end is connected to the gate of the first PMOS transistor P1; A second capacitor C2. The first end of the second capacitor C2 is connected to a voltage source, and the second end is connected to the gate of the second PMOS transistor P2; A first PMOS transistor P1. The gate of the first PMOS transistor P1 is connected to the first capacitor C1, the source is connected to the voltage source, and the drain is connected to the drain of the eleventh NMOS transistor N11; A second PMOS transistor P2. The gate of the second PMOS transistor P2 is connected to the second capacitor C2, the source is connected to the voltage source, and the drain is connected to the drain of the twelfth NMOS transistor N12; Second variable resistor R S 2. The first terminal of the second variable resistor R S 2 is connected to the gate of the first PMOS transistor P1, the second terminal is connected to the drain of the first PMOS transistor P1, and the third terminal is connected to the tuning voltage V b ; Third variable resistor R S 3. The first end of the third variable resistor R S 3 is connected to the gate of the second PMOS transistor P2, the second end is connected to the drain of the second PMOS transistor P2, and the third end is connected to the tuning voltage V b .

5. The multi-stage equalizer of the receiver analog front end for a high-speed serial link according to claim 3, wherein The negative capacitance circuit includes: A thirteenth NMOS transistor N13. The gate of the thirteenth NMOS transistor N13 is connected to the drain of a fourteenth NMOS transistor N14, the source is connected to a fifth current source I5, and the drain is connected to the first output terminal of the CTLE equalizer; A fourteenth NMOS transistor N14. The gate of the fourteenth NMOS transistor N14 is connected to the drain of the thirteenth NMOS transistor N13, the source is connected to a sixth current source I6, and the drain is connected to the second output terminal of the CTLE equalizer; A third capacitor C3. The first end of the third capacitor C3 is connected to the source of the thirteenth NMOS transistor N13, and the second end is connected to the source of the fourteenth NMOS transistor N14; A fifth current source I5, the first end of the fifth current source I5 is connected to the source of the thirteenth NMOS transistor N13, and the second end is grounded; A sixth current source I6, the first end of the sixth current source I6 is connected to the source of the fourteenth NMOS transistor N14, and the second end is grounded.

6. The multi-stage equalizer of the receiver analog front end for a high-speed serial link according to claim 1, wherein The buffer adopts a two-stage driving structure, which is used to drive the subsequent DFE circuit and provide a sufficient voltage signal swing; Both of the two-stage driving adopt the CML circuit structure. The first-stage buffer is used to improve the overall gain of the output buffer and isolate the previous-stage circuit from the second-stage buffer at the same time; the output end of the first-stage buffer is sequentially connected to the input end of the second-stage buffer.

7. The multi-stage equalizer of the receiver analog front end for a high-speed serial link according to claim 1, characterized in that The adder is designed based on the CML circuit structure and is used to sum the input signal and the tap feedback signal.

8. The multi-stage equalizer of the receiver analog front end for a high-speed serial link according to claim 1, characterized in that The selector is used to select and output two input signals under the control of a clock signal, and the last-stage selector is used to regenerate a high-speed serial signal from the odd and even signals again.

9. The multi-stage equalizer of the receiver analog front end for a high-speed serial link according to claim 1, characterized in that, The D flip-flop delays the output signal of the limiting amplifier by 1UI-3UI under the control of a clock signal and feeds it back to the first to third taps corresponding to the adder to eliminate the corresponding backward symbol tail.

10. A high-speed serial signal equalization method, characterized in that, The method is implemented based on the multi-stage equalizer of the receiver analog front end for a high-speed serial link according to any one of claims 1-9. The three-stage cascaded linear equalizer provides amplitude-frequency gain to achieve channel flattening. The three-tap DFE equalizer cooperates with the three-stage cascaded linear equalizer to further eliminate the residual inter-symbol interference without amplifying the noise.

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