Semiconductor processing chamber for deposition and etching

Abstract

An exemplary semiconductor substrate support can include a pedestal shaft. The semiconductor substrate support can include a platen. The platen can define a fluid channel across a first surface of the platen. The semiconductor substrate support can include a platen insulator positioned between the platen and the pedestal shaft. The semiconductor substrate support can include a conductive puck coupled with the first surface of the platen and configured to contact a substrate supported on the semiconductor substrate support. The semiconductor substrate support can include a conductive shield extending along a back surface of the platen insulator and coupled between a portion of the platen insulator and the pedestal shaft.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit and priority of U.S. Patent Application No. 17 / 014,195, filed September 8, 2020, entitled “SEMICONDUCTOR PROCESSING CHAMBERSFOR DEPOSITION AND ETCH”, which is incorporated herein by reference in its entirety.

[0003] This technology relates to the following applications, all filed simultaneously on September 8, 2020, entitled “SINGLECHAMBER FLOWABLE FILM FORMATION AND TREATMENTS” (Attorney’s File No.: 44018206US01(1190509)) and “SEMICONDUCTOR PROCESSING CHAMBERS FORDEPOSITION AND ETCH” (Attorney’s File No.: 44018254US01(1192137)). Each of these applications is incorporated herein by reference in its entirety for all purposes. Technical Field

[0004] This technology relates to semiconductor processing. More specifically, this technology relates to systems and methods for depositing and processing materials including flowable films. Background Technology

[0005] The fabrication of integrated circuits is made possible by processes that create complex patterned material layers on substrate surfaces. Creating patterned materials on a substrate requires controlled methods for forming and removing exposed materials. As device dimensions continue to shrink, material formation can impact subsequent operations. For example, in gap-filling operations, materials can be formed or deposited to fill trenches or other features formed on a semiconductor substrate. These filling operations can become challenging as features may be characterized by higher aspect ratios and reduced critical dimensions. For instance, continuous deposition can pinch off features, including between sidewalls within the feature, and may create voids within the feature, as deposition can occur on top of the feature and along its sidewalls. This can affect device performance and subsequent processing operations.

[0006] Therefore, there is a need for improved systems and methods that can be used to produce high-quality devices and structures. These and other needs are addressed by this technology. Summary of the Invention

[0007] An exemplary semiconductor substrate support may include a base shaft. The semiconductor substrate support may include a stage. The stage may define a fluid channel across a first surface of the stage. The semiconductor substrate support may include a stage insulator positioned between the stage and the base shaft. The semiconductor substrate support may include a conductive disk coupled to the first surface of the stage and configured to contact a substrate supported on the semiconductor substrate support. The semiconductor substrate support may include a conductive shield extending along a back surface of the stage insulator and coupled between a portion of the stage insulator and the base shaft.

[0008] In some embodiments, the support may include an insulating edge ring disposed on a recessed bracket of a conductive disk. The insulating edge ring may extend radially outward along the outer edge of the stage insulator. The insulating edge ring may contact a conductive shield. The conductive disk may include a coating along a surface configured to contact a substrate. The coating may extend along the recessed bracket on which the insulating edge ring is disposed. The coating may contain an insulating material similar to the insulating material constituting the insulating edge ring. The support may include a lifting rod assembly extending through the stage, the stage insulator, the conductive disk, and the conductive shield. The lifting rod assembly may include a lifting rod, a pad, a retainer, and a counterweight. A retainer may define a recess in which a portion of the stage insulator is disposed. The support may include an RF rod extending through a base shaft. The RF rod may be electrically coupled to the stage. The support may include a rod insulator extending about the RF rod along its length. The base shaft may be mounted on a hub, and the rod insulator may extend into the hub. The rod insulator may extend within a portion of the table insulator. The base shaft and the table insulator define a clean path that extends from the table insulator to the rod insulator. The clean path may continue along the interior and exterior of the rod insulator.

[0009] Some embodiments of this technology may cover a semiconductor processing system. The system may include a chamber body. The system may include a substrate support configured to support a semiconductor substrate. The substrate support may include a base shaft. The substrate support may include a stage defining a fluid channel across a first surface of the stage. The substrate support may include a stage insulator positioned between the stage and the base shaft. The substrate support may include a conductive disk coupled to the first surface of the stage and configured to contact the substrate supported on the semiconductor substrate. The substrate support may include a conductive shield extending along a back surface of the stage insulator and coupled between a portion of the stage insulator and the base shaft. The system may include a panel. The chamber body, the substrate support, and the panel define a processing area. The system may include a high-frequency plasma source coupled to the panel. The system may include a low-frequency plasma source coupled to the substrate support.

[0010] In some embodiments, the substrate support may include an electrostatic chuck. The semiconductor processing system may include a DC power supply coupled to the substrate support. A low-frequency plasma source may be configured to operate at less than or about 2 MHz. A high-frequency plasma source may be configured to operate at a pulse frequency greater than or about 13.56 MHz, less than or about 20 kHz, and a duty cycle less than or about 20%. The high-frequency plasma source may be configured to generate plasma with an effective power of less than or about 5 W. The system may include an insulating edge ring disposed on a recessed wall of a conductive disk. The insulating edge ring may extend radially outward along the outer edge of a stage insulator. The insulating edge ring may contact a conductive shield. The conductive disk may include a coating along a surface configured to contact the substrate. The coating may extend along the recessed wall on which the insulating edge ring is disposed. The system may include a first LC filter coupled to the substrate support and configured to virtually ground the high-frequency plasma source through the substrate support. The system may include a second LC filter, which is coupled to the panel and configured to virtually ground the low-frequency plasma source to the chamber body.

[0011] This technology offers several advantages over conventional systems and techniques. For example, improved cooling and plasma management can be provided by utilizing a substrate support according to this technology. Furthermore, repeatable plasma generation can be achieved during the deposition operation by performing deposition according to embodiments of this technology. These and other embodiments, along with their many advantages and features, are described in more detail below with reference to the accompanying drawings. Attached Figure Description

[0012] The nature and advantages of the disclosed technology can be further understood by referring to the rest of the specification and the accompanying drawings.

[0013] Figure 1 The figure shows a schematic cross-sectional view of an exemplary processing chamber according to some embodiments of the present technology.

[0014] Figure 2 A schematic partial cross-sectional view of a chamber according to some embodiments of the present technology is shown.

[0015] Figure 3 A schematic partial cross-sectional view of a substrate support assembly according to some embodiments of the present technology is shown.

[0016] Figure 4 A schematic partial cross-sectional view of a substrate support assembly according to some embodiments of the present technology is shown.

[0017] Figure 5 A schematic partial cross-sectional view of a substrate support assembly according to some embodiments of the present technology is shown.

[0018] Figures 6A to 6C A schematic partial cross-sectional view of a substrate support assembly according to some embodiments of the present technology is shown.

[0019] Figure 7 Exemplary operations in processing methods according to some embodiments of the present technology are shown.

[0020] Several accompanying drawings are included for illustrative purposes. It should be understood that the drawings are for illustrative purposes and should not be considered to scale unless specifically illustrated to scale. Furthermore, as illustrative drawings are provided to aid understanding and may not contain all aspects or information compared to a realistic representation, and may contain exaggerated material for illustrative purposes.

[0021] In the accompanying drawings, similar parts and / or features may have the same reference numerals. Furthermore, parts of the same type may be distinguished by a letter following the reference numeral to differentiate between similar parts. If only the first reference numeral is used in the description, the description applies to any of the similar parts having the same first reference numeral, regardless of the lettering. Detailed Implementation

[0022] In semiconductor device fabrication, amorphous silicon can be used in many structures and processes, including as a sacrificial material, such as a dummy gate material, or as a trench fill material. In gap-filling operations, some processes can utilize a flowable film formed under processing conditions to constrain the conformal nature of the deposition, allowing the deposited material to better fill features on the substrate. Flowable silicon materials are characterized by a relatively large amount of hydrogen and may be less dense than other formed films. Therefore, subsequent processing operations can be performed to cure the produced film. Conventional techniques utilize UV ​​curing processes to remove hydrogen and process the film. However, UV curing can cause significant film shrinkage, which can stress features and create voids within the structure. Furthermore, the processing is performed in a chamber separate from the deposition chamber, which reduces yield due to increased processing time.

[0023] As feature sizes continue to shrink, flowable films may face challenges with narrow features, potentially leading to even higher aspect ratios. For example, feature clamping may be more likely to occur due to deposition on the sidewalls of the feature, which could further restrict further inflow into the feature at small feature sizes and may create voids. Some conventional flowable film formation can be performed by generating radicals in remotely capacitively coupled plasma regions or in remotely coupled plasma source units to a chamber. However, for the cyclic formation of high aspect ratio features, this process may provide unreliable deposition. For example, recombination may challenge a consistent supply of radical effluent as radicals pass through chamber components (such as panels). Furthermore, remote plasma sources may fail to limit the amount of deposition within small-pitch features. This could lead to over-deposition within the feature, which could then limit or prevent complete penetration of the processed effluent. This can cause damage during subsequent processing, potentially resulting in substrate scrap.

[0024] This technology overcomes these limitations by decoupling high-frequency and low-frequency power supplies and utilizing trigger sequences that allow for low-power, repeatable plasma generation over short periods. This limits deposition during trench filling to a tightly controlled amount and ensures processing is completed during subsequent processing operations. Furthermore, this technology can be combined with a substrate support assembly that better controls temperature drift during processing operations, increasing the guarantee of stable and repeatable temperatures for each deposition cycle. After describing general aspects of a chamber (where plasma processing operations discussed below can be performed) according to some embodiments of this technology, specific chamber configurations and methods can be discussed. It should be understood that this technology is not intended to be limited to the specific films, chambers, and processes discussed, as the described techniques can be used to improve many film formation processes for any number of materials and can be applied to a wide variety of processing chambers and operations.

[0025] Figure 1The figure illustrates a cross-sectional view of an exemplary processing chamber 100 according to some embodiments of the present technology. The figure may illustrate an overview of a system incorporating one or more aspects of the present technology, and / or a system in which one or more deposition or other processing operations according to embodiments of the present technology can be performed. Additional details of the chamber 100 or the methods performed are further described below. According to some embodiments of the present technology, the chamber 100 can be used to form a film layer; however, it should be understood that the methods can be similarly performed in any chamber in which film formation may occur. The processing chamber 100 may include a chamber body 102, a substrate support 104 disposed within the chamber body 102, and a cover assembly 106 coupled to the chamber body 102 and enclosing the substrate support 104 in a processing space 120. A substrate 103 can be provided to the processing space 120 through an opening 126, which can be conventionally sealed using a slit valve or door for processing. During processing, the substrate 103 can be placed on a surface 105 of the substrate support. As indicated by arrow 145, the substrate support 104 can be rotated along axis 147, and axis 144 of the substrate support 104 can be located at axis 147. Alternatively, the substrate support 104 can be lifted and rotated as needed during the deposition process.

[0026] A plasma profile modulator 111 may be disposed in the processing chamber 100 to control the plasma distribution on the substrate 103 disposed on the substrate support 104. The plasma profile modulator 111 may include a first electrode 108, which may be disposed adjacent to the chamber body 102 and may separate the chamber body 102 from other components of the cover assembly 106. The first electrode 108 may be part of the cover assembly 106 or may be a separate sidewall electrode. The first electrode 108 may be annular or ring-shaped, and may be a ring electrode. The first electrode 108 may be a continuous ring around the circumference of the processing chamber 100 surrounding the processing space 120, or may be discontinuous at selected locations if desired. The first electrode 108 may also be a perforated electrode, such as a perforated ring or mesh electrode, or may be a flat electrode, such as, for example, a secondary gas distributor.

[0027] One or more isolators 110a, 110b, which may be dielectric materials, may contact the first electrode 108 and electrically and thermally isolate the first electrode 108 from the gas distributor 112 and the chamber body 102. The dielectric material may be, for example, ceramic or metal oxide, such as alumina and / or aluminum nitride. The gas distributor 112 may define an orifice 118 for dispensing the processing precursor into the processing space 120. The gas distributor 112 may be coupled to a first power source 142, such as an RF generator, RF power supply, DC power supply, pulsed DC power supply, pulsed RF power supply, or any other power source that may be coupled to the processing chamber. In some embodiments, the first power source 142 may be an RF power supply.

[0028] The gas distributor 112 can be a conductive gas distributor or a non-conductive gas distributor. The gas distributor 112 can also be formed from conductive and non-conductive components. For example, the body of the gas distributor 112 can be conductive, while the panel of the gas distributor 112 can be non-conductive. The gas distributor 112 can be, for example, made of... Figure 1 The gas distributor 112 may be grounded, either by the first power source 142 shown or by grounding in some embodiments.

[0029] The first electrode 108 may be coupled to a first tuning circuit 128, which controls the grounding path of the processing chamber 100. The first tuning circuit 128 may include a first electronic sensor 130 and a first electronic controller 134. The first electronic controller 134 may be or include a variable capacitor or other circuit elements. The first tuning circuit 128 may be or include one or more inductors 132. The first tuning circuit 128 may be any circuit that implements variable or controllable impedance under plasma conditions present in the processing space 120 during processing. In some embodiments shown, the first tuning circuit 128 may include a first circuit branch and a second circuit branch coupled in parallel between ground and the first electronic sensor 130. The first circuit branch may include a first inductor 132A. The second circuit branch may include a second inductor 132B coupled in series with the first electronic controller 134. The second inductor 132B may be disposed between the first electronic controller 134 and a node connecting both the first and second circuit branches to the first electronic sensor 130. The first electronic sensor 130 may be a voltage or current sensor and may be coupled to the first electronic controller 134, which may provide a certain degree of closed-loop control over the plasma conditions within the processing space 120.

[0030] The second electrode 122 may be coupled to the substrate support 104. The second electrode 122 may be embedded within the substrate support 104 or coupled to the surface of the substrate support 104. The second electrode 122 may be any other distributed arrangement of a plate, perforated plate, mesh, wire mesh, or conductive element. The second electrode 122 may be a tuning electrode and may be coupled to a second tuning circuit 136 via, for example, a conduit 146 disposed in a shaft 144 of the substrate support 104, the conduit 146 being, for example, a cable having a selected resistance (such as 50 ohms). The second tuning circuit 136 may have a second electronic sensor 138 and a second electronic controller 140, the second electronic controller 140 being a second variable capacitor. The second electronic sensor 138 may be a voltage or current sensor and may be coupled to the second electronic controller 140 to provide further control over the plasma conditions in the processing space 120.

[0031] A third electrode 124, which may be a bias electrode and / or an electrostatic chuck electrode, may be coupled to a substrate support 104. The third electrode may be coupled to a second power source 150 via a filter 148, which may be an impedance matching circuit. The second power source 150 may be DC power, pulsed DC power, RF bias power, pulsed RF source or bias power, or a combination of these or other power sources. In some embodiments, the second power source 150 may be RF bias power.

[0032] Figure 1 The cover assembly 106 and substrate support 104 can be used with any processing chamber for plasma or heat treatment. In operation, the processing chamber 100 can provide real-time control of plasma conditions within the processing space 120. A substrate 103 can be mounted on the substrate support 104, and processing gas can be allowed to flow through the cover assembly 106 using the inlet 114 according to any desired flow pattern. The gas can exit the processing chamber 100 through the outlet 152. Electricity can be coupled to the gas distributor 112 to establish plasma in the processing space 120. In some embodiments, a third electrode 124 can be used to subject the substrate to an electrical bias.

[0033] When stimulating the plasma in the processing space 120, a potential difference can be established between the plasma and the first electrode 108. A potential difference can also be established between the plasma and the second electrode 122. Electronic controllers 134 and 140 can then be used to adjust the flow characteristics of the ground path represented by two tuning circuits 128 and 136. Setpoints can be fed to the first tuning circuit 128 and the second tuning circuit 136 to provide independent control over the deposition rate and plasma density uniformity from center to edge. In embodiments where the electronic controllers can both be variable capacitors, electronic sensors can adjust the variable capacitors to independently maximize the deposition rate and minimize thickness non-uniformity.

[0034] Each of the tuning circuits 128 and 136 may have a variable impedance that can be adjusted using a corresponding electronic controller 134 or 140. When the electronic controllers 134 and 140 are variable capacitors, the capacitance range of each of the variable capacitors and the inductance of the first inductor 132A and the second inductor 132B can be selected to provide an impedance range. This range may depend on the frequency and voltage characteristics of the plasma, and may have a minimum value within the capacitance range of each variable capacitor. Therefore, when the capacitance of the first electronic controller 134 is at its minimum or maximum value, the impedance of the first tuning circuit 128 may be high, resulting in a minimum air or lateral coverage of the plasma shape on the substrate support. When the capacitance of the first electronic controller 134 approaches the value that minimizes the impedance of the first tuning circuit 128, the air coverage of the plasma can increase to its maximum, effectively covering the entire operating area of ​​the substrate support 104. When the capacitance of the first electronic controller 134 deviates from the minimum impedance setting, the plasma shape may shrink from the chamber wall and the air coverage of the substrate support may decrease. The second electronic controller 140 can have a similar effect, increasing or decreasing the air coverage of plasma on the substrate support as the capacitance of the second electronic controller 140 may be changed.

[0035] Electronic sensors 130 and 138 can be used to tune the respective circuits 128 and 136 in a closed loop. Depending on the type of sensor used, a setpoint for current or voltage can be installed in each sensor, and the sensor can be equipped with control software that determines adjustments to each corresponding electronic controller 134 and 140 to minimize deviations from the setpoint. Therefore, the plasma shape can be selected and dynamically controlled during processing. It should be understood that although the foregoing discussion is based on electronic controllers 134 and 140, which may be variable capacitors, any electronic component with adjustable characteristics can be used to provide adjustable impedance for tuning circuits 128 and 136.

[0036] Figure 2The illustration shows a schematic partial cross-sectional view of a processing chamber 200 according to some embodiments of the present technology. The chamber 200 may include any features, components, or characteristics of the processing chamber 100 described above, and may show additional features of the chamber, including a specific power supply coupled to the chamber. For example, the chamber 200 may include a chamber body 205. The chamber may include a substrate support 210, which may be configured to support a substrate during semiconductor processing. The chamber may include a panel 215, which, together with the base and the chamber body, may define a processing area above the substrate being processed.

[0037] Some conventional processing systems generate plasma within the processing area by applying power to the panel while grounding the base, or by applying source power to the base and grounding the panel. In some systems, an additional bias power supply can be coupled to the base to increase the directionality of the plasma effluent. It should be understood that a separate DC power supply for electrostatic adsorption can be coupled to the base, as described above for processing chamber 100, which, in addition to adsorbing the substrate, can also be operated to further bias the plasma generated in the processing chamber. This technique differs from conventional configurations by coupling two separate plasma power supplies to the nozzle and base as shown. For example, a first plasma power supply 220 can be coupled to the nozzle, while a second plasma power supply 230 can be coupled to the base. In some embodiments, the first plasma power supply 220 can be a high-frequency plasma power supply, while the second plasma power supply 230 can be a low-frequency plasma power supply. In some embodiments, the low-frequency plasma power supply 230 can be separate from the DC power supply, which can be used to electrostatically couple the substrate to the base.

[0038] The low-frequency plasma power supply can operate at a first frequency of less than or about 2 MHz, and can operate at frequencies of less than or about 1.5 MHz, less than or about 1.0 MHz, less than or about 800 kHz, less than or about 600 kHz, less than or about 500 kHz, less than or about 400 kHz, less than or about 350 kHz, less than or about 300 kHz, less than or about 250 kHz, less than or about 200 kHz, or lower. The high-frequency plasma power supply can operate at a second frequency of greater than or about 2 MHz, and can be greater than or about 10 MHz, greater than or about 13 MHz, such as 13.56 MHz, greater than or about 15 MHz, greater than or about 20 MHz, greater than or about 40 MHz, or higher.

[0039] Additional aspects of the plasma source can be used to further tune the plasma generated within the processing area. For example, a chamber according to embodiments of the present technology can be used to fill high aspect ratio features, wherein discrete amounts of deposition can be generated to limit void formation within the filled feature. Conventional chambers may be limited in reducing plasma power due to the inability to generate repeatable low-power plasma within a limited time period. The present technology can be used to produce material layers characterized by a thickness of less than or about 10 nm per cycle. To achieve this limited deposition, the deposition cycle can be limited, or the power used during deposition can be reduced. Conventional systems may not be able to reduce plasma power to less than or about 100 W, which could increase the amount of deposited material, and shortening the formation cycle to accommodate such higher power may limit the ability to generate repeatable plasma during multi-cycle deposition.

[0040] This technology overcomes these problems by generating low-power deposition plasma, characterized by an effective plasma power of less than or about 20 W, and further characterized by an effective plasma power of less than or about 15 W, less than or about 10 W, less than or about 8 W, less than or about 6 W, less than or about 5 W, less than or about 4 W, less than or about 3 W, or even lower. To generate such a low-power plasma during deposition, the system can operate at a high-frequency plasma power with a pulse frequency of less than or about 200 kHz, and can operate the plasma power with pulse frequencies of less than or about 150 kHz, less than or about 100 kHz, less than or about 80 kHz, less than or about 70 kHz, less than or about 60 kHz, less than or about 50 kHz, less than or about 40 kHz, less than or about 30 kHz, less than or about 20 kHz, less than or about 10 kHz, or even lower. Furthermore, and at any of the pulse frequencies mentioned, the high-frequency plasma power supply can operate with a reduced duty cycle, which can be less than or about 50%, and can be less than or about 45%, less than or equal to about 40%, less than or about 35%, less than or about 30%, less than or about 25%, less than or about 20%, less than or about 15%, less than or about 10%, less than or about 5%, or less.

[0041] In some embodiments, reduced pulse frequency and duty cycle may consistently challenge plasma generation. Low-power plasma, once generated, may result in low-rate deposition, limiting deposition per cycle; however, ignition may be challenged. Therefore, in some embodiments, plasma power may be operated in conjunction with a trigger sequence to facilitate plasma generation during deposition. For example, as described above, in some embodiments, deposition operations can be performed without a low-frequency plasma power source. However, in some embodiments during deposition operations, a low-frequency plasma power source may be operated to facilitate ignition. Furthermore, the low-frequency plasma power source may not be operated, and a power spike may be applied to a high-frequency plasma power source to facilitate ignition. The power spike may be applied directly through power management or through level-to-level operation of the high-frequency plasma power source.

[0042] A low-frequency plasma power supply can also be operated to control plasma formation and ion directionality during processing. By delivering low-frequency plasma power via the base, the plasma shell formed at the energized electrodes can facilitate the directionality of ion entry into the densified features. The low-frequency plasma power supply can operate at either the power levels described above or the pulse frequency, although in some embodiments, the second power supply 230 can operate at a greater plasma power than the first power supply 220 during processing. For example, the plasma power delivered by the second power supply during processing can be greater than or about 50 W, and can be greater than or about 100 W, greater than or about 200 W, greater than or about 300 W, greater than or about 400 W, greater than or about 500 W, greater than or about 600 W, greater than or about 700 W, greater than or about 800 W, or greater. By increasing the plasma power of the low-frequency power supply during plasma formation, a larger amount of plasma effluent can be generated. Applying greater low-frequency power from the base can increase the directionality of the delivery perpendicular to the plane spanning the substrate.

[0043] Additional adjustments can be made to further enhance the etching of deposited material along the sidewalls of the feature by modifying one or more characteristics of the provided plasma power or bias power. For example, in some embodiments, both the plasma power supply and the bias power supply can operate in continuous wave mode. Furthermore, one or both power supplies can operate in pulsed mode. In some embodiments, during processing, the high-frequency power supply can operate in either continuous wave or pulsed mode, while the low-frequency power supply can operate in pulsed mode. The pulse frequency of the low-frequency plasma power supply can be less than or about 1,000 Hz, and can be less than or about 900 Hz, less than or about 800 Hz, less than or about 700 Hz, less than or about 600 Hz, less than or about 500 Hz, less than or about 400 Hz, less than or about 300 Hz, less than or about 200 Hz, less than or about 100 Hz, or less. The duty cycle of the second power supply can be less than or about 50%, and the low-frequency plasma power can be operated at a duty cycle of less than or about 45%, less than or about 40%, less than or about 35%, less than or about 30%, less than or about 25%, less than or about 20%, less than or about 15%, less than or about 10%, less than or about 5%, or even lower. By operating the low-frequency power supply at a reduced duty cycle (such as a conduction time duty cycle of less than or about 50%), more time per cycle can be used to perform more isotropic etching within the feature based on the operation of the high-frequency power supply, which allows for better material removal from the sidewalls during densification operations.

[0044] The first plasma power source 220 can be virtually grounded via a base. For example, as shown, the first LC filter 225 can be coupled to the base and can virtually ground the high-frequency plasma source via the base. Similarly, the second plasma power source 230 can be grounded via the chamber. For example, the second LC filter can be coupled to a panel that can virtually ground the low-frequency plasma source, such as by connecting it to the chamber body or an external ground. By separating the high-frequency and low-frequency power sources, improved plasma generation and operation can be provided.

[0045] Figure 3 A schematic partial cross-sectional view of a substrate support assembly 300 according to some embodiments of the present technology is shown. As explained above, the present technology can be used in some embodiments to perform cryogenic deposition and curing within a single chamber. Configuring a semiconductor support assembly for cryogenic operation at low plasma power can present several challenges. For example, when using an electrostatic chuck, the substrate support surface or disk can be a dielectric material including electrodes. Electrodes that may include multiple electrodes can be one or both of adsorption electrodes that can be coupled to a DC power supply and plasma generation electrodes that can be coupled to an RF power supply.

[0046] A substrate support assembly according to some embodiments of the present technology may include a low-frequency power supply coupled to the substrate support assembly as discussed above. The substrate support assembly may also be configured to maintain the substrate at the temperature used for both deposition and processing operations. A substrate support assembly according to some embodiments of the present technology can overcome temperature gradients caused by dielectric materials by maintaining a conductive disk in contact with the substrate or by forming a thin coating of dielectric material across the surface of the conductive disk. Based on the low-level plasma processing performed according to some embodiments of the present technology, attention to substrate movement can be limited, thus eliminating the need for electrostatic chucks. Therefore, in some embodiments, the disk may be conductive, which can improve heat transfer and cooling of the substrate. Plasma performance may also affect substrate temperature. For example, the present technology may include the cyclic formation and processing of flowable films. Conventional techniques allow the substrate to be moved between two chambers where deposition and processing are performed separately, which can help ensure that the substrate remains at a set point temperature during each deposition operation. Since temperature can affect deposition rates and film flow characteristics, maintaining a consistent substrate temperature for each deposition cycle can improve film formation through characteristics.

[0047] Because this technique generates processing plasma within the same processing chamber where deposition occurs, cooling the substrate back to the deposition setpoint can be problematic due to plasma exposure during processing. While deposition plasma can occur at low plasma power, processing can be performed at much higher plasma power from the source plasma—potentially ten times or more—and this can increase the thermal load on the substrate. This can cause the substrate temperature to rise significantly more during processing than it might during deposition. This technique improves cooling by increasing heat transfer to the back of the substrate through a cooler conductive surface that is in contact with the wafer or has a thin coating therebetween.

[0048] The substrate support assembly 300 may be similar to substrate support 104 or substrate support 210 and may include any features, components, or characteristics of those supports, including any associated components or power sources. The substrate support assembly 300 may include a base shaft 305, which may be made of a conductive material. The worktable 310 may define one or more fluid channels 309 in its surface. The fluid channels 309 may include one or more channels, such as spirals or other meandering patterns, which may be coupled to a fluid source via inlet and outlet channels through the shaft. In embodiments, the fluid source may include a cooling or heating fluid, including a cooler to further reduce the fluid temperature. The substrate support may be configured to maintain a temperature below or about 100°C, and in some embodiments may be configured to maintain a temperature below or about 80°C, below or about 60°C, below or about 40°C, below or about 20°C, below or about 0°C, below or about -5°C, below or about -10°C, below or about -15°C, below or about -20°C, below or about -25°C, or lower.

[0049] A table insulator 315 may be disposed between the table 310 and the base shaft 305, and the table insulator 315 may extend completely around the table 310. In some embodiments, the table 310 may be completely recessed within the volume defined by the insulator 315. The base shaft 305 and the table 310 may each be made of a conductive material, such as a metal like aluminum or any other material that is thermally and / or electrically conductive. The disk 320 may be coupled to the table 310, and in some embodiments may also be made of aluminum or some other conductive material. In some embodiments, a substrate may be in direct contact with the disk, and in some embodiments, a coating may be formed between the disk and the substrate. A conductive shield 325 may extend along a surface of the table insulator 315 opposite to the surface on which the table 310 may be mounted. For example, the conductive shield 325 may be coupled between a portion of the table insulator 315 and the base shaft 305.

[0050] The substrate support assembly 300 may include one or more lifting rod assemblies 335 extending through the conductive shield, the stage insulator, the stage, and the conductive disk. In some embodiments, an insulating edge ring 330 may be mounted on a recessed bracket defined on the disk and extending around the outer edge of the disk. As shown, the edge ring 330 may extend radially outward along the outer edge of the stage insulator 315, and in some embodiments may extend over and contact the outer edge of the conductive shield 325. Thus, in some embodiments, the conductive stage and disk may be completely insulated from the conductive shield and the base shaft to limit or prevent short circuits between components. The conductive shield (which may all be made of conductive material) coupled to the base shaft may provide a more symmetrical grounding path for the high-frequency plasma power supply, which may improve plasma uniformity in some embodiments. Extending through the stage may be an RF rod 340, which may be coupled to an RF matching element of the low-frequency power supply as discussed above. A base shaft 305 may be mounted on a hub 345, and an RF rod 340 may extend through the hub 345. The RF rod 340 may have a rod insulator 350 extending around the RF rod, and the rod insulator 350 may extend along with the RF rod through each of the hub 345, the base shaft 305, the stage insulator 315, and the stage 310. By extending the rod insulator 350 along the length of the RF rod and into the hub, an RF leakage path to the base shaft can be prevented at the hub.

[0051] At the other end of the RF rod 340, the RF rod can be coupled to a conductive stage 310, which can serve as a plasma electrode. As will be further explained below, in embodiments where the dielectric coating extends along the disk 320, the conductive stage can also serve as an adsorption electrode. Because the stage itself can serve as an electrode, in some embodiments, the RF rod 340 can be recessed into a connection socket formed in the stage. The connection can be any type of connector, including Multilam or other multi-contact connectors on the RF rod. As shown, the rod insulator 350 can extend at least partially within the stage insulator 315. The stage insulator and rod insulator can be operated to completely enclose the RF rod 340 extending through the substrate support assembly into the processing chamber, which can further reduce or limit leakage paths that could otherwise lead to stray arcing. These components will be further described below.

[0052] Figure 4A schematic partial cross-sectional view of a substrate support assembly 300 according to some embodiments of the present technology is shown, and additional features of the assembly may be illustrated. As described above, in some embodiments, the disk 320 may be in direct contact with the substrate being processed. Furthermore, in some embodiments, a dielectric coating may be formed covering the surface of the disk. By forming a dielectric layer between the disk and the substrate being processed, the disk can operate as an electrostatic chuck. The coating may also be adapted to features of the substrate support assembly. For example, a recessed bracket 403 may be formed at the outer edge of the disk 320, and an edge ring may be disposed on the recessed bracket 403. Furthermore, a countersunk hole 405 for the lifting rod assembly may be formed to extend through the worktable 310 and the disk 320. A coating 410 may be formed on the substrate support surface of the disk 320 and may be conformally formed to extend across the recessed bracket to the outer edge of the disk. The coating 410 may also extend along the sidewall 412 of the hole 405, such as along the smaller inner diameter portion of the countersunk hole. In some embodiments, this may help prevent gas ignition at the lifting rod hole.

[0053] Electrostatic chucks typically have a dielectric disk, which can generate temperature increments and potentially lead to RF leakage through the disk. In low-power plasma processing according to some embodiments of this technology, the dielectric disk can further challenge plasma generation due to losses through the disk. To limit the effects of these losses, this technology alternatively forms a dielectric coating, in some embodiments of which may be maintained at a thickness of less than or about 1 mm, and may be maintained at a thickness of less than or about 800 μm, less than or about 600 μm, less than or about 500 μm, less than or about 400 μm, less than or about 300 μm, less than or about 200 μm, or less, although a thickness greater than or about 100 μm or greater than or about 200 μm may be maintained to ensure complete coverage of the disk surface to limit or prevent short circuits. The coating 410 can be made of any material, and in some embodiments it can be formed of the same material as the edge ring 330. The material can be ceramic or other dielectric material, such as alumina, or any other oxide, nitride, carbide or combination of materials that can limit short circuits of the substrate support assembly.

[0054] In some embodiments, recessed channels may be formed along the surface of the disk 320, allowing fluid flow to flow upwards through the base shaft and across the disk surface. The fluid flow may be an airflow of helium, argon, or some other gas. Because the fluid can be cooled during transport through the substrate support assembly, the gas can facilitate cooling of the substrate from the back side. Therefore, by regulating the fluid flow through the disk, improved cooling can be provided compared to conductive cooling from the support assembly alone. For example, by increasing the fluid flow during and / or after the processing operation, the substrate temperature can more easily return to the deposition setpoint temperature. By providing multiple recessed channels that transport individual fluid flow paths, different areas can be cooled at different rates, which can accommodate non-uniform temperature distributions across the substrate. Therefore, heat load issues generated during processing operations can be accommodated by the substrate support assembly according to the present technology, which can improve the uniformity of the deposition operation by ensuring a consistent substrate temperature in each deposition cycle.

[0055] Figure 5 A schematic partial cross-sectional view of a substrate support assembly 300 according to some embodiments of the present technology is shown, and additional aspects of the aforementioned lifting rod assembly 335 and additional features of the support assembly are also shown. As shown, the substrate support assembly 300 may include a conductive shield 325 extending along the back side of the worktable component. A worktable insulator 315 may be mounted on the conductive shield. A conductive worktable 310 may be positioned on the insulator and may define a plurality of fluid channels, as previously described, for cooling the substrate support assembly and the substrate. The substrate support assembly 300 may include a disk 320 and an edge ring 330 as previously described.

[0056] As shown in the figure, the lifting rod assembly 335 can extend through the conductive shield 325, the stage insulator 315, the stage 310, and the disk 320. The lifting rod assembly can be configured to restrict plasma generation within the lifting rod aperture and to restrict helium trapping (helium can flow into the aperture through the disk). As shown and discussed above, the countersunk hole can be formed through the disk, with a smaller diameter portion of the hole extending to the disk surface. The lifting rod 520 may be characterized by a top plug positioned directly below the passageway through the aperture through the disk. For example, the lifting rod 520 can be recessed from the substrate support surface of the disk by less than or about 2 mm, and can be recessed from the surface of the disk by less than or about 1 mm, less than or about 800 μm, less than or about 700 μm, less than or about 600 μm, less than or about 500 μm, less than or about 400 μm, less than or about 300 μm, less than or about 200 μm, or even smaller.

[0057] A pad 525 can be fitted into a hole through a disk and positioned abutting the inner edge of a disk 320. The pad 525 may define an internal path through which the lifting rod can extend and may define a tapered inlet that allows the lifting rod to be recessed and positioned on the pad as shown. The pad can be secured in place by a retainer 530, which can be fitted into a conductive shield 325, a table insulator 315, and a table 310. In some embodiments, each of the pad and the retainer may be formed of a dielectric or insulating component. A counterweight 535 may be coupled to the end of the lifting rod 520 opposite the substrate contact end and may hold the lifting rod in a recessed position during substrate processing. The lifting rod assembly may be passive in operation and may be actuated by a vertically recessed substrate support assembly. When the substrate support is retracted from the operating position, the counterweight may be contacted from below, and the lifting rod may extend upward through the assembly to lift the substrate from the support. In some embodiments of the art, any number of lifting rod assemblies may be included.

[0058] Because it can function as a conductive component for electrostatic chuck operation, the path through the lifting rod assembly hole can provide a pathway for arcing between components. Therefore, in some embodiments, a retainer can be formed and coupled to the assembled components to increase line spacing, such as by forming a tortuous path that can reduce potential and limit arcing from the conductive component. For example, a portion of the retainer 530 can extend into the stage 310. Furthermore, the retainer 530 can define a recess, such as an annular notch as shown, in which a portion of the stage insulator can be positioned.

[0059] Figure 6A A schematic partial cross-sectional view of a substrate support assembly 300 according to some embodiments of the present technology is shown, and additional features extending through the assembly's purification path may also be illustrated. While the processing area of ​​the chamber can be maintained under vacuum pressure, the internal components within the base shaft can be maintained closer to atmospheric pressure. Condensation may occur in these areas during cryogenic operation, which could lead to arcing at the RF rod or other corrosion within the substrate support assembly. Therefore, in some embodiments, additional purification paths extending around the RF rod and associated components may be formed to ensure that condensation within the system can be limited or prevented.

[0060] As shown, the purge path 605 can extend through the base shaft and the stage insulator 315. The purge path 605 can then extend laterally into the central region where the RF rod extends through the shaft. In some embodiments, a gap can be formed between the RF rod insulator 350 and other components within the stage 310. As shown, when the purge flow (which can be nitrogen or any other material) impinges on the stage 310, the flow can be directed downwards and around the stage, as well as circumferentially around the rod insulator, and around the rod insulator 350 from both the inside and outside. The purge path can extend downwards along the outside of the rod insulator and downwards along the inner surface of the rod insulator, such as between the rod insulator and the RF rod. This ensures that air can be removed from the substrate support assembly to prevent condensation.

[0061] Figure 6B A schematic partial cross-sectional view of a rod insulator 350 according to some embodiments of the present technology is shown. As shown, the rod insulator 350 may define a ledge 610 along its inner surface, and the ledge 610 may taper in an inner diameter from an end that can extend around the pressure plate 310, as shown above. The diameter may then decrease as the rod insulator extends along the length of the RF rod through the base. Furthermore, the rod insulator 350 may define one or more recesses 615 in its end, wherein the rod insulator may abut against the workbench 310. The recesses 615 ensure that purge gases can extend from the outside to the inside of the rod insulator for purging along the RF rod. Because a pathway can be formed in the recessed area within the workbench insulator, RF leakage can be controlled or prevented. This is in Figure 6C The image further illustrates that a purification path 605 extends upward along the base axis 305 and enters the worktable insulator 315. An additional groove 620 can be formed, which, when positioned on the insulator, creates a transverse channel between the worktable insulator and the worktable. This channel can then provide a fluid pathway into the central channel for purification around the RF rod.

[0062] Processing chamber 100 and / or processing chamber 200 may be used in some embodiments of the present technology for processing methods that may include the formation, etching, or curing of materials for semiconductor structures. The chamber may include any of the substrate support assembly components or features described above. It should be understood that the described chambers are not intended to be limiting, and any chamber that can be configured to perform the described operations may be used similarly. Figure 7Exemplary operations in a processing method 700 according to some embodiments of the present technology are illustrated. The method can be performed in a variety of processing chambers and on one or more hosts or tools, including the processing chamber 100 or processing chamber 200 described above. Method 700 may include a number of optional operations, which may or may not be specifically associated with some embodiments of the method according to the present technology. For example, many operations are described to provide a wider range of structural forms, but are not critical to the technology, or can be performed by easily understood alternative methods.

[0063] Method 700 may include additional operations prior to the commencement of the listed operations. For example, the additional processing operations may include forming a structure on a semiconductor substrate, which may include both forming and removing material. For example, a transistor structure, a memory structure, or any other structure may be formed. The preceding processing operations may be performed in a chamber in which method 700 can be performed, or the processing may be performed in one or more other processing chambers prior to conveying the substrate to one or more semiconductor processing chambers in which method 700 can be performed. In any case, method 700 may optionally include conveying the semiconductor substrate to a processing region of a semiconductor processing chamber, such as processing chamber 200 described above, or other chambers that may include the components described above. The substrate may be deposited on a substrate support, which may be a base such as substrate support 210, may be or include a substrate support assembly 300, and may reside in a processing region of the chamber, such as processing space 120 described above.

[0064] The substrate to be processed can be or includes any number of materials used for semiconductor processing. The substrate material can be or includes silicon, germanium, dielectric materials including silicon oxide or silicon nitride, metallic materials, or any combination of these materials; they can be substrates or materials formed on the structure. According to the present technology, features can be characterized in any shape or configuration. In some embodiments, features can be or include trench structures or holes formed within the substrate. Although features can be characterized in any shape or size, in some embodiments, features can be characterized in a higher aspect ratio or the ratio of the feature's depth to its width across the feature. For example, in some embodiments, features can be characterized in an aspect ratio greater than or about 5:1, and can be characterized in an aspect ratio greater than or about 10:1, greater than or about 15:1, greater than or about 20:1, greater than or about 25:1, greater than or about 30:1, greater than or about 40:1, greater than or about 50:1, or greater. In addition, the feature may be characterized by a narrow width or diameter of the span feature contained between the two sidewalls, such as a size less than or about 20 nm, and may be characterized by a span feature width less than or about 15 nm, less than or about 12 nm, less than or about 10 nm, less than or about 9 nm, less than or about 8 nm, less than or about 7 nm, less than or about 6 nm, less than or about 5 nm, or even smaller.

[0065] In some embodiments, method 700 may include optional processing operations, such as pretreatment, which may be performed to prepare the surface of the substrate for deposition. Once prepared, method 700 may include delivering one or more precursors to a processing region of a semiconductor processing chamber housing the structure. The precursors may include one or more silicon-containing precursors, and one or more diluents or carrier gases, such as inert gases or other gases delivered with the silicon-containing precursors. Although this method will be explained in relation to the production of flowable silicon films, it should be understood that the described methods and / or chambers, according to embodiments of the art, can be used to produce any quantity of material. At operation 705, plasma may be formed from a deposition precursor including silicon-containing precursors. Plasma may be formed within the processing region, which may allow deposition material to be deposited on the substrate. For example, in some embodiments, capacitively coupled plasma may be formed within the processing region by applying plasma power to the panel as described above. For example, a high-frequency power supply as discussed above may be operated at reduced effective plasma power to deposit material within features on the substrate.

[0066] At operation 710, a silicon-containing material can be deposited onto the substrate from the plasma effluent of a silicon-containing precursor. In some embodiments, the material can be a flowable silicon-containing material, which may be or include amorphous silicon. The deposited material can at least partially flow into features on the substrate to provide bottom-up gap filling. The deposited material can flow into the bottom of the features, although, as shown, a certain amount of material may remain on the sidewalls of the substrate. Although the amount deposited may be relatively small, the remaining material on the sidewalls may restrict subsequent flow.

[0067] The power applied during deposition can be a low-power plasma, which limits dissociation and maintains the hydrogen doping level in the deposited material. This hydrogen doping may contribute to the fluidity of the deposited material. Therefore, in some embodiments, the plasma power supply can deliver less than or about 100 W of plasma power to the panel, and can deliver less than or about 90 W, less than or about 80 W, less than or about 70 W, less than or about 60 W, less than or about 50 W, or even less. As previously explained, this power can be further attenuated by operating a high-frequency power supply with a pulse frequency and duty cycle, which can produce an effective power of less than or about 10 W, and can produce an effective power of less than or about 5 W, as discussed above.

[0068] Following a certain amount of deposition, in some embodiments of this technology, a processing or curing process can be performed, configured to densify the formed material and advantageously clean or etch back the material on the feature sidewalls. This process can be performed in the same chamber as the deposition and can be performed in a cyclic process to fill the feature. In some embodiments, the silicon-containing precursor flow can be stopped and the processing area can be purged. After purge, the processing precursor can flow into the processing area of ​​the processing chamber. The processing precursor can be or include hydrogen, helium, argon, or other inert materials that do not chemically react with the film. A processing plasma can be formed at operation 715, which can also be a capacitively coupled plasma formed within the processing area. While the formed deposition plasma can be formed by applying high-frequency plasma power to the panel or nozzle, and in some embodiments, a separate power source may not be included. The processing can utilize both a high-frequency power source and a low-frequency power source coupled to the substrate support as discussed above. During processing, the high-frequency power source can operate at a first power level, the low-frequency power source can operate at a second power level, and in embodiments of this technology, these two power levels can be similar or different.

[0069] While the high-frequency power supply can operate in pulsed and low effective power during plasma deposition, it can also operate in a continuous wave configuration during processing, and can be at any of the plasma power levels described above. The low-frequency power supply can operate in pulsed mode during processing, and can be at any of the pulse frequencies and / or duty cycles described above.

[0070] During the deposition operation, the low-frequency power supply may not be operated. As discussed above, to achieve repeatable plasma generation at low power, a trigger sequence can be used to ensure plasma generation during each deposition operation. The trigger sequence may include a first time period and a second time period, which together can generate a deposition time period. In some embodiments, to limit deposition, the deposition time period may be less than or about 30 seconds, and may be less than or about 20 seconds, less than or about 15 seconds, less than or about 10 seconds, less than or about 8 seconds, less than or about 6 seconds, less than or about 5 seconds, less than or about 4 seconds, or shorter. The first time period may be shorter than the second time period, and the first time period can be used to ensure plasma generation while limiting the impact on the deposition process. Therefore, in some embodiments, the first time period may be less than or about 2 seconds, and may be less than or about 1 second, less than or about 0.5 seconds, less than or about 0.4 seconds, less than or about 0.3 seconds, less than or about 0.2 seconds, less than or about 0.1 seconds, less than or about 0.09 seconds, less than or about 0.08 seconds, less than or about 0.07 seconds, less than or about 0.06 seconds, less than or about 0.05 seconds, or shorter.

[0071] In some embodiments, a first power may be applied by a high-frequency power source during a first time period, the first power being higher than a second power applied by the high-frequency power source during a second time period. For example, during the first time period, the first power may be greater than or about 50 W, and may be greater than or about 80 W, greater than or about 100 W, greater than or about 120 W, greater than or about 140 W, greater than or about 160 W, greater than or about 180 W, greater than or about 200 W, or higher. The high-frequency power source may then apply power during the second time period for the remainder of the deposition time at any of the effective power levels discussed above. Furthermore, the high-frequency power source may operate continuously during the deposition time, but during the first time period, a low-frequency power source may apply power at any of the power levels discussed above to ensure ignition. In another example, the high-frequency power source may operate in a multi-level pulse configuration during the first time period, and then switch the desired effective power during the second time period. The multi-level pulse may include multiple pulses, each pulse being less than 0.1 seconds, such as less than or about 50 microseconds, less than or about 40 microseconds, less than or about 30 microseconds, less than or about 20 microseconds, or shorter, and all of these occur during the first time period. The pulse may include a higher initial pulse for the first part of the pulse, followed by a lower second pulse for the second part of the pulse. These two parts of the pulse may occur at any of the power levels previously described.

[0072] During the processing operation, the substrate support assembly can be used to maintain the substrate temperature at operation 720 and to continue temperature control prior to subsequent deposition operations. For example, in addition to conductive cooling via the substrate support assembly, in some embodiments, a back gas can be provided and modulated to further control the substrate temperature during higher-power processing operations. Simultaneously or additionally, a more directionally delivered plasma effluent can penetrate the remaining film formed at the bottom of the feature and can reduce hydrogen doping at operation 725 to densify the film. After processing, the back gas can continue to flow to bring the temperature back to the deposition setpoint before subsequent deposition cycles.

[0073] While deposits can be formed in nanometers or larger, the thickness of the dense material can be controlled to less than or about 100 angstroms by performing the etching process as described above, and can be less than or about 90 angstroms, less than or about 80 angstroms, less than or about 70 angstroms, less than or about 60 angstroms, less than or about 50 angstroms, less than or about 40 angstroms, less than or about 30 angstroms, less than or about 20 angstroms, less than or about 10 angstroms, or even smaller. By controlling the thickness of the deposited material, it is easier to perform transitions to the entire thickness and to address penetration problems common in conventional processes. The process can then be repeated for any number of cycles to continue producing dense material through the feature.

[0074] Regarding the deposition precursors used during any of the formation operations, any number of precursors may be used in conjunction with this technique. Silicon-containing precursors that may be used during this period may include, but are not limited to, silanes (SiH4), disilanes (Si2H6), or other organosilanes, including cyclohexylsilane, silicon tetrafluoride (SiF4), silicon tetrachloride (SiCl4), dichlorosilane (SiH2Cl2), tetraethyl orthosilicate (TEOS), and any other silicon-containing precursors that can be used for silicon-containing film formation. In some embodiments, the silicon-containing material may be nitrogen-free, oxygen-free, and / or carbon-free. In any of the operations, one or more additional precursors may be included, such as inert precursors, which may include Ar, diatomic hydrogen, He, or other materials such as nitrogen, ammonia, or other precursors.

[0075] Temperature and pressure can also affect the operation of this technology. For example, in some embodiments, to promote membrane flow, the process can be carried out at temperatures below or about 20°C, and can be carried out at temperatures below or about 10°C, below or about 0°C, below or about -10°C, below or about -20°C, below or about -30°C, or lower. Throughout the method, including during processing and densification, the temperature can be maintained in any of these ranges. For any of the processes, the pressure within the chamber can also be maintained relatively low, such as a chamber pressure of less than or about 10 Torr, and the pressure can be maintained at less than or about 8 Torr, less than or about 6 Torr, less than or about 5 Torr, less than or about 4 Torr, less than or about 3 Torr, less than or about 2 Torr, less than or about 1 Torr, or lower. Furthermore, in some embodiments, the pressure can be maintained at different levels during deposition and processing. For example, the pressure during deposition can be maintained at greater than or about 1 Torr, such as greater than or about 2 Torr, greater than or about 3 Torr, or higher, and the pressure during processing can be maintained at less than or about 1 Torr, such as less than or about 0.8 Torr, less than or about 0.5 Torr, less than or about 0.1 Torr, or lower. By performing processes according to some embodiments of the present technology, improved filling of narrow features using silicon-containing or other flowable materials can be achieved while ensuring adequate temperature control of the substrate within a single processing chamber.

[0076] In the foregoing description, numerous details have been set forth for illustrative purposes to provide an understanding of various embodiments of the present technology. However, it will be apparent to those skilled in the art that certain embodiments may be practiced without some of these details or with additional details.

[0077] Several embodiments have been disclosed, and those skilled in the art will understand that various modifications, alternative structures, and equivalents can be used without departing from the spirit of the embodiments. Furthermore, some well-known processes and elements have not been described to avoid unnecessarily obscuring the scope of the invention. Therefore, the above description should not be considered as limiting the scope of the invention. Additionally, methods or processes may be described as sequential or stepwise, but it should be understood that operations may be performed simultaneously or in a different order than those listed.

[0078] Where a range of values ​​is provided, it should be understood that, unless the context explicitly specifies otherwise, each intermediate value between the upper and lower limits of this range is also specifically disclosed, up to the smallest part of the lower limit unit. Any narrower range between any stated or unstated intermediate value within the stated range and any other stated or intermediate value within this stated range is covered. The upper and lower limits of these narrower ranges may be independently included or excluded from this range, and each range in which either or both limits are not included, or both are included, is also covered within this technique, subject to any limits specifically excluded in the stated range. When the stated range includes one or both limits, the range excluding either or both of these limits is also included.

[0079] As used in the specification and appended claims, unless the context clearly specifies otherwise, the singular forms “a”, “an”, and “the” include plural references. Thus, for example, the reference to “a precursor” includes multiple such precursors, and the reference to “the layer” includes one or more layers and their equivalents known to those skilled in the art, and so on.

[0080] Furthermore, the terms “comprise(s)”, “comprising”, “contain(s)”, “containing”, “include(s)”, and “including” as used in this specification and the appended claims are intended to indicate the presence of the stated feature, integer, component, or operation, but do not exclude the presence or addition of one or more other features, integers, components, operations, actions, or groups.

Claims

1. A semiconductor substrate support, comprising: Base shaft; A worktable, wherein the worktable defines a fluid channel across a first surface of the worktable; A worktable insulator, wherein the worktable insulator is positioned between the worktable and the base shaft; A conductive disk, which is coupled to the first surface of the stage and configured to contact a substrate supported on the semiconductor substrate support; A conductive shielding element extends along the back side of the workbench insulator and is coupled between a portion of the workbench insulator and the base shaft; An RF rod extends through the base shaft and is electrically coupled to the worktable; as well as A rod insulator that extends around the RF rod along its length. The base shaft and the workbench insulator define a vertical portion of a purification path, the vertical portion being laterally spaced from the rod insulator, wherein the purification path has a lateral portion extending from the vertical portion to the rod insulator, and wherein the purification path has a third portion extending downward along the rod insulator.

2. The semiconductor substrate support as claimed in claim 1, further comprising: An insulating edge ring is disposed on a recessed wall of the conductive disk, wherein the insulating edge ring extends radially outward along the outer edge of the worktable insulator, and wherein the insulating edge ring contacts the conductive shield.

3. The semiconductor substrate support of claim 2, wherein the conductive disk comprises a coating along a surface configured to contact the substrate, wherein the coating extends along the recessed ledge on which the insulating edge ring is disposed.

4. The semiconductor substrate support of claim 3, wherein the coating comprises an insulating material constituting the insulating edge ring.

5. The semiconductor substrate support as claimed in claim 1, further comprising: A lifting rod assembly extending through the worktable, the worktable insulator, the conductive disk, and the conductive shield, wherein the lifting rod assembly includes: The lifting mast, liner, Fixtures, and Counterweight.

6. The semiconductor substrate support of claim 5, wherein the retainer defines a groove, and a portion of the stage insulator is disposed in the groove.

7. The semiconductor substrate support of claim 1, wherein the base shaft is mounted on a hub, and wherein the rod insulator extends into the hub.

8. The semiconductor substrate support of claim 1, wherein the rod insulator extends within a portion of the stage insulator.

9. The semiconductor substrate support of claim 1, wherein the purification path continues along the interior and exterior of the rod insulator.

10. A semiconductor processing system, comprising: The main body of the chamber; A substrate support member configured to support a semiconductor substrate, wherein the substrate support member comprises: Base shaft; A worktable, wherein the worktable defines a fluid channel across a first surface of the worktable; A worktable insulator, wherein the worktable insulator is positioned between the worktable and the base shaft; A conductive disk, which is coupled to the first surface of the stage and configured to contact a substrate supported on the semiconductor substrate; A conductive shielding element extends along the back side of the workbench insulator and is coupled between a portion of the workbench insulator and the base shaft; A panel, wherein the chamber body, the substrate support, and the panel define a processing area; A high-frequency plasma source, wherein the high-frequency plasma source is coupled to the panel; A low-frequency plasma source, wherein the low-frequency plasma source is coupled to the substrate support; An RF rod extends through the base shaft and is electrically coupled to the worktable; as well as A rod insulator that extends around the RF rod along its length. The base shaft and the workbench insulator define a vertical portion of a purification path, the vertical portion being laterally spaced from the rod insulator, wherein the purification path has a lateral portion extending from the vertical portion to the rod insulator, and wherein the purification path has a third portion extending downward along the rod insulator.

11. The semiconductor processing system of claim 10, wherein the substrate support includes an electrostatic chuck, and the semiconductor processing system further includes: A DC power supply is coupled to the substrate support.

12. The semiconductor processing system of claim 10, wherein the low-frequency plasma source is configured to operate at less than or equal to 2 MHz, and wherein the high-frequency plasma source is configured to operate at a pulse frequency greater than or equal to 13.56 MHz and less than or equal to 20 kHz and a duty cycle less than or equal to 20%.

13. The semiconductor processing system of claim 12, wherein the high-frequency plasma source is configured to generate plasma with an effective power of less than or equal to 5 W.

14. The semiconductor processing system of claim 10, further comprising: An insulating edge ring is disposed on a recessed wall of the conductive disk, wherein the insulating edge ring extends radially outward along the outer edge of the worktable insulator, and wherein the insulating edge ring contacts the conductive shield.

15. The semiconductor processing system of claim 14, wherein the conductive disk comprises a coating along a surface configured to contact the substrate, wherein the coating extends along the recessed ledge on which the insulating edge ring is disposed.

16. The semiconductor processing system of claim 10, further comprising: A first LC filter is coupled to the substrate support and configured to virtually ground the high-frequency plasma source through the substrate support.

17. The semiconductor processing system of claim 16, further comprising: A second LC filter, coupled to the panel and configured to virtually ground the low-frequency plasma source to the chamber body.

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