Column selection signal control circuit, storage circuit and semiconductor memory

Abstract

The present disclosure provides a column selection signal control circuit, a storage circuit and a semiconductor memory, which relate to the technical field of integrated circuit manufacturing. The column selection signal control circuit includes: a connection module, including a first number of column selection signal lines and a second number of switch tubes, each of the column selection signal lines controls a plurality of the switch tubes, and each of the switch tubes is used to control the reading of a bit line; a driving module, including a first number of driving units, each of the driving units is respectively connected to one of the column selection signal lines; a control module, connecting one or more control signals and the driving module, and used to control one or more of the first number of driving units to work according to the one or more control signals. The embodiment of the present disclosure can increase the turn-on speed of the column selection signal.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuit manufacturing, and in particular to a column selection signal control circuit, a storage circuit and a semiconductor memory capable of increasing the turn-on speed of a column selection signal. Background Art

[0002] In the CSL (column select signal) architecture and decoder circuit design of the common fourth-generation DDR (Double Data Rate SDRAM) chip (DDR4), one CSL signal line turns on 8 bit lines (BL) in a read / write process to achieve data transmission. When storage technology develops to the fifth-generation DDR chip (DDR5), one CSL signal line turns on 16 bit lines in a read / write process to transmit 16 bits of data. At this time, when the CSL architecture and decoding circuit of the DDR4 chip are used to design the CSL architecture and decoder of the DDR5 chip, the CSL signal line will be overloaded, the CSL working speed will be extremely slow, the pulse when the CSL is turned on will be too short, the slope of the signal will be too poor, the read / write time will be too long, or the read / write will fail directly.

[0003] This phenomenon is very obvious as the storage capacity of DDR5 increases. Before there is a breakthrough in the process, CSL work becomes increasingly difficult. The traditional CSL architecture design is no longer suitable for DDR5 circuit design.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0005] The purpose of the present disclosure is to provide a column selection signal control circuit, a storage circuit and a semiconductor memory, which are used to overcome the problem of slow start-up speed of the column selection signal caused by the limitations and defects of the related art at least to a certain extent.

[0006] According to a first aspect of the present disclosure, there is provided a column selection signal control circuit, comprising: a connection module, comprising a first number of column selection signal lines and a second number of switch tubes, each of the column selection signal lines controlling a plurality of the switch tubes, each of the switch tubes being used to control reading of a bit line; a driving module, comprising a first number of driving units, each of the driving units being respectively connected to one of the column selection signal lines; and a control module, connecting one or more control signals and the driving module, for controlling one or more of the first number of driving units to operate according to the one or more control signals.

[0007] In an exemplary embodiment of the present disclosure, the first number is two, the second number is sixteen, and each of the column selection signal lines controls eight of the switch tubes respectively.

[0008] In an exemplary embodiment of the present disclosure, the one or more control signals include a first control signal and a second control signal.

[0009] In an exemplary embodiment of the present disclosure, the driving unit includes a first driving unit and a second driving unit, and the control module is used to control the first driving unit and the second driving unit to work simultaneously when the first control signal is in a first state, control the first driving unit to work alone when the first control signal is in a second state and the second control signal is in the first state, and control the second driving unit to work alone when the first control signal is in a second state and the second control signal is in the second state.

[0010] In an exemplary embodiment of the present disclosure, the first state is a low level, and the second state is a high level.

[0011] In an exemplary embodiment of the present disclosure, the control module includes: a first NAND gate, a first input terminal connected to the first control signal, and a second input terminal connected to the second control signal; a second NAND gate, a first input terminal connected to the first control signal; an inverter, an input terminal connected to the second control signal, and an output terminal connected to the second input terminal of the second NAND gate.

[0012] In an exemplary embodiment of the present disclosure, when the first control signal is in the first state, it represents a burst length of sixteen; when the first control signal is in the second state and the second control signal is in the first state, it represents a burst length of eight, and data is output through the upper eight bit lines; when the first control signal is in the second state and the second control signal is in the second state, it represents a burst length of eight, and data is output through the lower eight bit lines.

[0013] In an exemplary embodiment of the present disclosure, the first end of the switch tube is connected to one of the bit lines, the second end is connected to a local data line, and the control end is connected to the column selection signal line.

[0014] According to a second aspect of the present disclosure, there is provided a storage circuit, comprising: a plurality of storage arrays; and a column selection signal control circuit as described in any one of the above items, wherein the column selection signal control circuit is used to read the plurality of storage arrays.

[0015] In an exemplary embodiment of the present disclosure, each of the memory arrays reads data on 16 bit lines at most at a time.

[0016] In an exemplary embodiment of the present disclosure, the driving module of the column selection signal control circuit includes eight groups of driving units, each group of the driving units includes a first driving unit and a second driving unit, the connection module of the column selection signal control circuit includes eight groups of column selection signal lines, each group of the column selection signal lines is used to read one of the storage arrays, each group of the column selection signal lines includes a first column selection signal line and a second column selection signal line, the first column selection signal line controls the upper eight bit lines to be connected to the upper eight local data lines respectively, and the second column selection signal line controls the lower eight bit lines to be connected to the lower eight local data lines respectively.

[0017] According to a third aspect of the present disclosure, a semiconductor memory is provided, comprising a column selection signal control circuit as described in any one of the above items.

[0018] In an exemplary embodiment of the present disclosure, the semiconductor memory is a dynamic random access memory.

[0019] In an exemplary embodiment of the present disclosure, the dynamic random access memory complies with the DDR5 memory specification.

[0020] According to a fourth aspect of the present disclosure, a chip is provided, comprising the column selection signal control circuit as described in any one of the above items.

[0021] The disclosed embodiment uses multiple driving units to drive multiple column selection signal lines, and controls multiple driving units to work simultaneously or any one driving unit to work alone, which can effectively reduce the load of each column selection signal line and reduce the phenomenon of slow operation of CSL caused by excessive load of column selection signal lines in traditional designs. At the same time, all or individual driving units are allowed to work, which can realize data reading in multiple modes, and turn off unnecessary driving units to reduce power consumption.

[0022] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0024] Figure 1 is a schematic structural diagram of a column selection signal control circuit in an exemplary embodiment of the present disclosure.

[0025] Figure 2is a schematic diagram of a column selection signal control circuit in one embodiment of the present disclosure.

[0026] Figure 3 Schematic diagram of a circuit of a control module in one embodiment of the present disclosure.

[0027] Figure 4 is a schematic diagram of a storage circuit in one embodiment of the present disclosure.

[0028] Figure 5 In one embodiment of the present disclosure Figure 4 Schematic diagram of the storage circuit shown.

[0029] Figure 6 Schematic diagram of signal improvement of column selection signal lines in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0030] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as being limited to the examples set forth herein; on the contrary, these embodiments are provided so that the present disclosure will be more comprehensive and complete, and the concepts of the example embodiments are fully conveyed to those skilled in the art. The described features, structures, or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced while omitting one or more of the specific details, or other methods, components, devices, steps, etc. may be adopted. In other cases, known technical solutions are not shown or described in detail to avoid obscuring various aspects of the present disclosure.

[0031] In addition, the accompanying drawings are only schematic diagrams of the present disclosure, and the same reference numerals in the drawings represent the same or similar parts, so their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities, which do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices.

[0032] The present disclosure provides a column address decoding circuit architecture that can be applied to storage circuits, and particularly relates to DRAM chip circuits. The embodiments of the present disclosure can be applied to improve the working condition of the CSL signal of the storage array part in the DRAM chip, but are not limited to this scope. When designing a storage chip, the circuit design architecture provided by the embodiments of the present disclosure can be adopted.

[0033] The exemplary embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0034] Figure 1 is a schematic structural diagram of a column selection signal control circuit in an exemplary embodiment of the present disclosure.

[0035] refer to Figure 1 , the column selection signal control circuit 100 may include:

[0036] The connection module 1 includes a first number n of column selection signal lines CSL1 to CSLn and a second number of switch tubes, each column selection signal line CSL controls multiple switch tubes, and each switch tube is used to control the reading of a bit line BL. n is an integer greater than or equal to 2. The second number is the total number of switch tubes connected to the n column selection data lines.

[0037] The driving module 2 includes a first number of driving units 21 - 2n, each of which is connected to one of the column selection signal lines CSL1 - CSLn.

[0038] The control module 3 is connected to one or more control signals CON and the driving module 2 , and is used to control one or more driving units of the first number n driving units 21 - 2n to work according to the one or more control signals CON.

[0039] exist Figure 1 In the illustrated embodiment, n driving units 21-2n drive n CSL signal lines CSL1-CSLn respectively, and each CSL signal line drives a plurality of switch tubes respectively. In an exemplary embodiment of the present disclosure, the first end of the switch tube is connected to a bit line, the second end is connected to a local data line, and the control end is connected to the column selection signal line. For example, CSL1 is connected to the gates of i switch tubes M11-M1i, the first end of the switch tube M11 is connected to the bit line BL11, the second end of the switch tube M11 is connected to the local signal line LIO11, the first end of the switch tube M12 is connected to the bit line BL12, the second end of the switch tube M12 is connected to the local signal line LIO12, and so on, the first end of the switch tube M1i is connected to the bit line BL1i, and the second end of the switch tube M1i is connected to the local signal line LIO1i. CSL2 is connected to j switch tubes, and CSLn is connected to k switch tubes. Similarly, the present disclosure is not repeated here.

[0040] exist Figure 1 In the illustrated embodiment, the first number is n, and the second number is i+j+...+k. i, j, and k are all natural numbers, and i, j, and k may be partially or completely equal, or may be mutually unequal. That is, the number of switch tubes connected to each column selection signal line may be partially the same, completely the same, or completely different.

[0041] The control module 3 can output CSL signals to the column selection signal lines CSL1 to CSLn at the same time by controlling one or more driving units in the driving module 2 to work simultaneously. The CSL signal on a CSL signal line reaches the gates of all the switch tubes connected to the CSL signal line almost at the same time, controls all the switch tubes connected to the CSL signal line to turn on, and then partially or completely transmits the data on the bit lines BL11 to BLnk to the local data signal lines LIO11 to LIOnk.

[0042] In some embodiments, the switch tubes connected to each CSL signal line are P-type transistors. In other embodiments, the conduction function of the switch tubes connected to each CSL can also be realized by other semiconductor elements or combinations of semiconductor elements, and the present disclosure does not impose any special restrictions on this. In addition, the control signal CON connected to the control module 3 is only used to indicate the existence of the control signal and is not used to limit the number of control signals. In the embodiments of the present disclosure, the control signal connected to the control module 3 can be one or more, and the present disclosure does not impose any special restrictions on this.

[0043] By using one control module to control multiple drive units and then control multiple CSL signal lines at the same time, multiple switch tubes connected to multiple CSL signal lines can be controlled at the same time to achieve simultaneous reading of multiple bit lines. Figure 1 The circuit provided by the illustrated embodiment can reduce the number of switch tubes controlled by each CSL signal line, thereby reducing the load of the CSL signal line and improving the quality of the CSL signal.

[0044] Although Figure 1 The illustrated embodiment shows more than two CSL signal lines and more than two drive units, but in other embodiments of the present disclosure, there may be only two CSL signal lines and the corresponding drive units may be only two, for example Figure 2 The embodiment shown.

[0045] Figure 2 is a schematic diagram of a column selection signal control circuit in one embodiment of the present disclosure.

[0046] refer to Figure 2 In an exemplary embodiment of the present disclosure, the first number may be two, the second number may be sixteen, and each column selection signal line controls eight switch tubes respectively.

[0047] exist Figure 2In the illustrated embodiment, the column selection signal line CSL1 controls the switch tubes M11-M18 to control the data transmission of the bit lines BL11-BL18 to the local data lines LIO11-LIO18; the column selection signal line CSL2 controls the switch tubes M21-M28 to control the data transmission of the bit lines BL21-BL28 to the local data lines LIO21-LIO28.

[0048] Figure 2 In the illustrated embodiment, the control module 3 is controlled by two control signals, and the control signal CON includes a first control signal CON1 and a second control signal CON2.

[0049] At this time, the driving module 2 includes a first driving unit 21 and a second driving unit 22, and the control module 3 is used to control the first driving unit 21 and the second driving unit 22 to work simultaneously when the first control signal CON1 is in the first state, control the first driving unit 21 to work alone when the first control signal CON1 is in the second state and the second control signal CON2 is in the first state, and control the second driving unit 22 to work alone when the first control signal CON1 is in the second state and the second control signal CON2 is in the second state. In other embodiments of the present disclosure, the number of control signals can be less or more, and the present disclosure does not impose any special restrictions on this.

[0050] Figure 2 The circuit of the illustrated embodiment retains the DDR4 architecture of one CSL signal line controlling eight switch tubes, and uses the control module 3 to simultaneously control CSL1 and CSL2 to be turned on at the same time, and then simultaneously control the turning on of 16 switch tubes to control the data on the 16 bit lines to be transmitted to the corresponding local data lines, that is, to realize the reading of 16 bit lines at the same time. Since the number of switch tubes controlled by the CSL signal line is 8, the load of the CSL signal line is low, and the quality of the CSL signal transmitted to the gate of the switch tube is good, so that the simultaneous reading of 16 bit lines can be realized under the premise of ensuring the quality of the CSL signal, avoiding the phenomenon of slow opening of the CSL signal in the related art. At the same time, when it is only necessary to read the data on 8 bit lines at one time, any one of the drive units can be set to work alone to reduce the power consumption of the circuit.

[0051] Figure 3 Schematic diagram of a circuit of a control module in one embodiment of the present disclosure. Figure 3 The circuit shown can be applied in Figure 2 In the embodiment shown.

[0052] refer to Figure 3 In an exemplary embodiment of the present disclosure, the control module 3 may include:

[0053] The first NAND gate 31 has a first input terminal connected to the first control signal CON1 , and a second input terminal connected to the second control signal CON2 .

[0054] The second NAND gate 32 has a first input terminal connected to the first control signal CON1 .

[0055] The inverter 33 has an input terminal connected to the second control signal CON2 , and an output terminal connected to the second input terminal of the second NAND gate 32 .

[0056] exist Figure 3 In the illustrated embodiment, the first state is a low level, and the second state is a high level. In one embodiment, the low level is 0V, and the high level is a power supply voltage commonly used by the first NAND gate 31, the second NAND gate 32, and the inverter 33. In other embodiments, the voltage of the low level may also be other values, such as a negative voltage, and the voltage of the high level may also be other values. Those skilled in the art may set the values ​​of the low level and the high level according to the control requirements, and the present disclosure is not limited thereto.

[0057] When the control module 3 is implemented by other circuits, the first state and the second state of the first control signal CON1 and the second control signal CON2 may also be other different states, such as states with different waveforms, states with different signal types, and so on.

[0058] In an exemplary embodiment of the present disclosure, when the first control signal is in the first state, the burst length (BL) is sixteen; when the first control signal is in the second state and the second control signal is in the first state, the burst length is eight, and the data is output through the upper eight bit lines; when the first control signal is in the second state and the second control signal is in the second state, the burst length is eight, and the data is output through the lower eight bit lines. In the embodiment of the present disclosure, the burst length represents the number of data bits continuously output from a data port under a read command of the memory.

[0059] when Figure 3 The circuit shown is used in Figure 2 In the illustrated embodiment, the output end of the first NAND gate 31 is connected to the first driving unit 21 , and the output end of the second NAND gate 32 is connected to the second driving unit 22 .

[0060] At this time, when the first control signal CON1 is in the first state (low level) and the second control signal CON2 is in the first state (low level), the inverter 33 outputs a high level, both input ends of the first NAND gate 31 input low levels, and the first NAND gate 31 outputs a high level; the two input ends of the second NAND gate 32 input low levels and high levels respectively, and the second NAND gate 32 outputs a high level, and the control module 3 drives the first drive unit 21 and the second drive unit 22 to work simultaneously.

[0061] When the first control signal CON1 is in the first state (low level) and the second control signal CON2 is in the second state (high level), the inverter 33 outputs a low level, the two input ends of the first NAND gate 31 input a low level and a high level respectively, and the first NAND gate 31 outputs a high level; the two input ends of the second NAND gate 32 both input a low level, and the second NAND gate 32 outputs a high level, and the control module 3 drives the first driving unit 21 and the second driving unit 22 to work simultaneously.

[0062] That is, when the first control signal CON1 is in the first state (low level), no matter what state the second control signal CON2 is in, the first driving unit 21 and the second driving unit 22 work simultaneously.

[0063] When the first control signal CON1 is in the second state (high level) and the second control signal CON2 is in the first state (low level), the inverter 33 outputs a high level, the two input ends of the first NAND gate 31 input a high level and a low level respectively, and the first NAND gate 31 outputs a high level; the two input ends of the second NAND gate 32 input a high level, and the second NAND gate 32 outputs a low level, and the control module 3 only drives the first driving unit 21 to work alone.

[0064] When the first control signal CON1 is in the second state (high level) and the second control signal CON2 is in the second state (high level), the inverter 33 outputs a low level, both input ends of the first NAND gate 31 input a high level, and the first NAND gate 31 outputs a low level; the two input ends of the second NAND gate 32 input a high level and a low level respectively, and the second NAND gate 32 outputs a high level, and the control module 3 only drives the second driving unit 22 to work alone.

[0065] It can be seen that when the first control signal CON1 is in the second state (high level), if the second control signal CON2 is in the first state, only the first driving unit 21 works alone; if the second control signal CON2 is in the second state, only the second driving unit 22 works alone.

[0066] When the first driving unit 21 is used to control the CSL signal corresponding to the upper eight bits of data and the second driving unit 21 is used to control the CSL signal corresponding to the lower eight bits of data, 16 bits of data can be read simultaneously through the first control signal CON1 and the second control signal CON2, or only the lower eight bits of data or the upper eight bits of data can be read. Figure 2 and Figure 3 The illustrated embodiment can reduce the phenomenon of slow operation of the CSL due to excessive CSL load in the CSL circuit design of DDR5 while retaining the CSL architecture of DDR4.

[0067] Figure 1 to Figure 3The column selection signal control circuit shown in any embodiment can be directly used to drive data reading of multiple memory arrays.

[0068] Figure 4 is a schematic diagram of a storage circuit in one embodiment of the present disclosure.

[0069] refer to Figure 4 The storage circuit 400 may include a plurality of storage arrays 41-4N and a column selection signal control circuit 100, and the column selection signal control circuit 100 is used to read the plurality of storage arrays, where N is an integer greater than or equal to 2.

[0070] exist Figure 4 In the illustrated embodiment, the storage array is, for example, a bank, a block, or a storage unit of other capacity. The storage array described in the present disclosure does not limit the number of storage cells. Those skilled in the art can set the number and storage capacity of the storage array controlled by a column selection signal control circuit 100 by themselves, and the present disclosure is not limited thereto.

[0071] In one embodiment, the plurality of column selection signal lines in the column selection signal control circuit 100 can be divided into a plurality of groups to drive one or more memory arrays, and the number of column selection signal lines in each group is greater than or equal to two. For example, a group of column selection signal lines can be used to drive one memory array.

[0072] The number of driving units in the driving module 2 in the column selection signal control circuit 100 may be equal to the number of column selection signal lines. These driving units may also be divided into multiple groups corresponding to the grouping of the column selection signal lines, and the number of driving units in each group is the same as the number of column selection signal lines corresponding to the group. The circuit of the control module 3 may include one or more Figure 3 A control module 3 can control multiple drive units, or control multiple groups of drive units. Figure 3 The circuit shown can control one or more drive units, or one or more groups of drive units. When one control module 3 is used to control multiple groups of drive units, the output end can be connected to drive units in different groups of drive units at the same time.

[0073] In the embodiment of the present disclosure, the number of storage units, the number of column selection signal lines connected to each storage unit, the number of switch tubes connected to each column selection signal line, and the connection relationship between the control module 3 and the driving unit can be set according to actual conditions. Figure 5 This is an embodiment provided by the present disclosure.

[0074] Figure 5 In one embodiment of the present disclosure Figure 4 Schematic diagram of the storage circuit shown.

[0075] refer to Figure 5 The storage circuit 500 includes eight storage arrays DQ0 to DQ7 and a column selection signal control circuit 100. The storage array DQ0 indicates that the data read from the array is output from the data port DQ0 of the storage, the storage array DQ1 indicates that the data read from the array is output from the data port DQ1 of the storage, and so on, the storage array DQ7 indicates that the data read from the array is output from the data port DQ7 of the storage. When reading data, each storage array is connected to 2 column selection signals CSL, and the eight storage arrays DQ0 to DQ7 are connected to 16 column selection signals CSL in total. The driving units 211 and 221 are respectively used to drive the column selection signal line CSL01 corresponding to the lower eight bits of data of the storage array DQ0 and the column selection signal line CSL02 corresponding to the upper eight bits of data. The driving units 212 and 222 are respectively used to drive the column selection signal line CSL03 corresponding to the lower eight bits of data of the storage array DQ1 and the column selection signal line CSL04 corresponding to the upper eight bits of data. The driving units 213 and 223 are respectively used to drive the column selection signal line CSL05 corresponding to the lower eight bits of data of the storage array DQ2 and the column selection signal line CSL06 corresponding to the upper eight bits of data. The driving units 214 and 224 are respectively used to drive the column selection signal line CSL07 corresponding to the lower eight bits of data of the storage array DQ3 and the column selection signal line CSL08 corresponding to the upper eight bits of data. The driving units 215 and 225 are respectively used to drive the column selection signal line CSL09 corresponding to the lower eight bits of data of the storage array DQ4 and the column selection signal line CSL10 corresponding to the upper eight bits of data. The driving units 216 and 226 are respectively used to drive the column selection signal line CSL11 corresponding to the lower eight bits of data of the storage array DQ5 and the column selection signal line CSL12 corresponding to the upper eight bits of data. The driving units 217 and 227 are respectively used to drive the column selection signal line CSL13 corresponding to the lower eight bits of data of the storage array DQ6 and the column selection signal line CSL14 corresponding to the upper eight bits of data. The driving units 218 and 228 are respectively used to drive the column selection signal line CSL15 corresponding to the lower eight bits of data of the storage array DQ7 and the column selection signal line CSL16 corresponding to the upper eight bits of data.

[0076] The control module 3 controls the data reading of eight storage arrays in total, and each storage array reads data on 16 bit lines at most at a time, so the control module 3 can simultaneously control the reading of 16*8=128 bits, i.e., 16 bytes of data at most. In some embodiments, only the lower eight bits of data or the upper eight bits of data in each storage array can be read, i.e., 8 bytes of data can be read at a time.

[0077] By using Figure 3The control module 3 shown controls the data reading of eight storage arrays at the same time, and can realize that each storage array reads the data on 16 bit lines at a time or reads the data on 8 bit lines at a time while reducing the load of each CSL signal line, thereby avoiding the problem of reduced CSL opening speed caused by excessive CSL data line load in related technologies.

[0078] also, Figure 5 The illustrated embodiment provides an architecture that retains one CSL in DDR4 and turns on eight bit lines. When the disclosed embodiment is applied to DDR5, two CSLs are turned on during the reading and writing process to obtain the effect of reading 16 bit lines at a time, which can reduce the phenomenon of slow operation of the CSL signal caused by excessive load on the CSL signal line in the traditional design. At the same time, when DDR5 works in BC8 (Burst Chop 8) mode, turning on one CSL signal line and turning off the mirrored CSL signal line and the corresponding drive unit can achieve a power saving effect and effectively reduce circuit power consumption.

[0079] Figure 5 The figure is only one embodiment of the present disclosure. In other embodiments, more bit lines can be read simultaneously in a storage array by turning on multiple CSL signal lines at one time. Alternatively, in one embodiment, multiple CSL signal lines can be turned on at one time, and the number of switch tubes connected to each CSL signal line is exactly the same or not exactly the same, so as to read multiple bit lines simultaneously in multiple storage arrays.

[0080] Figure 6 Schematic diagram of signal improvement of column selection signal lines in an embodiment of the present disclosure.

[0081] refer to Figure 6 In one embodiment, waveform A is an ideal waveform of a CSL signal, for example, a CSL signal output waveform measured from an output terminal of a driving unit. The pulse width is exemplarily 3 ns, and the signal amplitude is exemplarily 1 unit.

[0082] Waveform B is the actual waveform of the CSL signal measured at the gate of any switch tube when one CSL signal line drives sixteen switch tubes to read data on 16 bit lines at the same time in the related art. It can be seen from waveform B that due to the influence of multiple loads, the rising and falling edges of the CSL signal reaching the gate of the switch tube have a long slope, the effective pulse width is only 2ns, the signal amplitude is only 0.8 units, the signal quality is poor, and the delay for the signal level to reach the effective level is long, and the turn-on time of the CSL signal is slowed down.

[0083] Waveform C is the actual waveform of the CSL signal measured at the gate of any switch tube when the data on 16 bit lines are read simultaneously in the embodiment of the present disclosure. It can be seen from waveform C that by using the column selection signal control circuit provided by the embodiment of the present disclosure, the slopes of the rising and falling edges of the CSL signal reaching the gate of the switch tube are greatly shortened, the delay for the signal level to reach the effective level is short, the pulse width is close to 3ns (for example, 2.8ns), the signal amplitude is 1 unit, the similarity with the ideal waveform of waveform A is high, the signal quality is good, and the CSL signal is turned on faster.

[0084] Therefore, the column selection signal control circuit provided in the embodiments of the present disclosure and the storage circuit using the column selection signal control circuit have a faster CSL signal turn-on time, a better CSL signal driving effect, and can read multiple bit lines at a time without reducing the quality of the CSL signal waveform. Even if the number of bit lines read at a time further increases in the future development of storage technology, the circuit provided in the embodiments of the present disclosure can effectively guarantee the signal quality of the CSL signal.

[0085] In summary, the embodiments of the present disclosure effectively extend the application time of the existing CSL signal design architecture in the future development of storage technology, and have outstanding beneficial effects on the development of storage technology.

[0086] According to a third aspect of the present disclosure, a semiconductor memory is provided, comprising a column selection signal control circuit as described above.

[0087] In an exemplary embodiment of the present disclosure, the semiconductor memory is a dynamic random access memory.

[0088] In an exemplary embodiment of the present disclosure, the dynamic random access memory complies with the DDR5 memory specification.

[0089] According to a fourth aspect of the present disclosure, a chip is provided, comprising a column selection signal control circuit as shown in any of the above embodiments.

[0090] It should be noted that, although several modules or units of the device for action execution are mentioned in the above detailed description, this division is not mandatory. In fact, according to the embodiments of the present disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. On the contrary, the features and functions of one module or unit described above can be further divided into multiple modules or units to be embodied.

[0091] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are to be considered exemplary only, and the true scope and concept of the present disclosure are indicated by the claims.

Claims

1. A column selection signal control circuit, characterized in that: include: A connection module, comprising a first number of column selection signal lines and a second number of switch tubes, each of the column selection signal lines controls a plurality of the switch tubes, and each of the switch tubes is used to control the reading of a bit line; A driving module, comprising a first number of driving units, each of the driving units being respectively connected to one of the column selection signal lines; a control module, connected to one or more control signals and the driving module, and configured to control one or more driving units of the first number of driving units to operate according to the one or more control signals; Wherein, the one or more control signals include a first control signal and a second control signal; The driving unit comprises a first driving unit and a second driving unit, and the control module is used to control the first driving unit and the second driving unit to work simultaneously when the first control signal is in a first state, control the first driving unit to work alone when the first control signal is in a second state and the second control signal is in the first state, and control the second driving unit to work alone when the first control signal is in a second state and the second control signal is in the second state; When the first control signal is in the first state, it represents a burst length of sixteen; when the first control signal is in the second state and the second control signal is in the first state, it represents a burst length of eight, and data is output through the upper eight bit lines; when the first control signal is in the second state and the second control signal is in the second state, it represents a burst length of eight, and data is output through the lower eight bit lines.

2. The column selection signal control circuit according to claim 1, characterized in that: The first number is two, the second number is sixteen, and each of the column selection signal lines controls eight of the switch tubes respectively.

3. The column selection signal control circuit according to claim 1, characterized in that: The first state is a low level, and the second state is a high level.

4. The column selection signal control circuit according to claim 1, characterized in that: The control module comprises: A first NAND gate, a first input terminal of which is connected to the first control signal, and a second input terminal of which is connected to the second control signal; A second NAND gate, a first input terminal of which is connected to the first control signal; An inverter, having an input end connected to the second control signal, and an output end connected to the second input end of the second NAND gate.

5. The column selection signal control circuit according to claim 1, characterized in that: The first end of the switch tube is connected to one of the bit lines, the second end is connected to a local data line, and the control end is connected to the column selection signal line.

6. A storage circuit, characterized in that: include: Multiple storage arrays; The column selection signal control circuit according to claim 5, wherein the column selection signal control circuit is used to read the plurality of storage arrays; Wherein, each of the storage arrays reads data on a maximum of 16 bit lines at a time; The driving module of the column selection signal control circuit includes eight groups of driving units, each group of the driving units includes a first driving unit and a second driving unit, the connection module of the column selection signal control circuit includes eight groups of column selection signal lines, each group of the column selection signal lines is used to read one of the storage arrays, each group of the column selection signal lines includes a first column selection signal line and a second column selection signal line, the first column selection signal line controls the upper eight bit lines to be connected to the upper eight local data lines respectively, and the second column selection signal line controls the lower eight bit lines to be connected to the lower eight local data lines respectively.

7. A semiconductor memory, characterized in that: It comprises the column selection signal control circuit as described in any one of claims 1 to 5.

8. The semiconductor memory according to claim 7, wherein: The semiconductor memory is a dynamic random access memory.

9. The semiconductor memory according to claim 8, wherein: The dynamic random access memory complies with the DDR5 memory specification.

10. A chip, characterized in that: It comprises the column selection signal control circuit as described in any one of claims 1 to 5.

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