Semiconductor element structure and method of manufacturing the same

Abstract

A semiconductor device structure and a method of fabricating the same are provided. The semiconductor device structure includes a first substrate, a first well region, a first gate structure, a second gate structure, a first doped region, and a first conductive feature. The substrate has a first surface and a second surface opposite to the first surface. The first well region is in the first substrate. The first well region has a first conductivity type. The first gate structure is disposed on the second surface. The second gate structure is disposed on the second surface. The first doped region has a second conductivity type different from the first conductivity type. The first doped region is disposed between the first gate structure and the second gate structure. The first conductive feature extends between the first surface of the first substrate and the first doped region.

Description

Technical Field

[0001] This application claims priority and benefits to U.S. Patent Applications No. 17 / 511,231 and No. 17 / 514,507 (priority dates “October 26, 2021” and “October 29, 2021”), the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure provides a semiconductor device structure and a method for fabricating the same, particularly a semiconductor device structure with a doped region below an isolation feature and a method for fabricating the same. Background Technology

[0003] Doped regions within the substrate can be used to electrically isolate adjacent transistors. To form a PN junction, an external power supply voltage is required to electrically couple with the doped region. However, the conductive lines used to transmit the power supply voltage require additional area to accommodate them, which may adversely affect the performance of the semiconductor device structure.

[0004] The above description of "prior art" is merely to provide background information and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not establish prior art for this disclosure, and no description of "prior art" above should be considered part of this case. Summary of the Invention

[0005] One embodiment of this disclosure provides a semiconductor device structure. The semiconductor device structure includes a first substrate, a first well region, a first gate structure, a second gate structure, a first doped region, and a first conductive feature. The first substrate has a first surface and a second surface opposite to the first surface. The first well region is disposed in the first substrate. The first well region has a first conductivity type. The first gate structure is disposed on the second surface. The second gate structure is disposed on the second surface. The first doped region has a second conductivity type different from the first conductivity type. The first doped region is disposed between the first gate structure and the second gate structure. The first conductive feature extends between the first surface of the first substrate and the first doped region.

[0006] In some embodiments, the semiconductor device structure further includes an isolation feature adjacent to the second surface of the first substrate. The first doped region is located between the isolation feature and the first conductive feature.

[0007] In some embodiments, the semiconductor device structure further includes a conductive structure that penetrates the isolation feature and contacts the first doped region.

[0008] In some embodiments, the first conductive feature is electrically coupled to the conductive structure.

[0009] In some embodiments, the semiconductor device structure further includes a second well region disposed in the first substrate and surrounding the first gate structure and the second gate structure; and a third well region disposed in the first substrate and in contact with the second well region. The third well region is in contact with the first conductive feature, and each of the second well region and the third well region has the second conductivity type.

[0010] In some embodiments, the semiconductor device structure further includes a second doped region disposed in the third well region. The second doped region has the second conductivity type.

[0011] In some embodiments, the semiconductor device structure further includes a second conductive feature extending between the first surface of the first substrate and the second doped region.

[0012] In some embodiments, the first conductive feature has a first length in a first direction that is greater than the second conductive feature has a second length in the first direction.

[0013] In some embodiments, the second doped region is in contact with the first conductive feature.

[0014] In some embodiments, the second doped region is spaced apart from the first conductive feature.

[0015] In some embodiments, the semiconductor device structure further includes a circuit structure disposed on the first surface of the first substrate. The circuit structure is electrically connected to the first conductive feature.

[0016] In some embodiments, the semiconductor device structure further includes a circuit board bonded to the circuit structure. The circuit structure is disposed between the circuit board and the first substrate.

[0017] In some embodiments, the semiconductor device structure further includes a first dielectric layer disposed on the first surface of the first substrate. The circuit structure includes a terminal for contacting the first conductive feature and a dielectric structure for contacting the first dielectric layer.

[0018] Another embodiment of this disclosure provides a semiconductor device structure. The semiconductor device structure includes a substrate, a first well region, a first transistor, a second transistor, a first doped region, and a circuit structure. The substrate has an active surface and a back surface. The first well region is disposed in the substrate. The first well region has a first conductivity type. The first transistor is adjacent to the active surface of the substrate. The second transistor is adjacent to the active surface of the substrate. The first doped region includes a second conductivity type different from the first conductivity type. The first doped region is disposed between the first well region and the first transistor and the second transistor. The circuit structure is disposed on the back surface of the substrate. The circuit structure is configured to transmit or provide a voltage electrically coupled to the first doped region.

[0019] In some embodiments, the semiconductor device structure further includes a first conductive feature exposed from the back surface of the substrate. The first conductive feature electrically connects the circuit structure and the first doped region.

[0020] In some embodiments, the semiconductor device structure further includes a conductive structure extending from the active surface of the substrate. The conductive structure is electrically coupled to the first doped region.

[0021] In some embodiments, the semiconductor device structure further includes a first isolation feature disposed in the substrate and located between the first transistor and the second transistor. The conductive structure penetrates the first isolation feature.

[0022] In some embodiments, the conductive structure is vertically aligned with the first conductive feature.

[0023] In some embodiments, the semiconductor device structure further includes a second well region disposed in the substrate and surrounding the first doped region; and a third well region spaced apart from the active surface of the substrate and in contact with the second well region. The first conductive feature penetrates the third well region, and each of the second and third well regions has the second conductivity type.

[0024] In some embodiments, one side of the circuit structure and one side of the substrate are discontinuous.

[0025] Another embodiment of this disclosure provides a method for fabricating a semiconductor device structure. The method includes: providing a substrate having a first surface and a second surface opposite to the first surface, wherein the substrate includes a first well region having a first conductivity type; forming an isolation feature extending from the second surface of the substrate; forming a first transistor and a second transistor adjacent to the second surface of the substrate; forming a first doped region below the isolation feature, wherein the first doped region has a second conductivity type different from the first conductivity type; and providing a circuit structure on the first surface of the substrate, wherein the circuit structure is configured to transmit or provide a voltage electrically coupled to the first doped region.

[0026] In some embodiments, the fabrication method further includes forming a first conductive feature that extends between the first surface of the substrate and the first doped region. The first conductive feature is electrically coupled to the circuit structure.

[0027] In some embodiments, the fabrication method further includes forming a dielectric layer on the first surface of the substrate. The circuit structure has a dielectric structure and a terminal on a surface bonded to the first surface of the substrate. The dielectric layer of the substrate is in contact with the dielectric structure of the circuit structure, and the terminal of the circuit structure is in contact with the first conductive feature of the substrate.

[0028] In some embodiments, the preparation method further includes forming a second well region in the substrate to surround the first doped region; and forming a third well region spaced apart from the second surface of the substrate and in contact with the second well region.

[0029] In some embodiments, the preparation method further includes forming a second doped region in the third well region; and forming a second conductive feature that extends between the first surface of the substrate and the second doped region.

[0030] Another embodiment of this disclosure provides a method for fabricating a semiconductor device structure. The method includes: providing a substrate having a first surface and a second surface opposite to the first surface, wherein the substrate includes a first well region having a first conductivity type; forming a first transistor and a second transistor adjacent to the second surface of the substrate; forming a first doped region between the first transistor and the second transistor, wherein the first doped region has a second conductivity type different from the first conductivity type; and forming a first conductive feature extending between the first surface of the substrate and the first doped region.

[0031] In some embodiments, the fabrication method further includes providing a circuit structure on the first surface of the substrate. The circuit structure is configured to transmit or provide a voltage electrically coupled to the first doped region via the first conductive feature.

[0032] In some embodiments, the fabrication method further includes providing a circuit board on the circuit structure. The circuit board is bonded to the circuit structure via a solder ball.

[0033] Embodiments of this disclosure disclose a semiconductor device structure having a doped region in a substrate. The doped region has a different conductivity type than the well regions of the substrate. The doped region is configured to create a PN junction for electrically isolating adjacent transistors. Furthermore, the semiconductor device structure includes a conductive structure extending from the back surface of the substrate for electrical coupling with the doped region. A power supply, such as a DC bias voltage, is provided from the back surface to couple with the doped region through the conductive structure, creating a PN junction between the doped region and the well regions of the substrate. In a comparative example, conductive lines configured to couple with the doped region are disposed on the active surface of the substrate. These conductive lines require additional area to accommodate them, thus reducing the size of the active region of the transistor. Compared to the comparative example, embodiments of this disclosure can increase the size of the active region of the transistor, thus improving the performance of the semiconductor device structure.

[0034] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, enabling a better understanding of the detailed description that follows. Other technical features and advantages that define the subject matter of this disclosure will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure by modifying or designing other structures or processes. Those skilled in the art to which this disclosure pertains will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined in the appended patent claims. Attached Figure Description

[0035] When the drawings are considered in conjunction with the embodiments and the scope of the disclosed patent, a more comprehensive understanding of the disclosure can be obtained. The same element symbols in the drawings refer to the same elements.

[0036] Figure 1 This is a top view illustrating the layout of semiconductor device structures of some examples of this disclosure.

[0037] Figure 2A This is a sectional view. Some examples of this disclosure are illustrated along... Figure 1 The semiconductor device structure is shown by the dashed line A-A'.

[0038] Figure 2BThis is a cross-sectional view illustrating semiconductor device structures of some examples of this disclosure.

[0039] Figure 3 This is a cross-sectional view illustrating semiconductor device structures of some examples of this disclosure.

[0040] Figure 4 This is a cross-sectional view illustrating semiconductor device structures of some examples of this disclosure.

[0041] Figure 5 This is a cross-sectional view illustrating semiconductor device structures of some examples of this disclosure.

[0042] Figure 6A , Figure 6B , Figure 6C , Figure 6D , Figure 6E , Figure 6F , Figure 6G , Figure 6H , Figure 6I and Figure 6J The various fabrication stages of semiconductor device structures, exemplified by some examples of this disclosure, are shown.

[0043] Figure 7A and Figure 7B The various fabrication stages of semiconductor device structures, exemplified by some examples of this disclosure, are shown.

[0044] Figure 8 This is a flowchart illustrating methods for fabricating semiconductor device structures in some examples of this disclosure.

[0045] Figure 9 This is a flowchart illustrating methods for fabricating semiconductor device structures in some examples of this disclosure.

[0046] The reference numerals in the attached figures are explained as follows:

[0047] 10a: Semiconductor device structure

[0048] 10a': Semiconductor device structure

[0049] 10b: Semiconductor device structure

[0050] 10c: Semiconductor device structure

[0051] 10d: Semiconductor device structure

[0052] 20: Preparation method

[0053] 30: Preparation method

[0054] 110: Base

[0055] 110s1: Surface

[0056] 110s2: Surface

[0057] 110s2: Surface

[0058] 110s3: Surface

[0059] 112: Well Area

[0060] 114: Well Area

[0061] 116: Well Area

[0062] 118: Doped region

[0063] 120a: Transistor

[0064] 120b: Transistor

[0065] 121a: Gate structure

[0066] 121b: Gate structure

[0067] 122a: Doped region

[0068] 122b: Doped region

[0069] 123a: Doped region

[0070] 123b: Doped region

[0071] 131: Isolation Features

[0072] 132: Isolation Features

[0073] 133: Isolation Features

[0074] 140: Dielectric layer

[0075] 140o1: Opening

[0076] 140°2: Opening

[0077] 140°3: Opening

[0078] 140°4: Opening

[0079] 150: Doped region

[0080] 161a: Conductive structure

[0081] 161b: Conductive structure

[0082] 162a: Conductive structure

[0083] 162b: Conductive structure

[0084] 163a: Conductive structure

[0085] 163b: Conductive structure

[0086] 164: Conductive Structure

[0087] 171: Electrical conductivity characteristics

[0088] 172: Electrical conductivity characteristics

[0089] 180: Dielectric layer

[0090] 200: Circuit Structure

[0091] 200s1: Surface

[0092] 200s2: Surface

[0093] 200s3: Surface

[0094] 210: Base

[0095] 212: Isolation Features

[0096] 214: Gate Structure

[0097] 220: Dielectric structure

[0098] 230: Conductive structure

[0099] 231: Conductive via

[0100] 233a: Terminal

[0101] 233b: Terminal

[0102] 233c: terminal

[0103] 240: Terminal

[0104] 300: Circuit board

[0105] A-A': Dashed line

[0106] L1: Length

[0107] L2: Length

[0108] S21: Operation

[0109] S22: Operation

[0110] S23: Operation

[0111] S24: Operation

[0112] S25: Operation

[0113] S26: Operation

[0114] S27: Operation

[0115] S28: Operation

[0116] S29: Operation

[0117] S31: Operation

[0118] S32: Operation

[0119] S33: Operation

[0120] S34: Operation

[0121] V1: Power supply voltage

[0122] V2: Power supply voltage

[0123] V3: Power supply voltage

[0124] V4: Power supply voltage

[0125] XY: Plane

[0126] XZ: Plane

[0127] Z: Direction Detailed Implementation

[0128] The following disclosure provides numerous different embodiments or examples of various features as implementations of this disclosure. Specific embodiments or examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the dimensions of an element are not limited to the disclosed range or values, but may depend on process conditions and / or the desired properties of the element. Furthermore, the description of a first feature being formed "above" or "on" a second feature in the following description can include embodiments in which the first and second features are formed in direct contact, and can also include embodiments in which additional features may be formed between the first and second features, thereby potentially preventing direct contact between the first and second features. For simplicity and clarity, various features can be drawn at any scale. In the drawings, some layers / features may be omitted for simplicity.

[0129] It should be understood that although various elements may be described using terms such as first, second, etc., these elements should not be limited by the terms. Unless otherwise stated, terms are used only to distinguish one element from another. Thus, for example, the first element, first component, or first part discussed below may be referred to as the second element, second component, or second part without departing from the teachings of this disclosure.

[0130] It should be understood that the functions or steps described in this disclosure may occur in a different order than those shown in the figures. For example, two figures shown consecutively may actually be executed simultaneously, or sometimes in reverse order, depending on the functions or steps involved.

[0131] Please refer to Figure 1 and Figure 2A . Figure 1 This is a top view illustrating the layout of a semiconductor device structure 10a according to some examples of this disclosure. Figure 2A This is a sectional view. Some examples of this disclosure are illustrated along... Figure 1 The semiconductor device structure 10a is shown in the image taken along the dashed line A-A'.

[0132] In some embodiments, the semiconductor device structure 10a may include a substrate 110, transistors 120a and 120b, isolation features 131, 132 and 133, a dielectric layer 140, a doped region 150, conductive features 171 and 172, and a dielectric layer 180.

[0133] The substrate 110 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc. The substrate 110 may include an elementary semiconductor, including silicon or germanium in single-crystal, polycrystalline, or amorphous form; a compound semiconductor material, including at least one of silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; an alloy semiconductor material, including at least one of SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP; any other suitable material; or a combination thereof. In some embodiments, the alloy semiconductor substrate may be a SiGe alloy with a gradient Ge characteristic, wherein the composition of Si and Ge changes from the ratio at one location of the gradient Ge characteristic to the ratio at another location. In another embodiment, the SiGe alloy is formed on a silicon substrate. In some embodiments, the SiGe alloy may be mechanically tensioned by another material in contact with the SiGe alloy.

[0134] In some embodiments, substrate 110 may have a multilayer structure, or substrate 110 may include a multilayer compound semiconductor structure. Substrate 110 may have a surface 110s1 (or lower surface), a surface 110s2 (or upper surface), and a surface 110s3 (or side surface). Surface 110s2 is opposite to surface 110s1. Surface 110s3 may extend between surfaces 110s1 and 110s2. In this disclosure, surface 110s1 may also be referred to as the back surface. In this disclosure, surface 110s2 may also be referred to as the active surface.

[0135] Semiconductor device structure 10a may include a well region 112. The well region 112 may be located within the substrate 110. In some embodiments, the well region 112 includes a first conductivity type. In some embodiments, the first conductivity type is p-type. In some embodiments, the p-type dopant includes boron (B), other group 3 elements, or any combination thereof. In some embodiments, the first conductivity type is n-type. In some embodiments, the n-type dopant includes arsenic (As), phosphorus (P), other group 5 elements, or any combination thereof. The well region 112 may be referred to as a drift region.

[0136] Semiconductor device structure 10a may include well region 114. Well region 114 may be located within substrate 110 and surround a portion of well region 112. Figure 1 As shown, well region 114 may have a rectangular outline in the XY plane. In some embodiments, well region 114 may have an annular outline in the XY plane. Well region 114 may surround transistors 120a and 120b and doped region 150. Figure 2A As shown, well region 114 may be located below isolation features 132 or 133. Well region 114 may extend along the Z direction from the bottom surface of isolation features 132 or 133. Well region 114 may be separated from surface 110s2 of substrate 110. In some embodiments, well region 114 includes a second conductivity type different from the first conductivity type. In some embodiments, well region 114 may be configured to be electrically coupled to conductive feature 172, thus forming a PN junction between well region 112 and well region 114.

[0137] Semiconductor device structure 10a may include well region 116. Well region 116 may be located within substrate 110. Well region 116 may contact well region 114. More specifically, well region 116 may contact the bottom of well region 114, thus allowing well regions 114 and 116 to cooperatively surround well region 112 in the XZ plane. In some embodiments, well region 116 may be a continuous doped region in the XY plane. Well region 116 may be separated from surface 110s1 of substrate 110. Well region 116 may be separated from surface 110s2 of substrate 110. In some embodiments, well region 116 includes the second conductivity type. In some embodiments, well region 116 may be configured to be electrically coupled to conductive feature 172, thus forming a PN junction between well region 112 and well region 116.

[0138] Semiconductor device structure 10a may include a doped region 118. The doped region 118 may be disposed within a well region 116. In some embodiments, the doped region 118 may be disposed to be electrically coupled to a conductive feature 172. In some embodiments, the well region 116 may be a continuous doped region in the XY plane. In some embodiments, the doped region 118 includes the second conductivity type. In some embodiments, the dopant concentration of the doped region 118 may be greater than the dopant concentration of well regions 112, 114, or 116.

[0139] Transistors 120a and 120b are disposed on surface 110s2 of substrate 110. Transistor 120a and transistor 120b are electrically isolated. Transistor 120a may include gate structure 121a and doped regions 122a and 123a. Transistor 120b may include gate structure 121b and doped regions 122b and 123b.

[0140] like Figure 1 As shown, each gate structure 121a and 121b can extend along the Y direction. As shown in FIG. 2, each gate structure 121a and 121 can be disposed on the surface 110s2 of the substrate 110. Each gate structure 121a and 121b may include a gate dielectric (not shown) and a gate electrode (not shown). The gate dielectric may have a single-layer or multi-layer structure. In some embodiments, the gate dielectric may include a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, other dielectric materials, or combinations thereof. In some embodiments, the gate dielectric is a multi-layer structure, including an interface layer and a high-k (dielectric constant greater than 4) dielectric layer. The interface layer may include a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, other dielectric materials, or combinations thereof. The high-dielectric layer may include high-dielectric materials such as HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, other suitable high-dielectric materials, or combinations thereof. In some embodiments, the high-dielectric material may be selected from metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides, metal aluminates, and combinations thereof.

[0141] A gate electrode is disposed on the gate dielectric. The gate electrode may include polysilicon, silicon-germanium, and at least one metal material, including elements and compounds such as molybdenum (Mo), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), nickel silicide (NiSi), cobalt silicide (CoSi), or other suitable conductive materials known in the art. In some embodiments, the gate electrode includes a functional metal layer to provide a metal gate with an n-type or p-type metal function. Materials for p-type metal function gates include, for example, ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), conductive metal oxides, or other suitable materials. Materials for n-type metal function gates include, for example, hafnium-zirconium, titanium (Ti), tantalum (Ta), aluminum (Al), metal carbides (e.g., hafnium carbide, zirconium carbide, titanium carbide, and aluminum carbide), aluminum compounds, or other suitable materials.

[0142] Each of the doped regions 122a, 123a, 122b, and 123b is disposed in the substrate 110 and adjacent to the surface 110s2 of the substrate 110. Figure 1 As shown, each of the doped regions 122a, 123a, 122b, and 123b extends along the Y direction. Doped regions 122a and 123a are disposed on two opposite sides of the gate structure 121a. Doped regions 122b and 123b are disposed on two opposite sides of the gate structure 121b. Each of the doped regions 122a, 123a, 122b, and 123b includes the second conductivity type. Each pair of doped regions 122a and 123a, and each pair of doped regions 122b and 123b, can also be referred to as source / drain features.

[0143] Each isolation feature 131, 132, and 133 may be disposed within the substrate 110 and extend from the surface 110s2 of the substrate 110. In some embodiments, each isolation feature 131, 132, and 133 may be a shallow trench isolation (STI). Isolation feature 131 may be disposed between isolation features 132 and 133. Isolation feature 131 may be disposed between transistors 120a and 120b. In some embodiments, isolation features 132 and 133, as well regions 114 and 116, may define a closed region surrounding the doped region 150.

[0144] The dielectric layer 140 may be disposed on the surface 110s2 of the substrate 110. The dielectric layer 140 may include silicon oxide, carbon oxides such as silicon carbide (SiOC), silicate glass, tetrachlorosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fluorine-doped silicon glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), combinations thereof, and / or other suitable dielectric materials.

[0145] The doped region 150 is disposed in the substrate 110. For example... Figure 1 As shown, the doped region 150 can extend along the Y direction. The doped region 150 can be aligned with gate structures 121a and 121b. The doped region 150 can be disposed between transistors 120a and 120b. Figure 2A As shown, in some embodiments, the doped region 150 is disposed below the isolation feature 131. The doped region 150 may be covered by the isolation feature 131 along the Z direction. In some embodiments, the doped region 150 may be configured to create a PN junction between the well region 112 and the doped region 150, thereby electrically isolating transistor 120a from transistor 120b. The doped region 150 may include the second conductivity type. In some embodiments, the doped region 150 may have a dopant concentration greater than that of the well regions 112 or 114. In some embodiments, the doped region 150 may consist of multiple doped regions, and there may be no boundary or a distinct boundary between these doped regions.

[0146] Conductive feature 171 may extend from surface 110s1 of substrate 110. Conductive feature 171 may be configured to couple with doped region 150, thus creating a PN junction. In some embodiments, conductive feature 171 may extend between surface 110s1 of substrate 110 and doped region 150. In some embodiments, conductive feature 171 may contact doped region 150. In some embodiments, conductive feature 171 may be exposed from surface 110s1 of substrate 110. In some embodiments, conductive feature 171 may penetrate a portion of substrate 110. In some embodiments, well region 116 contacts and is electrically coupled to conductive feature 171. In some embodiments, doped region 118 contacts and is electrically coupled to conductive feature 171. In some embodiments, conductive feature 171 may include a pad layer (not shown), a barrier layer (not shown), and a conductive layer (not shown). The pad layer may include an oxide or other suitable material. The barrier layer may include titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), manganese nitride (MnN), or combinations thereof. The conductive layer may include metals such as tungsten (W), copper (Cu), ruthenium (Ru), iridium (Ir), nickel (Ni), osmium (Os), rhodium (Rh), aluminum (Al), molybdenum (Mo), cobalt (Co), alloys thereof, or combinations thereof. In some embodiments, conductive feature 171 may be electrically connected to a power supply voltage V4. In some embodiments, the power supply voltage V4 is transmitted from the surface 110s1 of the substrate 110 to the doped region 150. For example, the power supply voltage V4 may be transmitted via, but is not limited to, a circuit structure or circuit board connected to the surface 110s1 of the substrate 110.

[0147] Conductive feature 172 may extend from surface 110s1 of substrate 110. Conductive feature 172 may be configured to couple with doped region 118, thus creating a PN junction. In some embodiments, conductive feature 172 may contact doped region 118. In some embodiments, conductive feature 172 may be exposed from surface 110s1 of substrate 110. In some embodiments, conductive feature 172 may penetrate a portion of substrate 110. In some embodiments, conductive feature 172 may extend between surface 110s1 of substrate 110 and doped region 118. Figure 2A As shown, conductive feature 171 may have a length L1 along the Z direction. Conductive feature 172 may have a length L2 along the Z direction. In some embodiments, L1 is greater than L2. Conductive feature 172 may be made of a material similar to or the same as conductive feature 171. In some embodiments, such as Figure 1 As shown, well region 114 can overlap with conductive feature 172 along the Z direction.

[0148] The semiconductor device structure 10a may further include a dielectric layer 180. The dielectric layer 180 may be disposed adjacent to the surface 110s1 of the substrate 110. The dielectric layer 180 may include a dielectric material, such as silicon oxide, silicon nitride, or other suitable materials.

[0149] In a comparative example, the power supply voltage of the doped region 150 is transmitted from the active surface of the substrate and penetrates the isolation feature. These conductive lines used to transmit the aforementioned power supply voltage may require additional area to accommodate them. In contrast, the power supply voltage V4 is transmitted from the back surface of the surface 110s1 of the substrate 110. Therefore, the size of the isolation feature 131 can be reduced, thereby increasing the effective area of ​​the semiconductor device structure 10a.

[0150] Figure 2B This is a cross-sectional view illustrating a semiconductor device structure 10a' of some examples of this disclosure. Figure 2B Semiconductor device structure 10a' and Figure 2A The semiconductor device structure 10a is similar to that of the semiconductor device structure 10a', except that the semiconductor device structure 10a' further includes conductive structures 161a, 162a, 163a, 161b, 162b and 163b.

[0151] Each conductive structure 161a, 162a, 163a, 161b, 162b, and 163b can penetrate the dielectric layer 140. Each conductive structure 161a, 162a, 163a, 161b, 162b, and 163b can include a conductive material, such as a metal, like tungsten (W), copper (Cu), ruthenium (Ru), iridium (Ir), nickel (Ni), osmium (Os), rhodium (Rh), Al, molybdenum (Mo), cobalt (Co), alloys thereof, or combinations thereof. Conductive structure 161a can be electrically coupled to gate structure 121a. Conductive structure 162a can be electrically coupled to doped region 122a. Conductive structure 163a can be electrically coupled to doped region 123a. Conductive structure 161b can be electrically coupled to gate structure 121b. Conductive structure 162b can be electrically coupled to doped region 122b. The conductive structure 163b can be electrically coupled to the doped region 123b. In this disclosure, each of the conductive structures 161a, 162a, 163a, 161b, 162b and 163b can be referred to as a "zero metal layer (M0)".

[0152] In some embodiments, different power supply voltages can be applied to conductive structures 161a, 162a, and 163a. ​​For example, conductive structure 161a can be electrically connected to power supply voltage V1, conductive structure 162a can be electrically connected to power supply voltage V2, and conductive structure 163a can be electrically connected to power supply voltage V3. In some embodiments, each of power supply voltages V1, V2, and V3 is electrically isolated from doped region 150. In some embodiments, each of power supply voltages V1, V2, and V3 can be transmitted from surface 110s2 of substrate 110. For example, the conductive lines transmitting power supply voltages V1, V2, and V3 may include a first metal layer (M1) disposed on M0 and a second metal layer (M2) disposed on M1, and so on. Similarly, different power supply voltages can be applied to conductive structures 161b, 162b, and 163b.

[0153] Figure 3 This is a cross-sectional view illustrating a semiconductor device structure 10b of some examples of this disclosure. The semiconductor device structure 10b has a structure similar to that of the semiconductor device structure 10a', wherein the difference is that the semiconductor device structure 10b further includes a conductive structure 164.

[0154] A conductive structure 164 may be disposed on the surface 110s2 of the substrate 110. In some embodiments, the conductive structure 164 may penetrate the isolation feature 131. In some embodiments, the conductive structure 164 may be electrically coupled to the doped region 150. In some embodiments, the conductive structure 164 may contact the doped region 150. In some embodiments, the conductive structure 164 may be connected to the conductive feature 171 (or... Figure 2B The power supply voltage V4 shown is electrically coupled. The conductive structure 164 can be configured to couple electrical signals, such as... Figure 2B The power supply voltage shown is transmitted to other components (not shown). In this embodiment, not all power supply voltages are electrically coupled from the active surface of the substrate to transistors or other components. Therefore, the layout of the metal wires can be designed in a more flexible manner.

[0155] Figure 4 This is a cross-sectional view illustrating a semiconductor device structure 10c of some examples of this disclosure. Semiconductor device structure 10c has a structure similar to that of semiconductor device structure 10b, except for the doped region 118.

[0156] In some embodiments, the doped region 118 may be spaced apart from the conductive feature 171. In some embodiments, the doped region 118 may have the same annular profile as the well region 114. In some embodiments, the doped region 118 may have a plurality of mutually separated portions, each of which may be spaced apart from the conductive feature 171. Figure 1 A conductive feature 172 contact is shown in the top view.

[0157] Figure 5 This is a cross-sectional view illustrating a semiconductor device structure 10d of some examples of this disclosure.

[0158] Semiconductor device structure 10d has a similar structure to semiconductor device structure 10b, except that semiconductor device structure 10d further includes circuit structure 200 and circuit board 300.

[0159] In some embodiments, circuit structure 200 may be bonded or connected to surface 110s1 of substrate 110. Circuit structure 200 may be configured to provide or transmit a voltage electrically coupled to doped region 150. Circuit structure 200 may include surface 200s1 (or lower surface), surface 200s2 (or upper surface), and surface 200s3 (or side surface). Surface 200s2 is opposite to surface 200s1. Surface 200s2 of circuit structure faces surface 100s1 of substrate 100. Surface 200s3 extends between surface 200s1 and surface 200s2. In some embodiments, surface 200s3 of circuit structure 200 and surface 110s3 of substrate 110 are discontinuous. In some embodiments, surface 200s3 of circuit structure 200 is not coplanar with surface 110s3 of substrate 110. Circuit structure 200 may include substrate 210, dielectric structure 220, conductive structure 230, and terminal 240.

[0160] The substrate 210 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor on insulator (SOI) substrate, etc. The substrate 210 may include a basic semiconductor, including silicon or germanium in single crystal form, silicon or germanium in polycrystalline form, or germanium in amorphous form.

[0161] The circuit structure 200 may include multiple isolation features 212. The isolation features 212 may be embedded in the substrate 210. The isolation features 212 may be shallow trench isolation (STI).

[0162] The circuit structure 200 may further include a plurality of gate structures 214. The gate structures 214 may be disposed on the substrate 210. The gate structures 214 may be separated from each other by isolation features 212. Each gate structure 214 may include a gate dielectric (not shown) and a gate electrode (not shown).

[0163] Dielectric structure 220 may be disposed on substrate 210. Dielectric structure 220 may include multiple dielectric layers. Dielectric structure 220 may include oxides, nitrides, or other suitable materials. In some embodiments, the material of dielectric structure 220 may be similar to or the same as the material of dielectric layer 180. For example, both dielectric structure 220 and dielectric layer 180 include silicon oxide.

[0164] The conductive structure 230 may be disposed within the substrate 210 and the dielectric structure 220. The conductive structure 230 may be disposed to electrically connect the circuit board 300 and the conductive feature 171. The conductive structure 230 may be electrically coupled to the circuit board 300. The conductive structure 230 may include conductive materials such as tungsten (W), copper (Cu), ruthenium (Ru), iridium (Ir), Ni, osmium (Os), rhodium (Rh), Al, molybdenum (Mo), cobalt (Co), alloys thereof, or combinations thereof. The conductive structure 230 may include conductive vias 231, and terminals 233a, 233b, and 233c.

[0165] In some embodiments, the conductive via 231 may penetrate the substrate 210. In some embodiments, the conductive via 231 may penetrate a portion of the dielectric structure 220. In some embodiments, the conductive via 231 may be exposed from the surface 200s1 of the circuit structure 200.

[0166] In some embodiments, terminal 233a may be electrically coupled to conductive feature 171. In some embodiments, terminal 233a may be in contact with conductive feature 171. In some embodiments, each terminal 233b and 233c may be electrically coupled to a corresponding conductive feature 172. In some embodiments, each of terminals 233b and 233c may be in contact with a corresponding conductive feature 172. In some embodiments, each terminal 233a, 233b, and 233c may be exposed from surface 200s2 of circuit structure 200. In some embodiments, each of terminals 233a, 233b, and 233c may include a conductive pad or other unit.

[0167] In some embodiments, the substrate 110 may be hybrid-bonded with the circuit structure 200. For example, the substrate 110 is bonded to the dielectric layer 180 of the circuit structure 200 through the dielectric structure 220 of the circuit structure 200, and to the conductive features 171 and 172 of the substrate 110 through the terminals 233a, 233b and 233c of the circuit structure 200, thereby bonding the substrate 110 to the circuit structure 200.

[0168] Terminal 240 may be disposed on surface 200s1 of circuit structure 200. Terminal 240 may electrically connect conductive structure 230 of circuit structure 200 and circuit board 300. In some embodiments, terminal 240 is a solder ball (e.g., Sn ball).

[0169] The circuit board 300 can be connected to the circuit structure 200 via terminals 240. The circuit board 300 can be configured to supply power to the circuit structure 200. In some embodiments, the power supply may include, for example, a direct current (DC) bias. The circuit board may include, but is not limited to, a printed circuit board, a flexible printed circuit board, or other circuit boards.

[0170] In this embodiment, the circuit board 300 can provide power, electrically coupled from the surface 110s1 of the substrate 110 to the doped region 150. Therefore, transistor 120a can be electrically isolated from transistor 120b. Furthermore, the circuit board 300 can also provide power, electrically coupled to other components via conductive structure 164.

[0171] Figure 6A , Figure 6B , Figure 6C , Figure 6D , Figure 6E , Figure 6F , Figure 6G , Figure 6H , Figure 6I and Figure 6J The various fabrication stages of a semiconductor device structure 10b, representing some examples of this disclosure, are illustrated.

[0172] Reference Figure 6A A substrate 110 may be provided. A well region 112 may be formed in the substrate 110. Isolation features 131, 132 and 133 may be formed in the substrate 110 and adjacent to the surface 110s2 of the substrate 110.

[0173] Reference Figure 6B Gate structures 121a and 121b can be formed on the surface 110s2 of the substrate 110. Gate structures 121a and 121b can be formed on two opposite sides of the isolation feature 131.

[0174] Reference Figure 6C The dielectric layer 140 can be formed on the surface 110s2 of the substrate 110. The dielectric layer 140 can cover the surface 110s2 of the substrate 110. The dielectric layer 140 can cover the gate structures 121a and 121b. The dielectric layer 140 can be fabricated using chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), flowable CVD (FCVD), spin coating, or similar processes.

[0175] Reference Figure 6D Multiple openings 140o1, 140o2, 140o3, and 140o4 can be formed. Each opening 140o1, 140o2, 140o3, and 140o4 can penetrate the dielectric layer 140. Opening 140o4 can also penetrate the isolation feature 131. The openings 140o1, 140o2, 140o3, and 140o4 can be fabricated using etching processes, such as wet etching, dry etching, or other suitable processes.

[0176] Reference Figure 6EDoped regions 122a, 122b, 123a, 123b, and 150 can be formed within the substrate 110. Therefore, transistors 120a and 120b can be formed. In some embodiments, the doped regions 122a, 122b, 123a, 123b, and 150 can be fabricated using the same implantation process. In some embodiments, the doped regions 122a, 122b, 123a, 123b, and 150 can be fabricated using different implantation processes.

[0177] Reference Figure 6F Well regions 114 and 116 can be formed within the substrate 110. In some embodiments, well regions 114 and 116 can be fabricated using the same implantation process. In some embodiments, well regions 114 and 116 can be fabricated using different implantation processes.

[0178] Reference Figure 6G Doped region 118 can be formed within well region 116. It should be understood that the order in which well regions 112, 114, 116 and doped region 118 are formed can be modified.

[0179] Reference Figure 6H Conductive structures 161a, 162a, 163a, 161b, 162b, 163b, and 164 can be formed to fill openings 140o1, 140o2, 140o3, and 140o4. The conductive structures 161a, 162a, 163a, 161b, 162b, 163b, and 164 can be fabricated using sputtering, chemical vapor deposition (CVD), physical vapor deposition (PVD), electrochemical plating (ECP), electrodeposition (ELD), atomic layer deposition (ALD), or similar processes, or combinations thereof.

[0180] Reference Figure 6I A dielectric layer 180 may be formed on the surface 110s1 of the substrate 110. In some embodiments, the dielectric layer 180 may be fabricated by oxidation of the substrate 110. In some embodiments, a removal process may be performed prior to the formation of the dielectric layer 180 to remove the substrate 110 from the surface 110s1 of the substrate 110. In some embodiments, the removal process may include, for example, a chemical mechanical polishing process.

[0181] Reference Figure 6JConductive features 171 and 172 can be formed. Thus, a semiconductor device structure 10b can be produced. In some embodiments, a plurality of openings are formed to expose doped regions 150 and 118. These openings can extend from the surface 110s1 of the substrate 110. A pad layer (not shown), a barrier layer (not shown), and a conductive layer are then formed to fill these openings, forming conductive features 171 and 172. In some embodiments, the pad layer, barrier layer, and conductive layer can be fabricated using sputtering, CVD, PVD, ECP, ELD, ALD, or similar processes, or combinations thereof. Conductive feature 171 can contact doped region 150, while conductive feature 172 can contact doped region 118.

[0182] Figure 7A and Figure 7B This disclosure illustrates various fabrication stages of a semiconductor device structure 10d, representing some examples. In some embodiments, Figure 7A The previous initial stage and Figures 6A to 6J The stages described in the text are the same or similar. Figure 7A Depicting Figure 6J The stage following the stage described in the text.

[0183] Reference Figure 7A A circuit structure 200 can be provided and bonded to the surface 110s1 of the substrate 110. The surface 200s2 of the circuit structure 200 can be bonded to the surface 110s1 of the substrate 110. In some embodiments, the circuit structure 200 can be hybrid-bonded to the substrate 110. For example, the substrate 110 is bonded to the dielectric layer 180 of the substrate 110 through the dielectric structure 220 of the circuit structure 200, and to the conductive features 171 and 172 of the substrate 110 through the terminals 233a, 233b and 233c of the circuit structure 200.

[0184] Reference Figure 7B A circuit board 300 can be provided and bonded to the surface 200s1 of the circuit structure 200 via terminals 240. Thus, a semiconductor element structure 10d can be formed.

[0185] Figure 8 This is a flowchart illustrating a method for fabricating semiconductor device structures according to some examples of this disclosure 20.

[0186] Preparation method 20 begins with operation S21, in which a substrate is provided. The substrate has a first surface and a second surface opposite to the first surface, wherein the substrate includes a first well region having a first conductivity type.

[0187] Preparation method 20 continues with operation S22, in which an isolation feature is formed. The isolation feature extends from the second surface of the substrate.

[0188] The fabrication method 20 continues to operation S23, wherein a first transistor and a second transistor are formed adjacent to the second surface of the substrate.

[0189] Preparation method 20 continues with operation S24, wherein a first doped region is formed below the isolation feature. The first doped region has a second conductivity type different from the first conductivity type.

[0190] Preparation method 20 continues to operation S25, wherein a second well region is formed in the substrate and surrounds the first doped region.

[0191] Preparation method 20 continues with operation S26, wherein a third well region is formed. The third well region is spaced apart from and in contact with the second surface of the substrate.

[0192] Preparation method 20 continues with operation S27, wherein a second doped region is formed in the third well region.

[0193] Preparation method 20 continues to operation S28, wherein a first conductive feature is formed. The first conductive feature extends between the first surface of the substrate and the first doped region, wherein the first conductive feature is electrically coupled to the first doped region.

[0194] Preparation method 20 continues to operation S29, wherein a second conductive feature is formed. The second conductive feature extends between the first surface of the substrate and the second doped region.

[0195] Preparation method 20 is merely illustrative and is not intended to limit the scope of this disclosure beyond the claims. Additional operations may be provided before, during, or after each operation of preparation method 20, and some of these operations may be replaced, eliminated, or moved for other embodiments of the preparation method. In some embodiments, preparation method 20 may further include... Figure 8 Operations not described herein. In some embodiments, preparation method 20 may include... Figure 8 One or more operations described in the document.

[0196] Figure 9 This is a flowchart illustrating a method for fabricating semiconductor device structures according to some examples of this disclosure 30.

[0197] Fabrication method 30 begins with operation S31, wherein a substrate is provided. The substrate has a first surface and a second surface opposite the first surface, wherein the substrate includes a first well region having a first conductivity type. The substrate includes a first transistor and a second transistor adjacent to the second surface of the substrate. The substrate includes a first doped region having a second conductivity type different from the first conductivity type. The substrate includes a conductive feature extending between the first surface of the substrate and the first doped region.

[0198] Preparation method 30 continues to operation S32, wherein a dielectric layer is formed on the first surface of the substrate.

[0199] Preparation method 30 continues to operation S33, wherein a circuit structure is provided on the first surface of the substrate. The circuit structure is hybrid-bonded to the substrate.

[0200] Preparation method 30 continues to operation S34, wherein a circuit board is provided on the circuit structure. The circuit board is bonded to the circuit structure by a solder ball.

[0201] Preparation method 30 is merely illustrative and is not intended to limit the scope of this disclosure beyond the claims. Additional operations may be provided before, during, or after each operation of preparation method 30, and some of these operations may be replaced, eliminated, or moved for other embodiments of the preparation method. In some embodiments, preparation method 30 may include… Figure 9 One or more operations described in the document.

[0202] One embodiment of this disclosure provides a semiconductor device structure. The semiconductor device structure includes a first substrate, a first well region, a first gate structure, a second gate structure, a first doped region, and a first conductive feature. The first substrate has a first surface and a second surface opposite to the first surface. The first well region is disposed in the first substrate. The first well region has a first conductivity type. The first gate structure is disposed on the second surface. The second gate structure is disposed on the second surface. The first doped region has a second conductivity type different from the first conductivity type. The first doped region is disposed between the first gate structure and the second gate structure. The first conductive feature extends between the first surface of the first substrate and the first doped region.

[0203] Another embodiment of this disclosure provides a semiconductor device structure. The semiconductor device structure includes a substrate, a first well region, a first transistor, a second transistor, a first doped region, and a circuit structure. The substrate has an active surface and a back surface. The first well region is disposed in the substrate. The first well region has a first conductivity type. The first transistor is adjacent to the active surface of the substrate. The second transistor is adjacent to the active surface of the substrate. The first doped region includes a second conductivity type different from the first conductivity type. The first doped region is disposed between the first well region and the first transistor and the second transistor. The circuit structure is disposed on the back surface of the substrate. The circuit structure is configured to transmit or provide a voltage electrically coupled to the first doped region.

[0204] Another embodiment of this disclosure provides a method for fabricating a semiconductor device structure. The method includes: providing a substrate having a first surface and a second surface opposite to the first surface, wherein the substrate includes a first well region having a first conductivity type; forming an isolation feature extending from the second surface of the substrate; forming a first transistor and a second transistor adjacent to the second surface of the substrate; forming a first doped region below the isolation feature, wherein the first doped region has a second conductivity type different from the first conductivity type; and providing a circuit structure on the first surface of the substrate, wherein the circuit structure is configured to transmit or provide a voltage electrically coupled to the first doped region.

[0205] Another embodiment of this disclosure provides a method for fabricating a semiconductor device structure. The method includes: providing a substrate having a first surface and a second surface opposite to the first surface, wherein the substrate includes a first well region having a first conductivity type; forming a first transistor and a second transistor adjacent to the second surface of the substrate; forming a first doped region between the first transistor and the second transistor, wherein the first doped region has a second conductivity type different from the first conductivity type; and forming a first conductive feature extending between the first surface of the substrate and the first doped region.

[0206] Embodiments of this disclosure disclose a semiconductor device structure having a doped region in a substrate. The doped region has a different conductivity type than the well regions of the substrate. The doped region is configured to create a PN junction for electrically isolating adjacent transistors. Furthermore, the semiconductor device structure includes a conductive structure extending from the back surface of the substrate for electrical coupling with the doped region. A power supply, such as a DC bias voltage, is provided from the back surface to couple with the doped region through the conductive structure, creating a PN junction between the doped region and the well regions of the substrate. In a comparative example, conductive lines configured to couple with the doped region are disposed on the active surface of the substrate. These conductive lines require additional area to accommodate them, thus reducing the size of the active region of the transistor. Compared to the comparative example, embodiments of this disclosure can increase the size of the active region of the transistor, thus improving the performance of the semiconductor device structure.

[0207] While this disclosure and its advantages have been detailed, it should be understood that various changes, substitutions, and alternatives can be made without departing from the spirit and scope of this disclosure as defined by the scope of the disclosed patent. For example, many of the processes described above can be implemented in different ways, and many of the processes described above can be replaced by other processes or combinations thereof.

[0208] Furthermore, the scope of this disclosure is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used in accordance with this disclosure. Accordingly, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of the patent disclosed in this disclosure.

Claims

1. A semiconductor device structure, comprising: A first substrate having a first surface and a second surface opposite to the first surface; A first well region is disposed in the first substrate, wherein the first well region has a first conductivity type; A first gate structure is disposed on the second surface; A second gate structure is disposed on the second surface; A first doped region having a second conductivity type different from the first conductivity type, wherein the first doped region is disposed between the first gate structure and the second gate structure; A first conductive feature extends between the first surface of the first substrate and the first doped region. A second well region is disposed in the first substrate and surrounds the first gate structure and the second gate structure; A third well region is disposed in the first substrate and in contact with the second well region, wherein the third well region is in contact with the first conductive feature, and each of the second and third well regions has the second conductivity type; and A second doped region is disposed in the third well region, wherein the second doped region has the second conductivity type.

2. The semiconductor device structure as described in claim 1, further comprising: An isolation feature is adjacent to the second surface of the first substrate, wherein the first doped region is located between the isolation feature and the first conductive feature.

3. The semiconductor device structure as described in claim 2, further comprising: A conductive structure penetrates the isolation feature and contacts the first doped region.

4. The semiconductor device structure of claim 3, wherein the first conductive feature is electrically coupled to the conductive structure.

5. The semiconductor device structure as described in claim 1, further comprising: A second conductive feature extends between the first surface of the first substrate and the second doped region.

6. The semiconductor element structure of claim 5, wherein a first length of the first conductive feature in a first direction is greater than a second length of the second conductive feature in the first direction.

7. The semiconductor device structure of claim 5, wherein the second doped region is in contact with the first conductive feature.

8. The semiconductor device structure of claim 5, wherein the second doped region is spaced apart from the first conductive feature.

9. The semiconductor device structure as claimed in claim 1, further comprising: A circuit structure is disposed on the first surface of the first substrate, wherein the circuit structure is electrically connected to the first conductive feature.

10. The semiconductor device structure of claim 9, further comprising: A circuit board is bonded to the circuit structure, wherein the circuit structure is disposed between the circuit board and the first substrate.

11. The semiconductor device structure as described in claim 9, further comprising: A first dielectric layer is disposed on the first surface of the first substrate; The circuit structure includes a terminal for contacting the first conductive feature and a dielectric structure for contacting the first dielectric layer.

12. A semiconductor device structure, comprising: A substrate having an active surface and a back surface; A first well region is disposed in the substrate, wherein the first well region has a first conductivity type; A first transistor is adjacent to the active surface of the substrate; A second transistor is adjacent to the active surface of the substrate; A first doped region having a second conductivity type different from the first conductivity type, wherein the first doped region is disposed between the first well region and the first transistor and the second transistor; and A circuit structure is disposed on the back surface of the substrate, wherein the circuit structure is configured to transmit or provide a voltage electrically coupled to the first doped region.

13. The semiconductor device structure of claim 12, further comprising: A first conductive feature is exposed from the back surface of the substrate, wherein the first conductive feature electrically connects the circuit structure and the first doped region.

14. The semiconductor device structure of claim 13, further comprising: A conductive structure extends from the active surface of the substrate, wherein the conductive structure is electrically coupled to the first doped region.

15. The semiconductor device structure of claim 14, further comprising: A first isolation feature is disposed in the substrate and located between the first transistor and the second transistor, wherein the conductive structure penetrates the first isolation feature.

16. The semiconductor device structure of claim 14, wherein the conductive structure is perpendicularly aligned with the first conductive feature.

17. The semiconductor device structure of claim 13, further comprising: A second well region is disposed in the substrate and surrounds the first doped region; as well as A third well region, spaced apart from the active surface of the substrate and in contact with the second well region, wherein the first conductive feature penetrates the third well region, and each of the second and third well regions has the second conductive type.

18. The semiconductor device structure of claim 15, wherein one side of the circuit structure and one side of the substrate are discontinuous.

19. A method for fabricating a semiconductor device structure, comprising: A substrate is provided having a first surface and a second surface opposite to the first surface, wherein the substrate includes a first well region having a first conductivity type; Forming an isolation feature extending from the second surface of the substrate; A first transistor and a second transistor are formed adjacent to the second surface of the substrate; A first doped region is formed below the isolation feature, wherein the first doped region has a second conductivity type different from the first conductivity type; as well as A circuit structure is provided on the first surface of the substrate, wherein the circuit structure is configured to transmit or provide a voltage electrically coupled to the first doped region.

20. The preparation method according to claim 19, further comprising: A first conductive feature is formed, which extends between the first surface of the substrate and the first doped region, wherein the first conductive feature is electrically coupled to the circuit structure.

21. The preparation method according to claim 20, further comprising: A dielectric layer is formed on the first surface of the substrate, wherein the circuit structure has a dielectric structure and a terminal is provided on a surface bonded to the first surface of the substrate, wherein the dielectric layer of the substrate is in contact with the dielectric structure of the circuit structure, and the terminal of the circuit structure is in contact with the first conductive feature of the substrate.

22. The preparation method according to claim 20, further comprising: A second well region is formed in the substrate to surround the first doped region; as well as A third well region is formed that is spaced apart from the second surface of the substrate and in contact with the second well region.

23. The preparation method according to claim 22, further comprising: A second doped region is formed in this third well region; as well as A second conductive feature is formed, which extends between the first surface of the substrate and the second doped region.

24. A method for fabricating a semiconductor device structure, comprising: A substrate is provided having a first surface and a second surface opposite to the first surface, wherein the substrate includes a first well region having a first conductivity type; A first transistor and a second transistor are formed adjacent to the second surface of the substrate; A first doped region is formed between the first transistor and the second transistor, wherein the first doped region has a second conductivity type different from the first conductivity type; as well as A first conductive feature is formed, which extends between the first surface of the substrate and the first doped region.

25. The preparation method according to claim 24, further comprising: A circuit structure is provided on the first surface of the substrate, wherein the circuit structure is configured to transmit or provide a voltage electrically coupled to the first doped region via the first conductive feature.

26. The preparation method according to claim 25, further comprising: A circuit board is provided on the circuit structure, wherein the circuit board is bonded to the circuit structure by a solder ball.

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