lateral diffused metal oxide semiconductor element

Abstract

A lateral diffusion metal oxide semiconductor element mainly comprises a first fin structure disposed on a substrate, a second fin structure disposed beside the first fin structure, a shallow trench isolation disposed between the first fin structure and the second fin structure, a first gate structure disposed on the first fin structure, a second gate structure disposed on the second fin structure, and a gas hole disposed between the first gate structure and the second gate structure.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor device, and in particular, to a lateral diffused metal oxide semiconductor (LDMOS) device. BACKGROUND

[0002] Lateral diffused MOS (LDMOS) devices have been widely used in high voltage operating environments, such as CPU power supply, power management system, AC / DC converter, and high power or high frequency power amplifier, due to their high operating frequency and efficiency, and planar structure which is easy to integrate with other integrated circuits.

[0003] As the device size continues to shrink, the development of existing planar field effect transistor devices has faced the limit of fabrication process. In order to overcome the fabrication process limit, it has become a mainstream development trend to replace planar transistor devices with non-planar field effect transistor devices, such as fin field effect transistor (Fin FET) devices. Since the three-dimensional structure of the fin field effect transistor device can increase the contact area between the gate and the fin structure, the control of the gate on the carrier channel region can be further increased, thereby reducing the drain induced barrier lowering (DIBL) effect faced by small size devices and suppressing the short channel effect (SCE). Furthermore, the fin field effect transistor device can have a wider channel width under the same gate length, thereby obtaining doubled drain drive current. Even the threshold voltage of the transistor device can be regulated by adjusting the work function of the gate.

[0004] However, there are still many challenges in the integration of existing lateral diffused metal oxide semiconductor devices and fin structures as the device size continues to shrink, such as control of leakage current and breakdown voltage. Therefore, how to improve the existing high voltage device architecture is an important issue today. SUMMARY

[0005] A lateral diffusion metal oxide semiconductor device is disclosed in one embodiment of the present invention, which mainly comprises a first fin structure disposed on a substrate, a second fin structure disposed beside the first fin structure, a shallow trench isolation disposed between the first fin structure and the second fin structure, a first gate structure disposed on the first fin structure, a second gate structure disposed on the second fin structure, and a via hole disposed between the first gate structure and the second gate structure.

[0006] A lateral diffusion metal oxide semiconductor device is disclosed in another embodiment of the present invention, which mainly comprises a first fin structure disposed on a substrate, a second fin structure disposed beside the first fin structure, a third fin structure disposed between the first fin structure and the second fin structure, a first shallow trench isolation disposed between the first fin structure and the third fin structure, a second shallow trench isolation disposed between the second fin structure and the third fin structure, a first gate structure disposed on the first fin structure, a second gate structure disposed on the second fin structure, a third gate structure disposed on the third fin structure, and a first via hole disposed between the first gate structure and the third gate structure.

[0007] A lateral diffusion metal oxide semiconductor device is disclosed in another embodiment of the present invention, which mainly comprises a first fin structure disposed on a substrate, a second fin structure disposed beside the first fin structure, a third fin structure disposed between the first fin structure and the second fin structure, a first shallow trench isolation disposed between the first fin structure and the third fin structure, a second shallow trench isolation disposed between the second fin structure and the third fin structure, a first gate structure disposed on the first fin structure, a second gate structure disposed on the second fin structure, a third gate structure disposed on the third fin structure, and a first via hole disposed between the first gate structure and the third gate structure. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figures 1 to 4 A lateral diffusion metal oxide semiconductor device is disclosed in one embodiment of the present invention, which mainly comprises a first fin structure disposed on a substrate, a second fin structure disposed beside the first fin structure, a shallow trench isolation disposed between the first fin structure and the second fin structure, a first gate structure disposed on the first fin structure, a second gate structure disposed on the second fin structure, and a via hole disposed between the first gate structure and the second gate structure.

[0009] Figure 5 A lateral diffusion metal oxide semiconductor device is disclosed in one embodiment of the present invention, which mainly comprises a first fin structure disposed on a substrate, a second fin structure disposed beside the first fin structure, a shallow trench isolation disposed between the first fin structure and the second fin structure, a first gate structure disposed on the first fin structure, a second gate structure disposed on the second fin structure, and a via hole disposed between the first gate structure and the second gate structure.

[0010] Figure 6 A lateral diffusion metal oxide semiconductor device is disclosed in one embodiment of the present invention, which mainly comprises a first fin structure disposed on a substrate, a second fin structure disposed beside the first fin structure, a shallow trench isolation disposed between the first fin structure and the second fin structure, a first gate structure disposed on the first fin structure, a second gate structure disposed on the second fin structure, and a via hole disposed between the first gate structure and the second gate structure.

[0011] Figure 7 A lateral diffusion metal oxide semiconductor device is disclosed in one embodiment of the present invention, which mainly comprises a first fin structure disposed on a substrate, a second fin structure disposed beside the first fin structure, a shallow trench isolation disposed between the first fin structure and the second fin structure, a first gate structure disposed on the first fin structure, a second gate structure disposed on the second fin structure, and a via hole disposed between the first gate structure and the second gate structure. Figure 6 A lateral diffusion metal oxide semiconductor device is disclosed in one embodiment of the present invention, which mainly comprises a first fin structure disposed on a substrate, a second fin structure disposed beside the first fin structure, a shallow trench isolation disposed between the first fin structure and the second fin structure, a first gate structure disposed on the first fin structure, a second gate structure disposed on the second fin structure, and a via hole disposed between the first gate structure and the second gate structure.

[0012] Figure 8 A lateral diffusion metal oxide semiconductor device is disclosed in one embodiment of the present invention, which mainly comprises a first fin structure disposed on a substrate, a second fin structure disposed beside the first fin structure, a shallow trench isolation disposed between the first fin structure and the second fin structure, a first gate structure disposed on the first fin structure, a second gate structure disposed on the second fin structure, and a via hole disposed between the first gate structure and the second gate structure.

[0013] Figure 9For Figure 8 A cross-sectional view of a lateral diffusion metal oxide semiconductor element along the tangent CC' is shown in FIG. 1.

[0014] Figure 10 A structure diagram of a lateral diffusion metal oxide semiconductor element according to an embodiment of the present application is shown in FIG. 2.

[0015] Main element symbol explanation

[0016] 12: substrate

[0017] 14: first fin structure

[0018] 16: second fin structure

[0019] 18: P well

[0020] 20: N well

[0021] 22: shallow trench isolation

[0022] 24: gate structure

[0023] 26: gate structure

[0024] 28: gate structure

[0025] 30: gate structure

[0026] 32: gate dielectric layer

[0027] 34: gate material layer

[0028] 36: spacer

[0029] 38: source region

[0030] 40: drain region

[0031] 42: interlayer dielectric layer

[0032] 44: dielectric layer

[0033] 46: high dielectric constant dielectric layer

[0034] 48: work function metal layer

[0035] 50: low impedance metal layer

[0036] 52: hard mask

[0037] 54: interlayer dielectric layer

[0038] 56: contact plug

[0039] 58: contact plug

[0040] 60: air gap

[0041] 62: Gate structure

[0042] 64: Third fin structure

[0043] 66: Stomata Detailed Implementation

[0044] Please refer to Figures 1 to 4 , Figures 1 to 4 This is a schematic diagram of a method for fabricating a laterally diffused metal-oxide-semiconductor device according to an embodiment of the present invention, wherein... Figure 1 This is a top view of a laterally diffused metal-oxide-semiconductor device according to an embodiment of the present invention. Figures 2 to 4 Then it is Figure 1 A cross-sectional view of a laterally diffused metal-oxide-semiconductor device is fabricated along tangent AA'. (See diagram below.) Figures 1 to 2 As shown, a substrate 12 is first provided, and then multiple fin-like structures, such as a first fin-like structure 14 and a second fin-like structure 16, are formed on the substrate 12. A first well region (e.g., P-well 18) and a second well region (e.g., N-well 20) are formed within the first fin-like structure 14 and the second fin-like structure 16. Next, a shallow trench isolation (STI) 22 is formed between the first fin-like structure 14 and the second fin-like structure 20, with the upper surface of the shallow trench isolation 22 slightly lower than the upper surfaces of the first fin-like structure 14 and the second fin-like structure 16. The first well region (e.g., P-well 18) is entirely located within the first fin-like structure 14, while the second well region (e.g., N-well 20) is located within the second fin-like structure 16 and the first fin-like structure 14. Furthermore, the contact shallow trench isolation 22 is entirely located within the second well region (e.g., N-well 20).

[0045] In this embodiment, the substrate 12 is preferably made of a semiconductor material, such as a silicon substrate, an epitaxial silicon substrate, a silicon-germanium substrate, a silicon carbide substrate, or a silicon-on-insulator (SOI) substrate, and the shallow trench isolation 22 is preferably made of silicon oxide, but is not limited thereto. Furthermore, in this embodiment... Figure 1 Although the top view shows seven first fin-like structures 14 and seven second fin-like structures 16 extending along the X direction on the base 12 as an example, the number of fin-like structures is not limited to this and can be adjusted according to the manufacturing process or product requirements.

[0046] According to the preferred embodiment of the present application, the fin structures 14, 16 are preferably formed by a sidewall image transfer (SIT) process, which generally includes the following steps. First, a layout pattern is provided to a computer system, and the corresponding pattern is defined in a photo mask by appropriate computation. Then, a plurality of equidistant and equi-width patterned sacrificial layers are formed on the substrate by photolithography and etching processes, so that each of the patterned sacrificial layers has a strip-like appearance. Subsequently, deposition and etching processes are performed in sequence to form spacers on the sidewalls of the patterned sacrificial layers. After the patterned sacrificial layers are removed, etching processes are performed under the coverage of the spacers, so that the pattern formed by the spacers is transferred into the substrate. Finally, a fin cut process is performed to obtain the desired patterned structures, such as the strip-like patterned fin structures 14, 16.

[0047] In addition, the fin structures 14, 16 can also be formed by the following methods. First, a patterned mask (not shown) is formed on the substrate 12, and then an etching process is performed to transfer the pattern of the patterned mask into the substrate 12 to form the first and second fin structures 14, 16. Alternatively, a patterned hard mask layer (not shown) is formed on the substrate 12, and then an epitaxial process is performed to grow a semiconductor layer, such as a silicon germanium layer, on the substrate 12 exposed by the patterned hard mask layer, so that the semiconductor layer serves as the first and second fin structures 14, 16. These methods for forming the fin structures are also within the scope of the present application.

[0048] A gate structure 24 is then formed on the first fin structure 14, a gate structure 26 is formed on the first fin structure 14 to the left of the gate structure 24, and gate structures 28 and 30 are formed on the second fin structure 16. In the present embodiment, the gate structures can be formed by a gate-first process, a gate-last process, a high-k first process, or a high-k last process, depending on the process requirements. In the present embodiment, a high-k last process is used as an example. First, a gate dielectric layer 32 or a dielectric layer made of silicon oxide, a gate material layer 34 made of polysilicon, and a selective hard mask (not shown) are sequentially formed on the substrate 12. A patterned photoresist (not shown) is used as a mask to perform a pattern transfer process. The gate material layer 34 and the gate dielectric layer 32 are removed by a single etching or a sequential etching process. The patterned photoresist is then removed to form the gate structures 24, 26, 28, and 30 on the substrate 12.

[0049] At least one spacer 36 is then formed on the sidewalls of the gate structures 24, 26, 28, and 30. A source region 38 made of, for example, an N+ region is formed in the first fin structure 14 to the left of the gate structure 24, and a drain region 40 made of, for example, an N+ region is formed in the second fin structure 16 to the right of the gate structure 28. In the present embodiment, the spacer 36 can be a single spacer or a composite spacer, such as a bias spacer and a main spacer. The bias spacer and the main spacer can be made of the same or different materials, and can be selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbon nitride. The source region 38 and the drain region 40 can be doped with different dopants, such as P-type or N-type dopants, depending on the conductivity type of the transistors to be formed.

[0050] As shown in FIG. 1C, the substrate 12 is then thinned to form a substrate 42. The substrate 42 can be made of silicon, germanium, or a semiconductor material containing silicon and germanium. The substrate 42 can be thinned by a chemical mechanical polishing (CMP) process or a grinding process. The substrate 42 can be thinned to a thickness of, for example, 1-10 microns. Figure 3As shown, an interlayer dielectric layer 42 is then formed on the gate structures 24, 26, 28, 30 and the shallow trench isolation 22, and a planarization process is performed, for example, by chemical mechanical polishing (CMP) to remove part of the interlayer dielectric layer 42 and expose the gate material layer 34 made of polysilicon, so that the upper surface of each gate material layer 34 is flush with the upper surface of the interlayer dielectric layer 42. Subsequently, a metal gate replacement process is performed to convert the gate structures 24, 26, 28, 30 into metal gates. For example, a patterned mask (not shown) can be selectively formed to cover the interlayer dielectric layer 42, followed by a selective dry or wet etching process. For instance, an etching solution such as ammonia (NH4OH) or tetramethylammonium hydroxide (TMAH) can be used to remove the gate material layer 34 and even the gate dielectric layer 32 in the gate structures 24, 26, 28, and 30 to form grooves (not shown) in the interlayer dielectric layer 42. Subsequently, a dielectric layer 44, a high-dielectric-constant dielectric layer 46, and a conductive layer containing at least a work function metal layer 48 and a low-impedance metal layer 50 are sequentially formed in each groove. A planarization process is then performed to make the surfaces of the U-shaped high-dielectric-constant dielectric layer 46, the U-shaped work function metal layer 48, and the low-impedance metal layer 50 flush with the surface of the interlayer dielectric layer 42.

[0051] In this embodiment, the high dielectric constant dielectric layer 46 comprises a dielectric material with a dielectric constant greater than 4, such as hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), zirconium oxide (ZrO2), strontium titanate oxide (SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO4), and strontium bismuth tantalum oxide. lead zirconate titanate (SrBi₂Ta₂O₉, SBT) and lead zirconate titanate (PbZr)x Ti 1-x O3, PZT), barium strontium titanate (Ba x Sr 1- x The group consisting of TiO3, BST, or combinations thereof.

[0052] The work function metal layer 48 is preferably used to adjust the work function of the metal gate to make it suitable for N-type transistors (NMOS) or P-type transistors (PMOS). If the transistor is an N-type transistor, the work function metal layer 48 can be made of a metal material with a work function of 3.9 electron volts (eV) to 4.3 eV, such as titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl), hafnium aluminide (HfAl), or TiAlC (titanium aluminum carbide), but is not limited thereto; if the transistor is a P-type transistor, the work function metal layer 48 can be made of a metal material with a work function of 4.8 eV to 5.2 eV, such as titanium nitride (TiN), tantalum nitride (TaN), or tantalum carbide (TaC), but is not limited thereto. Another barrier layer (not shown) may be included between the work function metal layer 48 and the low impedance metal layer 50. The barrier layer may be made of materials such as titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN). The low impedance metal layer 50 may be selected from low resistance materials such as copper (Cu), aluminum (Al), tungsten (W), titanium-aluminum alloy (TiAl), cobalt-tungsten phosphide (CoWP), or combinations thereof. Since the conversion of a dummy gate into a metal gate according to the metal gate replacement fabrication process is a well-known technique in this field, it will not be described in detail here. Next, a portion of the high dielectric constant dielectric layer 46, a portion of the work function metal layer 48, and a portion of the low impedance metal layer 50 may be removed to form a groove (not shown). Then, a hard mask 52 is filled into the groove and made flush with the surface of the interlayer dielectric layer 42. The hard mask 52 may be selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide.

[0053] Then as Figure 4As shown, a photolithography and etching process is first performed to remove part of the interlayer dielectric layer 42 directly above the shallow trench isolation 22 to form a groove (not shown) that exposes or does not expose the surface of the shallow trench isolation 22. Then, one or more deposition processes are performed to form a pore 60 above the shallow trench isolation 22. More specifically, the pore 60 can be formed in this stage by first performing a flowable chemical vapor deposition (FCVD) process to conformally form a pad layer (not shown) in the groove but not filling the groove, selectively performing an etching process to remove part of the pad layer, and then performing a high-density plasma (HDP) process to form a dielectric layer, such as another interlayer dielectric layer 54, on the pad layer to fill the groove between the gate structures 24 and 28 and cover the gate structures 24, 26, 28, and 30. By combining the FCVD and HDP processes, the present invention can form the pore 60 directly above the shallow trench isolation 22 while filling the groove. In this embodiment, the interlayer dielectric layers 42 and 54 may contain the same or different materials, wherein both may contain silicon oxide such as tetraethyl orthosilicate (TEOS) or may contain an ultra-low dielectric constant dielectric layer, such as a porous dielectric material such as, but not limited to, silicon carbide (SiOC) or silicon carbide hydrogen (SiOCH).

[0054] A pattern transfer fabrication process is then performed, for example, by using a patterned mask to remove portions of the interlayer dielectric layers 42 and 54 adjacent to the gate structures 24, 26, 28, and 30 to form multiple contact holes (not shown) and expose the source region 38 and the drain region 40. Then, the desired conductive material is filled into each contact hole, such as a barrier layer material including titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc., and a low-resistance metal layer selected from low-resistance materials or combinations thereof, such as tungsten (W), copper (Cu), aluminum (Al), titanium-aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc. A planarization fabrication process is then performed, for example, by chemical mechanical polishing to remove some of the conductive material to form contact plugs 56 that contact and electrically connect the source region 38 and the drain region 40. This completes the fabrication of the semiconductor device according to the preferred embodiment of the present invention.

[0055] Please refer to again Figure 1 and Figure 4 , Figure 1 and Figure 4 This is a schematic diagram of the structure of a laterally diffused metal-oxide-semiconductor device according to an embodiment of the present invention, wherein... Figure 1This is a top view of a laterally diffused metal-oxide-semiconductor device according to an embodiment of the present invention. Figure 4 Then it is Figure 1 A cross-sectional view of a laterally diffused metal-oxide-semiconductor device is fabricated along tangent AA'. (See diagram below.) Figure 4 As shown, the laterally diffused metal-oxide-semiconductor device mainly includes a first fin structure 14 and a second fin structure 16 disposed on a substrate 12, a shallow trench isolation 22 disposed between the first fin structure 14 and the second fin structure 16, a gate structure 24 disposed on the first fin structure 14, a gate structure 28 disposed on the second fin structure 16, a source region 38 disposed on the first fin structure 14 on one side of the gate structure 24, a drain region 40 disposed on the second fin structure 16 on one side of the gate structure 28, interlayer dielectric layers 42 and 54 surrounding the gate structure 24 and the gate structure 28, a contact plug 56 disposed on the source region 38, a contact plug 58 disposed on the drain region 40, and a vent 60 disposed directly above the shallow trench isolation 22 between the gate structure 24 and the gate structure 28. Figure 1 As shown, the first fin structure 14 and the second fin structure 16 preferably extend along a first direction, such as the X direction, to contact the plug 56, while the plug 56 and the vent 60 extend along a second direction, such as the Y direction, on the substrate 12.

[0056] In this embodiment, gate structures 24, 26, 28, and 30 are metal gates. Gate structures 26, 28, and 30 are preferably dummy gate structures, and their widths are preferably smaller than the width of gate structure 24. The vent 60 is disposed within the interlayer dielectric layer 54. It should be noted that although the top surface of the vent 60 in this embodiment is slightly lower than the top surfaces of the gate structures 24 and 28 on both sides, it is not limited to this. According to other embodiments of the present invention, the top surface of the vent 60 may be flush with or slightly higher than the top surfaces of the gate structures 24 and 28. These variations are all within the scope of the present invention.

[0057] Please continue to refer to Figure 5 , Figure 5 This is a top view of a laterally diffused metal-oxide-semiconductor device according to an embodiment of the present invention. Figure 5 As shown, compared to Figure 1 The central vent 60 extends along the Y direction directly above the shallow groove separator 22 and is approximately elongated in shape with the contact plugs 58 on both sides. This invention can also... Figure 4When removing a portion of the interlayer dielectric layer 42 directly above the shallow trench isolation 22 using photolithography and etching processes, the photomask pattern used is adjusted to first form multiple openings (not shown) that appear circular from a top-viewing angle. Then, using FCVD and HDP processes, a pad layer and interlayer dielectric layer 54 are filled into the openings, simultaneously forming approximately circular vents 60 directly above the shallow trench isolation 22 between the gate structures 24 and 28. In this embodiment, the position of each vent 60 in the cross-sectional direction, including parameters such as height and width, can be approximately equal to... Figure 4 The positions of the vents 60 disclosed herein are such that, since each vent 60 is approximately located in the middle of the fin-like structure, and even when viewed from above, each vent 60 can be aligned in a straight line with the fin-like structures 14 and 16 on both sides, the number of vents 60 is preferably approximately equal to the number of fin-like structures on both sides. In other words, if seven fin-like structures are provided on each side of the vent 60 in this embodiment, then seven vents 60 are preferably conveniently located directly above the shallow trench isolation 22 between the gate structures 24 and 28.

[0058] Please continue to refer to Figures 6 to 7 , Figure 6 This is a top view of a laterally diffused metal-oxide-semiconductor device according to an embodiment of the present invention. Figure 7 Then it is Figure 6 A cross-sectional schematic diagram of a laterally diffused metal-oxide-semiconductor device is fabricated along the tangent BB'. (See diagram below.) Figure 6 and Figure 7 As shown, compared to Figure 4 The sidewalls of the gate structure 24 or spacer 36 on the left side of the shallow trench isolation 22 are flush with the sidewall of the first fin structure 14 below, and the sidewalls of the gate structure 28 or spacer 36 on the right side of the shallow trench isolation 22 are also flush with the sidewall of the second fin structure 16. In this embodiment, the sidewalls of the gate structures 24 and 28 on both sides of the shallow trench isolation 22 are preferably not flush with the edges of the fin structures on both sides. More specifically, the sidewall of the gate structure 24 on the left side of the shallow trench isolation 22 preferably extends slightly to the right and contacts the top surface of the shallow trench isolation 22, and similarly, the sidewall of the gate structure 28 on the right side of the shallow trench isolation 22 also extends slightly to the left and contacts the top surface of the shallow trench isolation 22.

[0059] Please continue to refer to Figures 8 to 9 , Figure 8 This is a top view of a laterally diffused metal-oxide-semiconductor device according to an embodiment of the present invention. Figure 9 Then it is Figure 8 A cross-sectional view of a laterally diffused metal-oxide-semiconductor device is fabricated along the tangent CC'. (See diagram below.) Figure 8 and Figure 9As shown, in this embodiment, another gate structure 62 can be set between the gate structure 24 and the gate structure 28 on the third fin structure 64. A shallow trench isolation 22 is provided between the gate structure 24 and the gate structure 62, and a shallow trench isolation 22 is provided between the gate structure 28 and the gate structure 62. A vent 60 and a vent 66 are respectively provided above the shallow trench isolation 22 on both sides of the gate structure 62.

[0060] In this embodiment, the gate structure 62 and the gate structures 24 and 28 on both sides are preferably fabricated in the same process and therefore preferably contain the same material, for example, all three contain metal gates. Furthermore, although the vents 60 and 66 on both sides of the gate structure 62 in this embodiment are slightly lower than the top surfaces of the gate structures 24 and 28, this is not a limitation. As in the aforementioned embodiments, the top surfaces of the vents 60 and 66 can be flush with or slightly higher than the top surfaces of the gate structures 24, 28, and 62. These variations are all within the scope of this invention. In addition... Figure 8 The vents 60 and 66 extend along the Y direction directly above the shallow groove separator 22 and are generally elongated in shape with the contact plugs 58 on both sides, but are not limited thereto. The present invention can also be compared with Figure 5 In this embodiment, a plurality of approximately circular vents 60 and 66 are formed directly above the shallow trench isolation 22 on both sides of the gate structure 62 from an upward viewing angle. All such variations are within the scope of this invention.

[0061] Please continue to refer to Figure 10 , Figure 10 This is a schematic diagram of the structure of a laterally diffused metal-oxide-semiconductor device according to an embodiment of the present invention. Figure 10 As shown, compared to Figures 8 to 9 By placing the gate structure 62 on the third fin structure 64, the present invention can further... Figure 2 When fabricating gate structures 24, 26, 28, and 30, a separate gate structure 62 is placed on the shallow trench isolation 22, and then compared with... Figures 3 to 4 The manufacturing process converts the gate structures 24, 26, 28, 30, and 62 into metal gates and forms vents 60 and 66 on both sides of the gate structure 62. Similar to the aforementioned embodiments, in this embodiment, although the vents 60 and 66 on both sides of the gate structure 62 are slightly lower than the top surfaces of the gate structures 24 and 28, this is not a limitation. The top surfaces of each vent 60 and 66 can be flush with or slightly higher than the top surfaces of the gate structures 24, 28, and 62; these variations are all within the scope of this invention. Furthermore, from a top viewpoint... Figure 10 The vents 60 and 66 located on both sides of the gate structure 62 can be roughly elongated or in multiple circular shapes, similar to the contact plugs 58 on both sides in the aforementioned embodiments. These variations are all within the scope of this invention.

[0062] In summary, the present invention mainly forms at least one vent directly above the shallow trench isolation between the active gate, such as the gate structure 24 in the aforementioned embodiment, and the dummy gate, such as the gate structure 28. The vent not only reduces the parasitic capacitance of the laterally diffused metal-oxide-semiconductor device, but also significantly improves the cut-off frequency (Ft) and maximum oscillation frequency (Fmax) of the device.

[0063] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A laterally diffused metal-oxide-semiconductor device, characterized in that, Include: The first fin-like structure is disposed on the base and extends in one direction; A second fin-like structure is disposed next to the first fin-like structure and extends along the direction, wherein the first fin-like structure and the second fin-like structure overlap each other along the direction; Shallow trench isolation is provided along this direction between the first fin structure and the second fin structure; A first gate structure is disposed on the first fin structure; A second gate structure is disposed on the second fin structure; and A vent is disposed between the first gate structure and the second gate structure along the direction, and the vent is disposed directly above the shallow trench isolation.

2. The laterally diffused metal-oxide-semiconductor device as claimed in claim 1, further comprising: The source region is located on the first fin structure on one side of the first gate structure; The drain region is located on the second fin structure on one side of the second gate structure; An interlayer dielectric layer surrounds the first gate structure and the second gate structure; and A first contact plug and a second contact plug, the first contact plug being disposed on the source region and the second contact plug being disposed on the drain region.

3. The laterally diffused metal-oxide-semiconductor device as claimed in claim 2, wherein the pore is disposed within the interlayer dielectric layer.

4. The laterally diffused metal-oxide-semiconductor device of claim 1, wherein the width of the second gate structure is smaller than the width of the first gate structure.

5. The laterally diffused metal-oxide-semiconductor device of claim 1, wherein the first gate structure and the second gate structure comprise a metal gate.

6. A laterally diffused metal-oxide-semiconductor device, characterized in that, Include: The first fin-like structure is disposed on the base and extends in one direction; The second fin-like structure is disposed next to the first fin-like structure and extends along the direction; A third fin-like structure is disposed between the first fin-like structure and the second fin-like structure and extends along the direction, wherein the first fin-like structure, the second fin-like structure and the third fin-like structure overlap each other along the direction; A first shallow groove is provided between the first fin structure and the third fin structure along this direction; A second shallow groove is provided between the second fin structure and the third fin structure along this direction; A first gate structure is disposed on the first fin structure; A second gate structure is disposed on the second fin structure; A third gate structure is disposed on the third fin structure; as well as A first vent is disposed between the first gate structure and the third gate structure along the direction, and the first vent is disposed directly above the first shallow trench isolation.

7. The laterally diffused metal-oxide-semiconductor device of claim 6, further comprising: The source region is located on the first fin structure on one side of the first gate structure; The drain region is located on the second fin structure on one side of the second gate structure; An interlayer dielectric layer surrounds the first gate structure and the second gate structure; and A first contact plug and a second contact plug, the first contact plug being disposed on the source region and the second contact plug being disposed on the drain region.

8. The laterally diffused metal-oxide-semiconductor device of claim 7, wherein the first pore is disposed within the interlayer dielectric layer.

9. The laterally diffused metal-oxide semiconductor device of claim 6, wherein the width of the second gate structure is smaller than the width of the first gate structure.

10. The laterally diffused metal-oxide-semiconductor device of claim 6, wherein the first gate structure and the second gate structure comprise metal gates.

11. The laterally diffused metal-oxide-semiconductor device of claim 6, further comprising a second pore disposed between the second gate structure and the third gate structure along the direction.

12. The laterally diffused metal-oxide-semiconductor device of claim 11, wherein the second pore is disposed directly above the second shallow trench isolation.

13. A laterally diffused metal-oxide-semiconductor device, characterized in that, Include: The first fin-like structure is disposed on the base and extends in one direction; A second fin-like structure is disposed next to the first fin-like structure and extends along the direction, wherein the first fin-like structure and the second fin-like structure overlap each other along the direction; Shallow trench isolation, disposed between the first fin structure and the second fin structure along this direction; A first gate structure is disposed on the first fin structure; A second gate structure is disposed on the second fin structure; A third gate structure is disposed on the shallow trench isolation; as well as A first vent is disposed between the first gate structure and the third gate structure along the direction, and the vent is disposed directly above the shallow trench isolation.

14. The laterally diffused metal-oxide-semiconductor device of claim 13, further comprising: The source region is located on the first fin structure on one side of the first gate structure; The drain region is located on the second fin structure on one side of the second gate structure; An interlayer dielectric layer surrounds the first gate structure and the second gate structure; and A first contact plug and a second contact plug, the first contact plug being disposed on the source region and the second contact plug being disposed on the drain region.

15. The laterally diffused metal-oxide-semiconductor device of claim 14, wherein the first pore is disposed within the interlayer dielectric layer.

16. The laterally diffused metal-oxide-semiconductor device of claim 13, wherein the width of the second gate structure is smaller than the width of the first gate structure.

17. The laterally diffused metal-oxide-semiconductor device of claim 13, wherein the first gate structure and the second gate structure comprise a metal gate.

18. The laterally diffused metal-oxide-semiconductor device of claim 17, further comprising a second pore disposed between the second gate structure and the third gate structure along the direction.

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