A method for optimizing phase-locked loop parameters of grid-connected converters

Abstract

The present invention discloses a method for optimizing the parameters of a phase-locked loop (PLL) of a grid-connected converter, and belongs to the technical field of grid-connected power generation of new energy. The method comprises the steps of S1: establishing a small-signal model of a synchronous phase-locked loop (PLL); S2: designing the anti-interference capability of the PLL, obtaining the PLL disturbance transfer function based on the small-signal model in S1, obtaining a linearization block diagram of the PLL in combination with the PLL structure, and obtaining the open-loop transfer function and anti-interference capability of the synchronous PLL; S3: designing the stability margin of the PLL based on the anti-interference capability of the PLL in S2; and S4: obtaining a selection range of the PLL parameters based on S2 and S3. The present invention effectively suppresses the frequency coupling oscillation phenomenon of the grid-connected converter caused by the asymmetric control of the PLL.

Description

Technical Field

[0001] The present invention relates to the technical field of new energy grid-connected power generation, and in particular to a method for optimizing parameters of a phase-locked loop of a grid-connected converter. Background Art

[0002] Grid-connected converters are crucial interfaces between renewable energy generation devices and the power grid. With the rapid development of renewable energy generation technologies and the widespread application of power electronics, large-scale grid-connected converters are being integrated into traditional power systems, leading to a clear trend toward power electronics. As the bridge between renewable energy generation systems and the larger power grid, the operating status and control performance of grid-connected converters are crucial to the stable operation of the grid and the quality of grid-connected power.

[0003] Currently, phase-locked loops (PLLs) are widely used as synchronization units between converters and power grids. Grid-connected converter systems require PLLs to detect grid voltage frequency and phase information to achieve source-grid synchronization between grid-connected devices and the grid. Synchronous coordinate system PLLs (Synchronous Frame Phase-Locked Loops) are widely used in grid-connected converters due to their simple structure. In a synchronous coordinate system PLL, phase detection is achieved in the dq coordinate system via Park transforms, and phase tracking only controls the q-axis component. This results in asymmetric cross-coupling between the d-axis and q-axis of the impedance model in the dq coordinate system. This introduces frequency-coupled oscillations in the time domain, distorting the grid-connected current waveform and reducing system stability. Therefore, suppressing frequency coupling is crucial to the stability of renewable energy access to the grid. Summary of the Invention

[0004] In view of the problems existing in the prior art, the present invention provides a phase-locked loop parameter optimization method for suppressing the frequency coupling oscillation of the grid-connected converter, the purpose of which is to effectively suppress the frequency coupling oscillation phenomenon of the grid-connected converter caused by the asymmetric control of the phase-locked loop.

[0005] The technical solution adopted in the present invention is as follows:

[0006] A method for optimizing phase-locked loop parameters of a grid-connected converter comprises the following steps:

[0007] S1: Establish a small signal model of a synchronous phase-locked loop;

[0008] S2: Design the anti-interference capability of the phase-locked loop. Based on the small signal model in S1, the phase-locked loop disturbance transfer function is obtained. Combined with the phase-locked loop structure, the phase-locked loop linearization block diagram is obtained. The open-loop transfer function and anti-interference capability of the synchronous phase-locked loop are also obtained.

[0009] S3: Design the phase-locked loop stability margin based on the phase-locked loop anti-interference capability in S2;

[0010] S4: derive the phase-locked loop parameter selection range based on S2 and S3.

[0011] Preferably, the mathematical expression of the small signal model of the synchronous phase-locked loop in S1 is established in the dq coordinate system, as shown in the following equations (1) to (5):

[0012]

[0013]

[0014]

[0015]

[0016]

[0017]

[0018] Where Δθ represents the phase difference between the dq coordinate system of the actual system and the dq coordinate system of the phase-locked loop control system, T Δθ Represents the transformation matrix, the superscript s 、 c They represent the physical quantities in the actual system and control system coordinate systems respectively. Subscript 0 represents the steady-state value of the variable, u represents the voltage variable, i represents the current variable, and αu pccd Indicates the small signal of the d-axis voltage at the PCC point, αu pccq Indicates the small signal value of the q-axis voltage at the PCC point, G pll (s) represents the PI link of the phase-locked loop control, s represents the Laplace operator, k pp Indicates the phase-locked loop proportional coefficient, k pi Indicates the phase-locked loop integral coefficient.

[0019] Preferably, the design process of the phase-locked loop anti-interference capability in S2 is:

[0020] According to the small signal model in S1, the phase-locked loop disturbance transfer function T is obtained. PLL (s), phase-locked loop disturbance transfer function T PLL The expression of (s) is as follows:

[0021]

[0022] Where: n 2 =v m k pi , 2ξω n =v m k pp , ξ is the damping ratio, ω n is the natural angular frequency, v m is the voltage amplitude at the PCC point;

[0023] Combined with T PLL (s) and the phase-locked loop structure, the phase-locked loop linearization block diagram is obtained, where K P and K I The expressions of are shown in formulas (8) and (9):

[0024] K p =2ξω n =v m k pi (8)

[0025]

[0026] Combining expressions (8) and (9), let K P and K I The relationship is:

[0027]

[0028] where K P and K I They represent the equivalent proportional coefficient and equivalent integral coefficient after the phase-locked loop is linearized, and g is an intermediate variable used to describe K P and K I According to the linearization block diagram of the phase-locked loop, the open-loop transfer function of the synchronous phase-locked loop is obtained:

[0029]

[0030] The open-loop transfer function is used to design the interference immunity, which is represented by R:

[0031]

[0032] Among them, ω d Indicates the angular frequency corresponding to the disturbance; determine the value range of R according to the actual situation and obtain g and K P relationship curve.

[0033] Furthermore, the anti-interference capability R is selected in the range of [-40dB, -20dB].

[0034] Preferably, the process of designing the phase-locked loop stability margin in S3 is:

[0035] According to the open-loop transfer function G obtained in the design of the anti-interference capability of the phase-locked loop in S2 o (s), and the stability margin of the phase-locked loop is obtained pm The expression is:

[0036]

[0037] Among them, ω c Denotes the open-loop transfer function Go The cutoff frequency of (s) is determined by the actual situation, and the stability margin φ is limited. pm The range of the intermediate variable g is obtained.

[0038] Furthermore, the specific process of S4 is as follows:

[0039] The intermediate variables g and K obtained from the phase-locked loop block diagram in S2 P The relationship curve, as well as the range of the intermediate variable g determined by the phase-locked loop stability margin in S3, obtain the intermediate variables g and K P The limited area, as needed in the intermediate variables g and K P Select the corresponding intermediate variables g and K within the limited area P The corresponding phase-locked loop parameters are calculated according to equations (8), (9) and (10).

[0040] In summary, the present invention has the following beneficial effects:

[0041] 1. The present invention can effectively suppress the frequency coupling oscillation phenomenon of the grid-connected converter caused by the asymmetric control of the phase-locked loop;

[0042] 2. In terms of parameter optimization, the present invention suppresses and optimizes parameters based on a phase-locked loop to different disturbance quantities;

[0043] 3. The present invention optimizes parameters based on a phase-locked loop to suppress disturbances entering the system;

[0044] 4. The present invention directly performs parameter optimization by setting the anti-interference capability and stability margin of the phase-locked loop system;

[0045] 5. The present invention only imposes conditional restrictions on the transfer function of the phase-locked loop itself, and does not require changes to the phase-locked loop structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The present invention will now be described by way of example with reference to the accompanying drawings, in which:

[0047] Figure 1 A schematic block diagram of the structure and control of the grid-connected converter of the present invention;

[0048] Figure 2 This is a schematic block diagram of a synchronous coordinate system phase-locked loop of the present invention;

[0049] Figure 3 This is a schematic block diagram of the synchronous coordinate system phase-locked loop linearization of the present invention;

[0050] Figure 4 2 is a grid-connected current waveform diagram when the phase-locked loop parameters in the embodiment do not adopt the present invention;

[0051] Figure 52. Fast Fourier analysis result of the grid-connected current waveform when the phase-locked loop parameters in the embodiment do not adopt the present invention;

[0052] Figure 6 This is a diagram showing the parameter selection ranges obtained by using the present invention in the examples;

[0053] Figure 7 2. The grid-connected current waveform diagram when the phase-locked loop parameters in the embodiment adopt the present invention;

[0054] Figure 8 FIG. 1 is a diagram showing the fast Fourier analysis result of the grid-connected current waveform when the phase-locked loop parameters in the embodiment are adopted according to the present invention. DETAILED DESCRIPTION

[0055] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of this application.

[0056] In the description of the embodiments of the present application, it should be noted that the terms "upper", "lower", "left", "right", "vertical", "horizontal", "inside", "outside", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the accompanying drawings, or are the orientation or positional relationship in which the product of the invention is usually placed when in use. They are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, they cannot be understood as limiting the present application. In addition, the terms "first", "second", "third", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0057] The following combination Figures 1-8 The present invention is described in detail.

[0058] A method for optimizing phase-locked loop parameters of a grid-connected converter comprises the following steps:

[0059] S1: Establish a small signal model of a synchronous phase-locked loop;

[0060] S2: Design the anti-interference capability of the phase-locked loop. Based on the small signal model in S1, the phase-locked loop disturbance transfer function is obtained. Combined with the phase-locked loop structure, the phase-locked loop linearization block diagram is obtained. The open-loop transfer function and anti-interference capability of the synchronous phase-locked loop are also obtained.

[0061] S3: Design the phase-locked loop stability margin based on the phase-locked loop anti-interference capability in S2;

[0062] S4: derive the phase-locked loop parameter selection range based on S2 and S3.

[0063] The mathematical expression of the small signal model of the synchronous phase-locked loop in S1 is established in the dq coordinate system, as shown in the following equations (1) to (5):

[0064]

[0065]

[0066]

[0067]

[0068]

[0069]

[0070] Where Δθ represents the phase difference between the dq coordinate system of the actual system and the dq coordinate system of the phase-locked loop control system, T Δθ Represents the transformation matrix, the superscript s 、 c They represent the physical quantities in the actual system and control system coordinate systems respectively. Subscript 0 represents the steady-state value of the variable, u represents the voltage variable, i represents the current variable, and Δu pccd Indicates the small signal value of the d-axis voltage at the PCC point, Δu pccq Indicates the small signal value of the q-axis voltage at the PCC point, G pll (s) represents the PI link of the phase-locked loop control, s represents the Laplace operator, k pp Indicates the phase-locked loop proportional coefficient, k pi Indicates the phase-locked loop integral coefficient.

[0071] The design process of the phase-locked loop anti-interference capability in S2 is as follows:

[0072] According to the small signal model in S1, the phase-locked loop disturbance transfer function T is obtained. PLL (s), phase-locked loop disturbance transfer function T PLL The expression of (s) is as follows:

[0073]

[0074] Where:n 2 =v m k pi , 2ξω n =v m k pp , ξ is the damping ratio, ω n is the natural angular frequency, v m is the voltage amplitude at the PCC point;

[0075] Combined with T PLL (s) and the phase-locked loop structure, the phase-locked loop linearization block diagram is obtained, where K P and K I The expressions of are shown in formulas (8) and (9):

[0076] K p =2ξω n =v m k pi (8)

[0077]

[0078] Combining expressions (8) and (9), let K P and K I The relationship is:

[0079]

[0080] where K P and K I They represent the equivalent proportional coefficient and equivalent integral coefficient after the phase-locked loop is linearized, and g is an intermediate variable used to describe K P and K I According to the linearization block diagram of the phase-locked loop, the open-loop transfer function of the synchronous phase-locked loop is obtained:

[0081]

[0082] The open-loop transfer function is used to design the interference immunity, which is represented by R:

[0083]

[0084] Among them, ω d Indicates the angular frequency corresponding to the disturbance; determine the value range of R according to the actual situation and obtain g and K P relationship curve.

[0085] The range of anti-interference capability R is [-40dB, -20dB].

[0086] The process of designing the phase-locked loop stability margin in S3 is:

[0087] According to the open-loop transfer function G obtained in the design of the anti-interference capability of the phase-locked loop in S2 o (s), and the stability margin of the phase-locked loop is obtained pm The expression is:

[0088]

[0089] Among them, ω c Denotes the open-loop transfer function G o The cutoff frequency of (s) is determined by the actual situation, and the stability margin φ is limited. pm The range of the intermediate variable g is obtained.

[0090] The specific process of S4 is:

[0091] The intermediate variables g and K obtained from the phase-locked loop block diagram in S2 P The relationship curve, as well as the range of the intermediate variable g determined by the phase-locked loop stability margin in S3, obtain the intermediate variables g and K P The limited area, as needed in the intermediate variables g and K P Select the corresponding intermediate variables g and K within the limited area P The corresponding phase-locked loop parameters are calculated according to equations (8), (9) and (10).

[0092] Figure 1 The structure and control schematic diagram of the grid-connected converter is shown in the figure. The grid-connected converter includes: a DC voltage source V dc ; The converter outputs three-phase current i oa 、i ob 、i oc ; PCC point voltage u pcc ; Grid three-phase voltage U ga 、U gb 、U gc ;Filter inductor L f ; Grid equivalent impedance L g ; The value of the converter output current in the dq coordinate system i od and i oq ; Phase-locked loop output angle θ pll ; Reference value of grid-connected current i dref and i qref ; G i (s) = k ip +k ii / s is the current proportional integral control link, k ip is the current loop proportional coefficient, k ii is the current loop integral coefficient; the output modulation signal m of the regulator in the dq coordinate system d 、m q, abc / dq is Parker transform; dq / abc is inverse Parker transform; SPWM is sinusoidal pulse width modulation.

[0093] right Figure 1 The system was simulated by MATLAB / Simulink. dc =700V, L f =3mH, U g =220V, grid frequency f0=50Hz, k ip =0.011, k ii =11.429, L g =12.8mH;

[0094] k pp =3,k pi =100 and the grid-connected current waveform and the grid-connected current fast Fourier analysis results are as follows: Figure 4 and Figure 5 As shown in the figure, the grid-connected current has obvious oscillation phenomenon, and the system is in an unstable state. Figure 5 The figure shows that the grid-connected current has frequency coupling phenomenon. Figure 5 It is shown in FIG. 1 that the main coupling frequency harmonics generated are 110 Hz and 10 Hz.

[0095] Take ω d =220π, substitute into the expression of R and draw two curves g and K based on the conditions of [-40dB, -20dB] P In this embodiment, the stability margin is set to 35°~60°, and the range of g is [0.668,2.489]. Based on the two obtained curves and the range of g, the parameter selection range is obtained as follows: Figure 6 .

[0096] In this embodiment, K is selected within the selection range. P =30, g=2, and K is obtained from formula (9): I =900, and then calculate k according to formula (7) and formula (8) ip =0.096, k ii =2.894, and the simulation results are as follows: Figure 7 and Figure 8 , we can see that the output current waveform is relatively smooth, without obvious oscillation, and the power quality and stability have been greatly improved. Figure 4 The frequency coupling phenomenon in the circuit is suppressed.

[0097] The above-described embodiments merely represent specific implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of protection of the present application. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the technical concept of the present application, and all such variations and improvements fall within the scope of protection of the present application.

Claims

1. A method for optimizing parameters of a grid-connected converter phase-locked loop, characterized in that: The steps include: S1: Establish a small signal model of a synchronous phase-locked loop; S2: Design the anti-interference capability of the phase-locked loop. Based on the small signal model in S1, the phase-locked loop disturbance transfer function is obtained. Combined with the phase-locked loop structure, the phase-locked loop linearization block diagram is obtained. The open-loop transfer function and anti-interference capability of the synchronous phase-locked loop are also obtained. S3: Design the phase-locked loop stability margin based on the phase-locked loop anti-interference capability in S2; S4: derive the phase-locked loop parameter selection range based on S2 and S3; The mathematical expression of the small signal model of the synchronous phase-locked loop in S1 is dq The coordinate system is established as follows: （6） in, G pll ( s ) represents the PI link of the phase-locked loop control, s represents the Laplace operator, k pp represents the phase-locked loop proportional coefficient, k pi Represents the phase-locked loop integral coefficient; The design process of the phase-locked loop anti-interference capability in S2 is as follows: According to the small signal model in S1, the phase-locked loop disturbance transfer function is obtained T PLL ( s ), the phase-locked loop perturbation transfer function T PLL ( s ) is expressed as follows: （7） in: w n 2 = v m k pi , 2 xw n = v m k pp , x is the damping ratio, w n is the natural angular frequency, v m is the voltage amplitude at the PCC point; Combine T PLL ( s ) and the phase-locked loop structure, the phase-locked loop linearization block diagram is obtained, where K P and K I The expressions of are shown in formulas (8) and (9): （8） （9） Combining expressions (8) and (9), let K P and K I The relationship is: （10） in K P and K I Respectively represent the equivalent proportional coefficient and equivalent integral coefficient after the phase-locked loop is linearized, is an intermediate variable, Used to describe K P and K I According to the linearization block diagram of the phase-locked loop, the open-loop transfer function of the synchronous phase-locked loop is obtained: （11） The anti-interference capability is designed using the open-loop transfer function. express: （12） in, Indicates the angular frequency corresponding to the disturbance; determined according to actual conditions The value range of K P relationship curve.

2. A method for optimizing parameters of a grid-connected converter phase-locked loop according to claim 1, characterized in that: The mathematical expression of the small signal model of the synchronous phase-locked loop in S1 is dq The coordinate system is established as shown in the following equations (1) to (5): （1） （2） （3） （4） （5） in, Represents the actual system dq Coordinate system and phase-locked loop control system dq The phase difference of the coordinate system, Represents the transformation matrix, the superscript 、 Represent the physical quantities in the actual system and control system coordinate systems respectively, and the subscript 0 represents the steady-state value of the variable. represents the voltage variable, represents the current variable, D u pccd Indicates PCC point d Shaft voltage small signal, D u pccq Indicates PCC point q Shaft voltage small signal quantity, Indicates PCC point d Steady-state value of shaft voltage.

3. The method for optimizing parameters of a grid-connected converter phase-locked loop according to claim 1, wherein: The anti-interference capability The selection range is [-40dB, -20dB].

4. The method for optimizing parameters of a grid-connected converter phase-locked loop according to claim 1, wherein: The process of designing the phase-locked loop stability margin in S3 is as follows: According to the open-loop transfer function obtained from the anti-interference design of the phase-locked loop in S2 G o ( s ), and obtain the stability margin of the phase-locked loop The expression is: （13） in, represents the open-loop transfer function G o ( s ) cut-off frequency, and the stability margin is limited according to the actual situation range, thereby obtaining the intermediate variable range.

5. The method for optimizing parameters of a grid-connected converter phase-locked loop according to claim 1, wherein: The specific process of S4 is: The intermediate variables obtained according to the phase-locked loop block diagram in S2 and K P Relationship curve, and intermediate variables determined by the phase-locked loop stability margin in S3 Get the intermediate variable in the range and K P The limited area, as needed in the intermediate variables and K P Select the corresponding intermediate variable within the limited area and K P The corresponding phase-locked loop parameters are calculated according to equations (8), (9) and (10).

Images