Switched capacitor power stage and switched capacitor transformer

Abstract

A switched-capacitor power stage and a switched-capacitor transformer, the switched-capacitor power stage comprising a first sub-power stage. The first sub-power stage comprises a first inductor, a first high switch, a first low switch, and a first set of switched-capacitor networks. The first inductor is coupled to an input terminal. The first high switch is coupled between the first inductor and an output terminal. The first low switch is coupled between the first inductor and a first transition node. The first set of switched-capacitor networks is coupled between the first transition node and the output terminal. Accordingly, switching loss, conduction loss, and ripple are all small, voltage conversion ratio is large, and efficiency is better.

Description

TECHNICAL FIELD

[0001] Embodiments described in this disclosure relate to transformer technology, and in particular, to a switched-capacitor power stage and a switched-capacitor transformer. BACKGROUND

[0002] With the development of technology, switched-capacitor converters have been applied to various circuits. In some related technologies, the voltage conversion ratio (VCR) of the switched-capacitor converter is preferable, but the switching loss, ripple, and hard charging loss thereof are large. In some related technologies, the switching loss, ripple, and hard charging loss of the switched-capacitor converter are small, but the voltage conversion ratio thereof will be limited (e.g., too small). SUMMARY

[0003] Some embodiments of the disclosure relate to a switched-capacitor power stage. The switched-capacitor power stage includes a first sub-power stage. The first sub-power stage includes a first inductor, a first high switch, a first low switch, and a first set of switched-capacitor networks. The first inductor is coupled to an input terminal. The first high switch is coupled between the first inductor and an output terminal. The first low switch is coupled between the first inductor and a first transition node. The first set of switched-capacitor networks is coupled between the first transition node and the output terminal.

[0004] In some embodiments, a transition voltage of the first transition node is greater than an input voltage of the input terminal.

[0005] In some embodiments, the switched-capacitor power stage further includes a second sub-power stage. The second sub-power stage includes a second inductor, a second high switch, a second low switch, and a second set of switched-capacitor networks. The second inductor is coupled to the input terminal. The second high switch is coupled between the second inductor and the output terminal. The second low switch is coupled between the second inductor and a second transition node. The second set of switched-capacitor networks is coupled between the second transition node and the output terminal.

[0006] In some embodiments, the switched-capacitor power stage further includes a third sub-power stage. The third sub-power stage includes a third inductor, a third high switch, a third low switch, and a third set of switched-capacitor networks. The third inductor is coupled to the input terminal. The third high switch is coupled between the third inductor and the output terminal. The third low switch is coupled between the third inductor and a third transition node. The third set of switched-capacitor networks is coupled between the third transition node and the output terminal.

[0007] In some embodiments, the first set of switched-capacitor networks includes a first switched-capacitor network and a second switched-capacitor network. Each of the first switched-capacitor network and the second switched-capacitor network includes a first switch, a second switch, a third switch, a fourth switch, and a capacitor. The first switch is coupled between a first transition node and a first internal node. The second switch is coupled between the first internal node and an output terminal. The third switch is configured to receive a voltage and is coupled to a second internal node. The fourth switch is coupled between the second internal node and the output terminal. The capacitor is coupled between the first internal node and the second internal node.

[0008] In some embodiments, a duty cycle sequentially includes a first time interval, a second time interval, a third time interval, and a fourth time interval. In the first time interval and the third time interval, the first high switch is turned on and the first low switch is turned off. In the second time interval and the fourth time interval, the first high switch is turned off and the first low switch is turned on.

[0009] In some embodiments, in the first time interval and the second time interval, the first switch in the first switched-capacitor network, the fourth switch in the first switched-capacitor network, the second switch in the second switched-capacitor network, and the third switch in the second switched-capacitor network are turned on, and the second switch in the first switched-capacitor network, the third switch in the first switched-capacitor network, the first switch in the second switched-capacitor network, and the fourth switch in the second switched-capacitor network are turned off. In the third time interval and the fourth time interval, the first switch in the first switched-capacitor network, the fourth switch in the first switched-capacitor network, the second switch in the second switched-capacitor network, and the third switch in the second switched-capacitor network are turned off, and the second switch in the first switched-capacitor network, the third switch in the first switched-capacitor network, the first switch in the second switched-capacitor network, and the fourth switch in the second switched-capacitor network are turned on.

[0010] Some embodiments of the disclosure relate to a switched-capacitor transformer. The switched-capacitor transformer includes a plurality of sub-power stages and a controller. Each of the sub-power stages includes an inductor, a high switch, a low switch, a set of switched-capacitor networks, and a driver. The inductor is coupled to an input terminal. The high switch is coupled between the inductor and an output terminal. The low switch is coupled between the inductor and a transition node. The set of switched-capacitor networks is coupled between the transition node and the output terminal. The driver is configured to control the set of switched-capacitor networks. The controller is configured to generate a plurality of control signals and a plurality of enable signals based on an output voltage of the output terminal, a first reference voltage, and a second reference voltage. The driver is further configured to generate a plurality of gate voltages to control a plurality of switches in the set of switched-capacitor networks based on the control signals and the enable signals.

[0011] In some embodiments, the driver is also used to output control signals to control the high switches and low switches in the sub-power stages.

[0012] In some embodiments, the controller includes a pulse control loop circuit and a frequency control loop circuit. The pulse control loop circuit generates control signals based on a transition voltage at a transition node and a first reference voltage. The frequency control loop circuit generates enable signals based on an output voltage and a second reference voltage.

[0013] In some embodiments, the pulse control loop circuit includes a sample-and-hold circuit, a mismatch correction circuit, and a sequential logic circuit. The sample-and-hold circuit generates a plurality of first signals based on a transition voltage. The mismatch correction circuit generates a plurality of second signals based on the first signals and a first reference voltage. The sequential logic circuit generates the control signals based on the second signals.

[0014] In some embodiments, the frequency control loop circuit includes an operational amplifier, a voltage-controlled oscillator (VCO), a counter, and a finite state machine (FSM) circuit. The operational amplifier generates a comparison signal based on the output voltage and a second reference voltage. The VCO generates a frequency clock signal based on the comparison signal. The FSM circuit generates enable signals based on the counting signals.

[0015] In some embodiments, the frequency control loop circuit further includes a phase splitter. The phase splitter is used to generate multiple phase signals according to the frequency clock signal and output these phase signals to the pulse control loop circuit.

[0016] In some embodiments, the frequency control loop circuit further includes a buffer. The buffer is coupled between the operational amplifier and the voltage-controlled oscillator.

[0017] In some embodiments, each of the switching capacitor network includes a first conversion unit circuit, a second conversion unit circuit, a third conversion unit circuit, and a fourth conversion unit circuit. Each of the first, second, third, and fourth conversion unit circuits includes a first switch, a second switch, a third switch, a fourth switch, and a capacitor. The first switch is coupled between a transition node and a first internal node. The second switch is coupled between the first internal node and an output terminal. The third switch is coupled to a second internal node. The fourth switch is coupled between the second internal node and the output terminal. The capacitor is coupled between the first and second internal nodes.

[0018] In some embodiments, the capacitance value of a capacitor in the second conversion unit circuit is twice the capacitance value of a capacitor in the first conversion unit circuit, the capacitance value of a capacitor in the third conversion unit circuit is twice the capacitance value of a capacitor in the second conversion unit circuit, and the capacitance value of a capacitor in the fourth conversion unit circuit is twice the capacitance value of a capacitor in the third conversion unit circuit. Attached Figure Description

[0019] To make the above and other objects, features, advantages and embodiments disclosed herein more apparent and understandable, the accompanying drawings are described below:

[0020] Figure 1 These are schematic diagrams of all capacitor-replacement power stages illustrated in accordance with some embodiments of this disclosure;

[0021] Figure 2A It is illustrated in accordance with some embodiments of this disclosure. Figure 1 A schematic diagram of the switching capacitor power stage in a first phase;

[0022] Figure 2B It is illustrated in accordance with some embodiments of this disclosure. Figure 2A A schematic diagram of the waveform of the signal.

[0023] Figure 3A It is illustrated in accordance with some embodiments of this disclosure. Figure 1 A schematic diagram of the switching capacitor power stage in a second phase;

[0024] Figure 3B It is illustrated in accordance with some embodiments of this disclosure. Figure 3A A schematic diagram of the waveform of the signal;

[0025] Figure 4 These are schematic diagrams of all capacitor-replacement power stages illustrated in accordance with some embodiments of this disclosure;

[0026] Figure 5 It is illustrated in accordance with some embodiments of this disclosure. Figure 4 A schematic diagram of the operation of multiple switching capacitor networks in four time intervals;

[0027] Figure 6 It is illustrated in accordance with some embodiments of this disclosure. Figure 4 The split architecture of these switching capacitor networks;

[0028] Figure 7 These are schematic diagrams of all capacitor-replacing transformers illustrated in accordance with some embodiments of this disclosure;

[0029] Figure 8 It is illustrated in accordance with some embodiments of this disclosure. Figure 7 A schematic diagram of a pulse control loop circuit;

[0030] Figure 9 These are schematic waveform diagrams of signals in multiple sub-power stages illustrated according to some embodiments of this disclosure; and

[0031] Figure 10 This is a schematic diagram illustrating a buffer coupled between an operational amplifier and a voltage-controlled oscillator, according to some embodiments of this disclosure.

[0032] [Symbol Explanation]

[0033] 100, 400, 710: Switch capacitor power stage

[0034] 600: Split Architecture

[0035] 700: Switching capacitor transformer

[0036] 720: Controller

[0037] 721: Pulse control loop circuit

[0038] 7211: Sample and Hold Circuit

[0039] 7212: Mismatch Correction Circuit

[0040] 7213: Sequential Logic Circuits

[0041] 722: Frequency control loop circuit

[0042] 7221, 7221A: Operational amplifier

[0043] 7222, 7222A: Voltage-controlled oscillator

[0044] 7223: Phase splitter

[0045] 7224: Counter

[0046] 7225: Finite State Machine Circuit

[0047] P1, P2, P3: Sub-power stages

[0048] IN: Input terminal

[0049] V IN Input voltage

[0050] OUT: Output terminal

[0051] V OUT Output voltage

[0052] L BOND :inductance

[0053] S H1 High switch

[0054] S L1 Low switch

[0055] SCN1, SCN2: Switching capacitor networks

[0056] TN1: Transition Node

[0057] VDD SC Transition voltage

[0058] V OUT_SC V SS :Voltage

[0059] V OUT_TARGET Target voltage

[0060] I OUT_BOND Current

[0061] phase

[0062] Subphase

[0063] TD1, TD2, TD3, TD4: Time intervals

[0064] CLK SH ,CLK SL ,CLK SC Switching signals

[0065] NN1, NN2: Internal nodes

[0066] S 1,1 ,S 1,2 ,S 1,3 ,S 1,4 ,S 2,1 ,S 2,2 ,S 2,3 ,S 2,4 ,S 1,1 [0],S 1,2 [0],S 1,3 [0],S 1,4 [0],S 1,1 [3:0],S 1,2 [3:0],S 1,3 [3:0],S 1,4 [3:0]: Switch

[0067] C1,C2,C1[0],C1[1],C1[2],C1[3]: Capacitor d

[0068] CELL0, CELL1, CELL2, CELL3: Conversion unit circuit

[0069] EN[0],EN[1],EN[2],EN[3],EN[3:0]: enable signal

[0070] C OUT Output capacitor

[0071] FS1: First Signal

[0072] FS2: Second signal

[0073] V REF1 V REF2 Reference voltage

[0074] F CLK Frequency clock signal

[0075] V PHASE1 V PHASE2 V PHASE3 Phase signal

[0076] V C Comparison signal

[0077] CNT[3:0]: Counting signal

[0078] RST: Reset signal

[0079] CS H1 CS L1 CS H2 CS L2 CS H3 CS L3 Control signals

[0080] DR1: Drive

[0081] CS 1,K [3:0],CS 2,K [3:0]: Gate signal

[0082] BUF: Buffer Detailed Implementation

[0083] The term "coupled" as used in this article can also refer to "electrical coupling," and the term "connection" can also refer to "electrical connection." "Coupled" and "connection" can also refer to two or more components cooperating or interacting with each other.

[0084] refer to Figure 1 . Figure 1 This is a schematic diagram of a switching capacitor power stage 100 illustrated in accordance with some embodiments of this disclosure.

[0085] by Figure 1For example, the switching capacitor power stage 100 contains multiple sub-power stages P1-P3. These sub-power stages P1-P3 have a similar architecture. For simplicity and ease of understanding, the following paragraphs will use sub-power stage P1 as an example.

[0086] Sub-power stage P1 includes inductor L BOND High switch S H1 Low switch S L1 And a set of switching capacitor networks SCN1-SCN2. Inductor L BOND Coupled to the input terminal IN. Input voltage V IN It is received at the IN input terminal. High switch S H1 Coupled to inductor L BOND Between the output terminal OUT and the low-side switch S. L1 Coupled to inductor L BOND Between transition node TN1 and the output terminal OUT. This switching capacitor network SCN1-SCN2 is coupled between transition node TN1 and the output terminal OUT. Inductor L BOND This can be achieved using bonding wire.

[0087] By controlling the high switch S H1 and low switching S L1 It can generate current I OUT_BOND Current I OUT_BOND Current flows through inductor L BOND And the transition voltage VDD SC This is generated at transition node TN1. The switching capacitor network SCN1-SCN2 is based on the transition voltage VDD. SC Generated voltage V OUT_SC Next, based on the voltage V OUT_SC and corresponding to current I OUT_BOND The voltage at the output terminal OUT generates the output voltage V. OUT .by Figure 1 Regarding the waveform example in the text, compared to the voltage V OUT_SC Output voltage V OUT Closer to the target voltage V OUT_TARGET .

[0088] The number of neutron power levels in the switching capacitor power stage 100 is merely an example and is not limited thereto in this disclosure.

[0089] The switching capacitor power stage 100 can operate in two phases.

[0090] Figure 2A It is illustrated in accordance with some embodiments of this disclosure. Figure 1 A schematic diagram of the switching capacitor power stage 100 in the first phase. Figure 2B It is illustrated in accordance with some embodiments of this disclosure. Figure 2AA schematic diagram of the waveform of the signal. Figure 3A It is illustrated in accordance with some embodiments of this disclosure. Figure 1 A schematic diagram of the switching capacitor power stage 100 in the second phase. Figure 3B It is illustrated in accordance with some embodiments of this disclosure. Figure 3A A schematic diagram of the waveform of the signal.

[0091] by Figure 2A as well as Figure 2B For example, in the first phase (e.g., phase) ), high switch S H1 Switched signal CLK SH On and low switch S L1 Switched signal CLK SL Cut off. In other words, the switching signal CLK. SH The first phase has an enable level, and the switching signal CLK SL The first phase has a disabled level. In this case, the input voltage V IN Can be passed through inductor L BOND and high switch S H1 Charge the output terminal OUT (e.g., current I). OUT_BOND To increase the output voltage V OUT Inductor L BOND It can also store data from the input voltage V. IN The energy. Additionally, the switches in this switching capacitor network SCN1-SCN2 can be controlled so that the fly capacitors in this switching capacitor network SCN1-SCN2 can charge the output terminal OUT to increase the output voltage V. OUT This flying capacitor is controlled by the switching signal CLK. SC control.

[0092] by Figure 2A as well as Figure 2B For example, due to inductance L BOND Additional current can be provided to the output terminal OUT in the first phase, and the output voltage V OUT It can descend relatively slowly. Based on this, ripples can be reduced.

[0093] by Figure 3A as well as Figure 3B For example, in the second phase (e.g., phase) ), high switch S H1 Switched signal CLK SH Cut-off and low switch S L1 Switched signal CLK SL On. In other words, the switching signal CLK is activated. SH The second phase has a disabled level, and the switching signal CLKSL The second phase has an enabling level. In this case, the inductor L BOND The energy stored in the [structure] can be used to charge the transition node TN1 to increase the transition voltage VDD. SC And the transition voltage VDD SC It can charge the output terminal OUT to support the output voltage V. OUT By controlling the switching signal CLK SH and switching signal CLK SL The duty cycle can generate an appropriate transition voltage VDD. SC .

[0094] by Figure 3A as well as Figure 3B For example, due to inductance L BOND It can operate as a voltage source to provide the transition voltage VDD at the transition node TN1. SC The input voltage V is higher than that at the input terminal IN. IN The voltage conversion ratio (VCR) of one of the switching unit circuits in the switching capacitor power stage 100 can be relatively large.

[0095] refer to Figure 4 . Figure 4 This is a schematic diagram illustrating a switching capacitor power stage 400 according to some embodiments of this disclosure. The switching capacitor power stage 400 is similar to... Figure 1 The switching capacitor power stage in the middle is 100. Figure 4 For example, taking the switching capacitor network SCN1 as an example, the switching capacitor network SCN1 includes a switch S 1,1 Switch S 1,2 Switch S 1,3 Switch S 1,4 And the flying capacitor C1. Switch S 1,1 Coupled between transition node TN1 and internal node NN1. Switch S 1,2 Coupled between internal node NN1 and output terminal OUT. Switch S 1,3 Used to receive voltage V SS It is also coupled to the internal node NN2. Switch S 1,4 A flying capacitor C1 is coupled between internal node NN2 and output terminal OUT. The flying capacitor C1 is coupled between internal node NN1 and internal node NN2. Figure 4 In the embodiment, switch S 1,1 Switch S 1,2 and switch S 1,4 It is implemented using a P-type transistor, while the switch S 1,3 It is implemented using N-type transistors, but this disclosure is not limited to this.

[0096] The switching capacitor network SCN2 has a similar architecture, so it will not be described further here. (Reference) Figure 5 . Figure 5 It is illustrated in accordance with some embodiments of this disclosure. Figure 4 A schematic diagram illustrating the operation of the switching capacitor networks SCN1-SCN2 in four time intervals. Similar to... Figure 4 The switching capacitor network SCN1 and switching capacitor network SCN2 contain switches S 2,1 Switch S 2,2 Switch S 2,3 Switch S 2,4 And the flying capacitor C2.

[0097] Taking sub-power stage P1 as an example, its duty cycle sequentially includes time intervals TD1, TD2, TD3, and TD4. Time intervals TD1 and TD3 correspond to the aforementioned first phase (e.g., phase). The time intervals TD2 and TD4 correspond to the aforementioned second phase (e.g., phase). In other words, in time interval TD1 (e.g., sub-phase) and time interval TD3 (e.g., sub-phase) ), the high-switching S of sub-power stage P1 H1 For conduction and the low switching S of sub-power stage P1 L1 This is the cutoff point. Within time interval TD2 (e.g., sub-phase) and time interval TD4 (e.g., sub-phase) ), the high-switching S of sub-power stage P1 H1 For the cutoff and the low switch S of sub-power stage P1 L1 To enable conduction.

[0098] by Figure 5 For example, in time interval TD1 (e.g., sub-phase) and time interval TD2 (e.g., sub-phase) Switch S of capacitor network SCN1 1,1 With switch S 1,4 And the switch S of the capacitor network SCN2 2,3 With switch S 2,2 To enable conduction. Additionally, switch S of the switching capacitor network SCN1 is activated. 1,2 With switch S 1,3 And the switch S of the capacitor network SCN2 2,1 With switch S 2,4 This is the deadline.

[0099] Conversely, in time interval TD3 (e.g., sub-phase) and time interval TD4 (e.g., sub-phase) Switch S of capacitor network SCN1 1,2 With switch S 1,3 And the switch S of the capacitor network SCN2 2,1 With switch S 2,4 To enable conduction. Additionally, switch S of the switching capacitor network SCN1 is activated. 1,1 With switch S 1,4 And the switch S of the capacitor network SCN2 2,3 With switch S 2,2 This is the deadline.

[0100] by Figure 5 as well as Figure 2B For example, in time interval TD1 (e.g., sub-phase) and time interval TD3 (e.g., sub-phase) When the output voltage V OUT When the inductance L drops, BOND The switching capacitor network SCN1-SCN2 is coupled in parallel. Inductor L BOND It can be operated as a current source to provide additional current I. OUT_BOND To support the output voltage V OUT Therefore, the output voltage V OUT It will descend more slowly and reduce ripples.

[0101] by Figure 5 as well as Figure 3B For example, in time interval TD2 (e.g., sub-phase) and time interval TD4 (e.g., sub-phase) Inductance L BOND The switching capacitor network SCN1-SCN2 is connected in series with the inductor L. BOND It can operate as a voltage source to make the transition voltage VDD SC Higher than the input voltage V IN Therefore, the output voltage V OUT It can be higher than the input voltage V IN one-half (V) IN / 2). In other words, the voltage conversion efficiency can be greater than 1 / 2.

[0102] The operations in the aforementioned time intervals TD1-TD4 can reduce ripple. Sub-power stages P2-P3 have a similar architecture, so they will not be described further here.

[0103] Compared to some related technologies with more switches, this disclosure has fewer switches, and therefore the switching loss and conduction loss in this disclosure are smaller.

[0104] Compared to some devices with the same switch, in this disclosure, more energy is supplied to the output voltage V in each duty cycle. OUT (For example: switching the speeding capacitors in capacitor networks SCN1-SCN2 in the first phase) Provides energy, and inductor L BOND In the second phase (Provides energy), so the ripple and hard charging losses in this disclosure are small, and the switching frequency (switching loss) in this disclosure is small.

[0105] Furthermore, this disclosure applies to applications with small capacitors. Small capacitors are easily saturated and have low peak inductance, therefore the conduction losses disclosed in this method will not increase significantly. Further, when the inductance L... BOND Coupled in parallel with the switching capacitor networks SCN1-SCN2 (e.g.: as well as Inductance L BOND Operates as a current source to make the output voltage V OUT The decrease is relatively slow, and when the inductance L BOND Coupled in series with the switching capacitor network SCN1-SCN2 (e.g.: as well as Inductance L BOND Operates as a voltage source to make the transition voltage VDD SC Greater than the input voltage V IN Therefore, ripple can be minimized and voltage conversion efficiency can be greater than 1 / 2 for better efficiency.

[0106] refer to Figure 6 . Figure 6 It is illustrated in accordance with some embodiments of this disclosure. Figure 4 The split architecture 600 of these switching capacitor networks is shown. The split architecture 600 is illustrated. Figure 4 The switching capacitor network SCN1-SCN2 is split into multiple switching unit circuits. In some embodiments, Figure 4 Each of the switching capacitor networks SCN1-SCN2 can be split into multiple switching unit circuits.

[0107] Figure 6 This example uses the switching capacitor network SCN1. Figure 6 For example, the switching capacitor network SCN1 is split into multiple switching unit circuits CELL0, CELL1, CELL2, and CELL3. Each of the switching unit circuits CELL0, CELL1, CELL2, and CELL3 has the same characteristics as... Figure 4 The architecture is similar to that of the switching capacitor network SCN1. Taking the switching unit circuit CELL0 as an example, the switching unit circuit CELL0 includes a switch S 1,1 [0], Switch S1,2 [0], Switch S 1,3 [0], Switch S 1,4 [0] and the flying capacitor C1[0].

[0108] Assumption Figure 4 The capacitance value of capacitor C1 in the Zhongfeichi series is C. FLY Therefore, the capacitance value of the flying capacitor C1[0] in the conversion unit circuit CELL0 can be C FLY / 15, the capacitance value of the flying capacitor C1[1] in the conversion unit circuit CELL1 can be 2C FLY / 15, the capacitance value of the flying capacitor C1[2] in the conversion unit circuit CELL2 can be 4C FLY / 15, the capacitance value of the flying capacitor C1[3] in the conversion unit circuit CELL3 can be 8C. FLY / 15. In other words, the capacitance of the flying capacitor C1[1] is twice that of the flying capacitor C1[0], the capacitance of the flying capacitor C1[2] is twice that of the flying capacitor C1[1], and the capacitance of the flying capacitor C1[3] is twice that of the flying capacitor C1[2].

[0109] By Figure 4 The switching capacitor network SCN1-SCN2 in the middle is split into Figure 6 , Figure 4 Switch S in 1,1 Switch S 1,2 Switch S 1,3 Switch S 1,4 And the flying capacitor C1 will be split. Enable signals EN[0]-EN[3] (related to the operating frequency) are used to generate gate signals, which are used to control these switches to control the utilization rate of these split capacitors. Accordingly, in light load mode, less energy is output to the output terminal OUT by controlling the utilization rate of these split capacitors. Because less energy is output to the output terminal OUT, less additional charge will accumulate in the output capacitor (e.g.: Figure 7 The output capacitor C OUT Accordingly, ripple can be reduced and switching losses can be avoided. Details about the enable signals EN[0]-EN[3] (enable signals EN[0:3]) will be described in detail in the following paragraphs.

[0110] Since the switching capacitor network SCN2 has a similar architecture, it will not be described in detail here.

[0111] refer to Figure 7 . Figure 7This is a schematic diagram of a switching capacitor transformer 700 illustrated according to some embodiments of the present disclosure. The switching capacitor transformer 700 includes a switching capacitor power stage 710 and a controller 720. The controller 720 is coupled to the switching capacitor power stage 710.

[0112] The switching capacitor power stage 710 is similar to Figure 4 The switching capacitor power stage in the middle is 400 and it has Figure 6 The split structure is 600. Taking sub-power stage P1 as an example, sub-power stage P1 also includes driver DR1, and driver DR1 is also used to control these high-frequency switches S. H1 These low-voltage switches S L1 And to turn these switches on or off in the switching capacitor networks SCN1-SCN2.

[0113] The controller 720 is used to determine the output voltage V located at the output terminal OUT. OUT Reference voltage V REF1 and reference voltage V REF2 Generate control signal CS H1 CS L1 CS H2 CS L2 CS H3 CS L3 And the enable signal EN[3:0].

[0114] by Figure 7 For example, controller 720 includes pulse control loop circuit 721, frequency control loop circuit 722, and output capacitor C. OUT .

[0115] The pulse control loop circuit 721 has a self-switching capacitor power stage 710 that receives the transition voltage VDD. SC The pulse control loop circuit 721 can operate based on the transition voltage VDD. SC and reference voltage V REF1 Generate control signal CS H1 CS L1 CS H2 CS L2 CS H3 CS L3 . Figure 8 It is illustrated in accordance with some embodiments of this disclosure. Figure 7 A schematic diagram of the pulse control loop circuit 721 in the image. Figure 7 as well as Figure 8 For example, the pulse control loop circuit 721 includes a sample-and-hold circuit 7211, a mismatch correction circuit 7212, and a sequential logic circuit 7213. The sample-and-hold circuit 7211 operates based on the transition voltage VDD. SCMultiple first signals FS1 are generated. The mismatch correction circuit 7212 generates these first signals FS1 and a reference voltage V. REF1 Multiple second signals FS2 are generated. The sequential logic circuit 7213 generates these second signals FS2 and the phase signal V. PHASE1 -V PHASE3 Generate control signal CS H1 CS L1 CS H2 CS L2 CS H3 CS L3 .

[0116] The driver DR1 in the sub-power stage P1 can receive the control signal CS. H1 CS L1 And output control signal CS H1 CS L1 To control the high switches S in the sub-power stage P1 respectively H1 And these low-switching S L1 By adjusting the control signal CS H1 CS L1 The duty cycle is to turn on or off these high-voltage switches S H1 And these low-switching S L1 This allows the transition voltage VDD to be... SC It has a relative output voltage V OUT An appropriate value.

[0117] Frequency control loop circuit 722 and output capacitor C OUT Coupled to the output terminal OUT. The frequency control loop circuit 722 can control the frequency based on the output voltage V. OUT and reference voltage V REF2 Generate an enable signal EN[3:0].

[0118] by Figure 7 For example, the frequency control loop circuit 722 includes an operational amplifier 7221, a voltage-controlled oscillator 7222, a phase splitter 7223, a counter 7224, and a finite state machine circuit 7225.

[0119] Operational amplifier 7221 operates based on output voltage V OUT and reference voltage V REF2 Generate comparison signal V C The voltage-controlled oscillator 7222 is based on the comparison signal V. C Generate frequency clock signal F CLK Comparison signal V C Related to output voltage V OUT When the output voltage V OUTToo low, the frequency generated by the voltage-controlled oscillator 7222 (e.g., the frequency clock signal F) CLK The frequency clock signal F will increase to prevent a decrease in output voltage. In other words, the frequency clock signal F... CLK Efficiency can be improved by adjusting the circuit load (e.g., the switching frequency can be controlled to be lower in light-load mode). The phase splitter 7223 operates based on the frequency clock signal F. CLK Generate phase signal V PHASE1 -V PHASE3 And the output phase signal V PHASE1 -V PHASE3 The pulse control loop circuit 721 is used. The counter 7224 operates based on the frequency clock signal F. CLK The counting signal CNT[3:0] is generated. The finite state machine circuit 7225 generates the enable signal EN[3:0] based on the counting signal CNT[3:0] and the reset signal RST.

[0120] Based on the above, driver DR1 receives control signal CS from pulse control loop circuit 721. H1 CS L1 It also receives the enable signal EN[3:0] from the frequency control loop circuit 722. Driver DR1 operates according to the control signal CS. H1 CS L1 And the enable signal EN[3:0] generates the gate signal CS 1,K [3:0] and CS 2,K [3:0]. Gate signal CS 1,K [3:0] Used to control these switches S in the switching capacitor network SCN1 1,1 [3:0]、S 1,2 [3:0]、S 1,3 [3:0]、S 1,4 [3:0](For example: gate signal CS) 1,1 [3:0] Control these switches S respectively 1,1 [3:0]), and the gate signal CS 2,K [3:0] is used to control these switches in the switching capacitor network SCN2.

[0121] The operation of the drivers in sub-power stages P2-P3 is similar to that of driver DR1 in sub-power stage P1, so it will not be described again here.

[0122] As described above, the switching capacitor power stage 710 is designed to include multiple sub-power stages P1-P3 to reduce ripple and frequency. However, the three inductors L in these sub-power stages P1-P3... BONDThere can be mismatch issues. For example, if the high switches and low switches in the sub-power stages P1-P3 are turned on at the same time, the sub-power stage with the smaller inductance value will receive more energy, resulting in increased ripple at the output OUT. Conversely, the sub-power stage with the larger inductance value will receive less energy. The mismatch correction circuit 7212 can be used to avoid mismatch problems.

[0123] refer to Figure 9 . Figure 9 This is a waveform diagram of the signals in sub-power stages P1-P3 illustrated in accordance with some embodiments of this disclosure.

[0124] The mismatch correction circuit 7212 can extend the on-time of the switch in the sub-power stage with a larger inductance value (e.g., sub-power stage P3) and shorten the on-time of the switch in the sub-power stage with a smaller inductance value (e.g., sub-power stage P2) to avoid the aforementioned mismatch problem.

[0125] by Figure 8 For example, the mismatch correction circuit 7212 includes a coarse adjustment circuit 72121 and a fine adjustment circuit 72122. The coarse adjustment circuit 72121 adjusts the switching time of the primary stage, while the fine adjustment circuit 72122 adjusts the switching time of the other secondary stages.

[0126] refer to Figure 10 . Figure 10 This is a schematic diagram of a buffer BUF coupled between an operational amplifier 7221A and a voltage-controlled oscillator 7222A, illustrated according to some embodiments of this disclosure.

[0127] The operational amplifier 7221A is similar to Figure 7 The operational amplifier 7221 is used in this circuit. The voltage-controlled oscillator 7222A is similar to... Figure 7 The voltage-controlled oscillator 7222 is used. A buffer BUF is coupled between the operational amplifier 7221A and the voltage-controlled oscillator 7222A. The buffer BUF has a small quiescent current and effectively improves transient response.

[0128] In summary, this invention exhibits low switching losses, low conduction losses, and low ripple, along with a high voltage conversion efficiency. Therefore, this invention demonstrates superior efficiency.

[0129] Although this disclosure has been described above with reference to embodiments, it is not intended to limit this disclosure. Any person skilled in the art can make various modifications and refinements without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this disclosure shall be determined by the scope defined in the appended claims.

Claims

1. A switching capacitor power stage, characterized in that, Include: A first sub-power stage, comprising: A first inductor is coupled to an input terminal; A first high-voltage switch is coupled between the first inductor and an output terminal; A first low-voltage switch is coupled between the first inductor and a first transition node; as well as A first set of switching capacitor networks is coupled between the first transition node and the output terminal; and A second sub-power stage, comprising: A second inductor is connected to this input terminal; A second high-voltage switch is coupled between the second inductor and the output terminal; A second low-voltage switch is coupled between the second inductor and a second transition node; as well as A second set of switching capacitors is coupled between the second transition node and the output terminal.

2. The switching capacitor power stage as described in claim 1, characterized in that, The transition voltage of the first transition node is greater than the input voltage of the input terminal.

3. The switching capacitor power stage as described in claim 2, characterized in that, Also includes: A third sub-power stage, comprising: A third inductor is connected to this input terminal; A third high-voltage switch is coupled between the third inductor and the output terminal; A third low-voltage switch is coupled between the third inductor and a third transition node; as well as A third set of switching capacitors is coupled between the third transition node and the output terminal.

4. The switching capacitor power stage as described in claim 1, characterized in that, The first set of switching capacitor networks includes a first switching capacitor network and a second switching capacitor network. Each of the first switching capacitor network and the second switching capacitor network includes: A first switch is coupled between the first transition node and a first internal node; A second switch is coupled between the first internal node and the output terminal; A third switch is used to receive a voltage and is coupled to a second internal node; A fourth switch is coupled between the second internal node and the output terminal; as well as A capacitor is coupled between the first internal node and the second internal node.

5. The switching capacitor power stage as described in claim 4, characterized in that, One work cycle consists of a first time interval, a second time interval, a third time interval, and a fourth time interval in sequence. During the first time interval and the third time interval, the first high switch is turned on and the first low switch is turned off. During the second and fourth time intervals, the first high switch is turned off and the first low switch is turned on.

6. The switching capacitor power stage as described in claim 5, characterized in that, During the first and second time intervals, the first switch, the fourth switch, the second switch, and the third switch in the first switching capacitor network are turned on, and the second switch, the third switch, the first switch, and the fourth switch in the second switching capacitor network are turned off. During the third and fourth time intervals, the first switch, the fourth switch, the second switch, and the third switch in the first switching capacitor network are turned off, while the second switch, the third switch, the first switch, and the fourth switch in the second switching capacitor network are turned on.

7. A switching capacitor transformer, characterized in that, Include: Multiple sub-power stages, each of the multiple sub-power stages comprising: An inductor is coupled to an input terminal; A high-voltage switch is coupled between the inductor and an output terminal; A low-voltage switch is coupled between the inductor and a transition node; as well as A set of switching capacitors is coupled between the transition node and the output terminal; as well as A driver is used to control this group of switching capacitor networks; as well as A controller is configured to generate multiple control signals and multiple enable signals based on an output voltage, a first reference voltage, and a second reference voltage at the output terminal. The driver is also used to generate multiple gate voltages based on the multiple control signals and the multiple enable signals to control multiple switches in the group of switching capacitor networks.

8. The switching capacitor transformer as described in claim 7, characterized in that, The driver is also used to output the plurality of control signals to control the high switches and low switches in the plurality of sub-power stages.

9. The switching capacitor transformer as described in claim 7, characterized in that, The controller includes: A pulse control loop circuit is used to generate the plurality of control signals based on a transition voltage of the transition node and the first reference voltage; and A frequency control loop circuit is used to generate the plurality of enable signals based on the output voltage and the second reference voltage.

10. The switching capacitor transformer as described in claim 9, characterized in that, The pulse control loop circuit includes: A sample-and-hold circuit is used to generate a plurality of first signals based on the transition voltage; A mismatch correction circuit is used to generate a plurality of second signals based on the plurality of first signals and the first reference voltage; as well as A sequential logic circuit for generating the plurality of control signals based on the plurality of second signals.

11. The switching capacitor transformer as described in claim 9, characterized in that, The frequency control loop circuit includes: An operational amplifier for generating a comparison signal based on the output voltage and the second reference voltage; A voltage-controlled oscillator is used to generate a frequency clock signal based on the comparison signal; A counter used to generate multiple counting signals based on a clock signal of that frequency; as well as A finite state machine circuit is used to generate the plurality of enable signals based on the plurality of counting signals.

12. The switching capacitor transformer as described in claim 11, characterized in that, The frequency control loop circuit also includes: A phase splitter is used to generate multiple phase signals according to the frequency clock signal and output the multiple phase signals to the pulse control loop circuit.

13. The switching capacitor transformer as described in claim 11, characterized in that, The frequency control loop circuit also includes: A buffer is coupled between the operational amplifier and the voltage-controlled oscillator.

14. The switching capacitor transformer as described in claim 7, characterized in that, Each component in this switching capacitor network includes a first conversion unit circuit, a second conversion unit circuit, a third conversion unit circuit, and a fourth conversion unit circuit. Each of the first conversion unit circuit, the second conversion unit circuit, the third conversion unit circuit, and the fourth conversion unit circuit includes: A first switch is coupled between the transition node and a first internal node; A second switch is coupled between the first internal node and the output terminal; A third switch is coupled to a second internal node; A fourth switch is coupled between the second internal node and the output terminal; as well as A capacitor is coupled between the first internal node and the second internal node.

15. The switching capacitor transformer as described in claim 14, characterized in that, The capacitance value of the capacitor in the second conversion unit circuit is twice the capacitance value of the capacitor in the first conversion unit circuit, the capacitance value of the capacitor in the third conversion unit circuit is twice the capacitance value of the capacitor in the second conversion unit circuit, and the capacitance value of the capacitor in the fourth conversion unit circuit is twice the capacitance value of the capacitor in the third conversion unit circuit.

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