A method and apparatus for reducing the number of switches and decoding in a resistive digital-to-analog converter

Abstract

The application discloses a method and device for reducing the number of switches and decoding of a resistance digital-to-analog converter, comprising a resistance Rz which divides a power supply VREFP into two parts and then divides the two parts by two unit resistances N Each voltage after the voltage division is connected to the source end of a right NMOS switch, and the drain end of the NMOS switch is cross-connected to two voltage transmission lines; the gate of the switch array NMOS is connected to a switch control signal generated by a digital decoding circuit, and the switch array NMOS is controlled by the decoding circuit to be in an on state or an off state. The application can realize the least number of switch stages, reduce the decoding scale, and can be well matched on a layout.

Description

Technical Field

[0001] This invention belongs to the field of resistive digital-to-analog converter technology, specifically relating to a method and apparatus for reducing the number of switches and decoding in a resistive digital-to-analog converter. Background Technology

[0002] The main function of a resistor divider DAC is achieved using a set of series resistors. Modern integrated circuit manufacturing processes easily ensure its relative accuracy; even with significant errors in the resistance values, the DAC's output remains monotonic—this is an advantage of resistor divider DACs. Several different types of resistor-series DACs exist, and the most direct way to achieve an N-bit DAC is through a DAC based on a decoder-converter. The number of bits in the resistors determines the DAC's resolution; an N-bit DAC requires 2... n The resistor network and switch network are connected in a tree structure. The resistor network structure is simple, and the switch network provides a high-impedance path for a given digital input signal, transmitting the corresponding codeword analog signal voltage to the output node. However, the delay of the switch network severely limits the speed of the DAC. Using combinational logic can speed up the process, but the improvement is limited. As the number of bits increases, the number of resistors and switches also increases significantly, consuming a large amount of chip area. The area doubles for every bit increase in resolution.

[0003] In existing designs, the resistor structure consists of identical unit resistors connected in series. The top of the resistor network is connected to a reference potential, and the bottom is connected to a low potential. The reference voltage is then divided by the resistor network into pairs of voltage values ​​with equal intervals, forming different weights. The switch array selects one of these voltage values ​​based on the codeword and passes it to the next stage circuit. This type of DAC structure is simple and easy to implement. Because the voltage of the previous stage will not be lower than that of the next stage, it exhibits excellent monotonicity and is often used to implement low-power DACs.

[0004] The main solutions currently available are as follows:

[0005] Option 1: As Figure 1 As shown, this resistor structure mainly consists of a resistor network and a switch array. The switch array uses a tree structure for voltage selection, and the required number of switches is... The advantage is that no decoder is needed, and the binary code can be directly controlled by switching. The disadvantage is that at medium and high resolutions, the number of switches increases rapidly, resulting in a larger total on-resistance and increased parasitic capacitance, which severely limits the speed of the DAC in low-speed applications.

[0006] Option 2: Figure 2 As shown, this resistor structure mainly consists of a resistor network, a switch array, and a decoder, requiring 2 switches. N The decoder uses a full decoding method, which has the advantage of minimizing the total on-resistance and parasitic capacitance; the disadvantage is that the decoding circuit is complex.

[0007] Option 3: As Figure 3 As shown, this resistor structure mainly consists of a resistor network, a switch array, and a decoder. The decoder uses Gray code decoding, with the horizontal axis representing M-bit decoding and the vertical axis representing N-bit decoding. Two switches are required. M *(2 N +1). The decoding process involves first converting the binary code into Gray code, and then performing the decoding. The advantage is that it represents a compromise between Scheme 1 and Scheme 2, reducing the number of switches while also simplifying the decoder. The disadvantage is that it still requires two switching stages, which limits its application; this scheme is mainly used in medium-to-high precision converters.

[0008] In existing technologies, the main drawbacks are the large number of switching stages, the large decoding scale, and the fact that some solutions make trade-offs between the two without achieving optimal results. Summary of the Invention

[0009] In order to overcome the shortcomings of the prior art, the present invention aims to provide a method and apparatus for reducing the number of switches and decoding in a resistive digital-to-analog converter, which can achieve the minimum number of switch stages, reduce the decoding scale, and achieve good matching on the layout.

[0010] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0011] A device for reducing the number of switches and decoding in a resistive digital-to-analog converter includes a resistor Rz, which splits the power supply VREFP in two and then passes it through 2... N A voltage divider is performed using unit resistors, where N is the number of bits in the resistor divider DAC. The effective number of bits in a resistor divider DAC is at most around 10. Each voltage after division is connected to the source of an NMOS switch. Following the order of the voltage connections, the drain of the m-th NMOS switch is connected to voltage transmission line VL2, and the drain of the n-th NMOS switch is connected to voltage transmission line VL1, where m is odd and n is even. Using these two transmission lines, the voltage across each unit resistor can be transmitted to the subsequent stage of the circuit. To transmit the voltage across the i-th (i = 0, 1, ..., N-1) resistor Ri to the subsequent stage, when i is even, voltage transmission line VL1 represents the low voltage level of resistor Ri, and voltage transmission line VL2 represents the high voltage level of resistor Ri. When i is odd, the low voltage level of resistor Ri is voltage transmission line VL2, and the high voltage level of resistor Ri is voltage transmission line VL1. N A switch array is formed by NMOS switches. The gate of each NMOS switch is connected to a switch control signal generated by a digital decoding circuit. Each NMOS switch in the switch array is controlled by the digital decoding circuit to be either on or off.

[0012] The resistance value of the resistor Rz is the same as the resistance value of 2. N The unit resistance.

[0013] The switch array maintains only one level of switches, using a single-level cascade method.

[0014] A method for reducing the number of switches and decoding in a resistive digital-to-analog converter (DAC) involves first splitting the power supply VREFP in two via resistor Rz, reducing the voltage to VREFP / 2. Then, the remaining VREFP / 2 voltage is passed through 2... N A unit resistor is used to divide the voltage, and each resulting voltage is connected to the source of the NMOS switch on the right. Finally, the voltages are crossed through the drain of the NMOS switch to two voltage transmission lines, VL1 and VL2. Control signal Y<N-1:0> These are switching control signals generated by a digital decoding circuit. These control signals are connected to the gate terminals of the NMOS switching array. The NMOS switching array is controlled by the decoding circuit to be either on or off. For example, if the control signal generated by the decoding circuit is 1 (high level), the connected NMOS will be turned on; if the control signal generated by the decoding circuit is 0 (low level), the connected NMOS will be turned off.

[0015] When adjacent code numbers of the decoding circuit are turned on, only two switches perform the on / off action at a time. In the initial state, i.e., when the decoding circuit is 000, switches M0 to M1 in the switch array... N All are in the off state; when the decoding circuit is 001, the two NMOS switches M0 and M1 in the switch array are in the on state, and the MOS switches M2 to M... N All are in the off state; when the code word count is increased by 1, that is, when the decoding circuit is 010, NMOS switch M0 changes from the on state to the off state, and NMOS switch M2 changes from the off state to the on state. Therefore, in this state, M1 and M2 are in the on state, and the rest are in the off state.

[0016] The decoding circuit conversion principle is as follows: In the initial state of the decoder, when the code word is 000, the control signals Y of the two NMOS transistors M0 and M1 are... <0> and Y <1> Both are at high level, meaning these two NMOS transistors are in the ON state, while the other NMOS transistors are in the OFF state. This makes the voltages across resistor R0 on the two transmission lines VL1 and VL2 respectively, i.e., VL1 = 0 and VL2 = VR.

[0017] The transmission lines VL1 and VL2 represent the voltage values ​​across each unit resistor in the resistor string. In a segmented hybrid DAC, these two transmission lines serve as the coarse conversion voltages for the higher bits of the DAC. Furthermore, transmission lines VL1 and VL2 are connected in series with the subsequent lower-order conversion circuit. The lower-order conversion circuit further processes the coarse conversion voltages from the higher bits into fine conversion voltages. When connecting the lower-order conversion circuit, the lower-order conversion circuit is allowed to freely choose between transmission lines VL1 and VL2.

[0018] One specific implementation circuit of the low-order conversion structure is as follows: If the low-order converter is a PMOS differential pair, it can complete the voltage-to-current conversion. The low-order input signal is connected to the left gate terminal VP of the PMOS differential pair. When the VP voltage is VL1 = 0, the circuit conversion current is at its maximum. When the VP voltage switches to VL2 = VR, the PMOS gate terminal VP voltage increases, |VGS| decreases, so the VP current at the left end of the differential pair decreases, and the VN current at the other end of the differential pair increases, thereby completing the conversion between adjacent codewords in the low-order conversion structure. When codeword 000 is converted in this conversion cycle, the differential pair switch of the low-order conversion switches from transmission line VL1 to transmission line VL2 to increase the output. Then, when codeword 001 is converted in the next conversion cycle, the differential pair switch of the low-order conversion switches from transmission line VL2 to transmission line VL1 to increase the output. The conversion of other codewords is similar.

[0019] The beneficial effects of this invention are:

[0020] This invention reduces the size of the decoding circuit while maintaining the use of a single-stage switch in the resistor string switch array. At the same time, it enables the switch to conduct two adjacent NMOS at a time, greatly reducing glitches. The VREFP is first pre-processed by dividing it in half, which can reduce the operating current and also ensure layout matching. The three modules of the circuit design are kept to be of equal length, which can be better laid out and connected on the layout. Attached Figure Description

[0021] Figure 1 The circuit structure is based on the existing technical solution.

[0022] Figure 2 The circuit structure is the second existing technical solution.

[0023] Figure 3 The circuit structure is the existing technical solution three.

[0024] Figure 4 This is the circuit structure of the present invention.

[0025] Figure 5 This is a schematic diagram of the subsequent circuit of the present invention.

[0026] Figure 6This is a schematic diagram of the voltage-to-current differential pair of the present invention.

[0027] Figure 7 This is a schematic diagram of the resistor string layout of the present invention. Detailed Implementation

[0028] The present invention will now be described in further detail with reference to the accompanying drawings.

[0029] The structural principle of the present invention is as follows Figure 4 As shown, first through resistor R Z The VREFP is split in two, and then the remaining VREFP / 2 voltage is passed through 2 N Each voltage generated by a unit resistor is connected to the source terminal of the NMOS switch on the right. The drain terminal of the NMOS switch is then cross-connected to two voltage transmission lines: transmission line VL1 and transmission line VL2. The switch control signal Y generated by the digital decoding circuit...<N-1:0> Each of these is connected to the gate of each NMOS transistor in the switch array, where the NMOS switch array is controlled by a decoding circuit to be either on or off.

[0030] The specific circuit principle is as follows: Figure 4 As shown, taking N=3 as an example, first pass through resistor Rz (resistance value is the same as 2). 3 The unit resistance) splits the power supply VREFP in two, reducing the voltage to VREFP / 2. Then, the remaining voltage VREFP / 2 is passed through 2 3 The voltage is divided by a unit resistor, and each resulting voltage is connected to the source of the NMOS switch on the right. Finally, the voltage is cross-connected to two voltage transmission lines, VL1 and VL2, through the drain of the NMOS switch. The control signals Y<7:0> are switch control signals generated by a digital decoding circuit, and these control signals are connected to the gate of the NMOS transistors in the switch array. The NMOS switch array is controlled by the decoding circuit to be on or off. For example, if the control signal generated by the decoding circuit is 1 (high level), the connected NMOS transistors are turned on; if the control signal generated by the decoding circuit is 0 (low level), the connected NMOS transistors are turned off.

[0031] The switch array maintains only one level of switches, using a single-level cascade method.

[0032] As can be seen from the table below, this invention combines the advantages of Scheme 2 and Scheme 3. The switch array only maintains one level of switching. As can be seen from Table 1, this advantage becomes more and more obvious as the number of input bits increases.

[0033] Option 2 is a traditional decoder that uses a full decoding method. As the number of input bits increases, the complexity of the decoding circuit increases exponentially, which increases the dynamic power consumption of the DAC logic section.

[0034] The decoder in Scheme 3 consists of Gray code and a decoding section. Compared to binary code, Gray code changes only one bit between adjacent code numbers, greatly reducing the generation of switching glitches. In contrast, the decoding circuit of this application, as shown in Table 2, only requires two switches to turn on and off at a time when adjacent code numbers are on. For example, when codeword 001 is converted to 010, Y... <0> and Y <2> Two controlled NMOS transistors perform switching operations. The circuit employs a modular triggering method, specifically a 4x4 switch control array composed of 2-to-4 decoders.

[0035] Table 1. Comparison of the advantages of the technical solution of the present invention and traditional solutions.

[0036] Number of switches required for each scheme decoder N＝3 N＝4 N＝5 N＝6 N＝7 Option 1 none 14 30 62 126 254 Option 2 Full Decoding 9 17 33 65 129 Option 3 Gray code + decoding / / / 72 136 This plan Decoding 9 17 33 65 129

[0037] As shown in Table 2, the logic conversion truth table, taking a three-bit conversion process as an example, the circuit conversion principle is as follows: In the initial state of the decoder, when the code word is 000, the control signals Y of the two NMOS transistors M0 and M1 are... <0> and Y <1> When the signal is high, the NMOS switch is in the ON state, and the other NMOS switches are in the OFF state. The two transmission lines correspond to the voltages across resistor R0, i.e., VL1 = 0 and VL2 = VR, where...

[0038] Assuming VREFP = 5V and VREFN = 0V, then VR = 321.5mV. VL1 and VL2 serve as the high-level coarse conversion voltages in the segmented hybrid structure. When connecting to the low-level conversion circuit, the low-level conversion circuit can freely choose VL1 and VL2; VL1 and VL2 serve as the high-level conversion voltages in the segmented hybrid structure, such as... Figure 5 The diagram shows the circuit connections between transmission lines VL1 and VL2 and the subsequent low-order conversion structure. In the circuit system, Figure 4 and Figure 5 It is connected in series.

[0039] like Figure 6 As shown Figure 5One implementation circuit for the low-to-mid bit conversion structure, if the low-bit converter is a PMOS differential pair, can complete the voltage-to-current conversion. The low-bit input signal is connected to the left gate terminal VP of the PMOS differential pair. When the VP voltage is VL1 = 0, the circuit conversion current is at its maximum. When the VP voltage changes to VL2 = VR = 312.5mV, the PMOS gate terminal VP voltage increases, |VGS| decreases, so the VP current at the left end of the differential pair decreases, and the current at the other end VN increases, thus completing the conversion between low-bit codewords. During the carry-over in the high-bit conversion circuit, i.e., the resistor series voltage divider circuit, when switching to the next codeword 001, NMOS transistors M1 and M2 are turned on, and the others are turned off. That is, the two transmission lines correspond to the voltages across resistor R1, i.e., VL1 = 625mV and VL2 = 312.5mV respectively. When the highest codeword 111 is converted, NMOS transistors M6 and M7 are turned on, and the others are turned off. That is, the two transmission lines correspond to the voltages across resistor R7 respectively.

[0040] When codeword 000 is converted in the previous conversion cycle, the low-order conversion differential pair switch is connected to VL2 to increase the output. When codeword 001 is converted in this conversion cycle, the low-order differential pair switch is connected to VL1 to increase the output. The same applies to the conversion of other codewords.

[0041] Table 2 Truth Table for Decoder Circuit

[0042]

[0043] For circuit layout, this invention can divide VREFP into two resistors R. Z (resistance equals 2) N The sum of the unit resistances is evenly distributed across the two ends of the resistor array, and the resistor string array connecting the switch is wrapped within it. This can further improve the matching degree of the resistor array, as shown in the schematic diagram. Figure 7 As shown, the switch array adopts a single-level cascade method, which can better correspond to the resistors connected to it on the layout. The resistor array, switch array and decoder array can maintain the same length, which allows for better connection of the circuit layout.

Claims

1. A device for reducing the number of switches and decoding in a resistive digital-to-analog converter, characterized in that, Includes resistor Rz, which splits the power supply VREFP in two and then passes it through 2 N A voltage divider is performed using unit resistors, where N is the number of bits in the resistor divider DAC. Each voltage after division is connected to the source of an NMOS switch. Following the order of the voltage connections, the drain of the m-th NMOS switch is connected to voltage transmission line VL2, and the drain of the n-th NMOS switch is connected to voltage transmission line VL1, where m is odd and n is even. Using these two transmission lines, the voltage across each unit resistor can be transmitted to the next stage of the circuit. To transmit the voltage across the i-th (i=0, 1, ..., N-1) resistor Ri to the next stage, when i is even, voltage transmission line VL1 is the low voltage level of resistor Ri, and voltage transmission line VL2 is the high voltage level of resistor Ri; when i is odd, the low voltage level of resistor Ri is voltage transmission line VL2, and the high voltage level of resistor Ri is voltage transmission line VL1. N A switch array is formed by NMOS switches. The gate of each NMOS switch is connected to a switch control signal generated by a digital decoding circuit. Each NMOS switch in the switch array is controlled by the digital decoding circuit to be either on or off.

2. The apparatus for reducing the number of switches and decoding in a resistive digital-to-analog converter according to claim 1, characterized in that, The resistance value of the resistor Rz is the same as the resistance value of 2. N The unit resistance.

3. The apparatus for reducing the number of switches and decoding in a resistive digital-to-analog converter according to claim 1, characterized in that, The switch array maintains only one level of switches, using a single-level cascade method.

4. A method for reducing the number of switches and decoding in a resistive digital-to-analog converter based on the apparatus of any one of claims 1-3, characterized in that, First, the power supply VREFP is split in two by resistor Rz, reducing the voltage to VREFP / 2. Then, the remaining VREFP / 2 voltage is passed through 2... N A unit resistor is used to divide the voltage, and each voltage generated is connected to the source terminal of the NMOS switch on the right. Finally, the voltage is crossed through the drain terminal of the NMOS switch to two voltage transmission lines, transmission line VL1 and transmission line VL2. The control signal Y...<N-1:0> These are switch control signals generated by a digital decoding circuit. These control signals are connected to the gate terminals of the NMOS transistors in the switch array. The NMOS switch array is controlled by the decoding circuit to be in either a conducting or off state.

5. A method for reducing the number of switches and decoding in a resistive digital-to-analog converter according to claim 4, characterized in that, When adjacent code numbers of the decoding circuit are turned on, only two switches perform the on / off action at a time. In the initial state, i.e., when the decoding circuit is 000, switches M0~M in the switch array... N All are in the off state; When the decoding circuit is set to 001, the two NMOS switches M0 and M1 in the switch array are in the ON state, and the MOS switches M2~M... N All are in the off state; When the code word count is incremented by 1, i.e. the decoding circuit is 010, NMOS switch M0 changes from the on state to the off state, and NMOS switch M2 changes from the off state to the on state. Therefore, in this state, M1 and M2 are in the on state, and the rest are in the off state.

6. A method for reducing the number of switches and decoding in a resistive digital-to-analog converter according to claim 4, characterized in that, The decoding circuit conversion principle is as follows: In the initial state of the decoder, when the code word is 000, the control signals Y of the two NMOS transistors M0 and M1 are... <0> and Y <1> Both are at high level, meaning these two NMOS transistors are in the ON state, while the other NMOS transistors are in the OFF state. This makes the voltages across resistor R0 on the two transmission lines VL1 and VL2 respectively, i.e., VL1=0 and VL2=VR. .

7. A method for reducing the number of switches and decoding in a resistive digital-to-analog converter according to claim 4, characterized in that, The transmission lines VL1 and VL2 represent the voltage values ​​across each unit resistor in the resistor string. In a segmented hybrid DAC, these two transmission lines serve as the coarse conversion voltages for the higher bits of the DAC. Furthermore, transmission lines VL1 and VL2 are connected in series with the subsequent lower-order conversion circuit. The lower-order conversion circuit further processes the coarse conversion voltages from the higher bits into fine conversion voltages. When connecting the lower-order conversion circuit, the lower-order conversion circuit is allowed to freely choose between transmission lines VL1 and VL2.

8. A method for reducing the number of switches and decoding in a resistive digital-to-analog converter according to claim 7, characterized in that, One specific implementation circuit of the low-order conversion structure is as follows: If the low-order converter is a PMOS differential pair, it can complete the voltage-to-current conversion. The low-order input signal is connected to the left gate terminal VP of the PMOS differential pair. When the VP voltage is VL1=0, the current of the circuit conversion is the maximum. When the VP voltage changes to VL2=VR, the PMOS gate terminal VP voltage increases, |VGS| decreases, then the VP current at the left end of the differential pair decreases, and the VN current at the other end of the differential pair increases. This completes the conversion between adjacent codewords of the low-order conversion structure. When codeword 000 is converted in this conversion cycle, the differential pair switch of the low-order conversion switches from transmission line VL1 to transmission line VL2 to increase the output. Then, when codeword 001 is converted in the next conversion cycle, the differential pair switch of the low-order conversion switches from transmission line VL2 to transmission line VL1 to increase the output. The conversion of other codewords is the same.

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