A base station GNSS clock synchronization method and system based on EPLD
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANDONG INSPUR SCI RES INST CO LTD
- Filing Date
- 2022-09-16
- Publication Date
- 2026-06-09
AI Technical Summary
Existing GNSS clock synchronization systems suffer from GPS deviation and phase oscillation issues in base stations, leading to mutual interference between base stations, which is difficult to effectively resolve with current technologies.
An EPLD-based base station GNSS clock synchronization method is adopted. By using a large phase-locked loop composed of an EPLD phase detection module and a CPU, the clock offset caused by external interference is eliminated through phase detection processing and voltage adjustment, combined with the long-term stability characteristics of GNSS and the short-term stability characteristics of OCXO.
It achieves stable and reliable clock synchronization for base station equipment, solves GPS deviation and phase oscillation problems, provides a stable clock source, and reduces costs.
Smart Images
Figure CN116033539B_ABST
Abstract
Description
Technical Field
[0001] This invention discloses a method and system, relating to the field of signal synchronization technology, specifically a base station GNSS clock synchronization method and system based on EPLD. Background Technology
[0002] TDD systems, because uplink and downlink signals operate on the same frequency but use different time slots, are inherently prone to self-interference. If clocks are out of sync between different base stations, with a deviation greater than 1.5µs, mutual interference will occur. Ensuring air interface synchronization is achieved using GNSS synchronization schemes. However, existing GNSS clock synchronization systems may suffer from defects such as GPS misalignment and phase oscillation. These defects have become a nightmare for field base stations, placing significant pressure on maintenance teams in various locations. Summary of the Invention
[0003] This invention addresses the problems of existing technologies by providing a base station GNSS clock synchronization method and system based on EPLD, which has the characteristics of strong versatility and simple implementation, and has broad application prospects.
[0004] The specific solution proposed in this invention is as follows:
[0005] This invention provides a base station GNSS clock synchronization method based on EPLD, utilizing a base station GNSS clock synchronization system for clock synchronization. The base station GNSS clock synchronization system includes a GNSS clock processing module and a synchronization code stream timing module.
[0006] The GNSS clock processing module includes a GNSS receiver module, an EPLD phase detector module, a CPU, a DAC, an OCXO clock source, and an EPLD frequency divider module.
[0007] The synchronous code stream timing module includes a PLL, an EPLD frequency division module, and an SCC module.
[0008] The GNSS receiver module receives GPS satellite signals and outputs a GPS PP1S signal to the EPLD phase detector module. The OCXO clock source outputs two 10MHz signals. One of these 10MHz signals is divided into an OCXO PP1S signal by the EPLD frequency divider within the GNSS clock processing module and then sent to the EPLD phase detector module. The EPLD phase detector module performs phase detection on the OCXO PP1S and GPS PP1S signals, generating a phase lead or lag flag and calculating the difference between the two signals. This difference is then sent to the CPU. The CPU processes the difference and controls the DAC to output the corresponding voltage value, adjusting the frequency output of the OCXO clock source.
[0009] Another 10MHz signal output from the OCXO clock source enters the PLL. After frequency multiplication by the PLL, multiple clock signals are output. One clock signal is connected to the EPLD phase detector module as the phase detector clock for the EPLD phase detector module. The other clock signal is divided by the EPLD frequency divider module in the synchronous code stream timing module to obtain a 40ms signal and sent to the SSC module for synchronous code stream timing output. The PP1S signal is sent from the EPLD phase detector module to the EPLD frequency divider module in the synchronous code stream timing module. The PP1S signal is the OCXO PP1S single pulse signal. The PP1S signal is used as the synchronous reset signal for the 40ms timing output of the synchronous code stream to clear the 40ms clock offset caused by external interference.
[0010] Furthermore, in the aforementioned EPLD-based base station GNSS clock synchronization method, the phase detection processing of the OCXO PP1S signal and the GPS PP1S signal using the EPLD phase detection module to generate a phase lead or lag flag includes:
[0011] If a phase lead flag is generated, the OCXO PP1S signal leads the GPS PP1S signal, indicating that the OCXO clock source operates at a frequency higher than 10MHz.
[0012] If a phase lag flag is generated, the OCXO PP1S signal lags behind the GPS PP1S signal, indicating that the OCXO clock source operates at a frequency lower than 10MHz.
[0013] Preferably, in the EPLD-based base station GNSS clock synchronization method, the step of controlling the DAC to output a corresponding voltage value after processing the difference via CPU, and adjusting the frequency output of the OCXO clock source, includes:
[0014] The CPU filters the difference, and then uses the processed difference to control the DAC to output the corresponding voltage value through the SPI register, thereby adjusting the frequency output of the OCXO clock source.
[0015] Preferably, in the GNSS clock synchronization method for a base station based on EPLD, the GNSS receiving module uses an SMA antenna to receive GPS satellite signals and outputs GPS PP1S signals. The CPU uses a UART interface to initialize and configure the GNSS receiving module and read relevant signals.
[0016] Preferably, in the EPLD-based base station GNSS clock synchronization method, the PLL is AD9523, which has two internal phase-locked loops and outputs a 61.44MHz clock signal for synchronizing the code stream and phase detection.
[0017] This invention also provides a base station GNSS clock synchronization system based on EPLD, the base station GNSS clock synchronization system including a GNSS clock processing module and a synchronization code stream timing module.
[0018] The GNSS clock processing module includes a GNSS receiver module, an EPLD phase detector module, a CPU, a DAC, an OCXO clock source, and an EPLD frequency divider module.
[0019] The synchronous code stream timing module includes a PLL, an EPLD frequency division module, and an SCC module.
[0020] The GNSS receiver module receives GPS satellite signals and outputs a GPS PP1S signal to the EPLD phase detector module. The OCXO clock source outputs two 10MHz signals. One of these 10MHz signals is divided into an OCXO PP1S signal by the EPLD frequency divider within the GNSS clock processing module and then sent to the EPLD phase detector module. The EPLD phase detector module performs phase detection processing on the OCXO PP1S signal and the GPS PP1S signal, generating a phase lead or lag flag and calculating the difference between the OCXO PP1S and GPS PP1S signals. The EPLD phase detector module sends this difference value to the CPU. After processing the difference value, the CPU controls the DAC to output the corresponding voltage value, adjusting the frequency output of the OCXO clock source.
[0021] Another 10MHz signal from the OCXO clock source enters the PLL. After frequency multiplication by the PLL, multiple clock signals are output. One clock signal is connected to the EPLD phase detector module as the phase detector clock for the EPLD phase detector module. The other clock signal is divided by the EPLD frequency divider module in the synchronous code stream timing module to obtain a 40ms signal and sent to the SSC module for synchronous code stream timing output. The EPLD phase detector module sends the PP1S signal to the EPLD frequency divider module in the synchronous code stream timing module. The PP1S signal is the OCXO PP1S single pulse signal. The PP1S signal is used as the synchronous reset signal for the 40ms timing output of the synchronous code stream to clear the 40ms clock offset caused by external interference.
[0022] Furthermore, in the aforementioned EPLD-based base station GNSS clock synchronization system, the EPLD phase detection module performs phase detection processing on the OCXO PP1S signal and the GPS PP1S signal to generate a phase lead or lag flag, including:
[0023] If a phase lead flag is generated, the OCXO PP1S signal leads the GPS PP1S signal, indicating that the OCXO clock source operates at a frequency higher than 10MHz.
[0024] If a phase lag flag is generated, the OCXO PP1S signal lags behind the GPS PP1S signal, indicating that the OCXO clock source operates at a frequency lower than 10MHz.
[0025] Preferably, in the EPLD-based base station GNSS clock synchronization system, the CPU processes the difference and controls the DAC to output a corresponding voltage value, adjusting the frequency output of the OCXO clock source, including:
[0026] The CPU filters the difference, and then uses the processed difference to control the DAC to output the corresponding voltage value through the SPI register, thereby adjusting the frequency output of the OCXO clock source.
[0027] Preferably, in the GNSS clock synchronization system based on EPLD, the GNSS receiving module uses an SMA antenna to receive GPS satellite signals and outputs GPS PP1S signals. The CPU uses the UART interface to initialize and configure the GNSS receiving module and read relevant signals.
[0028] Preferably, in the EPLD-based base station GNSS clock synchronization system, the PLL is an AD9523, which has two internal phase-locked loops and outputs a 61.44MHz clock signal for synchronizing the code stream and phase detection.
[0029] The advantages of this invention are:
[0030] This invention provides a GNSS clock synchronization method for base stations based on EPLD. Addressing the defects of GPS deviation and phase oscillation in GNSS clocks on base stations, the invention improves the GNSS clock synchronization system by using a low-cost EPLD as the phase detector and frequency divider. This EPLD, along with the CPU, DAC, and OCXO chips, forms a large phase-locked loop (PLL). The large PLL does not contain nested smaller PLLs, thus preventing PLL oscillation. The PP1S signal of the EPLD phase detector is a single-pulse signal of the OCXO PP1S signal, which is introduced into the SSC synchronization code stream module. It synchronizes with the PP1S signal of the GNSS clock processing module every second, periodically clearing clock offsets caused by external interference and resolving the GPS deviation problem. This base station GNSS clock synchronization method also combines the long-term stability characteristics of GNSS and the short-term stability characteristics of OCXO, providing a stable and reliable clock source for the entire base station equipment. Attached Figure Description
[0031] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0032] Figure 1 This is a schematic diagram of the system module structure and interaction of the present invention.
[0033] Figure 2 This is a block diagram of signal detection processing in the EPLD phase detection module.
[0034] Figure 3 This is a schematic diagram of the state switching of the clock synchronization system in the base station board. Detailed Implementation
[0035] GNSS clock synchronization systems may suffer from defects such as GPS misalignment and phase oscillation. GPS misalignment manifests as the clock system being in a locked state from the BBU perspective, but information from the base station's RRU indicates an excessively high IOT (Interference Time). By shutting down stations in the center of the interference area one by one, the specific interfering station can be located. Phase oscillation manifests as a sudden jump in the DIF value of the phase detector when the clock is in a locked state, such as from "0" to "3" or "4," followed by oscillation, transitioning from a locked state to an "abnormal" state.
[0036] This invention addresses the problems of GPS deviation and phase oscillation in base stations by providing a GNSS clock synchronization method based on EPLD that can solve the above problems.
[0037] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, so that those skilled in the art can better understand and implement the present invention. However, the embodiments described are not intended to limit the present invention.
[0038] This invention provides a base station GNSS clock synchronization method based on EPLD, utilizing a base station GNSS clock synchronization system for clock synchronization. The base station GNSS clock synchronization system includes a GNSS clock processing module and a synchronization code stream timing module.
[0039] The GNSS clock processing module includes a GNSS receiver module, an EPLD phase detector module, a CPU, a DAC, an OCXO clock source, and an EPLD frequency divider module.
[0040] The synchronous code stream timing module includes a PLL, an EPLD frequency division module, and an SCC module.
[0041] The GNSS receiver module receives GPS satellite signals and outputs a GPS PP1S signal to the EPLD phase detector module. The OCXO clock source outputs two 10MHz signals. One of these 10MHz signals is divided into an OCXO PP1S signal by the EPLD frequency divider within the GNSS clock processing module and then sent to the EPLD phase detector module. The EPLD phase detector module performs phase detection on the OCXO PP1S and GPS PP1S signals, generating a phase lead or lag flag and calculating the difference between the two signals. This difference is then sent to the CPU. The CPU processes the difference and controls the DAC to output the corresponding voltage value, adjusting the frequency output of the OCXO clock source.
[0042] Another 10MHz signal output from the OCXO clock source enters the PLL. After frequency multiplication by the PLL, multiple clock signals are output. One clock signal is connected to the EPLD phase detector module as the phase detector clock for the EPLD phase detector module. The other clock signal is divided by the EPLD frequency divider module in the synchronous code stream timing module to obtain a 40ms signal and sent to the SSC module for synchronous code stream timing output. The PP1S signal is sent from the EPLD phase detector module to the EPLD frequency divider module in the synchronous code stream timing module. The PP1S signal is the OCXO PP1S single pulse signal. The PP1S signal is used as the synchronous reset signal for the 40ms timing output of the synchronous code stream to clear the 40ms clock offset caused by external interference.
[0043] In further preferred embodiments, some implementations of the method of the present invention can be referenced. For example, the base station GNSS clock synchronization system improved by the method of the present invention includes a GNSS clock processing module and a synchronization code stream timing module.
[0044] The GNSS clock processing module includes a GNSS receiver module, an EPLD phase detector module, a CPU, a DAC, an OCXO clock source, and an EPLD frequency divider module.
[0045] The synchronous code stream timing module includes a PLL, an EPLD frequency division module, and an SCC module, as referenced. Figure 1 ,
[0046] The GNSS receiver module receives GPS satellite signals through an SMA antenna and outputs GPS PP1S signals. It communicates with the CPU through a UART interface, through which the CPU initializes and configures the GNSS receiver module and reads relevant signals.
[0047] The OCXO clock source outputs a high-precision 10MHz signal. After passing through a 1-to-4 clock buffer, one 10MHz signal is output to the PLL for use in the synchronization code stream timing module. The other 10MHz signal is output to the EPLD frequency divider module in the GNSS clock processing module. The EPLD frequency divider module internally divides the signal to 1Hz, i.e., OCXO PP1S. Figure 1 As shown.
[0048] The OCXO PP1S and GPS PP1S signals undergo phase detection processing within the EPLD phase detection module, generating phase lead and lag flags. If the OCXO PP1S leads the GPS PP1S, the OCXO operating frequency is higher than 10MHz; if the OCXO PP1S lags the GPS PP1S, the OCXO operating frequency is lower than 10MHz. The lead and lag flags can be reset using the OCXO PP1S Middle signal. (Refer to...) Figure 2 As shown.
[0049] After the OCXO PP1S and GPS PP1S complete phase detection processing inside the EPLD phase detection module, the calculated difference DIF signal enters the CPU. The CPU first performs filtering processing, and then controls the DAC to output the corresponding voltage value through SPI write register. Based on the lead or lag situation, the frequency output of the OCXO is adjusted in time.
[0050] The 10MHz signal output from the clock buffer enters the PLL. The PLL multiplies the 10MHz signal and outputs multiple 61.44MHz clock signals. One of the 61.44MHz signals is connected to the EPLD phase detector module as the phase detection clock for the EPLD phase detector.
[0051] Another 61.44MHz signal is used for synchronization stream setting. This signal is divided by the EPLD frequency divider in the synchronization stream timing module to obtain a 40ms signal. The PP1S signal from the EPLD phase detector module is a single pulse signal from the OCXO PP1S. This signal is then fed into the 40ms EPLD frequency divider module as the synchronization reset signal for the 40ms counter. Thus, the 40ms timing signal used to generate the synchronization stream is synchronized with the OCXO's PP1S every second, periodically clearing the 40ms clock offset caused by external interference. Using this improved synchronization system, GPS deviation problems can be addressed.
[0052] Preferably, in the embodiments of the method of the present invention, the PLL can be AD9523, which has two internal phase-locked loops and outputs a 61.44MHz clock signal for synchronizing the code stream and phase detection.
[0053] The GNSS receiver module can use ublox's LEA-M8T-0 GNSS timing module, which can output time pulse frequencies from 0.25Hz to 10MHz. The time pulse accuracy is less than 20ns in Clear Sky mode and less than or equal to 500ns in Indoor mode.
[0054] The EPLD can use the LCMXO2280, which is from LatinTech's Mach XO series. It features up to 271 I / Os, sysMEM embedded block RAM, up to 7.7KB of distributed RAM, supports IEEE standard 1149.1 boundary scan, and supports operating voltages of 3.3V and 1.8V.
[0055] The OXCO clock source can be OC22L5D39-10MHz, with a voltage control range of 0-5V, an initial frequency accuracy of 0.1ppm, a frequency temperature stability of less than 3ppb, a power supply voltage frequency stability of less than 1ppb, and a load frequency stability of less than 1ppb.
[0056] The CPU can be an x86 architecture. The CPU initializes and configures the GNSS module via UART. It receives the phase-detected signal from the EPLD, filters it, and controls the output of the DAC chip via the SPI interface. The changing voltage of the DAC output controls the output frequency of the OCXO. The DAC can be a DAC8550, and the CPU adjusts its output via the SPI interface.
[0057] In the improved base station GNSS clock synchronization system of this invention, the GNSS receiving module states can be divided into STARTUP, WARMUP, FAST, LOCK, HOLDOVER, HOLDOVERTIMEOUT, and ABNORMAL. The GNSS receiving module continuously outputs PP1S. The CPU determines that the clock is available for 5 consecutive times, and the GNSS receiving module enters the FAST state from the STARTUP state. In the FAST state, if the locking condition (±10 units) is met 30 consecutive times, the GNSS receiving module enters the LOCK state; otherwise, the clock is unavailable, and the state remains in FAST. If the phase difference is too large, the EPLD phase difference is reset. In the LOCK state, if the clock is unavailable, it directly enters the HOLDOVER state; if the locking condition (±30 units) is not met for 30 consecutive times, it enters the ABNORMAL abnormal state from the LOCK state. After entering the HOLDOVER state, if the clock is available for 5 consecutive times, the phase difference is checked. If the locking condition (±10 units) is met 300 times consecutively and the clock is available, it can re-enter the LOCK state. If the clock is unavailable for more than 8 hours, it will transition from the HOLDOVER state to the HOLDOVERTIMEOUT state; a factory reset of the HOLDOVER state will return it to the initial STARTUP state. In the current HOLDOVERTIMEOUT state, if a check is performed every 10 seconds, and the clock is confirmed to be available after 6 consecutive checks, the GNSS receiver module will enter the WARMUP state. If the current ABNORMAL state is abnormal and the abnormality persists for more than 10 seconds, it will enter the WARMUP state.
[0058] The CPU can monitor the status of the GNSS receiver module at any time via the UART interface. When the GNSS receiver module is locked, it outputs stable PP1S and TOD information. Both the GPS PP1S output and the OCXO PP1S output from the PLLAD9523 enter the EPLD, where phase detection processing is performed. The processed result is then filtered by the CPU. After further processing, the CPU adjusts the DAC output via the SPI interface, and finally, the DAC adjusts the OCXO frequency output via the voltage-controlled pin. In other words, the EPLD, PD, CPU, DAC, and OCXO form a large PLL, while the digital PLLAD9523 is not involved in this large PLL. The 61.44MHz output of the digital PLLAD9523 is used for timing the synchronous code stream output, providing multiple SSC and SCK outputs to various baseband boards in the BBU, thereby ensuring clock synchronization throughout the entire base station system.
[0059] The present invention addresses the GPS deviation and phase oscillation problems of GNSS clocks in base stations by designing a solution that combines the long-term stability characteristics of GNSS and the short-term stability characteristics of OCXO through EPLD and CPU software phase detection filtering, providing a stable and reliable clock source for the entire base station equipment.
[0060] This invention also provides a base station GNSS clock synchronization system based on EPLD, the base station GNSS clock synchronization system including a GNSS clock processing module and a synchronization code stream timing module.
[0061] The GNSS clock processing module includes a GNSS receiver module, an EPLD phase detector module, a CPU, a DAC, an OCXO clock source, and an EPLD frequency divider module.
[0062] The synchronous code stream timing module includes a PLL, an EPLD frequency division module, and an SCC module.
[0063] The GNSS receiver module receives GPS satellite signals and outputs a GPS PP1S signal to the EPLD phase detector module. The OCXO clock source outputs two 10MHz signals. One of these 10MHz signals is divided into an OCXO PP1S signal by the EPLD frequency divider within the GNSS clock processing module and then sent to the EPLD phase detector module. The EPLD phase detector module performs phase detection processing on the OCXO PP1S signal and the GPS PP1S signal, generating a phase lead or lag flag and calculating the difference between the OCXO PP1S and GPS PP1S signals. The EPLD phase detector module sends this difference value to the CPU. After processing the difference value, the CPU controls the DAC to output the corresponding voltage value, adjusting the frequency output of the OCXO clock source.
[0064] Another 10MHz signal from the OCXO clock source enters the PLL. After frequency multiplication by the PLL, multiple clock signals are output. One clock signal is connected to the EPLD phase detector module as the phase detector clock for the EPLD phase detector module. The other clock signal is divided by the EPLD frequency divider module in the synchronous code stream timing module to obtain a 40ms signal and sent to the SSC module for synchronous code stream timing output. The EPLD phase detector module sends the PP1S signal to the EPLD frequency divider module in the synchronous code stream timing module. The PP1S signal is the OCXO PP1S single pulse signal. The PP1S signal is used as the synchronous reset signal for the 40ms timing output of the synchronous code stream to clear the 40ms clock offset caused by external interference.
[0065] The information interaction and execution process between the modules in the above system are based on the same concept as the method embodiment of the present invention, and the specific details can be found in the description of the method embodiment of the present invention, and will not be repeated here.
[0066] Similarly, this invention addresses the defects of GPS deviation and phase oscillation in GNSS clocks on base stations by improving the GNSS clock synchronization system. It employs a low-cost EPLD as the phase detector and frequency divider, forming a large phase-locked loop (PLL) with the CPU, DAC, and OCXO chips. This large PLL does not contain nested smaller PLLs, preventing PLL oscillation. The PP1S signal of the EPLD phase detector is a single-pulse signal of the OCXO PP1S, which is introduced into the SSC synchronization stream module. It synchronizes with the PP1S signal of the GNSS clock processing module every second, periodically clearing clock offsets caused by external interference and resolving the GPS deviation problem. This base station GNSS clock synchronization also combines the long-term stability characteristics of GNSS with the short-term stability characteristics of OCXO, providing a stable and reliable clock source for the entire base station equipment.
[0067] It should be noted that not all steps and modules in the above processes and system structures are mandatory; some steps or modules can be omitted as needed. The execution order of the steps is not fixed and can be adjusted as required. The system structures described in the above embodiments can be physical or logical structures. That is, some modules may be implemented by the same physical entity, or some modules may be implemented by multiple physical entities, or they may be implemented by certain components in multiple independent devices.
[0068] The above-described embodiments are merely preferred embodiments provided to fully illustrate the present invention, and the scope of protection of the present invention is not limited thereto. Equivalent substitutions or modifications made by those skilled in the art based on the present invention are all within the scope of protection of the present invention. The scope of protection of the present invention is defined by the claims.
Claims
1. A base station GNSS clock synchronization method based on EPLD, characterized in that: Clock synchronization is achieved using a base station GNSS clock synchronization system, which includes a GNSS clock processing module and a synchronization code stream timing module. The GNSS clock processing module includes a GNSS receiver module, an EPLD phase detector module, a CPU, a DAC, an OCXO clock source, and an EPLD frequency divider module. The synchronous code stream timing module includes a PLL, an EPLD frequency division module, and an SSC module. The GNSS receiver module receives GPS satellite signals and outputs a GPS PP1S signal to the EPLD phase detector module. The OCXO clock source outputs two 10MHz signals. One of these 10MHz signals is divided into an OCXO PP1S signal by the EPLD frequency divider within the GNSS clock processing module and then sent to the EPLD phase detector module. The EPLD phase detector module performs phase detection on the OCXO PP1S and GPS PP1S signals, generating a phase lead or lag flag and calculating the difference between the two signals. This difference is then sent to the CPU. The CPU processes the difference and controls the DAC to output the corresponding voltage value, adjusting the frequency output of the OCXO clock source. Another 10MHz signal output from the OCXO clock source enters the PLL. After frequency multiplication by the PLL, multiple clock signals are output. One clock signal is connected to the EPLD phase detector module as the phase detector clock for the EPLD phase detector module. The other clock signal is divided by the EPLD frequency divider module in the synchronous code stream timing module to obtain a 40ms signal and sent to the SSC module for synchronous code stream timing output. The PP1S signal is sent from the EPLD phase detector module to the EPLD frequency divider module in the synchronous code stream timing module. The PP1S signal sent by the EPLD phase detector module is a single pulse signal of OCXO PP1S. The PP1S signal sent from the EPLD phase detector module to the EPLD frequency divider module in the synchronous code stream timing module is used as the synchronous reset signal for the 40ms timing output of the synchronous code stream, which is used to clear the 40ms clock offset caused by external interference.
2. The GNSS clock synchronization method for a base station based on EPLD according to claim 1, characterized in that: The step of performing phase detection processing on the OCXO PP1S signal and the GPS PP1S signal through the EPLD phase detection module to generate a phase lead or lag indicator includes: If a phase lead flag is generated, the OCXO PP1S signal leads the GPS PP1S signal, indicating that the OCXO clock source operates at a frequency higher than 10MHz. If a phase lag flag is generated, the OCXO PP1S signal lags behind the GPS PP1S signal, indicating that the OCXO clock source operates at a frequency lower than 10MHz.
3. A GNSS clock synchronization method for a base station based on EPLD according to claim 1 or 2, characterized in that: The process of controlling the DAC to output a corresponding voltage value after processing the difference via the CPU, and adjusting the frequency output of the OCXO clock source, includes: The CPU filters the difference, and then uses the processed difference to control the DAC to output the corresponding voltage value through the SPI register, thereby adjusting the frequency output of the OCXO clock source.
4. The GNSS clock synchronization method for a base station based on EPLD according to claim 1, characterized in that: The GNSS receiver module uses an SMA antenna to receive GPS satellite signals and outputs GPS PP1S signals. The CPU uses the UART interface to initialize and configure the GNSS receiver module and read relevant signals.
5. A GNSS clock synchronization method for a base station based on EPLD according to claim 1, characterized in that: The PLL is an AD9523, which has two internal phase-locked loops and outputs a 61.44MHz clock signal for synchronizing the code stream and phase detection.
6. A base station GNSS clock synchronization system based on EPLD, characterized in that: The base station GNSS clock synchronization system includes a GNSS clock processing module and a synchronization code stream timing module. The GNSS clock processing module includes a GNSS receiver module, an EPLD phase detector module, a CPU, a DAC, an OCXO clock source, and an EPLD frequency divider module. The synchronous code stream timing module includes a PLL, an EPLD frequency division module, and an SSC module. The GNSS receiver module receives GPS satellite signals and outputs a GPS PP1S signal to the EPLD phase detector module. The OCXO clock source outputs two 10MHz signals. One of these 10MHz signals is divided into an OCXO PP1S signal by the EPLD frequency divider within the GNSS clock processing module and then sent to the EPLD phase detector module. The EPLD phase detector module performs phase detection processing on the OCXO PP1S signal and the GPS PP1S signal, generating a phase lead or lag flag and calculating the difference between the OCXO PP1S and GPS PP1S signals. The EPLD phase detector module sends this difference value to the CPU. After processing the difference value, the CPU controls the DAC to output the corresponding voltage value, adjusting the frequency output of the OCXO clock source. Another 10MHz signal from the OCXO clock source enters the PLL. After frequency multiplication by the PLL, multiple clock signals are output. One clock signal is connected to the EPLD phase detector module as the phase detector clock for the EPLD phase detector module. The other clock signal is divided by the EPLD frequency divider module in the synchronous code stream timing module to obtain a 40ms signal and sent to the SSC module for synchronous code stream timing output. The EPLD phase detector module sends a PP1S signal to the EPLD frequency divider module in the synchronous code stream timing module. The PP1S signal sent by the EPLD phase detector module is a single pulse signal of OCXO PP1S. The PP1S signal sent by the EPLD phase detector module to the EPLD frequency divider module in the synchronous code stream timing module is used as the synchronous reset signal for the 40ms timing output of the synchronous code stream, which is used to clear the 40ms clock offset caused by external interference.
7. A GNSS clock synchronization system for a base station based on an EPLD according to claim 6, characterized in that: The EPLD phase detection module performs phase detection processing on the OCXO PP1S signal and the GPS PP1S signal to generate a phase lead or lag indicator, including: If a phase lead flag is generated, the OCXO PP1S signal leads the GPS PP1S signal, indicating that the OCXO clock source operates at a frequency higher than 10MHz. If a phase lag flag is generated, the OCXO PP1S signal lags behind the GPS PP1S signal, indicating that the OCXO clock source operates at a frequency lower than 10MHz.
8. A base station GNSS clock synchronization system based on EPLD according to claim 6 or 7, characterized in that: After processing the difference, the CPU controls the DAC to output a corresponding voltage value, adjusting the frequency output of the OCXO clock source, including: The CPU filters the difference, and then uses the processed difference to control the DAC to output the corresponding voltage value through the SPI register, thereby adjusting the frequency output of the OCXO clock source.
9. A base station GNSS clock synchronization system based on EPLD according to claim 6, characterized in that GNSS The receiver module uses an SMA antenna to receive GPS satellite signals and outputs GPS PP1S signals. The CPU uses the UART interface to initialize and configure the GNSS receiver module and read relevant signals.
10. A base station GNSS clock synchronization system based on EPLD according to claim 6, characterized in that: The PLL is an AD9523, which has two internal phase-locked loops and outputs a 61.44MHz clock signal for synchronizing the code stream and phase detection.