A base station GNSS clock synchronization method and system based on EPLD

By using a large phase-locked loop composed of an EPLD phase detector module and a CPU, combined with the characteristics of GNSS and OCXO, the problems of GPS deviation and phase difference oscillation in base stations were solved, achieving stable clock synchronization of base station equipment and reducing costs.

CN116033539BActive Publication Date: 2026-06-09SHANDONG INSPUR SCI RES INST CO LTD
2 Cites 0 Cited by

Patent Information

Application Number
CN202211130831.1
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2022-09-16
Publication Date
2026-06-09
Estimated Expiration
2042-09-16

AI Technical Summary

Technical Problem

Existing GNSS clock synchronization systems suffer from GPS deviation and phase oscillation issues in base stations, leading to mutual interference between base stations, which is difficult to effectively resolve with current technologies.

Method used

An EPLD-based base station GNSS clock synchronization method is adopted. By using a large phase-locked loop composed of an EPLD phase detection module and a CPU, the clock offset caused by external interference is eliminated through phase detection processing and voltage adjustment, combined with the long-term stability characteristics of GNSS and the short-term stability characteristics of OCXO.

Benefits of technology

It achieves stable and reliable clock synchronization for base station equipment, solves GPS deviation and phase oscillation problems, provides a stable clock source, and reduces costs.

✦ Generated by Eureka AI based on patent content.
Patent Text Reader

Abstract

The application discloses a base station GNSS clock synchronization method and system based on EPLD, and relates to the technical field of signal synchronization; in view of defects such as GPS run-off and phase difference oscillation of a GNSS clock on a base station, the GNSS clock synchronization system is improved, a low-cost EPLD is used as a phase detector and a frequency divider, and a CPU, a DAC and an OCXO chip are combined to form a large phase-locked loop, the large phase-locked loop does not have a small phase-locked loop nested therein, and thus cannot cause phase-locked loop oscillation; a single pulse signal of an OCXO PP1S of the EPLD phase detector is introduced into an SSC synchronization code stream module, and the single pulse signal is synchronized with a PP1S of a GNSS clock processing module every second; clock offset caused by external interference is removed in a timely manner, and the GPS run-off problem is solved; the base station GNSS clock synchronization also combines the long stabilization characteristic of the GNSS and the short stabilization characteristic of the OCXO, and provides a stable and reliable clock source for the entire base station equipment.
Need to check novelty before this filing date? Find Prior Art