Semiconductor structure and method for manufacturing the same

Abstract

The present invention relates to the field of semiconductors and provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure comprises: a substrate including spaced-apart bit lines and semiconductor channels, wherein the bit lines extend along a first direction, the semiconductor channels are located on a portion of the top surface of the bit lines, and in a direction perpendicular to the top surface of the bit lines, the semiconductor channels include a first region, a second region, and a third region arranged sequentially; a dielectric layer located between adjacent bit lines and on the surface of the semiconductor channels; a first gate layer surrounding the dielectric layer in the second region and extending in a second direction, the first direction being different from the second direction; a second gate layer surrounding the dielectric layer in the third region, the second gate layer being spaced apart from the first gate layer in a direction perpendicular to the top surface of the bit lines; and an insulating layer located between adjacent semiconductor channels on the same bit line and isolating the first gate layer from the second gate layer located on the adjacent dielectric layers. The present invention can at least improve the electrical performance of the semiconductor structure.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductors, and in particular to a semiconductor structure and a method for manufacturing the same. Background Art

[0002] As the integration density of dynamic memory develops towards a higher direction, while studying the arrangement of transistors in the dynamic memory array structure and how to reduce the size of individual functional devices in the dynamic memory array structure, it is also necessary to consider the impact of small-sized functional devices on the overall electrical performance of the semiconductor structure.

[0003] When a vertical gate-all-around (GAA) transistor structure is used as a dynamic memory select transistor (access transistor), the area occupied by it can reach 4F. 2 (F: the minimum pattern size obtainable under given process conditions). In principle, higher density efficiency can be achieved. However, due to the small spacing between adjacent small-sized functional devices, the interaction effect between adjacent functional devices is difficult to control, which will affect the overall electrical performance of the semiconductor structure. Summary of the Invention

[0004] The embodiments of the present application provide a semiconductor structure and a method for manufacturing the same, which are at least beneficial to improving the electrical performance of the semiconductor structure.

[0005] According to some embodiments of the present application, on one hand, an embodiment of the present application provides a semiconductor structure, comprising: a substrate, the substrate comprising bit lines and semiconductor channels arranged at intervals, the bit lines extending along a first direction, the semiconductor channels being located on a portion of a top surface of the bit lines, and in a direction perpendicular to the top surface of the bit lines, the semiconductor channels comprising a first region, a second region, and a third region arranged in sequence; a dielectric layer located between adjacent bit lines and located on a surface of the semiconductor channel; a first gate layer surrounding the dielectric layer in the second region and extending along a second direction, the first direction being different from the second direction; a second gate layer surrounding the dielectric layer in the third region, the second gate layer being spaced apart from the first gate layer in a direction perpendicular to the top surface of the bit lines; an insulating layer located between adjacent semiconductor channels on the same bit line and isolating the first gate layer and the second gate layer located on adjacent dielectric layers.

[0006] In some embodiments, in a plane perpendicular to the sidewall of the semiconductor channel, the semiconductor channel surrounded by the first gate layer has a first cross-section, and the semiconductor channel surrounded by the second gate layer has a second cross-section, and the area of the first cross-section is greater than the area of the second cross-section.

[0007] In some embodiments, in a direction from the bit line to the semiconductor channel, a length of the first gate layer is greater than a length of the second gate layer.

[0008] In some embodiments, in a direction perpendicular to a sidewall of the semiconductor channel, a thickness of the first gate layer is greater than a thickness of the second gate layer.

[0009] In some embodiments, a single first gate layer extends along the second direction and surrounds adjacent semiconductor channels on adjacent bit lines, and a single second gate layer surrounds only a single semiconductor channel.

[0010] In some embodiments, the second gate layer includes at least one of lanthanide elements and / or zirconium.

[0011] In some embodiments, the semiconductor structure further includes: an electrical contact structure located on a surface of the second gate layer away from the substrate, and on a surface of the dielectric layer located in a portion of the third region.

[0012] In some embodiments, the semiconductor structure further includes: a metal-semiconductor compound structure, located at least in the bit line facing the bottom surface of the insulating layer.

[0013] In some embodiments, the depth of the metal-semiconductor compound structure gradually increases along the direction from the semiconductor channels located on both sides of the insulating layer to the insulating layer.

[0014] In some embodiments, in a plane perpendicular to a sidewall of the semiconductor channel, cross-sectional areas of the semiconductor channel in the first region, the second region, and the third region decrease in sequence.

[0015] In some embodiments, the dielectric layer includes: a first dielectric layer located between adjacent bit lines and between the semiconductor channels in the first region on adjacent bit lines; a second dielectric layer located on the sidewalls of the semiconductor channels in the first region and the sidewalls of the first dielectric layer in the first region; a third dielectric layer surrounding the sidewalls of the semiconductor channels in the second region; and a fourth dielectric layer surrounding the sidewalls of the semiconductor channels in the third region and located on the top surface of the semiconductor channels.

[0016] In some embodiments, the first gate layer is located at least partially on the top surface of the first dielectric layer and the second dielectric layer, and the second gate layer is located at least partially on the top surface of the third dielectric layer.

[0017] In some embodiments, the insulating layer includes: a first insulating layer, located between the dielectric layers and the first gate layers of adjacent semiconductor channels, and extending along the second direction, and the top surface of the first insulating layer is not lower than the top surface of the third region; a second insulating layer, located on the top surface of the first gate layer, and located between the first insulating layer and the second gate layer; a third insulating layer, located on the top surface of the second gate layer, and located between the second insulating layer and the dielectric layer.

[0018] According to some embodiments of the present application, on the other hand, embodiments of the present application further provide a method for manufacturing a semiconductor structure, comprising: providing a substrate, the substrate comprising bit lines and semiconductor channels arranged at intervals, the bit lines extending along a first direction, the semiconductor channels being located on a portion of a top surface of the bit lines, and in a direction perpendicular to the top surface of the bit lines, the semiconductor channels comprising a first region, a second region, and a third region arranged in sequence; forming a dielectric layer, the dielectric layer being located between adjacent bit lines and on a surface of the semiconductor channel; forming a first gate layer, the first gate layer surrounding the dielectric layer in the second region; forming a second gate layer, the second gate layer surrounding the dielectric layer in the third region, and in a direction perpendicular to the top surface of the bit lines, the second gate layer and the first gate layer are spaced apart; forming an insulating layer, the insulating layer being located between adjacent semiconductor channels on the same bit line.

[0019] In some embodiments, the step of providing a substrate includes: providing an initial substrate, wherein the initial substrate has an initial first dielectric layer extending along the first direction; patterning the initial substrate and the initial first dielectric layer to form the bit lines and the semiconductor channels arranged at intervals, and the initial first dielectric layer located between adjacent bit lines, wherein the top surface of the initial first dielectric layer is not lower than the top surface of the semiconductor channel, and the sidewalls of the semiconductor channel, the sidewalls of the initial first dielectric layer, and a portion of the top surface of the bit line form a trench, and the trench extends along the second direction.

[0020] In some embodiments, the steps of forming the dielectric layer, the first gate layer, the second gate layer, and the insulating layer include: forming a first dielectric layer between adjacent bit lines and between the semiconductor channels in the first region on adjacent bit lines, and forming a second dielectric layer on the sidewalls of the trench in the first region; forming a first insulating layer, the first insulating layer being located in the trench and isolating the adjacent second dielectric layer, the top surface of the first insulating layer being no lower than the top surface of the semiconductor channel; forming a third dielectric layer and the first gate layer on the sidewalls of the trench in the second region, the top surface of the third dielectric layer being higher than the top surface of the first gate layer; forming a second insulating layer, the second insulating layer being located between the first insulating layer and the third dielectric layer; forming a fourth dielectric layer and the second gate layer on the sidewalls of the trench in the third region, the top surface of the fourth dielectric layer being higher than the top surface of the second gate layer; forming a third insulating layer, the third insulating layer being located between the second insulating layer and the fourth dielectric layer, the first dielectric layer, the second dielectric layer, the third dielectric layer, and the fourth dielectric layer together constituting the dielectric layer; and the first insulating layer, the second insulating layer, and the third insulating layer together constituting the insulating layer.

[0021] In some embodiments, the steps of forming the first dielectric layer, the second dielectric layer, and the first insulating layer include: forming an initial second dielectric layer on the sidewall of the trench, with a first gap between adjacent initial second dielectric layers; forming the first insulating layer in the first gap; and etching the initial first dielectric layer and the initial second dielectric layer using the first insulating layer as a mask to form the first dielectric layer and the second dielectric layer.

[0022] In some embodiments, before forming the first insulating layer and after forming the initial second dielectric layer, a metal silicide treatment is performed on a portion of the top surface of the bit line exposed by the initial second dielectric layer to form a metal semiconductor compound structure.

[0023] In some embodiments, the steps of forming the third dielectric layer, the first gate layer and the second insulating layer include: forming an initial third dielectric layer on the sidewalls of the semiconductor channel in the second region and the third region, with a second gap between the initial third dielectric layer and the first insulating layer; forming the first gate layer in part of the second gap in the second region; forming the second insulating layer in the remaining second gap; and etching the initial third dielectric layer using the second insulating layer as a mask to form the third dielectric layer.

[0024] In some embodiments, the steps of forming the fourth dielectric layer, the second gate layer and the third insulating layer include: forming a fourth dielectric layer on the sidewall of the third region, with a third gap between the fourth dielectric layer and the second insulating layer; forming the second gate layer in part of the third gap; and forming the third insulating layer in the remaining third gap.

[0025] In some embodiments, after forming the second gate layer and before forming the third insulating layer, the method further includes: doping the second gate layer with at least one of lanthanide elements and / or zirconium.

[0026] In some embodiments, the preparation method further includes forming an electrical contact structure, wherein the step of forming the electrical contact structure includes: patterning the insulating layer to expose the second gate layer and forming a through hole; and forming the electrical contact structure in the through hole.

[0027] The technical solution provided by the embodiments of the present application has at least the following advantages:

[0028] In the above technical solution, a vertical GAA transistor is formed in the substrate, and the bit line is buried in the substrate and located below the semiconductor channel, thereby forming a 3D stacked semiconductor structure, and the transistor reaches 4F 2 The arrangement is designed to improve the integration density of the semiconductor structure. In addition, the first gate layer and the second gate layer are designed to control the same semiconductor channel respectively, so that the control capabilities of the first gate layer and the second gate layer over the semiconductor channel complement each other. When the control capability of one gate layer over the semiconductor channel is low, which may cause excessive leakage current, the control capability of the other gate layer over the semiconductor channel compensates for the deficiency. This helps to ensure that the first gate layer and the second gate layer have good control capabilities over the semiconductor channel as a whole, thereby helping to reduce leakage current in the semiconductor structure and improve the overall electrical performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] One or more embodiments are exemplarily described by the pictures in the corresponding drawings. These exemplifications do not constitute limitations on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute proportional limitations.

[0030] Figures 1 to 18 This is a schematic diagram of the cross-sectional structures corresponding to each step in the method for manufacturing a semiconductor structure provided in another embodiment of the present application. DETAILED DESCRIPTION

[0031] As can be seen from the background art, the electrical performance of current semiconductor structures needs to be improved.

[0032] Analysis has found that in the current GAA transistor structure, each semiconductor channel corresponds to a gate layer, and the on / off state of the semiconductor channel is controlled by applying a voltage to the gate layer. However, to achieve higher integration density, the distance between the gate electrode layer and the semiconductor layer is reduced, and the size of the gate electrode layer itself is also reduced. Both of these increase gate-induced drain leakage (GIDL) and reduce the on / off ratio of the semiconductor channel, making it difficult for the gate electrode layer to control the off state of the semiconductor channel, thereby reducing the electrical performance of the semiconductor structure.

[0033] The present application provides a semiconductor structure and a method for manufacturing the same. In the semiconductor structure, a first gate layer and a second gate layer correspond to the same semiconductor channel and respectively control the semiconductor channel, so that the control capabilities of the first gate layer and the second gate layer over the semiconductor channel complement each other, which is beneficial to ensuring that the first gate layer and the second gate layer have good control capabilities over the semiconductor channel as a whole, thereby facilitating the reduction of GIDL in the semiconductor structure. By adjusting the voltage applied to the first gate layer and the second gate layer, the on / off ratio of the semiconductor channel is increased, thereby improving the overall sensitivity of controlling the on / off of the semiconductor channel, thereby facilitating the improvement of the overall electrical performance of the semiconductor structure.

[0034] The following detailed description of the various embodiments of the present application is provided in conjunction with the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present application to facilitate a better understanding of the present application. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present application can still be implemented.

[0035] An embodiment of the present application provides a semiconductor structure, which will be described in detail below with reference to the accompanying drawings. Figures 1 to 4 This is a schematic diagram of the structure corresponding to the semiconductor structure provided in one embodiment of the present application. Figure 1 A schematic top view of a semiconductor structure provided in one embodiment of the present application is shown. Figure 2 for Figure 1 The schematic cross-sectional view of the semiconductor structure shown is along the first cross-sectional direction AA1. Figure 3 for Figure 1 The schematic cross-sectional view of the semiconductor structure shown is along the second cross-sectional direction BB1. Figure 4 It is a cross-sectional schematic diagram of a semiconductor structure in which a first gate layer surrounds a semiconductor channel and a second gate layer surrounds a semiconductor channel.

[0036] refer to Figures 1 to 4The semiconductor structure includes: a substrate 100 including bit lines 101 and semiconductor channels 102 arranged at intervals, wherein the bit lines 101 extend along a first direction X, and the semiconductor channels 102 are located on a portion of a top surface of the bit lines 101. In a direction Z perpendicular to the top surface of the bit lines 101, the semiconductor channels 102 include a first region I, a second region II, and a third region III arranged in sequence; a dielectric layer 103 located between adjacent bit lines 101 and on a surface of the semiconductor channels 102; a first gate layer 104 surrounding the dielectric layer 103 in the second region II and extending along a second direction Y, wherein the first direction X is different from the second direction Y; a second gate layer 105 surrounding the dielectric layer 103 in the third region III and spaced apart from the first gate layer 104 in a direction perpendicular to the top surface of the bit lines 101; and an insulating layer 106 located between adjacent semiconductor channels 102 on the same bit line 101 and isolating the first gate layer 104 from the second gate layer 105 located on adjacent dielectric layers 103.

[0037] Among them, the semiconductor channel 102, the dielectric layer 103 surrounding the sidewalls of the semiconductor channel 102, the first gate layer 104 and the second gate layer 105 constitute a vertical GAA transistor. The base 100 includes a substrate 110, and the bit line 101 is located between the substrate 110 and the GAA transistor, thereby forming a 3D stacked semiconductor structure, which is beneficial to improving the integration density of the semiconductor structure.

[0038] It should be noted that the first region I and the third region III can both serve as the source or drain of the GAA transistor, and the first gate layer 104 and the second gate layer 105 are both used to control the on or off state of the GAA transistor.

[0039] In some embodiments, continue to refer to Figure 1 , the first direction X is perpendicular to the second direction Y, so that the semiconductor channel 102 presents a 4F 2 (F: the minimum pattern size obtainable under given process conditions) arrangement is beneficial to improving the integration density of the semiconductor structure. In other embodiments, the first direction and the second direction intersect, and the angle between the two directions may not be 90°.

[0040] It should be noted that the substrate 100 has a plurality of bit lines 101 arranged at intervals, and each bit line 101 may be in contact with at least one first region I. Figure 2 In the figure, four mutually spaced bit lines 101 and each bit line 101 in contact with four first regions I are taken as an example. In actual applications, the number of bit lines 101 and the number of first regions I in contact with each bit line 101 can be reasonably set according to electrical requirements.

[0041] The following will be combined Figures 1 to 4 The semiconductor structure is described in more detail.

[0042] In some embodiments, the substrate 100 may be made of an elemental semiconductor material or a crystalline inorganic compound semiconductor material. The elemental semiconductor material may be silicon or germanium; the crystalline inorganic compound semiconductor material may be silicon carbide, silicon germanium, gallium arsenide, or indium gallium.

[0043] In some embodiments, the substrate 100 includes a bit line 101 and a semiconductor channel 102, and the substrate 100, the bit line 101, and the semiconductor channel 102 may have the same semiconductor element. The semiconductor channel 102 and the bit line 101 may be formed using the same film layer structure. The film layer structure is composed of semiconductor elements, so that the semiconductor channel 102 and the bit line 101 are an integrated structure, thereby improving the interface state defects between the semiconductor channel 102 and the bit line 101 and improving the electrical performance of the semiconductor structure.

[0044] The semiconductor element may include at least one of silicon, carbon, germanium, arsenic, gallium, and indium. The following description will be given exemplarily assuming that both the bit line 101 and the semiconductor channel 102 include silicon.

[0045] In some embodiments, the semiconductor structure may further include: a metal-semiconductor compound structure 111 , located at least in the bit line 101 facing the bottom surface of the insulating layer 106 .

[0046] The metal-semiconductor compound structure 111 has a relatively low resistivity compared to unmetallized semiconductor materials. Therefore, the bit line 101 including the metal-semiconductor compound structure 111 has a lower resistivity than the semiconductor channel 102. This helps reduce the resistance of the bit line 101 itself and the contact resistance between the bit line 101 and the semiconductor channel 102 in the first region I, further improving the electrical performance of the semiconductor structure. Furthermore, the resistivity of the bit line 101 is also lower than that of the substrate 110.

[0047] It should be noted that, in some embodiments, the material of the region of the bit line 101 located directly below the first region I may be a semiconductor material, and the material of the portion of the bit line 101 not covered by the first region I may be a metal-semiconductor compound. It is understood that as device dimensions continue to shrink or manufacturing process parameters are adjusted, the material of the portion of the bit line 101 located directly below the first region I may be a semiconductor material, and the material of the remaining portion of the bit line 101 located directly below the first region I may also be a metal-semiconductor compound, with the "remaining portion" herein being located outside the "partial portion."

[0048] For example, reference Figure 2The multiple metal-semiconductor compound structures 111 in the bit line 101 are interconnected to form a portion of the bit line 101, and the metal-semiconductor compound structure 111 may be partially located in the bit line 101 and partially located in the semiconductor channel 102 of the first region I. In other embodiments, the multiple metal-semiconductor compound structures in the same bit line may be spaced apart from each other.

[0049] Figure 2 The area of substrate 100 defined by the dotted-line frame, which is similar to an oval, is the metal-semiconductor compound structure 111. In practical applications, there is no limitation on the size of the contact area between adjacent metal-semiconductor compound structures 111. In other embodiments, the entire thickness of the bit line may be a metal-semiconductor compound structure 111.

[0050] In some embodiments, continue to refer to Figure 2 For a single metal semiconductor compound structure 111 , the depth of the metal semiconductor compound structure 111 gradually increases along the direction from the semiconductor channels 102 located on both sides of the insulating layer 106 to the insulating layer 106 , ie, along the directions C1 and C2 .

[0051] Taking silicon as the semiconductor element as an example, the material of the metal-semiconductor compound structure 111 includes at least one of cobalt silicide, nickel silicide, molybdenum silicide, titanium silicide, tungsten silicide, tantalum silicide or platinum silicide.

[0052] In some embodiments, the semiconductor channel 102 may contain a dopant element to improve the conductivity of the semiconductor channel 102, thereby reducing the on-state voltage between the first region I and the third region III, that is, reducing the on-state voltage between the source and drain of the GAA transistor. The dopant element may be a P-type dopant element or an N-type dopant element. Specifically, the N-type dopant element may be at least one of arsenic, phosphorus, or antimony; the P-type dopant element may be at least one of boron, indium, or gallium.

[0053] In some embodiments, the GAA transistor can be a junctionless transistor, meaning that the doping elements in the first region I, second region II, and third region III are of the same type. "Junctionless" refers to the absence of a PN junction, meaning that the doping concentrations of the doping elements in the first region I, second region II, and third region III are the same. This has the following advantages: Firstly, no additional doping is required in the first region I and third region III, thereby avoiding the difficulty in controlling the doping process for the first region I and third region III. This is especially true as transistor dimensions continue to shrink, as additional doping in the first region I and third region III makes doping concentration control even more difficult. Secondly, since the device is a junctionless transistor, it avoids the use of ultra-steep source-drain concentration gradient doping processes, which would create ultra-steep PN junctions at the nanometer scale. This avoids problems such as threshold voltage drift and increased leakage current caused by doping mutations, and helps suppress short channel effects, thereby further improving the integration density and electrical performance of the semiconductor structure. It should be understood that the additional doping here refers to doping performed to make the doping element type in the first region I and third region III different from the doping element type in the second region II.

[0054] Continue to refer Figure 2 and Figure 3 In a plane perpendicular to the sidewalls of the semiconductor channel 102, the semiconductor channel 102 surrounded by the first gate layer 104 has a first cross-section, and the semiconductor channel 102 surrounded by the second gate layer 105 has a second cross-section, with the area of the first cross-section being greater than the area of the second cross-section. This reduces the cross-sectional area of the semiconductor channel 102 surrounded by the second gate layer 105, which improves the second gate layer 105's ability to control the semiconductor channel 102. Specifically, the required threshold voltage is reduced, making it easier to control the on / off state of the GAA transistor. This also helps compensate for the instability of the first gate layer 104's ability to control the semiconductor channel 102 by adjusting the second gate layer 105's ability to control the semiconductor channel 102, thereby ensuring good overall control over the semiconductor channel 102 and improving the overall electrical performance of the semiconductor structure.

[0055] In addition, the control capabilities of the first gate layer 104 and the second gate layer 105 over the semiconductor channel 102 complement each other. If one of the gate layers lacks the ability to shut off the semiconductor channel 102, a large leakage current will be caused. For example, during GIDL, the other gate layer is improved to achieve the shutdown of the semiconductor channel 102, thereby ensuring that the first gate layer 104 and the second gate layer 105 have good control capabilities over the semiconductor channel 102 as a whole, which is beneficial to reducing the leakage current in the semiconductor structure and improving the overall electrical performance of the semiconductor structure.

[0056] The ratio of the area of the first cross section to the area of the second cross section may be 1.5 to 2.5.

[0057] In some embodiments, in a plane perpendicular to the sidewall of the semiconductor channel 102 , the cross-sectional areas of the semiconductor channel 102 in the first region I, the second region II, and the third region III may decrease sequentially.

[0058] Continue to refer Figure 2 and Figure 3 The dielectric layer 103 may include: a first dielectric layer 113, located between adjacent bit lines 101 and between the semiconductor channels 102 in the first region I on the adjacent bit lines 101; a second dielectric layer 123, located on the sidewalls of the semiconductor channel 102 in the first region I and the sidewalls of the first dielectric layer 113 in the first region I; a third dielectric layer 133, surrounding the sidewalls of the semiconductor channel 102 in the second region II; and a fourth dielectric layer 143, surrounding the sidewalls of the semiconductor channel 102 in the third region III and located on the top surface of the semiconductor channel 102.

[0059] The first dielectric layer 113 located between adjacent bit lines 101 is used to achieve electrical insulation between adjacent bit lines 101. The first dielectric layer 113, the second dielectric layer 123, and the insulating layer 106 located between the semiconductor channels 102 in the first region I on the adjacent bit lines 101 work together to achieve electrical insulation between the semiconductor channels 102 in the first region I spaced apart along the first direction X and / or spaced apart along the second direction Y. The third dielectric layer 133 surrounding the sidewalls of the semiconductor channels 102 in the second region II can be used to isolate the first gate layer 104 from the semiconductor channels 102 in the second region II. The fourth dielectric layer 143 and the insulating layer 106 surrounding the surfaces of the semiconductor channels 102 in the third region III work together to achieve electrical insulation between the semiconductor channels 102 in the third region III spaced apart along the first direction X and / or spaced apart along the second direction Y.

[0060] In some embodiments, the third dielectric layer 133 may also be located on a portion of the sidewall of the second dielectric layer 123 , which is beneficial to further ensure the insulation between the first gate layer 104 and the semiconductor channel 112 ; the fourth dielectric layer 143 may also be located on a portion of the sidewall of the third dielectric layer 133 , which is beneficial to further ensure the insulation between the second gate layer 105 and the semiconductor channel 112 .

[0061] In some embodiments, the material of the first dielectric layer 113, the material of the second dielectric layer 123, the material of the third dielectric layer 133, and the material of the fourth dielectric layer 143 can be the same, for example, all of which are silicon oxide; in other embodiments, the material of the first dielectric layer, the material of the second dielectric layer, the material of the third dielectric layer, and the material of the fourth dielectric layer can be different, as long as all of the four materials have good insulation effects.

[0062] In some embodiments, the cross-sectional areas of the semiconductor channel 102 in the first region I, the second region II, and the third region III decrease sequentially, such that the periphery of the orthographic projection of the fourth dielectric layer 143 on the substrate 110 is located within the periphery of the orthographic projection of the third dielectric layer 133 on the substrate 110, and the periphery of the orthographic projection of the third dielectric layer 133 on the substrate 110 is located within the periphery of the combined orthographic projections of the second dielectric layer 123 and the first dielectric layer 113 on the substrate 110. The first gate layer 104 is located at least partially on the top surface of the first dielectric layer 113 and the second dielectric layer 123, and the second gate layer 105 is located at least partially on the top surface of the third dielectric layer 133. This helps prevent the first gate layer 104 and the second gate layer 105 from being directly opposite each other in the direction z, that is, prevents the orthographic projection of the first gate layer 104 on the substrate 110 from being located within the orthographic projection of the second gate layer 105 on the substrate 110, thereby reducing mutual interference between the first gate layer 104 and the second gate layer 105.

[0063] In some embodiments, reference Figure 4 A single first gate layer 104 extends along the second direction Y and surrounds adjacent semiconductor channels 102 on adjacent bit lines 101. A single second gate layer 105 surrounds only the single semiconductor channel 102. The outer periphery of the orthographic projection of the third dielectric layer 133 on the substrate 110 may coincide with the outer periphery of the orthographic projection of the second gate layer 105 on the substrate 110. Adjacent second gate layers 105 are separated by an insulating layer 106.

[0064] The material of the first gate layer 104 and the material of the second gate layer 105 may include at least one of polysilicon, titanium nitride, tantalum nitride, copper or tungsten.

[0065] In some embodiments, the vertical distance between the top surface of the first gate layer 104 away from the bit line 101 and the bottom surface of the second gate layer 105 close to the bit line 101 can be 20 nm to 60 nm. This helps avoid the generation of large parasitic capacitance between the first gate layer 104 and the second gate layer 105, reduces mutual interference between the first gate layer 104 and the second gate layer 105, and thus helps ensure that the first gate layer 104 and the second gate layer 105 have good control over the semiconductor channel 102.

[0066] In some embodiments, in the direction from the bit line 101 to the semiconductor channel 102, the length of the first gate layer 104 is greater than the length of the second gate layer 105. This helps ensure that the first gate layer 104 surrounds a larger area of the semiconductor channel 102, thereby improving the control capability of the first gate layer 104 over the semiconductor channel 102.

[0067] The ratio of the length of the first gate layer 104 to the length of the second gate layer 105 is 1.5-4.

[0068] In some embodiments, the thickness of the first gate layer 104 is greater than the thickness of the second gate layer 105 in a direction perpendicular to the sidewalls of the semiconductor channel 102. This helps increase the volume of the first gate layer 104 itself, thereby ensuring a lower resistance of the first gate layer 104 itself, thereby improving the control ability of the first gate layer 104 over the semiconductor channel 102.

[0069] The ratio of the thickness of the first gate layer 104 to the thickness of the second gate layer 105 is 1.2-2.

[0070] In some embodiments, the second gate layer 105 includes at least one lanthanide element and / or zirconium. This helps improve the electrical properties of the second gate layer 105 itself, thereby enhancing the second gate layer 105's ability to control the semiconductor channel 102. Furthermore, when the second gate layer 105 is smaller than the first gate layer 104, the conductivity of the second gate layer 105 can be improved by doping the second gate layer 105 with at least one lanthanide element and / or zirconium, thereby compensating for the difference in conductivity between the first and second gate layers 104, 105 due to the size difference. This reduces the difference in the control capabilities of the first and second gate layers 104, 105 over the semiconductor channel 102, thereby improving the overall stability of the semiconductor structure.

[0071] In some embodiments, the insulating layer 106 includes: a first insulating layer 116, located between the dielectric layers 103 and the first gate layer 104 of adjacent semiconductor channels 102, and extending along the second direction Y, and the top surface of the first insulating layer 116 is not lower than the top surface of the third region III; a second insulating layer 126, located on the top surface of the first gate layer 104, and located between the first insulating layer 116 and the second gate layer 105; a third insulating layer 136, located on the top surface of the second gate layer 105, and located between the second insulating layer 126 and the dielectric layer 103.

[0072] The first insulating layer 116, the second insulating layer 126, and the third insulating layer 136 work together to achieve electrical insulation between adjacent semiconductor channels 102, between adjacent first gate layers 104, and between adjacent second gate layers 105. Furthermore, the second insulating layer 126 located on top of the first gate layer 104 can achieve electrical insulation between the first gate layer 104 and other conductive structures, and the third insulating layer 136 located on top of the second gate layer 105 can achieve electrical insulation between the second gate layer 105 and other conductive structures.

[0073] In some embodiments, the material of the first insulating layer 116, the material of the second insulating layer 126, and the material of the third insulating layer 136 can be the same, for example, all are silicon nitride; in other embodiments, the material of the first insulating layer, the material of the second insulating layer, and the material of the fourth insulating layer can be different, as long as all three are materials with good insulating effects, and for the same etching process, there is a high etching selectivity ratio between the material of the insulating layer and the material of the dielectric layer.

[0074] In some embodiments, the semiconductor structure may further include an electrical contact structure 107 located on a portion of the surface of the second gate layer 105 away from the bit line 101, and on a portion of the surface of the dielectric layer 103 in the third region III. For example, the electrical contact structure 107 may be located on a portion of the top surface of the second gate layer 105 and a portion of the sidewall of the second gate layer 105 extending downward from the top surface, and may also be located on a portion of the top surface of the fourth dielectric layer 143 and a portion of the sidewall of the fourth dielectric layer 143 extending downward from the top surface.

[0075] The electrical contact structure 107 is used to control the potential of the second gate layer 105. In some embodiments, a voltage can be applied directly to the second gate layer 105 through the electrical contact structure 107, so that each second gate layer 105 is individually controlled. In other embodiments, a patterned conductive layer (not shown) can be formed to connect different electrical contact structures, so that different second gate layers can be controlled with the same voltage. In practical applications, this can improve electrical requirements and control the number of electrical connection structures connected to the same conductive layer.

[0076] In some embodiments, the semiconductor structure may further include: a barrier layer 108 surrounding the sidewalls of the electrical contact structure 107; and a mask layer 118 located between adjacent barrier layers 108 and covering the exposed top surfaces of the dielectric layer 103 and the insulating layer 106. The barrier layer 108 may be made of silicon oxide, and the mask layer 118 may be made of photoresist.

[0077] To summarize, the sidewalls of the same semiconductor channel 102 are surrounded by the first gate layer 104 and the second gate layer 105, so that the control capabilities of the first gate layer 104 and the second gate layer 105 over the semiconductor channel 102 complement each other. For example, when the first gate layer 104 has a low control capability over the semiconductor channel 102, which may cause excessive leakage current, the second gate layer 105 controls the semiconductor channel 102 to compensate for the deficiency, thereby ensuring that the first gate layer 104 and the second gate layer 105 have a good overall control capability over the semiconductor channel 102, which is beneficial to reducing the leakage current in the semiconductor structure and improving the overall electrical performance of the semiconductor structure.

[0078] Another embodiment of the present application further provides a method for manufacturing a semiconductor structure, which can be used to form the above-mentioned semiconductor structure.

[0079] Figures 1 to 18 This is a schematic diagram of the cross-sectional structures corresponding to each step in the manufacturing method of the semiconductor structure provided in another embodiment of the present application. The manufacturing method of the semiconductor structure provided in another embodiment of the present application will be described in detail below in conjunction with the accompanying drawings. The parts that are the same or corresponding to the above-mentioned embodiments will not be described in detail below.

[0080] It should be noted that, in order to facilitate description and clearly illustrate the steps of the semiconductor structure manufacturing method, the Figures 1 to 18 All of them are schematic diagrams of local structures of semiconductor structures.

[0081] in, Figure 6 for Figure 5 The structure shown is a cross-sectional schematic diagram along the first cross-sectional direction AA1, Figure 7 for Figure 5 The structure shown is a cross-sectional schematic diagram along the second cross-sectional direction BB1. It should be noted that one or both of the cross-sectional schematic diagrams along the first cross-sectional direction AA1 and the cross-sectional schematic diagram along the second cross-sectional direction BB1 will be provided later according to the needs of description.

[0082] refer to Figures 5 to 7 A substrate 100 is provided. The substrate 100 includes spaced bit lines 101 and semiconductor channels 102. The bit lines 101 extend along a first direction X. The semiconductor channels 102 are located on a portion of the top surface of the bit lines 101. In a direction Z perpendicular to the top surface of the bit lines 1-1, the semiconductor channels 102 include a first region I, a second region II, and a third region III arranged in sequence. A dielectric layer 103 is formed. The dielectric layer 103 is located between adjacent bit lines 101 and on a surface of the semiconductor channels 102.

[0083] It should be noted that the first region I and the third region III can both serve as the source or drain of a GAA transistor having a semiconductor channel 102 formed subsequently, part of the second region II corresponds to the first gate layer 104 of the GAA transistor formed subsequently, and part of the third region III corresponds to the second gate layer 105 of the GAA transistor formed subsequently.

[0084] In some embodiments, providing the substrate 100 may include the following steps:

[0085] An initial substrate (not shown) is provided, wherein the initial substrate has an initial first dielectric layer (not shown) extending along a first direction X; Figures 5 to 7The initial substrate and the initial first dielectric layer are patterned to form alternately arranged bit lines 101 and semiconductor channels 102, and an initial first dielectric layer 153 located between adjacent bit lines 101. The top surface of the initial first dielectric layer 153 is no lower than the top surface of the semiconductor channels 102. The sidewalls of the semiconductor channels 102, the sidewalls of the initial first dielectric layer 153, and a portion of the top surface of the bit lines 101 form a trench 109. The trench 109 extends along the second direction Y.

[0086] The initial substrate can be made of an elemental semiconductor material or a crystalline inorganic compound semiconductor material. Elemental semiconductor materials can be silicon or germanium; crystalline inorganic compound semiconductor materials can be silicon carbide, silicon germanium, gallium arsenide, or indium gallium. The initial substrate serves as the foundation for forming bit lines 101 and semiconductor channels 102. While the initial substrate and initial first dielectric layer 153 are patterned to form bit lines 101 and semiconductor channels 102, substrate 110 is also formed.

[0087] The method of patterning the initial substrate and the initial first dielectric layer includes a self-aligned quadruple patterning (SAQP) technique or a self-aligned double patterning (SADP) technique.

[0088] In some embodiments, the initial substrate may also be doped and annealed to allow the initial substrate to be doped with N-type or P-type doping elements. This helps improve the conductivity of the semiconductor channel 102 formed based on the initial substrate, thereby reducing the on-state voltage between the first region I and the third region III, that is, reducing the on-state voltage between the source and drain of the subsequently formed GAA transistor. Furthermore, doping the initial substrate with N-type or P-type doping elements helps improve the conductivity of the bit line 101 formed based on the initial substrate, thereby reducing the contact resistance between the first region I and the bit line 101, thereby improving the electrical performance of the semiconductor structure.

[0089] The doping element is a P-type doping element or an N-type doping element. Specifically, the N-type doping element may be at least one of arsenic, phosphorus or antimony; the P-type doping element may be at least one of boron, indium or gallium.

[0090] refer to Figures 8 to 18, forming a first gate layer 104, the first gate layer 104 surrounds the dielectric layer 103 in the second region II; forming a second gate layer 105, the second gate layer 105 surrounds the dielectric layer 103 in the third region III, and the second gate layer 105 is spaced apart from the first gate layer 104 in a direction Z perpendicular to the top surface of the bit line 101; and forming an insulating layer 106, the insulating layer 106 is located between adjacent semiconductor channels 102 on the same bit line 101.

[0091] In some embodiments, when the sidewalls of the semiconductor channel 102, the sidewalls of the initial first dielectric layer 153, and a portion of the top surface of the bit line 101 form a trench 109 (refer to FIG. Figure 6 ), forming the dielectric layer 103, the first gate layer 104, the second gate layer 105 and the insulating layer 106 may include the following steps:

[0092] refer to Figures 8 to 10 A first dielectric layer 113 is formed between adjacent bit lines 101 and between semiconductor channels 102 in the first region I on adjacent bit lines 101. A second dielectric layer 123 is formed on the sidewalls of the trench 109 in the first region I. A first insulating layer 116 is formed. The first insulating layer 116 is located within the trench 109 and isolates the adjacent second dielectric layer 123. The top surface of the first insulating layer 116 is not lower than the top surface of the semiconductor channel 102.

[0093] Among them, the top surface of the first insulating layer 116 is not lower than the top surface of the semiconductor channel 102, which is conducive to the subsequent formation of a second gap between the first insulating layer 116 and the semiconductor channel 102 in the second region II and the third region III. Subsequently, a first gate layer and a second gate layer with precise dimensions can be formed in the second gap by self-alignment. The first gate layer and the second gate layer with high dimensional accuracy can be formed without the need for an etching process, which is conducive to simplifying the steps of forming the first gate layer and the second gate layer. By adjusting the size of the second gap, a small-sized first gate layer and a second gate layer can be obtained.

[0094] In some embodiments, forming the first dielectric layer 113, the second dielectric layer 123, and the first insulating layer 116 may include the following steps:

[0095] refer to Figure 8 , in groove 109 (reference Figure 6 ) sidewalls, with a first gap between adjacent initial second dielectric layers 163. In some embodiments, the initial second dielectric layer 163 can be formed using the following process steps: a deposition process is performed to form a surface covering the top surface and all exposed sidewalls of the semiconductor channel 102, and also formed on the exposed top surface and sidewalls of the initial first dielectric layer 153. The material of the initial second dielectric layer 163 includes silicon oxide.

[0096] Continue to refer Figure 8 , forming a first insulating layer 116 in the first gap. In some embodiments, the first insulating layer 116 can be formed using the following process steps: forming a first insulating film covering the top surface of the initial second dielectric layer 163 and filling the first gap; performing a chemical mechanical planarization process on the first insulating film until the initial second dielectric layer 163 is exposed, and the remaining first insulating film serves as the first insulating layer 116. The material of the first insulating layer 116 includes silicon nitride.

[0097] The material of the initial first dielectric layer 153 and the material of the initial second dielectric layer 163 are the same, which facilitates the subsequent removal of part of the initial first dielectric layer 153 and part of the initial second dielectric layer 163 by the same removal step to form the second spacer.

[0098] In some embodiments, continue to refer to Figure 8 Before forming the first insulating layer 116 and after forming the initial second dielectric layer 163 , a metal silicide treatment is performed on a portion of the top surface of the bit line 101 exposed by the initial second dielectric layer 163 to form a metal semiconductor compound structure 111 .

[0099] The metal-semiconductor compound structure 111 has a relatively low resistivity compared to unmetallized semiconductor materials. Therefore, the bit line 101 including the metal-semiconductor compound structure 111 has a lower resistivity than the semiconductor channel 102. This helps reduce the resistance of the bit line 101 itself and the contact resistance between the bit line 101 and the semiconductor channel 102 in the first region I, further improving the electrical performance of the semiconductor structure.

[0100] In some embodiments, the step of performing a metal silicide process on the portion of the top surface of the bit line 101 exposed by the initial second dielectric layer 163 may include forming a metal layer (not shown) on the exposed top surface of the bit line 101, wherein the metal layer provides metal elements for the metal-semiconductor compound structure 111. The material of the metal layer includes at least one of cobalt, nickel, molybdenum, titanium, tungsten, tantalum, or platinum.

[0101] In other embodiments, the metal silicide treatment may not be performed on the exposed top surface of the bit line, and the first insulating layer may be directly formed on the exposed top surface of the bit line.

[0102] Then, combined with the reference Figure 8 and Figures 9 and 10 The initial first dielectric layer 153 and the initial second dielectric layer 163 are etched using the first insulating layer 116 as a mask to form the first dielectric layer 113 and the second dielectric layer 123 .

[0103] refer to Figures 11 to 18 , in the groove 109 of the second region II (refer to Figure 6) on the sidewalls of the trench 109 in the third region III, a third dielectric layer 133 and a first gate layer 104 are formed, with a top surface of the third dielectric layer 133 being higher than a top surface of the first gate layer 104; a second insulating layer 126 is formed, with the second insulating layer 126 being located between the first insulating layer 116 and the third dielectric layer 133; a fourth dielectric layer 143 and a second gate layer 105 are formed on the sidewalls of the trench 109 in the third region III, with a top surface of the fourth dielectric layer 143 being higher than a top surface of the second gate layer 105; a third insulating layer 136 is formed, with the third insulating layer 136 being located between the second insulating layer 126 and the fourth dielectric layer 143. The first dielectric layer 113, the second dielectric layer 123, the third dielectric layer 133, and the fourth dielectric layer 143 together constitute the dielectric layer 103; and the first insulating layer 116, the second insulating layer 126, and the third insulating layer 136 together constitute the insulating layer 106.

[0104] In some embodiments, forming the third dielectric layer 133 , the first gate layer 104 , and the second insulating layer 126 may include the following steps:

[0105] refer to Figures 11 to 13 An initial third dielectric layer 173 is formed on the sidewalls of the semiconductor channel 102 in the second region II and the third region III, with a second gap 129 between the initial third dielectric layer 173 and the first insulating layer 116. In some embodiments, the initial third dielectric layer 173 can be formed using the following process steps: thermally oxidizing the exposed surfaces of the semiconductor channel 102 in the second region II and the third region III to form the initial third dielectric layer 173. The material of the initial third dielectric layer 173 is silicon oxide. In other embodiments, the initial third dielectric layer covering the surfaces of the semiconductor channel in the second and third regions can also be formed using a deposition process.

[0106] refer to Figure 12 and Figure 13 , in the second interval 129 of the second zone II (reference Figure 11 ) to form a first gate layer 104. The step of forming the first gate layer 104 may include: referring to Figure 11 , forming an initial first gate layer 114, the initial first gate layer 114 fills the second spacer 129 and is located on the top surface of the initial third dielectric layer 173; Figure 12 , the sidewalls of the semiconductor channel 102 surrounding the third region III, part of the sidewalls of the semiconductor channel 102 surrounding the second region II, and the initial first gate layer 114 located on the top surface of the initial third dielectric layer 173 are etched away, and the remaining initial first gate layer 114 serves as the first gate layer 104. The first gate layer 104 only surrounds part of the sidewalls of the semiconductor channel 102 in the second region II.

[0107] refer to Figure 14, forming a second insulating layer 126 in the remaining second spacers 129. In some embodiments, the second insulating layer 126 may be formed by the following process steps: performing a deposition process to form a second insulating layer 126 that fills the remaining second spacers 129 (refer to FIG. Figure 12 ) and covering the top surface of the initial third dielectric layer 173; chemical mechanical polishing is performed on the second dielectric film and the first dielectric layer 116 until the initial third dielectric layer 173 is exposed, and the remaining second dielectric film serves as the second dielectric layer 126. The material of the second dielectric film includes silicon nitride.

[0108] Combined with reference Figure 14 and Figure 15 , the initial third dielectric layer 173 is etched using the second insulating layer 126 as a mask to form a third dielectric layer 133 .

[0109] During the step of forming the third dielectric layer 133, not only the top surface of the semiconductor channel 102 is exposed, but also the sidewalls of the semiconductor channel 102 in the third region III are exposed, preparing for the subsequent formation of the fourth dielectric layer and the second gate layer. In some embodiments, the initial third dielectric layer 173 can be etched to a depth of 10 nm to 30 nm in the direction Z.

[0110] In some embodiments, forming the fourth dielectric layer 143 , the second gate layer 105 , and the third insulating layer 136 may include the following steps:

[0111] Continue to refer Figure 15 A fourth dielectric layer 143 is formed on the sidewalls of the third region III, with a third spacer 139 between the fourth dielectric layer 143 and the second insulating layer 126. The second gate layer 105 is formed in a portion of the third spacer 139. In some examples, the fourth dielectric layer 143 is also formed on the top surface of the third region III. The fourth dielectric layer 143 can be formed using the following process steps: thermally oxidizing the surface of the semiconductor channel 102 in the third region III to form the fourth dielectric layer 143. The material of the fourth dielectric layer 143 is silicon oxide. In other embodiments, the fourth dielectric layer can also be formed by a deposition process to cover the surface of the semiconductor channel in the third region.

[0112] The step of forming the second gate layer 105 may include: forming an initial second gate layer (not shown), the initial second gate layer filling the third spacer 139 and being located on the top surface of the fourth dielectric layer 143; etching a portion of the sidewalls of the semiconductor channel 102 surrounding the third region III and the initial second gate layer located on the top surface of the fourth dielectric layer 143, and the remaining initial second gate layer serving as the second gate layer 105, where the second gate layer 105 only surrounds a portion of the sidewalls of the semiconductor channel 102 in the third region III.

[0113] refer to Figure 17 , in the remaining third interval 139 (reference Figure 15 ) to form a third insulating layer 136. In some embodiments, the third insulating layer 136 can be formed using the following process steps: performing a deposition process to form a third insulating film that fills the remaining third spacers 139 and covers the top surface of the fourth dielectric layer 143; and performing chemical mechanical polishing on the third insulating film and the first insulating layer 116 until the fourth dielectric layer 143 is exposed, with the remaining third insulating film serving as the third insulating layer 136. The material of the third insulating layer 136 can be silicon nitride.

[0114] In some embodiments, after forming the second gate layer 105 and before forming the third insulating layer 136, the manufacturing method may further include doping the second gate layer 105 with at least one lanthanide element and / or zirconium. This helps improve the electrical properties of the second gate layer 105, thereby enhancing the ability of the second gate layer 105 to control the semiconductor channel 102. Furthermore, when the second gate layer 105 is smaller than the first gate layer 104, doping the second gate layer 105 with lanthanum and / or zirconium improves the conductivity of the second gate layer 105, thereby compensating for the difference in conductivity between the first and second gate layers 104, 105 due to the size difference. This reduces the difference in the ability of the first and second gate layers 104, 105 to control the semiconductor channel 102, thereby improving the overall stability of the semiconductor structure.

[0115] The following process steps may be used to dope at least one of the lanthanide elements and / or zirconium into the second gate layer 105: Figure 16 , in the remaining third interval 139 (reference Figure 15 ) is formed in the semiconductor structure. The temperature of the environment in which the semiconductor structure is located is then increased. The metal element is doped into the second gate layer 105 by utilizing the thermal diffusion of the metal element in the diffusion layer 149. It should be noted that the doping depth of the metal element in the second gate layer 105 increases as the temperature of the environment in which the semiconductor structure is located increases. The material of the diffusion layer 149 can be at least one of a lanthanide oxide such as lanthanum oxide, scandium oxide, or cerium oxide, or zirconium oxide.

[0116] After the process of doping the second gate layer 105 with at least one of the lanthanide elements and / or zirconium is completed, the remaining diffusion layer 149 is removed to expose the second gate layer 105 in preparation for the subsequent formation of the third insulating layer 136 on the top surface of the second gate layer 105 .

[0117] In some embodiments, reference Figure 18 and Figures 1 to 4 After forming the third insulating layer 136 , the manufacturing method may further include: patterning the insulating layer 106 to expose the second gate layer 105 , and forming a through hole 159 ; and forming an electrical contact structure 108 in the through hole 159 .

[0118] In some embodiments, forming the electrical contact structure 108 may include the following steps: Figure 18 A mask layer 118 having an opening is formed on the top surface formed by the insulating layer 106 and the fourth dielectric layer 143, and part of the opening is opposite to part of the second gate layer 105 in the direction Z. Therefore, when the insulating layer 106 is etched using the mask layer 118 as a mask, part of the second gate layer 105 is exposed to form a through hole 159. Figure 2 After forming the through hole 159 and before forming the electrical contact structure 108, a barrier layer 108 may be formed on the sidewall of the through hole 159. The barrier layer 108 may be made of silicon oxide, and the mask layer 118 may be made of photoresist.

[0119] In summary, the formation of the second spacer 129 between the first insulating layer 116 and the semiconductor channel 102 in the second region II and the third region III facilitates the self-alignment formation of the first gate layer 104 and the second gate layer 105 with precise dimensions within the second spacer 129. This allows the formation of the first gate layer 104 and the second gate layer 105 with high dimensional accuracy without the need for an etching process. Furthermore, by adjusting the size of the second spacer 129, a small first gate layer 104 and the second gate layer 105 can be obtained. Furthermore, by forming the first gate layer 104 and the second gate layer 105 in different regions on the sidewall of the same semiconductor channel 102, the control capabilities of the first gate layer 104 and the second gate layer 105 over the semiconductor channel 102 complement each other, thereby ensuring that the first gate layer 104 and the second gate layer 105 have good overall control capabilities over the semiconductor channel 102, thereby facilitating the reduction of leakage current in the semiconductor structure and improving the overall electrical performance of the semiconductor structure.

[0120] Those skilled in the art will appreciate that the above-described embodiments are specific examples for implementing the present application, and that in actual applications, various changes in form and detail may be made thereto without departing from the spirit and scope of the present application. Any person skilled in the art may make changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be subject to the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that include: a substrate comprising bit lines and semiconductor channels arranged at intervals, the bit lines extending along a first direction, the semiconductor channels being located on a portion of a top surface of the bit lines, and comprising a first region, a second region, and a third region arranged in sequence in a direction perpendicular to the top surface of the bit lines; a dielectric layer, located between adjacent bit lines and on a surface of the semiconductor channel; a first gate layer surrounding the dielectric layer in the second region and extending along a second direction, wherein the first direction is different from the second direction; a second gate layer surrounding the dielectric layer in the third region, wherein the second gate layer is spaced apart from the first gate layer in a direction perpendicular to the top surface of the bit line; an insulating layer, located between adjacent semiconductor channels on the same bit line and isolating the first gate layer and the second gate layer located on adjacent dielectric layers; The single first gate layer extends along the second direction and surrounds adjacent semiconductor channels on adjacent bit lines, and the single second gate layer only surrounds a single semiconductor channel.

2. The semiconductor structure according to claim 1, wherein In a plane perpendicular to the sidewall of the semiconductor channel, the semiconductor channel surrounded by the first gate layer has a first cross-section, and the semiconductor channel surrounded by the second gate layer has a second cross-section, and an area of the first cross-section is greater than an area of the second cross-section.

3. The semiconductor structure according to claim 1, wherein: In a direction from the bit line to the semiconductor channel, the length of the first gate layer is greater than the length of the second gate layer.

4. The semiconductor structure according to claim 1, wherein: In a direction perpendicular to the sidewall of the semiconductor channel, the thickness of the first gate layer is greater than the thickness of the second gate layer.

5. The semiconductor structure according to claim 1, wherein The second gate layer includes at least one of lanthanide elements and / or zirconium.

6. The semiconductor structure according to claim 1, wherein Also includes: The electrical contact structure is located on a surface of the second gate layer away from the bit line and on a surface of the dielectric layer in a portion of the third region.

7. The semiconductor structure according to claim 1, wherein: Also includes: The metal-semiconductor compound structure is at least located in the bit line facing the bottom surface of the insulating layer.

8. The semiconductor structure according to claim 7, wherein: Along the direction from the semiconductor channels located on both sides of the insulating layer to the insulating layer, the depth of the metal-semiconductor compound structure gradually increases.

9. The semiconductor structure according to claim 1, wherein: In a plane perpendicular to the sidewall of the semiconductor channel, the cross-sectional areas of the semiconductor channel in the first region, the cross-sectional areas of the semiconductor channel in the second region, and the cross-sectional areas of the semiconductor channel in the third region decrease in sequence.

10. The semiconductor structure according to claim 9, wherein: The dielectric layer includes: A first dielectric layer is located between adjacent bit lines and between the semiconductor channels of the first region on adjacent bit lines; a second dielectric layer, located on a sidewall of the semiconductor channel in the first region and a sidewall of the first dielectric layer in the first region; a third dielectric layer surrounding the sidewalls of the semiconductor channel in the second region; The fourth dielectric layer surrounds the sidewalls of the semiconductor channel in the third region and is located on the top surface of the semiconductor channel.

11. The semiconductor structure according to claim 10, wherein: The first gate layer is located at least partially on the top surface of the first dielectric layer and the second dielectric layer, and the second gate layer is located at least partially on the top surface of the third dielectric layer.

12. The semiconductor structure according to claim 1, wherein The insulating layer comprises: a first insulating layer, located between the dielectric layers of adjacent semiconductor channels and between the first gate layer, and extending along the second direction, wherein a top surface of the first insulating layer is not lower than a top surface of the third region; a second insulating layer, located on a top surface of the first gate layer and between the first insulating layer and the second gate layer; The third insulating layer is located on the top surface of the second gate layer and between the second insulating layer and the dielectric layer.

13. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising bit lines and semiconductor channels arranged at intervals, the bit lines extending along a first direction, the semiconductor channels being located on a portion of a top surface of the bit lines, and the semiconductor channels comprising a first region, a second region, and a third region arranged in sequence in a direction perpendicular to the top surface of the bit lines; forming a dielectric layer, wherein the dielectric layer is located between adjacent bit lines and on a surface of the semiconductor channel; forming a first gate layer, wherein the first gate layer surrounds the dielectric layer in the second region and extends along a second direction, wherein the first direction is different from the second direction; forming a second gate layer, wherein the second gate layer surrounds the dielectric layer in the third region, and the second gate layer is spaced apart from the first gate layer in a direction perpendicular to the top surface of the bit line; forming an insulating layer, wherein the insulating layer is located between adjacent semiconductor channels on the same bit line; The single first gate layer extends along the second direction and surrounds adjacent semiconductor channels on adjacent bit lines, and the single second gate layer only surrounds a single semiconductor channel.

14. The manufacturing method according to claim 13, wherein: The step of providing a substrate comprises: Providing an initial substrate, wherein the initial substrate has an initial first dielectric layer extending along the first direction; The initial substrate and the initial first dielectric layer are patterned to form the spaced-apart bit lines and the semiconductor channels, and the initial first dielectric layer is located between adjacent bit lines, wherein a top surface of the initial first dielectric layer is not lower than a top surface of the semiconductor channels, and sidewalls of the semiconductor channels, sidewalls of the initial first dielectric layer, and portions of the top surfaces of the bit lines form trenches, and the trenches extend along the second direction.

15. The manufacturing method according to claim 14, wherein: The steps of forming the dielectric layer, the first gate layer, the second gate layer and the insulating layer include: forming a first dielectric layer between adjacent bit lines and between the semiconductor channels of the first region on adjacent bit lines; forming a second dielectric layer on the sidewalls of the trench in the first region; forming a first insulating layer, wherein the first insulating layer is located in the trench and isolates the adjacent second dielectric layer, and a top surface of the first insulating layer is not lower than a top surface of the semiconductor channel; forming a third dielectric layer and the first gate layer on the sidewalls of the trench in the second region, wherein a top surface of the third dielectric layer is higher than a top surface of the first gate layer; forming a second insulating layer, wherein the second insulating layer is located between the first insulating layer and the third dielectric layer; forming a fourth dielectric layer and the second gate layer on the sidewalls of the trench in the third region, wherein a top surface of the fourth dielectric layer is higher than a top surface of the second gate layer; A third insulating layer is formed, where the third insulating layer is located between the second insulating layer and the fourth dielectric layer. The first dielectric layer, the second dielectric layer, the third dielectric layer, and the fourth dielectric layer together constitute the dielectric layer. The first insulating layer, the second insulating layer, and the third insulating layer together constitute the insulating layer.

16. The manufacturing method according to claim 15, wherein the step of forming the first dielectric layer, the second dielectric layer and the first insulating layer comprises: forming an initial second dielectric layer on the sidewall of the trench, with a first gap between adjacent initial second dielectric layers; forming the first insulating layer in the first space; The initial first dielectric layer and the initial second dielectric layer are etched using the first insulating layer as a mask to form the first dielectric layer and the second dielectric layer.

17. The manufacturing method according to claim 16, wherein: Before forming the first insulating layer and after forming the initial second dielectric layer, a metal silicide treatment is performed on a portion of the top surface of the bit line exposed by the initial second dielectric layer to form a metal semiconductor compound structure.

18. The manufacturing method according to claim 15, wherein: The steps of forming the third dielectric layer, the first gate layer and the second insulating layer include: forming an initial third dielectric layer on the sidewalls of the semiconductor channel in the second region and the third region, with a second gap between the initial third dielectric layer and the first insulating layer; forming the first gate layer in a portion of the second gap in the second region; forming the second insulating layer in the remaining second spaces; The initial third dielectric layer is etched using the second insulating layer as a mask to form the third dielectric layer.

19. The manufacturing method according to claim 15, wherein: The steps of forming the fourth dielectric layer, the second gate layer and the third insulating layer include: forming a fourth dielectric layer on the sidewall of the third region, with a third gap between the fourth dielectric layer and the second insulating layer; forming the second gate layer in a portion of the third space; The third insulating layer is formed in the remaining third space.

20. The manufacturing method according to claim 19, wherein: After forming the second gate layer and before forming the third insulating layer, the method further includes: doping at least one of lanthanide elements and / or zirconium into the second gate layer.

21. The manufacturing method according to claim 14, wherein: The method further includes forming an electrical contact structure, wherein the step of forming the electrical contact structure includes: patterning the insulating layer to expose the second gate layer and forming a through hole; The electrical contact structure is formed in the through hole.

Images