Display panel and display device

Abstract

The display panel and display device provided by the embodiments of the present disclosure include: an array substrate, including: scan lines, data lines, and sub-pixels; at least two sub-pixels adjacent to each other along the first direction and the second direction constitute a pixel island; an opposing substrate; a liquid crystal layer; a supporting portion, including: a plurality of first supporting portions and a plurality of second supporting portions; each supporting portion includes: a first sub-support portion and a second sub-support portion; one of the first sub-support portion and the second sub-support portion is arranged on a surface of the array substrate facing the opposing substrate, and the other is arranged on a surface of the opposing substrate facing the array substrate; the orthographic projection of the first sub-support portion divides the orthographic projection of the second sub-support portion into a first part and a second part; in each supporting portion, the length of the first part is not equal to the length of the second part.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the continuous development of display technology, three-dimensional (3D) display technology has attracted more and more attention. Three-dimensional display technology can make the display image three-dimensional and realistic. Its principle is: use the left and right eyes of a person to receive the left eye image and the right eye image with a certain parallax respectively. When the two parallax images are received by the left and right eyes of a person respectively, the image information is superimposed and fused through the brain to construct a 3D visual display effect.

[0003] In order to achieve compatibility between ultra-multi-viewpoint 3D display and light field display, the traditional sub-pixel is made into a pixel island structure, and each pixel island contains multiple sub-pixels. In order to achieve ultra-high resolution display, the sub-pixel size is reduced. When the sub-pixel spacing in the pixel island structure is smaller, that is, the pixel density (PPI) is higher, the number of viewpoints is more, the viewing continuity is better, and it is also compatible with light field display. However, after the PPI increases, the sub-pixel layout is more difficult and the sub-pixel aperture ratio is not high. Summary of the invention

[0004] An embodiment of the present disclosure provides a display panel, the display panel comprising:

[0005] An array substrate, comprising: a plurality of scan lines extending along a first direction, a plurality of data lines extending along a second direction, and a plurality of sub-pixels located in an area divided by the plurality of scan lines and the plurality of data lines; the first direction intersects with the second direction; the plurality of sub-pixels include a plurality of sub-pixel rows arranged along the second direction, each sub-pixel row includes a plurality of sub-pixels arranged along the first direction; at least two sub-pixels adjacent to each other along the first direction and the second direction constitute a pixel island;

[0006] An opposite substrate, arranged opposite to the array substrate;

[0007] A liquid crystal layer is located between the array substrate and the opposite substrate;

[0008] A plurality of support portions are located between an array substrate and an opposing substrate, and an orthographic projection of the support portion on the array substrate is located between orthographic projections of adjacent sub-pixel rows on the array substrate; each support portion comprises: a first sub-support portion and a second sub-support portion, the first sub-support portion extends along a first direction, and the second sub-support portion extends along a second direction; one of the first sub-support portion and the second sub-support portion is arranged on a surface of the array substrate facing the opposing substrate, and the other of the first sub-support portion and the second sub-support portion is arranged on a surface of the opposing substrate facing the array substrate; the orthographic projection of the first sub-support portion on the array substrate divides the orthographic projection of the second sub-support portion on the array substrate into a first part and a second part; in each support portion, the length of the first part in the second direction is not equal to the length of the second part in the second direction.

[0009] In some embodiments, the plurality of support portions include: a plurality of first support portions and a plurality of second support portions;

[0010] In each first supporting portion, the length of the first portion in the second direction is greater than the length of the second portion in the second direction;

[0011] In each second supporting portion, a length of the first portion in the second direction is smaller than a length of the second portion in the second direction.

[0012] In some embodiments, the colors of the plurality of sub-pixels in each sub-pixel row are the same;

[0013] The opposite substrate comprises: a light shielding layer; the light shielding layer only comprises a plurality of first light shielding portions extending along a first direction;

[0014] The orthographic projection of the first light shielding portion on the array substrate covers the orthographic projection of the scanning line on the array substrate and the orthographic projection of the supporting portion on the array substrate.

[0015] In some embodiments, the sub-pixel rows include: a red sub-pixel row, a blue sub-pixel row, and a green sub-pixel row;

[0016] The width of the first light shielding portion between the red sub-pixel row and the blue sub-pixel row in the second direction is greater than the width of the first light shielding portion between the red sub-pixel row and the green sub-pixel row in the second direction;

[0017] Furthermore, a width of the first light shielding portion between the red sub-pixel row and the blue sub-pixel row in the second direction is greater than a width of the first light shielding portion between the blue sub-pixel row and the green sub-pixel row in the second direction.

[0018] In some embodiments, an orthographic projection of the support portion on the array substrate is located between adjacent blue sub-pixel rows and green sub-pixel rows.

[0019] In some embodiments, when the plurality of supporting portions include a plurality of first supporting portions and a plurality of second supporting portions, adjacent blue sub-pixel rows and red sub-pixel rows include a first supporting portion or a second supporting portion.

[0020] In some embodiments, when the plurality of support portions include a plurality of first support portions and a plurality of second support portions, the first support portions and the second support portions are included between adjacent blue sub-pixel rows and adjacent red sub-pixel rows.

[0021] In some embodiments, the length of the first portion of the first supporting portion in the second direction is equal to the length of the second portion of the second supporting portion in the second direction.

[0022] In some embodiments, the length of the second portion of the first supporting portion in the second direction is equal to the length of the first portion of the second supporting portion in the second direction.

[0023] In some embodiments, an orthographic projection of the second sub-support portion on the array substrate is symmetrical with respect to an orthographic projection of the first sub-support portion on the array substrate.

[0024] In some embodiments, the pattern of the orthographic projection of the support portion on the array substrate is a cross.

[0025] In some embodiments, a width of the first sub-support portion in the second direction is equal to a width of the second sub-support portion in the first direction.

[0026] In some embodiments, a length of the first sub-support portion in the first direction is greater than a length of the second sub-support portion in the second direction.

[0027] In some embodiments, the first sub-support portion is disposed on a surface of the counter substrate facing the array substrate;

[0028] The second sub-support portion is arranged on a surface of the array substrate facing the opposite substrate.

[0029] In some embodiments, the array substrate specifically includes:

[0030] a first substrate base plate;

[0031] The first conductive layer is located on the side of the first substrate facing the opposite substrate; it includes: a data line, and a first electrode of a driving transistor electrically connected to the data line;

[0032] The second conductive layer is located on a side of the first conductive layer away from the first substrate; it includes: a second electrode of the driving transistor;

[0033] The pixel electrode layer is located on the side of the second conductive layer away from the first conductive layer, and includes a plurality of pixel electrodes corresponding to the sub-pixels one by one; the pixel electrodes are electrically connected to the second electrode of the driving transistor.

[0034] In some embodiments, a minimum distance between an edge of an orthographic projection of the second electrode of the driving transistor and an edge of an orthographic projection of the data line on the first substrate is 0.8 micrometers to 1 micrometer.

[0035] In some embodiments, it also includes:

[0036] The active layer is located between the first substrate and the first conductive layer, and includes: a plurality of active layer patterns corresponding to the sub-pixels one by one;

[0037] The shape of the orthographic projection of the pattern of the active layer on the first substrate has a corner, and the orthographic projection of the pattern of the active layer on the first substrate has a first groove at the corner.

[0038] In some embodiments, it also includes:

[0039] A gate conductive layer, located between the active layer and the first conductive layer, including a control electrode of the driving transistor and a scanning line;

[0040] A gate insulating layer, located between the active layer and the gate conductive layer;

[0041] A first interlayer insulating layer, located between the gate conductive layer and the first conductive layer;

[0042] a second interlayer insulating layer, located between the first conductive layer and the second conductive layer;

[0043] A first passivation layer, located between the second conductive layer and the pixel electrode;

[0044] The second electrode of the driving transistor contacts the active layer through a first via hole penetrating the second interlayer insulating layer, the first interlayer insulating layer and the gate insulating layer;

[0045] The pixel electrode is in contact with the second electrode of the driving transistor through a second via hole penetrating the first passivation layer;

[0046] A minimum distance between an edge of an orthographic projection of the second via hole on the first base substrate and an edge of an orthographic projection of the first via hole between the base substrates is greater than or equal to 0.35 micrometers and less than or equal to 0.7 micrometers.

[0047] In some embodiments, a minimum distance between an edge of an orthographic projection of the second via hole on the first substrate and an edge of an orthographic projection of the control stage of the driving transistor on the first substrate is greater than or equal to 1 micrometer and less than or equal to 2 micrometers.

[0048] In some embodiments, it also includes:

[0049] The common electrode layer is located on a side of the pixel electrode layer away from the second conductive layer, and includes: a common electrode;

[0050] The gate conductive layer also includes:

[0051] The common electrode line is electrically connected to the common electrode; the common electrode line is arranged between adjacent blue sub-pixel rows and red sub-pixel rows.

[0052] A display device provided by an embodiment of the present disclosure includes the display panel provided by an embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0054] Figure 1 A schematic diagram of a cross-sectional structure of a display panel provided in an embodiment of the present disclosure;

[0055] Figure 2 A schematic diagram of a planar structure of an array substrate provided in an embodiment of the present disclosure;

[0056] Figure 3 A schematic diagram of a planar structure of another array substrate provided in an embodiment of the present disclosure;

[0057] Figure 4 A schematic diagram of a planar structure of another array substrate provided in an embodiment of the present disclosure;

[0058] Figure 5 A schematic diagram of a planar structure of a facing substrate provided in an embodiment of the present disclosure;

[0059] Figure 6 A schematic diagram of a planar structure of another array substrate provided in an embodiment of the present disclosure;

[0060] Figure 7 A schematic diagram of a planar structure of another array substrate provided in an embodiment of the present disclosure;

[0061] Figure 8 The embodiment of the present disclosure provides Figure 7 Cross-sectional view of AA';

[0062] Fig. 9 A schematic diagram of the structure of a light shielding layer in an array substrate provided in an embodiment of the present disclosure;

[0063] Fig.10 A schematic diagram of the structure of an active layer in an array substrate provided in an embodiment of the present disclosure;

[0064] Fig.11A schematic diagram of the structure of a gate conductive layer in an array substrate provided in an embodiment of the present disclosure;

[0065] Fig.12 A schematic diagram of a via hole in a first interlayer insulating layer in an array substrate provided by an embodiment of the present disclosure;

[0066] Fig.13 A schematic diagram of the structure of a first conductive layer in an array substrate provided in an embodiment of the present disclosure;

[0067] Fig.14 A schematic diagram of a via hole in a second interlayer insulating layer in an array substrate provided by an embodiment of the present disclosure;

[0068] Fig.15 A schematic diagram of the structure of a second conductive layer in an array substrate provided in an embodiment of the present disclosure;

[0069] Fig.16 A schematic diagram of a via hole in a first passivation layer in an array substrate provided by an embodiment of the present disclosure;

[0070] Fig.17 A schematic structural diagram of a pixel electrode layer in an array substrate provided in an embodiment of the present disclosure;

[0071] Fig.18 A schematic diagram of the structure of a common electrode layer in an array substrate provided in an embodiment of the present disclosure;

[0072] Fig.19 A schematic diagram of a planar structure of another array substrate provided with a common electrode line area according to an embodiment of the present disclosure;

[0073] Fig. 20 The embodiments of the present disclosure provide Fig.19 A schematic diagram of the structure of the gate conductive layer corresponding to the region shown;

[0074] Fig.21 The embodiments of the present disclosure provide Fig.19 A schematic diagram of the structure of the second interlayer insulating layer corresponding to the region shown;

[0075] Fig. 22 The embodiments of the present disclosure provide Fig.19 A schematic diagram of the structure of the second conductive layer corresponding to the area shown;

[0076] Fig.23 The embodiments of the present disclosure provide Fig.19 A schematic diagram of the structure of the first passivation layer corresponding to the region shown;

[0077] Fig.24 The embodiments of the present disclosure provide Fig.19 A schematic diagram of the structure of the pixel electrode layer corresponding to the area shown;

[0078] Fig.25 The embodiments of the present disclosure provide Fig.19 A schematic diagram of the structure of the second passivation layer corresponding to the region shown;

[0079] Fig.26 The embodiments of the present disclosure provide Fig.19 A schematic diagram of the structure of the common electrode layer corresponding to the area shown;

[0080] Fig. 27 A schematic diagram of the structure of a display device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0081] To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme of the embodiments of the present application will be clearly and completely described below in conjunction with the drawings of the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. And in the absence of conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. Based on the described embodiments of the present application, all other embodiments obtained by ordinary technicians in the field without creative work belong to the scope of protection of this application.

[0082] Unless otherwise defined, the technical terms or scientific terms used in this application should be understood by people with ordinary skills in the field to which this application belongs. "First", "second" and similar words used in this application do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and other similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and other similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0083] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual proportions, but are only intended to illustrate the content of the present application. The same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions.

[0084] The present disclosure provides a display panel provided by the present disclosure, such as Figure 1 , Figure 2 , Figure 3 , Figure 4 As shown, the display panel includes:

[0085] An array substrate 1 comprises: a plurality of scan lines 2 extending along a first direction X, a plurality of data lines 3 extending along a second direction Y, and a plurality of sub-pixels 4 located in an area divided by the plurality of scan lines 2 and the plurality of data lines 3; the first direction X and the second direction Y intersect; at least two sub-pixels adjacent to each other along the first direction X and the second direction Y constitute a pixel island 6; the plurality of sub-pixels 4 are divided into a plurality of sub-pixel rows 5 arranged along the second direction Y, and each sub-pixel row 5 comprises a plurality of sub-pixels 4 arranged along the first direction X;

[0086] An opposite substrate 7, arranged opposite to the array substrate 1;

[0087] The liquid crystal layer 8 is located between the array substrate 1 and the counter substrate 7;

[0088] A plurality of support portions 9 are located between the array substrate 1 and the opposing substrate 7, and the orthographic projection of the support portion 9 on the array substrate 1 is located between the orthographic projections of adjacent sub-pixel rows 5 on the array substrate 1; each support portion 9 comprises: a first sub-support portion 12 and a second sub-support portion 13, the first sub-support portion 12 extends along a first direction X, and the second sub-support portion 13 extends along a second direction Y; one of the first sub-support portion 12 and the second sub-support portion 13 is arranged on a surface of the array substrate 1 facing the opposing substrate 7, and the other of the first sub-support portion 12 and the second sub-support portion 13 is arranged on a surface of the opposing substrate 7 facing the array substrate 1; the orthographic projection of the first sub-support portion 12 on the array substrate 1 divides the orthographic projection of the second sub-support portion 13 on the array substrate 1 into a first part 14 and a second part 15; in each support portion 9, the length of the first part 14 in the second direction Y is not equal to the length of the second part 15 in the second direction Y.

[0089] In the display panel provided by the embodiment of the present disclosure, each support part includes a first sub-support part and a second sub-support part which are arranged on different substrates and extend in different directions. The orthographic projection of the first sub-support part on the array substrate divides the orthographic projection of the second sub-support part on the array substrate into a first part and a second part, that is, the first sub-support part has a certain sliding distance relative to the second sub-support part, so as to avoid the first sub-support part and the second sub-support part from scratching the remaining film layers due to sliding during the preparation process of the display panel. Among them, the length of the first part in the second direction of the support part is not equal to the length of the second part in the second direction, so that the maximum sliding distance of each support part is the sum of the longer length of the first part and the second part in the second direction and the width of the second sub-support part in the second direction. Compared with the case where the length of the first part in the second direction of each support part is equal to the length of the second part in the second direction, the maximum sliding distance of the support part can be increased. In this way, the display panel provided by the embodiment of the present disclosure can reduce the length of the light shielding area of ​​the display panel covering the support part in the second direction without changing the sliding distance of the support part, thereby increasing the area of ​​the sub-pixel light-transmitting area, increasing the sub-pixel aperture ratio, and further improving the display effect and user experience.

[0090] It should be noted that Figure 2 , Figure 3 , Figure 4 is a plan view of the array substrate, Figure 1 For example it could be Figure 2 , Figure 3 , Figure 4 A cross-sectional view of a partial area along the first direction X.

[0091] In some embodiments, Figure 2 , Figure 3 As shown, the lengths h6 of the first portions 14 in the plurality of support portions 9 in the second direction Y are all equal; and the lengths h7 of the second portions 15 in the plurality of support portions 9 in the second direction Y are all equal.

[0092] In some embodiments, Figure 2 As shown, among the plurality of support portions 9 , a length h6 of the first portion 14 in the second direction Y is greater than a length h7 of the second portion 15 in the second direction Y.

[0093] Or, if Figure 3 As shown, among the plurality of support portions 9 , a length h6 of the first portion 14 in the second direction Y is smaller than a length h7 of the second portion 15 in the second direction Y.

[0094] In some embodiments, Figure 4As shown, the plurality of support portions 9 include: a plurality of first support portions 10 and a plurality of second support portions 11; each first support portion 10 includes: a first sub-support portion 12 and a second sub-support portion 13; each second support portion 11 includes: a first sub-support portion 12 and a second sub-support portion 13;

[0095] In the first supporting portion 12 , the length h1 of the first portion 14 in the second direction Y is greater than the length h2 of the second portion 15 in the second direction Y; in the second supporting portion 13 , the length h3 of the first portion 14 in the second direction Y is less than the length h4 of the second portion 15 in the second direction Y.

[0096] In the display panel provided by the embodiment of the present disclosure, each support part includes a first sub-support part and a second sub-support part which are arranged on different substrates and extend in different directions. The orthographic projection of the first sub-support part on the array substrate divides the orthographic projection of the second sub-support part on the array substrate into a first part and a second part, that is, the first sub-support part has a certain sliding distance relative to the second sub-support part, so as to avoid the first sub-support part and the second sub-support part from scratching the remaining film layers due to sliding during the preparation process of the display panel. Among them, the upward sliding distance of the first support part is the sum of the length of the first part in the first support part in the second direction and the width of the second sub-support part in the second direction, and the downward sliding distance of the second support part is the sum of the length of the second part in the second direction and the width of the second sub-support part in the second direction. Compared with the case where the length of the first part in the second direction of each support part is equal to the length of the second part in the second direction, the distance of the support part sliding upward and downward can be increased. In addition, since the display panel includes two support parts, the first support part and the second support part, the total sliding distance of the support part can be increased compared with the case where the length of the first part in the second direction of each support part is equal to the length of the second part in the second direction. In this way, the display panel provided by the embodiment of the present disclosure can reduce the length of the shading area of ​​the display panel covering the support part in the second direction without changing the sliding distance of the support part, thereby increasing the area of ​​the sub-pixel light-transmitting area and the sub-pixel aperture ratio, thereby improving the display effect and enhancing the user experience.

[0097] It should be noted that Figure 4 Where H1 is the distance that the first sub-support portion in the first support portion slides upward, and H2 is the distance that the first sub-support portion in the second support portion slides downward, then the total sliding distance of the display panel support portion is H1+H2. Figure 4 Only some sub-pixels and supporting parts are shown, and only one scan line and data line are shown to illustrate the display panel provided by the embodiment of the present disclosure. In specific implementation, the number of sub-pixels, the number of supporting parts, the number of scan lines, and the number of data lines can be set according to actual needs.

[0098] It should be noted that the display panel provided in the embodiment of the present disclosure is a liquid crystal display panel, which may be a twisted nematic (TN) type, a vertical alignment (VA) type, an in-plane switching (IPS) type, or an advanced super dimensional switch (ADS) type liquid crystal display panel.

[0099] In some embodiments, Figure 2 , Figure 3 , Figure 4 As shown, the colors of the multiple sub-pixels 4 in each sub-pixel row 5 are the same.

[0100] This can avoid crosstalk between different viewpoints and alleviate moiré patterns.

[0101] In some embodiments, Figure 2 , Figure 3 , Figure 4 As shown, the sub-pixel row 5 includes: a red sub-pixel row 16, a blue sub-pixel row 18, and a green sub-pixel row 17. Figure 2 , Figure 3 , Figure 4 As shown, the red sub-pixel row 16 includes a plurality of red sub-pixels R arranged along the first direction X, the green sub-pixel row 17 includes a plurality of green sub-pixels G arranged along the first direction X, and the blue sub-pixel row 18 includes a plurality of blue sub-pixels B arranged along the first direction X.

[0102] In some embodiments, Figure 2 , Figure 3 , Figure 4 , Figure 5 As shown, the opposite substrate includes: a light shielding layer; the light shielding layer only includes a plurality of first light shielding portions 19 extending along the first direction X;

[0103] The orthographic projection of the first light shielding portion 19 on the array substrate covers the orthographic projection of the scanning line 2 on the array substrate and the orthographic projection of the supporting portion 9 on the array substrate.

[0104] In some embodiments, Figure 2 , Figure 3 , Figure 4 , Figure 5 As shown, the width of the first light shielding portion 19 between the red sub-pixel row 16 and the blue sub-pixel row 18 in the second direction Y is greater than the width of the first light shielding portion 19 between the red sub-pixel row 16 and the green sub-pixel row 17 in the second direction Y;

[0105] Furthermore, the width of the first light shielding portion 19 between the red sub-pixel row 16 and the blue sub-pixel row 18 in the second direction Y is greater than the width of the first light shielding portion 19 between the blue sub-pixel row 18 and the green sub-pixel row 17 in the second direction Y.

[0106] It should be noted that Figure 2 , Figure 3 , Figure 4 The area encircled by the dotted line is the area covered by the orthographic projection of the first light shielding portion 19 on the array substrate.

[0107] It should be noted that Figure 2 , Figure 3 , Figure 4 , Figure 5 The size ratio of the first light shielding portion between the sub-pixel rows does not represent the actual ratio, and the area between the blue sub-pixel row and the red sub-pixel row is larger only to clearly illustrate the structure of the support portion.

[0108] It should be noted that Figure 5 is a plan view of the opposite substrate. Figure 5 As shown, the opposite substrate further includes a color resist 20 disposed in the light shielding layer opening area. The color of the color resist 20 corresponds to the color of the sub-pixel one by one, that is, the color resist 20 includes a red color resist r, a blue color resist b and a green color resist g.

[0109] It should be noted that in the related art, the pattern of the light shielding layer of the opposite substrate is in a grid shape, and the grid openings are the light-transmitting areas corresponding to the sub-pixels. In the display panel provided by the embodiment of the present disclosure, the light shielding layer of the opposite substrate only includes a first light shielding portion extending along the first direction, that is, no light shielding portion is provided in the second direction. Compared with the light shielding layer with a grid pattern in the related art, the aperture ratio of the sub-pixels can be increased, and since the colors of a row of sub-pixels extending in the first direction are the same, not providing a light shielding portion extending in the second direction will not affect the display effect.

[0110] In some embodiments, Figure 2 , Figure 3 , Figure 4 As shown, the orthographic projection of the support portion 9 on the array substrate is located between the adjacent blue sub-pixel row 18 and green sub-pixel row 16 .

[0111] That is, in the display panel provided by the embodiment of the present disclosure, the support portion is disposed in an area where the width of the first light shielding portion in the second direction Y is relatively wide.

[0112] It should be noted that, compared with the red sub-pixels and the blue sub-pixels, the luminous efficiency of the green sub-pixels is more affected by the aperture ratio. Therefore, the display panel provided by the embodiment of the present disclosure has a first light shielding portion with a wider width in the second direction Y disposed between the red sub-pixel row and the blue sub-pixel row, which can avoid the influence of increasing the width of the first light shielding portion in the second direction Y on the green sub-pixels.

[0113] When the plurality of support portions include a first support portion and a second support portion, in some embodiments, as Figure 4 As shown, a first supporting portion 10 or a second supporting portion 11 is included between adjacent blue sub-pixel rows 18 and red sub-pixel rows 16 .

[0114] Alternatively, when the plurality of support portions include a first support portion and a second support portion, in some embodiments, as Figure 6 As shown, a first support portion 10 and a second support portion 11 are included between adjacent blue sub-pixel rows 18 and red sub-pixel rows 16 .

[0115] In some embodiments, Figure 4 , Figure 6 As shown, the length h1 of the first portion 14 in the first supporting portion 10 in the second direction Y is equal to the length h4 of the second portion 15 in the second supporting portion 11 in the second direction Y.

[0116] In some embodiments, Figure 4 , Figure 6 As shown, the length h2 of the second portion 15 in the first supporting portion 10 in the second direction Y is equal to the length h3 of the first portion 14 in the second supporting portion 11 in the second direction Y.

[0117] In some embodiments, Figure 2 , Figure 3 , Figure 4 , Figure 6 As shown, the orthographic projection of the second sub-support portion 12 on the array substrate is symmetrical with respect to the orthographic projection of the first sub-support portion 13 on the array substrate.

[0118] In some embodiments, Figure 2 , Figure 3 , Figure 4 , Figure 6 As shown, the pattern of the orthographic projection of the support portion 9 on the array substrate is a cross.

[0119] It should be noted that the cross pattern in the embodiment of the present disclosure refers to a pattern formed by vertically crossing bar patterns extending in different directions.

[0120] like Figure 2 , Figure 3 , Figure 4 , Figure 6As shown, the first sub-support portion and the second sub-support portion included in the support portion are strip patterns with different extension directions, and the first sub-support portion and the second sub-support portion are vertically crossed to form a cross-shaped pattern.

[0121] In some embodiments, Figure 2 , Figure 3 , Figure 4 , Figure 6 As shown, the width of the first sub-support portion 10 in the second direction Y is equal to the width of the second sub-support portion 11 in the first direction X.

[0122] In some embodiments, Figure 2 , Figure 3 , Figure 4 , Figure 6 As shown, the length of the first sub-support portion 10 in the first direction X is greater than the length of the second sub-support portion 11 in the second direction Y.

[0123] In this way, the supporting strength of the supporting portion in the first direction can be increased.

[0124] That is, when the supporting strength of the supporting part remains unchanged, the arrangement of the first sub-support part and the second sub-support part provided in the embodiment of the present disclosure can reduce the length of the second sub-support part in the second direction, thereby reducing the width of the first shading layer covering the supporting part in the second direction and increasing the aperture ratio of the sub-pixel.

[0125] In a specific implementation, the length of the first sub-support portion in the first direction and the length of the second sub-support portion in the first direction are 20 microns, and the width of the first sub-support portion in the second direction and the width of the second sub-support portion in the first direction are 6 microns. The minimum distance between the edge of the first light shielding portion extending in the first direction and the first sub-support portion can be about 5 microns. The length of the first light shielding portion located between the red sub-pixel row and the blue sub-pixel row in the first direction is 44 microns, the width in the second direction is 10 microns, and the minimum distance between the edge of the first light shielding portion extending in the first direction and the second sub-support portion is 3 microns. In the first support portion, the upward or downward sliding distance of the first sub-support portion is 12 microns, and in the second support portion, the downward sliding distance of the first sub-support portion is 12 microns. That is, the sliding distance of the support portion is 24 microns. In actual design, the sliding distance of the support portion needs to refer to the size of the display panel, the size of the external force used in the product specification test specification, and the force area. When designing the size of the second sub-support portion, factors such as the sliding distance of the support portion, the contact support force of the support portion, the material of the support portion, and the height need to be considered. In the specific design, when the sub-pixel length is 52um and the pixel pitch is 9.75 microns, when the design of the first support portion and the second support portion provided in the embodiment of the present disclosure is adopted, the maximum width of the first shading portion in the second direction is 30 microns, which can ensure that the average aperture ratio of the sub-pixel is greater than 50%.

[0126] In some embodiments, Figure 1 As shown, the first sub-support portion 12 is disposed on the surface of the opposite substrate 7 facing the array substrate 1;

[0127] The second sub-support portion 13 is disposed on the surface of the array substrate 1 facing the opposite substrate 7 .

[0128] In some embodiments, Figure 7 , Figure 8 As shown, the array substrate specifically includes:

[0129] A first substrate 21;

[0130] The first conductive layer 22 is located on the side of the first substrate facing the opposite substrate; it includes: a data line 48, and a first electrode 36 of a driving transistor electrically connected to the data line;

[0131] The second conductive layer 23 is located on the side of the first conductive layer away from the first substrate; it includes: a second electrode 37 of the driving transistor;

[0132] The pixel electrode layer 24 is located on the side of the second conductive layer away from the first conductive layer, and includes a plurality of pixel electrodes 47 corresponding to the sub-pixels one by one; the pixel electrodes are electrically connected to the second electrode of the driving transistor.

[0133] That is, in the embodiment of the present disclosure, the second electrode of the driving transistor and the data line are arranged in different conductive layers. In this way, even if the distance between the edge of the orthographic projection of the second electrode of the driving transistor on the first substrate and the edge of the orthographic projection of the data line on the first substrate is reduced, it will not cause a short circuit between the second electrode of the driving transistor and the data line, which can simplify the design difficulty of the array substrate layout.

[0134] It should be noted that Figure 8 For example, it can be along Figure 7 Cross-sectional view along line AA'.

[0135] In some embodiments, the width of the scan line is 2.5 microns-3.5 microns. The smaller the resistivity of the material of the gate conductive layer, the wider the scan line can be set. The resistivity of the material of the gate conductive layer can be selected in the range of 0.07 square resistance (Ω / □)-0.1Ω / □.

[0136] In some embodiments, the width of the data line is 1.5 micrometers to 1.8 micrometers. In order to prevent the line from being broken in the overlapped area with the scan line, a compensating widening design is adopted in the overlapped area with the scan line, and the single side is widened by 0.5 micrometers.

[0137] In some embodiments, a minimum distance between an edge of an orthographic projection of the second electrode of the driving transistor and an edge of an orthographic projection of the data line on the first substrate is 0.8 micrometers to 1 micrometer.

[0138] In some embodiments, the width of the second electrode of the driving transistor is 4.3 micrometers to 6.65 micrometers.

[0139] In some embodiments, Figure 7 , Figure 8 As shown, the array substrate further includes:

[0140] The active layer 26 is located between the first base substrate 21 and the first conductive layer 22, and includes: a plurality of active layer patterns corresponding to the sub-pixels one by one;

[0141] like Fig.10 As shown, the shape of the orthographic projection of the pattern of the active layer 26 on the first substrate has a corner, and the orthographic projection of the pattern of the active layer on the first substrate has a first groove at the corner.

[0142] In some embodiments, the material of the active layer includes, for example, polysilicon. The active layer includes a semiconductor region and a conductor region. In a specific implementation, for example, a self-aligned process can be used to perform low-temperature doping to form a conductor region. To ensure doping accuracy, the distance between the edge of the positive projection of the active layer on the first substrate and the edge of the positive projection of the scanning line on the first substrate is 1 micron to 1.5 microns, and to ensure the accuracy of the corner shape of the active layer, it is necessary to perform exposure compensation design at the corner, that is, when the hollowing is 1 micron, a first groove is formed.

[0143] In some embodiments, Figure 7 , Figure 8 As shown, the array substrate further includes:

[0144] The light shielding layer 25 is located between the active layer 26 and the first base substrate 21;

[0145] The buffer layer 40 is located between the light shielding layer 25 and the active layer 26;

[0146] The gate conductive layer 27 is located between the active layer 26 and the first conductive layer 22, and includes a control electrode 39 of the driving transistor and a scanning line;

[0147] A gate insulating layer 35 is located between the active layer 26 and the gate conductive layer 27;

[0148] A first interlayer insulating layer 29, located between the gate conductive layer 27 and the first conductive layer 22;

[0149] A second interlayer insulating layer 31, located between the first conductive layer 22 and the second conductive layer 23;

[0150] A first passivation layer 33, located between the second conductive layer 23 and the pixel electrode layer 24;

[0151] The second electrode of the driving transistor contacts the active layer 26 through a first via hole 32 penetrating the second interlayer insulating layer, the first interlayer insulating layer and the gate insulating layer;

[0152] The pixel electrode is in contact with the second electrode of the driving transistor through a second via hole 34 penetrating the first passivation layer 33;

[0153] The first electrode of the driving transistor contacts the active layer through a third via hole 30 penetrating the first interlayer insulating layer and the gate insulating layer.

[0154] It should be noted that the light shielding layer is used to shield the channel region of the driving transistor.

[0155] In some embodiments, a size of the first via hole is 1.5 micrometers to 2.5 micrometers.

[0156] In some embodiments, the second via hole has a size of 2.5-3.5 microns.

[0157] In some embodiments, a size of the third via hole is 1.5 micrometers to 2.5 micrometers.

[0158] To avoid via etching residue, in some embodiments, the minimum distance between the edge of the orthographic projection of the second via on the first substrate and the edge of the orthographic projection of the first via between the substrates is greater than or equal to 0.35 microns and less than or equal to 0.7 microns.

[0159] In order to prevent the first via hole from being connected to the scan line and causing a short circuit between the control level of the driving transistor and the second pole, in some embodiments, the minimum distance between the edge of the orthographic projection of the second via hole on the first substrate and the edge of the orthographic projection of the control level of the driving transistor on the first substrate is greater than or equal to 1 micron and less than or equal to 2 microns.

[0160] In some embodiments, Figure 7 , Fig.17 As shown, the array substrate further includes:

[0161] The common electrode layer 28 is located on a side of the pixel electrode layer 24 away from the second conductive layer 23 and includes: a common electrode 38;

[0162] The second passivation layer 41 is located between the common electrode layer 28 and the pixel electrode layer 24 .

[0163] In some embodiments, Fig.19 As shown, the gate conductive layer 27 further includes:

[0164] The common electrode line 46 is electrically connected to the common electrode 38 ; the common electrode line is disposed between adjacent blue sub-pixel rows and red sub-pixel rows.

[0165] In a specific implementation, for example, a common electrode line may be arranged in a region corresponding to the support portion between the blue sub-pixel row and the red sub-pixel row, so as to avoid the arrangement of the common electrode line affecting the aperture ratio of the display panel.

[0166] In some embodiments, the second conductive layer 23 further includes a connecting electrode 49; the connecting electrode 49 is electrically connected to the common electrode line 46 through a fourth via 50 penetrating the second interlayer insulating layer and the first interlayer insulating layer; the common electrode 38 is electrically connected to the connecting electrode 49 through a fifth via 52 penetrating the second passivation layer and a sixth via 51 penetrating the first passivation layer. The fourth via, the fifth via, and the sixth via have overlapping orthographic projections on the first substrate.

[0167] It should be noted that the pixel electrode layer and the common electrode layer may be made of materials with high transmittance. The pixel electrode layer and the common electrode layer may include, for example, indium tin oxide (ITO). That is, the array substrate may be provided with two layers of ITO. The first layer of ITO is used as the pixel electrode layer, thereby reducing the number of vias and improving the aperture ratio.

[0168] In specific implementation, the pixel pitch can be designed to be 9.75 microns, for example. In this case, ITO with the highest transmittance can be used. In this way, the width-to-length ratio of the common electrode cutout is 4.8 microns / 4.95 microns, that is, the entire layer of common electrode set in the light-transmitting area of ​​the pixel is hollowed out by 4.8 microns.

[0169] It should be noted that Figures 9 to 18 respectively Figure 7 The areas shown correspond to patterns of the light shielding layer 25 , the active layer 26 , the gate conductive layer 27 , the first interlayer insulating layer 29 , the first conductive layer 22 , the second interlayer insulating layer 31 , the second conductive layer 23 , the first passivation layer 33 , the pixel electrode layer 24 , and the common electrode layer 28 . Figure 20 to Figure 27 for Fig.19 The regions shown correspond to the patterns of the gate conductive layer 27, the second interlayer insulating layer 31, the second conductive layer 23, the first passivation layer 33, the pixel electrode layer 24, the second passivation layer 41, and the common electrode layer 28. Fig.12 , Fig.14 , Fig.16 , Fig.21 , Fig.23 , Fig.25 Only the patterns of the via holes in each insulating layer are shown. Fig.19 The corresponding active layer pattern reference Fig.10 , Fig.19 The corresponding pattern of the first conductive layer 22 is referenced Fig.13 .

[0170] Next, taking the manufacturing of the second sub-supporting portion on the side of the array substrate facing the opposite substrate as an example, the preparation of the array substrate in the display panel provided by the embodiment of the present disclosure is described by way of example. The preparation method of the array substrate includes the following steps:

[0171] S101, depositing a light shielding layer material on a first substrate, and forming a pattern of the light shielding layer by a graphic process;

[0172] S102, depositing a buffer layer material to form a buffer layer;

[0173] S103, depositing semiconductor material, and etching to form a pattern of an active layer;

[0174] S103, depositing a gate insulating layer material to form a gate insulating layer;

[0175] S104, depositing a gate metal material, etching to form a pattern of a gate metal layer, and performing a semiconductor self-aligned doping process to form a conductive region in the active layer;

[0176] S105, depositing a first interlayer insulating layer material, and etching to form a third via hole;

[0177] S106, depositing a metal material to form a first conductive layer, and etching to form a pattern of the first conductive layer;

[0178] S107, depositing a second interlayer insulating layer material, and etching to form a first via hole;

[0179] S108, depositing a metal material to form a second conductive layer, and etching to form a pattern of the second conductive layer;

[0180] S109, depositing a material for a first passivation layer to form a first passivation layer, and forming a second via hole by using an exposure process;

[0181] S110, depositing ITO to form a pixel electrode layer, and etching to form a pixel electrode;

[0182] S111, depositing a material for a second passivation layer to form a second passivation layer and etching to form a peripheral area via hole;

[0183] S112, depositing ITO to form a common electrode layer, and etching to form a pattern of the common electrode;

[0184] S113 , depositing a second sub-support material and etching to form a pattern of the second sub-support.

[0185] The present disclosure provides a display device, such as Fig. 27 As shown, it includes a display panel 42 provided in an embodiment of the present disclosure.

[0186] In some embodiments, Fig. 27 As shown, the display device also includes:

[0187] The cylindrical lens structure 43 is located at the light-emitting side of the display panel; the cylindrical lens structure includes a plurality of cylindrical lenses arranged in an array.

[0188] In some embodiments, Fig. 27 As shown, the display device also includes:

[0189] A light-transmitting spacer layer 44 is located between the display panel 42 and the cylindrical lens structure 43;

[0190] The flat layer 45 is located on a side of the cylindrical lens structure 45 away from the light-transmitting spacer layer 44 .

[0191] In some embodiments, when the display panel is a liquid crystal display panel, the display device further includes a backlight module located on the display panel away from the cylindrical lens structure.

[0192] In some embodiments, the display device further comprises:

[0193] Eye-tracking is used to determine the user's gaze area on the display device in real time.

[0194] In this way, the display information of each sub-pixel in the pixel island corresponding to the gaze area of ​​the user's eyes on the display device can be determined according to the determined gaze area of ​​the user's eyes on the display device.

[0195] In specific implementation, since the sub-pixel subdivision is performed in the pixel island (which can be used as a sub-pixel for two-dimensional image (2D) display), the same resolution as 2D display can be maintained in the three-dimensional image (3D) display mode, and combined with eye-tracking, a multi-viewpoint display with a large viewing angle can be achieved, and a 3D display with a higher pixel density (ppi) can be achieved, with a larger amount of information, lower color crosstalk between adjacent viewpoints, and the user's dizziness when watching 3D images can be reduced, thereby improving the user experience. When the display device is provided with a cylindrical lens array, the cylindrical lens array can not only perform pixel mapping on the sub-pixels in the pixel island, but also perform light field modulation on the outgoing light of the pixel island, so that the final outgoing light of the pixel island forms multiple viewpoints, thereby realizing light field 3D display.

[0196] The display device provided in the embodiment of the present disclosure is any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a laptop computer, a digital photo frame, a navigator, etc. Other essential components of the display device should be understood by a person skilled in the art, and will not be described in detail here, nor should they be used as a limitation of the present disclosure. The implementation of the display device can refer to the embodiment of the display panel above, and the repeated parts will not be described in detail.

[0197] In summary, the display panel provided by the embodiment of the present disclosure is a display device, and each support portion includes a first sub-support portion and a second sub-support portion which are arranged on different substrates and extend in different directions. The orthographic projection of the first sub-support portion on the array substrate divides the orthographic projection of the second sub-support portion on the array substrate into a first part and a second part, that is, the first sub-support portion has a certain sliding distance relative to the second sub-support portion, so as to avoid the first sub-support portion and the second sub-support portion from scratching the remaining film layers due to sliding during the preparation of the display panel. Among them, the upward sliding distance of the first support portion is the sum of the length of the first part in the first support portion in the second direction and the width of the second sub-support portion in the second direction, and the downward sliding distance of the second support portion is the sum of the length of the second part in the second direction and the width of the second sub-support portion in the second direction. Compared with the case where the length of the first part in the second direction of each support portion is equal to the length of the second part in the second direction, the distance of the support portion sliding upward and downward can be increased. In addition, since the display panel includes two support portions, the first support portion and the second support portion, the total sliding distance of the support portion can be increased compared with the case where the length of the first part in the second direction of each support portion is equal to the length of the second part in the second direction. In this way, the display panel provided by the embodiment of the present disclosure can reduce the length of the shading area of ​​the display panel covering the support part in the second direction without changing the sliding distance of the support part, thereby increasing the area of ​​the sub-pixel light-transmitting area and the sub-pixel aperture ratio, thereby improving the display effect and enhancing the user experience.

[0198] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0199] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if these modifications and variations of the embodiments of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A display panel, wherein: The display panel comprises: An array substrate, comprising: a plurality of scan lines extending along a first direction, a plurality of data lines extending along a second direction, and a plurality of sub-pixels located in an area divided by the plurality of scan lines and the plurality of data lines; the first direction intersects with the second direction; the plurality of sub-pixels include a plurality of sub-pixel rows arranged along the second direction, each of the sub-pixel rows includes a plurality of sub-pixels arranged along the first direction; at least two sub-pixels adjacent to each other along the first direction and the second direction constitute a pixel island; an opposite substrate, arranged opposite to the array substrate; A liquid crystal layer, located between the array substrate and the opposite substrate; A plurality of support portions, located between the array substrate and the opposing substrate, and the orthographic projections of the support portions on the array substrate are located between the orthographic projections of adjacent sub-pixel rows on the array substrate; each of the support portions comprises: a first sub-support portion and a second sub-support portion, the first sub-support portion extending along the first direction, and the second sub-support portion extending along the second direction; one of the first sub-support portion and the second sub-support portion is arranged on a surface of the array substrate facing the opposing substrate, and the other of the first sub-support portion and the second sub-support portion is arranged on a surface of the opposing substrate facing the array substrate; the orthographic projection of the first sub-support portion on the array substrate divides the orthographic projection of the second sub-support portion on the array substrate into a first part and a second part; in each of the support portions, the length of the first part in the second direction is not equal to the length of the second part in the second direction; The colors of the plurality of sub-pixels in each sub-pixel row are the same; The counter substrate comprises: a light shielding layer; the light shielding layer only comprises a plurality of first light shielding portions extending along a first direction; The sub-pixel rows include: a red sub-pixel row, a blue sub-pixel row and a green sub-pixel row; A width of the first light shielding portion between the red sub-pixel row and the blue sub-pixel row in the second direction is greater than a width of the first light shielding portion between the red sub-pixel row and the green sub-pixel row in the second direction; Furthermore, a width of the first light shielding portion between the red sub-pixel row and the blue sub-pixel row in the second direction is greater than a width of the first light shielding portion between the blue sub-pixel row and the green sub-pixel row in the second direction.

2. The display panel according to claim 1, wherein: The plurality of support parts include: a plurality of first support parts and a plurality of second support parts; In each of the first supporting portions, the length of the first portion in the second direction is greater than the length of the second portion in the second direction; In each of the second supporting portions, a length of the first portion in the second direction is smaller than a length of the second portion in the second direction.

3. The display panel according to claim 1 or 2, wherein: The orthographic projection of the first light shielding portion on the array substrate covers the orthographic projection of the scanning line on the array substrate and the orthographic projection of the supporting portion on the array substrate.

4. The display panel according to claim 1, wherein: The orthographic projection of the supporting portion on the array substrate is located between the adjacent blue sub-pixel row and the adjacent green sub-pixel row.

5. The display panel according to claim 4, wherein: When the plurality of support portions include a plurality of first support portions and a plurality of second support portions, the first support portion or the second support portion is included between adjacent blue sub-pixel rows and adjacent red sub-pixel rows.

6. The display panel according to claim 5, wherein: When the plurality of support portions include a plurality of first support portions and a plurality of second support portions, the first support portions and the second support portions are included between adjacent blue sub-pixel rows and adjacent red sub-pixel rows.

7. The display panel according to any one of claims 2, 5 to 6, wherein: The length of the first portion of the first supporting portion in the second direction is equal to the length of the second portion of the second supporting portion in the second direction.

8. The display panel according to claim 7, wherein: The length of the second portion of the first supporting portion in the second direction is equal to the length of the first portion of the second supporting portion in the second direction.

9. The display panel according to any one of claims 1, 2, 4 to 6, and 8, wherein: The orthographic projection of the second sub-support portion on the array substrate is symmetrical with respect to the orthographic projection of the first sub-support portion on the array substrate.

10. The display panel according to claim 9, wherein: The pattern of the orthographic projection of the support portion on the array substrate is a cross.

11. The display panel according to any one of claims 1, 2, 4 to 6, 8, and 10, wherein: The width of the first sub-support portion in the second direction is equal to the width of the second sub-support portion in the first direction.

12. The display panel according to any one of claims 1, 2, 4 to 6, 8, and 10, wherein: The length of the first sub-support portion in the first direction is greater than the length of the second sub-support portion in the second direction.

13. The display panel according to any one of claims 1, 2, 4 to 6, 8, and 10, wherein: The first sub-support portion is disposed on a surface of the opposite substrate facing the array substrate; The second sub-support portion is disposed on a surface of the array substrate facing the opposite substrate.

14. The display panel according to any one of claims 1, 4 to 6, 8 and 10, wherein: The array substrate specifically comprises: a first substrate base plate; A first conductive layer is located on a side of the first substrate facing the opposite substrate; it includes: the data line, and a first electrode of a driving transistor electrically connected to the data line; A second conductive layer is located on a side of the first conductive layer away from the first substrate; and includes: a second electrode of the driving transistor; The pixel electrode layer is located on a side of the second conductive layer away from the first conductive layer, and includes a plurality of pixel electrodes corresponding to the sub-pixels one by one; the pixel electrodes are electrically connected to the second electrode of the driving transistor.

15. The display panel according to claim 14, wherein: The minimum distance between the edge of the orthographic projection of the second electrode of the driving transistor on the first substrate and the edge of the orthographic projection of the data line on the first substrate is 0.8 micrometers to 1 micrometer.

16. The display panel according to claim 14, wherein: Also includes: An active layer, located between the first base substrate and the first conductive layer, comprising: a plurality of active layer patterns corresponding to the sub-pixels one by one; The orthographic projection of the pattern of the active layer on the first substrate has a corner, and the orthographic projection of the pattern of the active layer on the first substrate has a first groove at the corner.

17. The display panel according to claim 16, wherein: Also includes: A gate conductive layer, located between the active layer and the first conductive layer, including a control electrode of the driving transistor and the scanning line; A gate insulating layer, located between the active layer and the gate conductive layer; A first interlayer insulating layer, located between the gate conductive layer and the first conductive layer; A second interlayer insulating layer, located between the first conductive layer and the second conductive layer; a first passivation layer, located between the second conductive layer and the pixel electrode; The second electrode of the driving transistor contacts the active layer through a first via hole penetrating the second interlayer insulating layer, the first interlayer insulating layer and the gate insulating layer; The pixel electrode is in contact with the second electrode of the driving transistor through a second via hole penetrating the first passivation layer; A minimum distance between an edge of an orthographic projection of the second via hole on the first base substrate and an edge of an orthographic projection of the first via hole between the base substrates is greater than or equal to 0.35 micrometers and less than or equal to 0.7 micrometers.

18. The display panel according to claim 17, wherein: A minimum distance between an edge of an orthographic projection of the second via hole on the first substrate and an edge of an orthographic projection of the control stage of the driving transistor on the substrate is greater than or equal to 1 micrometer and less than or equal to 2 micrometers.

19. The display panel according to claim 17, wherein: Also includes: The common electrode layer is located on a side of the pixel electrode layer away from the second conductive layer, and includes: a common electrode; The gate conductive layer further comprises: A common electrode line is electrically connected to the common electrode; the common electrode line is arranged between the adjacent blue sub-pixel row and the adjacent red sub-pixel row.

20. A display device, wherein: The invention comprises a display panel according to any one of claims 1 to 19.

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