A wafer production fixture

By designing a chip production fixture for crystal oscillator manufacturing, the problem of wafer coating and automated placement in the prior art is solved, and the automation and precision of the chip manufacturing process is realized, and the manufacturing cost is reduced.

CN116043180BActive Publication Date: 2025-06-20GUANGZHOU JINGYOU ELECTRONICS TECH
View PDF 1 Cites 0 Cited by

Patent Information

Application Number
CN202211726232.6
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2022-12-29
Publication Date
2025-06-20
Estimated Expiration
2042-12-29

AI Technical Summary

Technical Problem

In the prior art, there are problems of low efficiency and high manufacturing costs in the crystal oscillator manufacturing process, especially in the precise coating and automated placement of wafers.

Method used

A wafer production fixture is designed, including an upper clamp, an intermediate plate and a lower clamp. Multiple wafer clamping units are provided on the intermediate plate. The fixture forms through holes through multiple electrode plates to achieve automated placement of the wafer and improve the coating accuracy.

Benefits of technology

Through this fixture, the automation and precision of the wafer manufacturing process is achieved, manufacturing costs are reduced, and operating efficiency and coating accuracy are improved.

✦ Generated by Eureka AI based on patent content.

Smart Images

  • Figure CN116043180B_ABST
    Figure CN116043180B_ABST
Patent Text Reader

Abstract

The present invention relates to the field of jigs, and specifically provides a wafer production jig, which includes an upper clamping plate, an intermediate plate, and a lower clamping plate. The intermediate plate is clamped between the upper clamping plate and the lower clamping plate and forms a plurality of wafer clamping units therebetween. Among them, the specific structure of each wafer clamping unit is as follows: A wafer cavity and an intermediate conduction cavity are provided on the intermediate plate, and the intermediate conduction cavity includes a first type of intermediate conduction cavity and a second type of intermediate conduction cavity; An upper electrode cavity and an upper conduction cavity are provided on the upper clamping plate; A lower electrode cavity and a lower conduction cavity are provided on the lower clamping plate; At least a part of the upper electrode cavity forms an up-down channel with the first type of intermediate conduction cavity and the lower conduction cavity; At least a part of the lower electrode cavity forms a down-up channel with the second type of intermediate conduction cavity and the upper conduction cavity. It is used to solve the problems of improving the coating accuracy of wafers and the automation of operations, and achieves the effects of multiple wafer styles, improving the coating accuracy, enhancing the operation efficiency, simplifying the process, and reducing the cost.
Need to check novelty before this filing date? Find Prior Art

Description

Technical Field

[0001] The present invention relates to the field of fixtures, and more particularly to a wafer production fixture. Background Art

[0002] With the rapid development of chips, the manufacturing of semiconductor components has also become an industry with rapidly expanding demand. The quartz crystal resonator is referred to as quartz crystal or crystal, crystal oscillator. As a necessary product to provide a stable time frequency signal in the circuit so that semiconductor components can work uniformly, its manufacturing process requirements are quite high. The crystal oscillator is a resonant device made using the piezoelectric effect of quartz crystal. Its basic structure is to cut a thin slice from a quartz crystal at a certain azimuth angle (the thin slice is referred to as a wafer, which can be square, rectangular or circular, etc.), apply a silver layer on its two corresponding surfaces as electrodes, weld a lead wire on each electrode and connect it to the pin, and then add a package shell to form a crystal oscillator. Since quartz crystal is an ionic crystal with a regular distribution of crystal lattices, when it undergoes mechanical deformation, such as stretching or compression, it can produce electric polarization, which is called piezoelectric phenomenon. The natural frequency of the piezoelectric effect of quartz crystal depends not only on its geometric size and cutting type, but also on the thickness of the chip. When a certain film layer is coated on the chip, the thickness of the chip increases, and the natural frequency of the chip will be attenuated accordingly. This effect of quartz crystal is the mass load effect.

[0003] In order to achieve accurate wafer coating in the prior art, workers need to place the wafer with a manual suction pen, which leads to low efficiency. However, if the manual operation is replaced by a robot that automatically places the wafer by sucking the wafer, the diameter of the positioning hole is very small, and it is difficult for the robot to accurately place the wafer in the positioning hole. Therefore, achieving accurate wafer coating automation has become a problem in the prior art. In the manufacturing process of crystal oscillators, since the thickness of the wafer directly affects the fundamental frequency, how to simplify the steps of silver coating, lead welding, and coating and ensure the thickness and flatness of the wafer has also become a problem that needs to be solved in this field.

[0004] How to simplify the crystal oscillator manufacturing process and reduce the manufacturing cost through the design of the wafer fixture is a technical problem that needs to be solved in this solution. Summary of the invention

[0005] The present invention aims to overcome at least one defect (shortcoming) of the above-mentioned prior art and provide a chip production fixture for solving the problems of simplifying the crystal oscillator manufacturing process, reducing manufacturing costs and improving the coating accuracy and operation automation of the chip.

[0006] The technical solution adopted by the present invention is a wafer production fixture, which includes an upper clamping plate, an intermediate plate, and a lower clamping plate. The intermediate plate is clamped between the upper clamping plate and the lower clamping plate and forms a plurality of wafer clamping units therebetween. The plurality of wafer clamping units are distributed in multiple regions, and each region includes an array formed by arranging several wafer clamping units. Among them, the specific structure of each wafer clamping unit is as follows: The intermediate plate is provided with a wafer cavity for accommodating the wafer and several intermediate conduction cavities distributed around the wafer cavity and communicating with the wafer cavity. The intermediate conduction cavities include a first type of intermediate conduction cavity and a second type of intermediate conduction cavity; The upper clamping plate is provided with an upper electrode cavity for electroplating to form an upper electrode sheet and an upper conduction cavity separated from the upper electrode cavity. The upper conduction cavity corresponds to the second type of intermediate conduction cavity; The lower clamping plate is provided with a lower electrode cavity for electroplating to form a lower electrode sheet and a lower conduction cavity separated from the lower electrode cavity. The lower conduction cavity corresponds to the first type of intermediate conduction cavity; At least a part of the upper electrode cavity is communicated with the first type of intermediate conduction cavity and the lower conduction cavity to form an up-and-down channel; At least a part of the lower electrode cavity is communicated with the second type of intermediate conduction cavity and the upper conduction cavity to form a down-and-up channel.

[0007] Further, the upper electrode cavity includes an upper main cavity and an upper extension cavity communicating with the upper main cavity. The area of the upper main cavity is smaller than that of the wafer cavity. The intermediate plate is clamped between the upper clamping plate and the lower clamping plate, and the upper main cavity does not exceed the wafer cavity. The upper extension cavity is communicated with the first type of intermediate conduction cavity and the lower conduction cavity to form an up-and-down channel; The lower electrode cavity includes a lower main cavity and a lower extension cavity communicating with the lower main cavity. The area of the lower main cavity is smaller than that of the wafer cavity. The intermediate plate is clamped between the upper clamping plate and the lower clamping plate, and the lower main cavity does not exceed the wafer cavity. The lower extension cavity is communicated with the second type of intermediate conduction cavity and the upper conduction cavity to form a down-and-up channel. This is beneficial to directly form leads between the fixtures, reduces the step of welding leads in the wafer manufacturing process, effectively improves the wafer manufacturing efficiency and reduces the wafer manufacturing cost.

[0008] Further, the outer contours of the upper extension cavity, the first type of intermediate conduction cavity, and the lower conduction cavity overlap vertically in part to form an up-and-down channel with the same cross-section; The outer contours of the lower extension cavity, the second type of intermediate conduction cavity, and the upper conduction cavity overlap vertically in part to form a down-and-up channel with the same cross-section. This is beneficial to the fact that when electrons flow inside the leads, the electron potential energy does not change.

[0009] Further, the area of the upper main cavity or the lower main cavity accounts for 1 / 2 to 9 / 10 of the area of the wafer cavity. This is beneficial to extending the service life of the leads in the wafer.

[0010] Further, the edges of the upper main cavity and the lower main cavity do not coincide with the edge of the wafer cavity. This is beneficial to reducing the influence of the leads on the fundamental frequency of the wafer.

[0011] Further, the shapes and layouts of the upper electrode cavity and the upper conduction cavity are the same as those of the lower electrode cavity and the lower conduction cavity, but in opposite directions or symmetrically. The same shapes of the positive and negative leads in opposite directions or symmetrically are beneficial to increasing the versatility of the leads and adapting to crystal oscillators of different specifications, improving the usage frequency of the fixture, and enhancing the production efficiency of the fixture.

[0012] Further, the wafer cavity and the middle conduction cavity are rectangular. The middle conduction cavity includes four parts that are symmetrically distributed at the four corners of the wafer cavity and partially overlap with the wafer cavity. The area of the overlapping part accounts for 1 / 4 to 1 / 2 of the area of the middle conduction cavity. The upper main cavity and the lower main cavity, the upper conduction cavity and the lower conduction cavity are rectangular. The areas of the upper conduction cavity and the lower conduction cavity are the same as and correspond to that of the middle conduction cavity. The upper extension cavity is L-shaped and includes a vertical part and a horizontal part that communicate with the upper main cavity. The area of the horizontal part is the same as and corresponds to that of the middle conduction cavity. The lower extension cavity is L-shaped and includes a vertical part and a horizontal part that communicate with the lower main cavity. The area of the horizontal part is the same as and corresponds to that of the middle conduction cavity. The upper extension cavity and the upper conduction cavity are diagonally arranged on the upper main cavity, and the lower extension cavity and the lower conduction cavity are diagonally arranged on the lower main cavity. The shapes and layouts of the upper electrode cavity and the upper conduction cavity are the same as those of the lower electrode cavity and the lower conduction cavity, and are symmetrically arranged with the center of the wafer cavity as the center, so that the first type of middle conduction cavity forming the upper and lower channels and the second type of middle conduction cavity forming the lower and upper channels are diagonally distributed on the wafer cavity. This is beneficial for the wafer to adapt to different frequencies and improve the production efficiency of the fixture.

[0013] Further, the wafer cavity and the middle conduction cavity are rectangular. The middle conduction cavity includes two parts that are adjacent to each other at two corners of the wafer cavity and partially overlap with the wafer cavity. The area of the overlapping part accounts for 1 / 4 to 1 / 2 of the area of the middle conduction cavity. The upper main cavity and the lower main cavity, the upper conduction cavity and the lower conduction cavity are rectangular. The areas of the upper conduction cavity and the lower conduction cavity are the same as and correspond to that of the middle conduction cavity. The upper extension cavity is L-shaped and includes a vertical part and a horizontal part that communicate with the upper main cavity. The area of the horizontal part is the same as and corresponds to that of the middle conduction cavity. The lower extension cavity is L-shaped and includes a vertical part and a horizontal part that communicate with the lower main cavity. The area of the horizontal part is the same as and corresponds to that of the middle conduction cavity. The upper extension cavity and the upper conduction cavity are arranged at adjacent corners on the upper main cavity, and the lower extension cavity and the lower conduction cavity are arranged at adjacent corners on the lower main cavity. The shapes and layouts of the upper electrode cavity and the upper conduction cavity are the same as those of the lower electrode cavity and the lower conduction cavity, and are axisymmetrically arranged with the center of the wafer cavity as the axis of symmetry, so that the first type of middle conduction cavity forming the upper and lower channels and the second type of middle conduction cavity forming the lower and upper channels are distributed at adjacent corners on the wafer cavity. This is beneficial for the wafer to adapt to different frequencies and improve the production efficiency of the fixture.

[0014] Further, guide grooves communicating with the wafer cavity are provided at the other two corners of the wafer cavity. This is beneficial for adapting to crystal oscillators that require multiple leads and improving the production efficiency of the fixture.

[0015] Furthermore, the wafer cavity and the intermediate conduction cavity are rectangular. The intermediate conduction cavity includes four parts that are symmetrically distributed at the four corners of the wafer cavity and partially overlap with the wafer cavity. The area of the overlapping part accounts for 1 / 4 to 1 / 2 of the area of the intermediate conduction cavity. It includes two adjacent upper conduction cavities, two adjacent lower conduction cavities, two adjacent upper extension cavities, and two adjacent lower extension cavities. The upper main cavity and the lower main cavity, the upper conduction cavity and the lower conduction cavity are rectangular. The areas of the upper conduction cavity and the lower conduction cavity are the same as and corresponding to that of the intermediate conduction cavity. The upper extension cavity is L-shaped and includes a vertical part and a horizontal part that communicate with the upper main cavity. The area of the horizontal part is the same as and corresponding to that of the intermediate conduction cavity. The lower extension cavity is L-shaped and includes a vertical part and a horizontal part that communicate with the lower main cavity. The area of the horizontal part is the same as and corresponding to that of the intermediate conduction cavity. The upper extension cavity and the upper conduction cavity are diagonally arranged on the upper main cavity. The lower extension cavity and the lower conduction cavity are diagonally arranged on the lower main cavity. The upper electrode cavity and the upper conduction cavity, and the lower electrode cavity and the lower conduction cavity have the same shape and layout and are symmetrically arranged with respect to the center axis of the wafer cavity, so that two first-type intermediate conduction cavities forming the upper and lower channels and two second-type intermediate conduction cavities forming the lower and upper channels are axially symmetrically distributed on the wafer cavity. This is beneficial for the wafer to adapt to different frequencies and improves the production efficiency of the fixture.

[0016] Compared with the prior art, the beneficial effects of the present invention are as follows: A through-hole fixture for placing wafers is formed by using multiple electrode plates, realizing the automatic placement of wafers in multiple wafer styles, improving the coating accuracy of wafers, enhancing the automation efficiency of operations, simplifying the manufacturing process, and reducing the manufacturing cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is an enlarged schematic diagram of the wafer cavity structure of the present invention.

[0018] Figure 2 It is a top electrode plan view of the first group of fixtures of a preferred embodiment of the present invention.

[0019] Figure 3 It is a bottom electrode plan view of the first group of fixtures of a preferred embodiment of the present invention.

[0020] Figure 4 It is a middle electrode plan view of the first group of fixtures of a preferred embodiment of the present invention.

[0021] Figure 5 It is a top electrode plan view of the second group of fixtures of a preferred embodiment of the present invention.

[0022] Figure 6 It is a bottom electrode plan view of the second group of fixtures of a preferred embodiment of the present invention.

[0023] Figure 7It is the plan view of the middle electrode of the second group of jigs in a preferred embodiment of the present invention.

[0024] Figure 8 It is the plan view of the upper electrode of the third group of jigs in a preferred embodiment of the present invention.

[0025] Figure 9 It is the plan view of the lower electrode of the third group of jigs in a preferred embodiment of the present invention.

[0026] Figure 10 It is the plan view of the middle electrode of the third group of jigs in a preferred embodiment of the present invention.

[0027] Figure 11 It is the plan view of the upper electrode of the fourth group of jigs in a preferred embodiment of the present invention.

[0028] Figure 12 It is the plan view of the lower electrode of the fourth group of jigs in a preferred embodiment of the present invention.

[0029] Figure 13 It is the plan view of the middle electrode of the fourth group of jigs in a preferred embodiment of the present invention.

[0030] Explanation of the attached drawing reference numerals: upper clamping plate 100, upper electrode cavity 110, upper main cavity 111, upper extension cavity 112, upper conduction cavity 120, middle plate 200, first type of middle conduction cavity 210, second type of middle conduction cavity 220, lower clamping plate 300, lower electrode cavity 310, lower main cavity 311, lower extension cavity 312, lower conduction cavity 320. Detailed implementation manners

[0031] The attached drawings of the present invention are only for illustrative purposes and should not be construed as a limitation to the present invention. To better illustrate the following embodiments, some components in the attached drawings will be omitted, enlarged or reduced, which do not represent the dimensions of the actual product; for those skilled in the art, it is understandable that some well-known structures and their descriptions in the attached drawings may be omitted.

[0032] Embodiment 1

[0033] As Figure 1As shown, the wafer production fixture of this embodiment is used to hold a wafer for a double-anchor silver-plated electrode layer. The fixture is divided into three layers, namely an upper clamping plate 100, an intermediate plate 200, and a lower clamping plate 300. The thicknesses of both the upper clamping plate 100 and the lower clamping plate 300 are 0.15 mm, and the thickness of the intermediate plate 200 is 0.07 mm. The intermediate plate 300 is clamped between the upper clamping plate 100 and the lower clamping plate 300, and a plurality of wafer clamping units are formed therebetween. The plurality of wafer clamping units are distributed in multiple regions, and each region includes an array formed by arranging a number of wafer clamping units. Among them, the specific structure of each wafer clamping unit is as follows: A wafer cavity for accommodating the wafer and a number of intermediate conduction cavities distributed around the wafer cavity and communicating with the wafer cavity are provided on the intermediate plate 200. The intermediate conduction cavities include a first type of intermediate conduction cavity 210 and a second type of intermediate conduction cavity 220; An upper electrode cavity 110 for electroplating to form an upper electrode sheet and an upper conduction cavity 120 separated from the upper electrode cavity 110 are provided on the upper clamping plate 100. The upper conduction cavity 120 corresponds to the second type of intermediate conduction cavity 220; A lower electrode cavity 310 for electroplating to form a lower electrode sheet and a lower conduction cavity 320 separated from the lower electrode cavity 310 are provided on the lower clamping plate 300. The lower conduction cavity 320 corresponds to the first type of intermediate conduction cavity 210; At least a part of the upper electrode cavity 110 is communicated with the first type of intermediate conduction cavity 210 and the lower conduction cavity 320 to form an upper-lower channel 410; At least a part of the lower electrode cavity 310 is communicated with the second type of intermediate conduction cavity 220 and the upper conduction cavity 120 to form a lower-upper channel 420.

[0034] The upper electrode cavity 110 includes an upper main cavity 111 and an upper extension cavity 112. The area of the upper main cavity 111 is smaller than that of the wafer cavity. The intermediate plate 200 is clamped between the upper clamping plate 100 and the lower clamping plate 300, and the upper main cavity 111 does not extend beyond the wafer cavity. The upper extension cavity 112 is communicated with the first type of intermediate conduction cavity 210 and the lower conduction cavity 320 to form an upper-lower channel 410. The lower electrode cavity 310 includes a lower main cavity 311 and a lower extension cavity 312 communicated with the lower main cavity 311. The area of the lower main cavity 311 is smaller than that of the wafer cavity. The intermediate plate 200 is clamped between the upper clamping plate 100 and the lower clamping plate 300, and the lower main cavity 311 does not extend beyond the wafer cavity. The lower extension cavity 312 is communicated with the second type of intermediate conduction cavity 220 and the upper conduction cavity 120 to form a lower-upper channel 420. In this embodiment, the upper-lower channel 410 is used to restrict the flow direction of the electrode material silver to form a positive lead connected to the wafer cavity, and the lower-upper channel 420 is used to restrict the flow direction of the electrode material silver to form a negative lead connected to the wafer.

[0035] The upper extension cavity 112, the first type of intermediate conduction cavity 210, and the lower conduction cavity 320 have overlapping outer contours up and down, forming an upper and lower channel 410 with the same cross-section; the lower extension cavity 312, the second type of intermediate conduction cavity 220, and the upper conduction cavity 120 have overlapping outer contours up and down, forming a lower and upper channel 420 with the same cross-section. In this embodiment, since the cross-sectional area of the end of the upper and lower channel 410 is the same as that of its root, when the electrode material silver is applied and flows through the upper and lower channel 410, the formed positive lead has a consistent wire width from the port to the root, and the cross-sectional area does not change. After power-on, when electrons flow from the end to the root in the positive lead, their electron potential energy does not change.

[0036] The area of the upper main cavity 111 or the lower main cavity 311 accounts for 1 / 2 to 9 / 10 of the area of the wafer cavity. In this embodiment, the areas of the upper main cavity 111 and the lower main cavity 311 are equal, but both are slightly smaller than the area of the wafer cavity. The area sizes of the upper main cavity 111 and the lower main cavity 311 replace the bonding point sizes of the two leads in the prior art, but they extend the service life of the lead bonding.

[0037] The edges of the upper main cavity 111 and the lower main cavity 311 do not coincide with the edges of the wafer cavity. In this embodiment, the connecting edge of the upper main cavity 111 and the wafer cavity is covered by the vertical and horizontal parts of the upper extension cavity 112. Correspondingly, the connecting edge of the lower main cavity 311 and the wafer cavity is covered by the vertical and horizontal parts of the lower extension cavity 312. When the edge of the upper main cavity 111 or the lower main cavity 311 coincides with the edge of the wafer cavity, it may increase the thickness of the wafer, thus affecting the vibration of the wafer.

[0038] The upper electrode cavity 110 and the upper conduction cavity 120 have the same shape and layout as the lower electrode cavity 310 and the lower conduction cavity 320, but in opposite or symmetric directions. In this embodiment, as Figures 2 to 4 shown, the upper electrode cavity, the upper conduction cavity have the same shape and layout as the lower electrode cavity, the lower conduction cavity, but the two are diagonally symmetric in direction; as Figures 5 to 7 shown, the upper electrode cavity, the upper conduction cavity have the same shape and layout as the lower electrode cavity, the lower conduction cavity, but the two are symmetric up and down in direction; as Figures 8 to 10 shown, the upper electrode cavity, the upper conduction cavity have the same shape and layout as the lower electrode cavity, the lower conduction cavity, but the two are symmetric left and right in direction; as Figures 11 to 13 shown, the upper electrode cavity, the upper conduction cavity have the same shape and layout as the lower electrode cavity, the lower conduction cavity, but the two are symmetric up and down in direction.

[0039] The wafer cavity and the intermediate conduction cavity are rectangular. The intermediate conduction cavity includes four, symmetrically distributed at the four corners of the wafer cavity, and partially overlaps with the wafer cavity. The area of the overlapping part accounts for 1 / 4 to 1 / 2 of the area of the intermediate conduction cavity. The upper main cavity 111 and the lower main cavity 311, the upper conduction cavity 120 and the lower conduction cavity 320 are rectangular. The areas of the upper conduction cavity 120 and the lower conduction cavity 320 are the same as and correspond to that of the intermediate conduction cavity. The lower extension cavity 312 is L-shaped, including a vertical part and a horizontal part communicating with the lower main cavity 311. The area of the horizontal part is the same as and corresponds to that of the intermediate conduction cavity. The upper extension cavity 112 and the upper conduction cavity 120 are diagonally arranged on the upper main cavity 111. The lower extension cavity 312 and the lower conduction cavity 320 are diagonally arranged on the lower main cavity 311. The upper electrode cavity 110 and the upper conduction cavity 120, and the lower electrode cavity 310 and the lower conduction cavity 320 have the same shape and layout, and are symmetrically arranged with the center of the wafer cavity as the symmetry axis, so that the first type of intermediate conduction cavity 210 forming the up-down channel 410 and the second type of intermediate conduction cavity 220 forming the down-up channel 420 are diagonally distributed on the wafer cavity. In this embodiment, when the wafer is subjected to mechanical pressure, the potential difference generated by it due to the piezoelectric effect is affected by the lead distance at the diagonal position. As Figures 2 to 4 shown, the leads of the wafer are located at the diagonal positions, and the lead distance is approximately 1.64 mm, which is the diagonal distance of a rectangle with a length of 1.3 mm and a width of 1 mm for the wafer.

[0040] The wafer cavity and the intermediate conduction cavity are rectangular. The intermediate conduction cavity includes two, adjacent to each other at two corners of the wafer cavity, and () partially overlaps with the wafer cavity. The area of the overlapping part accounts for 1 / 4 to 1 / 2 of the area of the intermediate conduction cavity. The upper main cavity 111 and the lower main cavity 311, the upper conduction cavity 120 and the lower conduction cavity 320 are rectangular. The areas of the upper conduction cavity 120 and the lower conduction cavity 320 are the same as and correspond to that of the intermediate conduction cavity. The upper extension cavity 112 is L-shaped, including a vertical part and a horizontal part communicating with the upper main cavity 111. The area of the horizontal part is the same as and corresponds to that of the intermediate conduction cavity. The lower extension cavity 312 is L-shaped, including a vertical part and a horizontal part communicating with the lower main cavity 311. The area of the horizontal part is the same as and corresponds to that of the intermediate conduction cavity. The upper extension cavity 112 and the upper conduction cavity 120 are adjacent to each other at the upper main cavity 111. The lower extension cavity 312 and the lower conduction cavity 320 are adjacent to each other at the lower main cavity 311. The upper electrode cavity 110 and the upper conduction cavity 120, and the lower electrode cavity 310 and the lower conduction cavity 320 have the same shape and layout, and are axially symmetrically arranged with the center of the wafer cavity as the symmetry axis, so that the first type of intermediate conduction cavity 210 forming the up-down channel 410 and the second type of intermediate conduction cavity 220 forming the down-up channel 420 are adjacent to each other at the wafer cavity. In this embodiment, as Figures 5 to 7As shown, the leads of the wafer are located at the adjacent corners of the long side, and the lead distance is 1.3 mm of the length of a rectangle with a length of 1.3 mm and a width of 1 mm of the wafer.

[0041] Two other corners of the wafer cavity are provided with guide grooves communicating with the wafer cavity. In this embodiment, as Figure 4 and 5 shown, the guide grooves are arranged at the adjacent corners of the long side or the adjacent corners of the short side of the wafer cavity, and the guide grooves are used to introduce the electrode material silver as the other two leads of the wafer. To adapt to a crystal oscillator that requires four pins.

[0042] The wafer cavity and the middle conduction cavity are rectangular. The middle conduction cavity includes four, symmetrically distributed at the four corners of the wafer cavity, and partially overlaps with the wafer cavity. The overlapping area accounts for 1 / 4 to 1 / 2 of the area of the middle conduction cavity; it includes two adjacent upper conduction cavities 120, two adjacent lower conduction cavities 320, two adjacent upper extension cavities 112 and two adjacent lower extension cavities 312; the upper main cavity 111 and the lower main cavity 311, the upper conduction cavity 120 and the lower conduction cavity 320 are rectangular, and the areas of the upper conduction cavity 120 and the lower conduction cavity 320 are the same as and correspond to those of the middle conduction cavity; the upper extension cavity 112 is L-shaped, including a vertical part and a horizontal part communicating with the upper main cavity 111, and the area of the horizontal part is the same as and corresponds to that of the middle conduction cavity; the lower extension cavity 312 is L-shaped, including a vertical part and a horizontal part communicating with the lower main cavity 311, and the area of the horizontal part is the same as and corresponds to that of the middle conduction cavity; the upper extension cavity 112 and the upper conduction cavity 120 are diagonally arranged on the upper main cavity 111, the lower extension cavity 312 and the lower conduction cavity 320 are diagonally arranged on the lower main cavity 311, and the upper electrode cavity 110 and the upper conduction cavity 120, and the lower electrode cavity 310 and the lower conduction cavity 320 have the same shape and layout, and are symmetrically arranged with respect to the center axis of the wafer cavity, so that two first-type middle conduction cavities 210 forming the upper and lower channels 410 and two second-type middle conduction cavities 220 forming the lower and upper channels 420 are axially symmetrically distributed on the wafer cavity. In this embodiment, as Figures 8 to 10 shown, the leads of the wafer are located at the adjacent corners of the long side, and the lead distance is 1.3 mm of the length of a rectangle with a length of 1.3 mm and a width of 1 mm of the wafer; as Figures 11 to 13 shown, the leads of the wafer are located at the adjacent corners of the short side, and the lead distance is 1 mm of the length of a rectangle with a length of 1.3 mm and a width of 1 mm of the wafer.

[0043] Embodiment 2

[0044] In this embodiment, the electrode material of the wafer is silver. Since silver has a very low contact resistance and excellent plastic deformation property, it is the preferred electrode material. The electrode type of the wafer is double-anchor because the double-anchor can focus energy on the center of the wafer and maximize the stability and lifespan of the wafer. The double-anchor is of the sputtering type. The film layer of the silver-plated wafer is selected as a high-stress film layer, such as film layers of Ni, Cr, Mo, Zr, Ni-Cr, Ti, stainless steel, etc.

[0045] To ensure the lifespan of the wafer, use tweezers to hold the edge of the wafer and do not touch the center of the wafer with fingers to avoid leaving oil stains, which will otherwise reduce the vibration ability of the wafer. Soak the new wafer in analytical pure for 1 minute before use, then use plastic tweezers and wipe off the analytical pure with lint-free paper or a clean silk cloth. At the same time, wipe the fixture with lint-free paper or silk cloth dipped in alcohol. Before assembling the wafer, use a balloon to blow off any possible residual dust on the wafer and the fixture. Any particles or ash layers between the wafer and the fixture will affect the electrical contact and generate stress points, thus changing the crystal vibration mode. After the wafer is assembled, use the balloon to blow the surface of the wafer again to remove the scattered dust.

[0046] After the crystal oscillator socket is coated multiple times, a relatively thick film will be deposited on its surface. If it is not removed, the reverse sputtering caused by ion bombardment will affect the test accuracy of the crystal oscillator wafer. The film layer can be removed first by sandblasting or using sandpaper, and then soaked in alcohol for about 5 minutes. If it can be ultrasonically cleaned, the effect will be better. Finally, bake it in an oven at 110°C for 15 minutes and then it can be used.

[0047] During the process of depositing the coating film, note that after the film layer on the wafer reaches a certain thickness, a new wafer should be replaced because the thicker the film layer, the lower the fundamental frequency of the crystal oscillator will be. If the decrease is too much, the crystal oscillator will have a frequency hopping phenomenon and cannot work stably. If the deposition continues, there will be a phenomenon of oscillation stop. In addition to replacing the wafer due to too thick a deposited film layer, a new wafer also needs to be replaced when the evaporation rate shows a significant abnormality or there is obvious film layer peeling or flaking on the surface of the wafer. Keeping sufficient cooling water to keep the temperature of the crystal oscillator head in the range of 20 - 50 degrees is better.

[0048] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the technical solutions of the present invention and are not limitations on the specific implementation manners of the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the claims of the present invention shall be included within the protection scope of the claims of the present invention.

Claims

1. A wafer production fixture, comprising an upper clamping plate (100), an intermediate plate (200) and a lower clamping plate (300). The intermediate plate (200) is clamped between the upper clamping plate (100) and the lower clamping plate (300) and forms a plurality of wafer clamping units therebetween. The plurality of wafer clamping units are distributed in multiple regions, and each region includes an array formed by arranging a plurality of wafer clamping units. It is characterized in that, The specific structure of each wafer clamping unit is as follows: On the middle plate (200), a wafer cavity for accommodating a wafer and a number of middle conduction cavities distributed around the wafer cavity and communicating with the wafer cavity are provided. The middle conduction cavities include a first type of middle conduction cavity (210) and a second type of middle conduction cavity (220); On the upper clamping plate (100), an upper electrode cavity (110) for electroplating to form an upper electrode sheet and an upper conduction cavity (120) separated from the upper electrode cavity (110) are provided. The upper conduction cavity (120) corresponds to the second type of middle conduction cavity (220); On the lower clamping plate (300), a lower electrode cavity (310) for electroplating to form a lower electrode sheet and a lower conduction cavity (320) separated from the lower electrode cavity (310) are provided. The lower conduction cavity (320) corresponds to the first type of middle conduction cavity (210); The upper electrode cavity (110) includes an upper main cavity (111) and an upper extension cavity (112) communicating with the upper main cavity (111). The area of the upper main cavity (111) is smaller than that of the wafer cavity. The upper extension cavity (112) communicates with the first type of middle conduction cavity (210) and the lower conduction cavity (320) to form an up-down channel (410); The lower electrode cavity (310) includes a lower main cavity (311) and a lower extension cavity (312) communicating with the lower main cavity (311). The area of the lower main cavity (311) is smaller than that of the wafer cavity. The lower extension cavity (312) communicates with the second type of middle conduction cavity (220) and the upper conduction cavity (120) to form a down-up channel (420); The outer contours of the upper extension cavity (112), the first type of middle conduction cavity (210), and the lower conduction cavity (320) overlap vertically in part to form an up-down channel (410) with the same cross-section; The outer contours of the lower extension cavity (312), the second type of middle conduction cavity (220), and the upper conduction cavity (120) overlap vertically in part to form a down-up channel (420) with the same cross-section; The area of the upper main cavity (111) or the lower main cavity (311) accounts for 1 / 2 to 9 / 10 of the area of the wafer cavity; The edges of the upper main cavity (111) and the lower main cavity (311) do not coincide with the edges of the wafer cavity; 2. The wafer production fixture according to claim 1, characterized in that, The upper electrode cavity (110) and the upper conduction cavity (120) have the same shape and layout as the lower electrode cavity (310) and the lower conduction cavity (320), but in opposite directions or symmetrically; 3. The wafer production fixture according to claim 1 or 2, characterized in that, The wafer cavity and the middle conduction cavities are rectangular. The middle conduction cavities include four, symmetrically distributed at the four corners of the wafer cavity and partially overlapping with the wafer cavity. The overlapping area accounts for 1 / 4 to 1 / 2 of the area of the middle conduction cavity; The upper main cavity (111) and the lower main cavity (311), the upper conduction cavity (120) and the lower conduction cavity (320) are rectangular. The areas of the upper conduction cavity (120) and the lower conduction cavity (320) are the same as and correspond to those of the middle conduction cavity; The upper extension cavity (112) is L-shaped, including a vertical part and a horizontal part communicating with the upper main cavity (111). The area of the horizontal part is the same as and corresponds to that of the middle conduction cavity; The lower extension cavity (312) is L-shaped and includes a vertical portion and a horizontal portion that communicate with the lower main cavity (311). The area of the horizontal portion is the same as and corresponds to that of the middle conduction cavity. The upper extension cavity (112) and the upper conduction cavity (120) are diagonally arranged on the upper main cavity (111), and the lower extension cavity (312) and the lower conduction cavity (320) are diagonally arranged on the lower main cavity (311). The upper electrode cavity (110) and the upper conduction cavity (120), and the lower electrode cavity (310) and the lower conduction cavity (320) have the same shape and layout and are symmetrically arranged with respect to the center of the wafer cavity, so that the first type of middle conduction cavity (210) forming the up and down channels (410) and the second type of middle conduction cavity (220) forming the down and up channels (420) are diagonally distributed on the wafer cavity.

4. The wafer production fixture according to claim 1 or 2, characterized in that, The wafer cavity and the middle conduction cavity are rectangular. The middle conduction cavity includes two, which are adjacent and distributed at two corners of the wafer cavity and partially overlap with the wafer cavity. The area of the overlapping portion accounts for 1 / 4 to 1 / 2 of the area of the middle conduction cavity. The upper main cavity (111) and the lower main cavity (311), and the upper conduction cavity (120) and the lower conduction cavity (320) are rectangular. The areas of the upper conduction cavity (120) and the lower conduction cavity (320) are the same as and correspond to that of the middle conduction cavity. The upper extension cavity (112) is L-shaped and includes a vertical portion and a horizontal portion that communicate with the upper main cavity (111). The area of the horizontal portion is the same as and corresponds to that of the middle conduction cavity. The lower extension cavity (312) is L-shaped and includes a vertical portion and a horizontal portion that communicate with the lower main cavity (311). The area of the horizontal portion is the same as and corresponds to that of the middle conduction cavity. The upper extension cavity (112) and the upper conduction cavity (120) are arranged at adjacent corners on the upper main cavity (111), and the lower extension cavity (312) and the lower conduction cavity (320) are arranged at adjacent corners on the lower main cavity (311). The upper electrode cavity (110) and the upper conduction cavity (120), and the lower electrode cavity (310) and the lower conduction cavity (320) have the same shape and layout and are axially symmetrically arranged with respect to the center of the wafer cavity, so that the first type of middle conduction cavity (210) forming the up and down channels (410) and the second type of middle conduction cavity (220) forming the down and up channels (420) are distributed at adjacent corners on the wafer cavity.

5. The wafer production fixture according to claim 4, characterized in that, Guide grooves communicating with the wafer cavity are provided at the other two corners of the wafer cavity.

6. The wafer production fixture according to claim 1 or 2, characterized in that, The wafer cavity and the middle conduction cavity are rectangular. The middle conduction cavity includes four, which are symmetrically distributed at the four corners of the wafer cavity and partially overlap with the wafer cavity. The area of the overlapping portion accounts for 1 / 4 to 1 / 2 of the area of the middle conduction cavity. It includes two adjacent upper conduction cavities (120), two adjacent lower conduction cavities (320), two adjacent upper extension cavities (112) and two adjacent lower extension cavities (312). The upper main cavity (111) and the lower main cavity (311), and the upper conduction cavity (120) and the lower conduction cavity (320) are rectangular. The areas of the upper conduction cavity (120) and the lower conduction cavity (320) are the same as and correspond to that of the middle conduction cavity. The upper extension cavity (112) is in an L shape and includes a vertical part and a horizontal part that communicate with the upper main cavity (111). The area of the horizontal part is the same as and corresponds to that of the middle conduction cavity. The lower extension cavity (312) is in an L shape and includes a vertical part and a horizontal part that communicate with the lower main cavity (311). The area of the horizontal part is the same as and corresponds to that of the middle conduction cavity. The upper extension cavity (112) and the upper conduction cavity (120) are diagonally arranged on the upper main cavity (111), and the lower extension cavity (312) and the lower conduction cavity (320) are diagonally arranged on the lower main cavity (311). The upper electrode cavity (110) and the upper conduction cavity (120) have the same shape and layout as the lower electrode cavity (310) and the lower conduction cavity (320), and are symmetrically arranged with respect to the center axis of the wafer cavity, so that the two first-type middle conduction cavities (210) forming the upper and lower channels (410) and the two second-type middle conduction cavities (220) forming the lower and upper channels (420) are axially symmetrically distributed on the wafer cavity.

Citation Information

Patent Citations

  • Quartzy wafer plate film fixture

    CN206736353U