A test system for both chip performance test and function verification

Abstract

The application discloses a chip performance test and function verification dual-purpose test system, which comprises a crimping connector and a system circuit board, a test adapter circuit board is arranged at the upper end of the crimping connector, a plurality of crimping pins are arranged at the lower end of the crimping connector, each of the crimping pins is provided with a first contact part and a second contact part which are distributed along the length direction of the crimping pin, the test adapter circuit board is electrically connected with the plurality of crimping pins, a plurality of through holes are formed in the system circuit board and correspond to the plurality of crimping pins, an upper signal through hole and a lower signal through hole which are spaced from each other are arranged in each of the through holes, the upper signal through hole is used for electrically connecting a chip to be tested, and the lower signal through hole is used for electrically connecting a detection chip. In the technical scheme, two contact parts are arranged on one crimping pin, and two signal through holes which are relatively arranged and are used for connecting signals are formed on the system circuit board, so that the performance test and the function verification can be simultaneously tested and verified.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip testing, in particular to a chip performance testing and function verification dual-purpose testing system. BACKGROUND

[0002] In recent years, the electrical characteristic testing technology of chips has developed rapidly, and chip testing is divided into function testing and performance testing. The usual way of high-speed channel performance testing is to develop a separate chip electrical characteristic testing board, then connect the high-speed interface of the chip to the radio frequency testing connector through the PCB wiring, and then connect the connector to the network analyzer to detect the high-speed interface performance of the chip through the network analyzer; while the function testing is to directly interconnect two chips that realize functions, and then verify the physical channel logic function.

[0003] However, the existing testing method cannot simultaneously perform performance testing and function testing. Therefore, the vulnerabilities in performance testing and function testing cannot be verified with each other, and the performance verification and function verification schemes are separated, which is not conducive to troubleshooting. SUMMARY

[0004] The main purpose of the present application is to provide a chip performance testing and function verification dual-purpose testing system, which can simultaneously perform chip performance testing and function verification.

[0005] To achieve the above purpose, the chip performance testing and function verification dual-purpose testing system provided by the present application comprises:

[0006] A compression connector is provided, wherein the upper end of the compression connector is provided with a testing adapter circuit board, the lower end of the compression connector is provided with a plurality of compression pins, each of the compression pins is provided with a first contact portion and a second contact portion distributed along the length direction of the compression pin, and the testing adapter circuit board is electrically connected with the plurality of compression pins; and

[0007] A system circuit board is provided, wherein a plurality of through holes are formed on the system circuit board corresponding to the plurality of compression pins, each of the through holes is provided with an upper signal through hole and a lower signal through hole which are spaced apart from each other, the upper signal through hole is used to electrically connect a chip to be tested, and the lower signal through hole is used to electrically connect a detection chip.

[0008] Among them, each of the compression pins can move relative to the system circuit board, each of the compression pins has a first position and a second position in its moving stroke, at the first position, only the first contact portion of the compression pin can be inserted into the upper signal through hole to be electrically connected, at the second position, the first contact portion of the compression pin can be inserted into the lower signal through hole to be electrically connected, and the second contact portion of the compression pin can be inserted into the upper signal through hole to be electrically connected.

[0009] Preferably, the crimp connector is inserted into the lower end of the test adapter circuit board.

[0010] Preferably, the crimp connector comprises a male crimp connector and a female crimp connector, the female crimp connector is inserted into the lower end of the male crimp connector.

[0011] The test adapter circuit board is installed on the upper end of the male crimp connector, and the plurality of crimp pins are installed on the lower end of the female crimp connector.

[0012] Preferably, the female crimp connector and the male crimp connector are electrically connected through the plug-in connector.

[0013] Preferably, the system circuit board comprises an upper PCB and a lower PCB, the upper PCB and the lower PCB are pressed together.

[0014] The upper signal via is provided in the upper PCB, and the lower signal via is provided in the lower PCB.

[0015] Preferably, a radio frequency connector is installed on the upper end of the test adapter circuit board, the radio frequency connector is electrically connected to the test adapter circuit board, and the radio frequency connector is used to test the performance of the chip by externally connecting a network analyzer.

[0016] Preferably, the radio frequency connector is electrically connected to an oscilloscope to observe the performance of the chip to be tested.

[0017] Preferably, the crimp pin comprises a pin column and two abutting protrusions protruding from the side surface of the pin column, the first contact part is provided with a first abutting protrusion, and the second contact part is provided with a second abutting protrusion.

[0018] Preferably, the system circuit board is provided with a plurality of ground vias, and the plurality of ground vias are arranged close to the plurality of signal vias.

[0019] Preferably, the material of the crimp pin comprises copper material.

[0020] In the technical scheme of the present application, a test system for chip performance test and function verification is provided, two contact parts are arranged on a crimping pin, the first contact part and the second contact part are arranged in sequence along the axial direction of the crimping pin, correspondingly, the chip to be tested is connected to the system circuit board, the system circuit board is formed with signal vias corresponding to the crimping pin, a plurality of upper signal holes are formed on the inner edge upper end of the signal via, and a plurality of lower signal holes are formed on the inner edge lower end of the signal via, when the system performs performance test, the crimping pin is partially inserted into the signal via, and the first contact part is in contact with the upper signal hole; when the system performs function verification, the crimping pin is completely inserted into the signal via, the first contact part is in contact with the lower signal hole, and the second contact part is in contact with the upper signal hole, so as to realize the interconnection of the chip to be tested and the detection chip. BRIEF DESCRIPTION OF DRAWINGS

[0021] In order to more clearly illustrate the technical scheme in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced below, and obviously, the drawings in the following description can obtain other drawings from the structures shown in the drawings without creative labor for those skilled in the art.

[0022] Figure 1 FIG. 1 is a perspective structural schematic view of an embodiment of the chip performance test and function verification dual-purpose test system provided by the present application;

[0023] Figure 2 FIG. 2 is a partial enlarged view of the upper signal via and the lower signal via in FIG. 1; Figure 1

[0024] Figure 3 FIG. 3 is a perspective structural schematic view of the crimping pin in FIG. 1. Figure 1

[0025] Explanation of reference numerals:

[0026]

[0027] The implementation, functional features and advantages of the present application will be further described with reference to the embodiments and the accompanying drawings. DETAILED DESCRIPTION

[0028] The technical scheme in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the protection scope of the present application. ​​

[0029] It should be noted that all directional indications, such as upper, lower, left, right, front, back, and the like, are only used to explain the relative position relationship, movement condition and the like between components in a certain specific posture (as shown in the drawings), and if the specific posture changes, the directional indications will also change accordingly.

[0030] In addition, the description involving "first", "second" and the like in the present application is only for the purpose of description, and cannot be understood as indicating or implying the relative importance of the indicated technical features or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include at least one of the features. In addition, the technical solutions of each embodiment can be combined with each other, but it must be based on the realization of ordinary skilled in the art, when the combination of technical solutions appears contradictory or cannot be realized, it should be considered that the combination of technical solutions does not exist, nor within the protection scope required by the present application.

[0031] In recent years, the electrical property test technology of chip has developed rapidly, and chip test is divided into function test and performance test. The usual way of high-speed channel performance test is to develop a separate chip electrical property test board, then connect the high-speed interface of the chip to the RF test connector through the PCB wiring, and then connect the connector to the network analyzer, and detect the high-speed interface performance of the chip through the network analyzer. The function test is to directly interconnect two chips that realize the function, and then verify the physical channel logic function.

[0032] However, the existing test method cannot perform performance test and function test at the same time. Therefore, the vulnerabilities in performance test and function test cannot be verified with each other, and the performance verification and function verification schemes are separated, which is not conducive to troubleshooting.

[0033] To solve the above problems, the present application provides a chip performance test and function verification dual-purpose test system 1000, which aims to provide a system that can simultaneously perform chip performance test and function verification, Figures 1 to 3 The structural schematic diagram of an embodiment of the chip performance test and function verification dual-purpose test system 1000 provided by the present application.

[0034] Please refer to Figures 1 to 3The application provides a chip performance test and function verification dual-purpose test system 1000, which comprises a crimp connector 1, a test adapter circuit board 2 arranged at the upper end of the crimp connector 1 and a system circuit board 4.

[0035] Specifically, the system circuit board 4 is electrically connected with the chip to be tested, the crimp connector 1 is lowered so that the first contact portions 52 of the plurality of crimp pins 5 are respectively inserted into the plurality of upper signal vias 41 on the system circuit board 4, the crimp connector 1 feeds back test signals to the radio frequency connector 3 through the test adapter circuit board 2, and the radio frequency connector 3 is externally connected with an oscilloscope, so that the signal quality of the chip to be tested can be observed from the oscilloscope to realize performance test of the chip to be tested.

[0036] The chip to be tested is electrically connected with the upper signal vias 41 of the system circuit board 4, the detection chip is electrically connected with the lower signal vias 42, each first contact portion 52 and each second contact portion 51 of each crimp pin 5 is respectively in contact with each lower signal via 42 and each upper signal via 41, the plurality of crimp pins 5 are used to realize interconnection between the chip to be tested and the detection chip, so as to realize function verification of the chip to be tested.

[0037] In order to install the crimp connector 1, the crimp connector 1 is inserted into the lower end of the test adapter circuit board 2, the protrusion formed on the crimp connector 1 is inserted into the groove arranged opposite to the test adapter circuit board 2, so that the crimp connector 1 is fixed, and when the crimp connector 1 needs to be replaced, the crimp connector 1 can be disassembled and replaced by being taken out of the groove of the test adapter circuit board 2.

[0038] For further reference Figure 1The crimping connector includes a male crimping connector 11 and a female crimping connector 12 which is inserted into the lower end of the male crimping connector 11. The upper end of the male crimping connector 11 is provided with the test adapter circuit board 2 and is electrically connected to the male crimping connector 11 to transmit test signals. The lower end of the female crimping connector 12 is provided with a plurality of crimping pins 5. Each crimping pin 5 corresponds to a different test signal.

[0039] It should be noted that the crimping pins 5 can be integrally provided with the female crimping connector 12 or connected to the female crimping connector 12 through an insertion structure. The present application does not limit this. In an embodiment of the present application, the crimping pins 5 are integrally provided with the female crimping connector 12 through welding. This simple and stable structure can prevent the crimping pins 5 from deforming or breaking when they are tested vertically.

[0040] To transmit test signals from the chip under test to an oscilloscope during performance testing, the female crimping connector 12 is electrically connected to the male crimping connector 11 through an insertion connector. When the crimping pins 5 are in the first position, the first contact part 52 of the crimping pin 5 is electrically connected to the upper signal via hole 41. The test signal is transmitted to the first contact part 52 of the crimping pin 5 through the upper signal via hole 41 and then transmitted to the female crimping connector 12 from the crimping pin 5. The male crimping connector 11 is electrically connected to the female crimping connector 12. The signal is transmitted to the test adapter circuit board 2 through the crimping connector 1 and then observed by the oscilloscope through the radio frequency connector 3 on the test adapter circuit board 2 to test the performance of the chip under test.

[0041] To further optimize the production process of the system circuit board 4, the system circuit board 4 includes an upper PCB and a lower PCB which are pressed together. The upper signal via hole 41 is provided in the upper PCB and the lower signal via hole 42 is provided in the lower PCB. This structure reduces the complexity of the process, optimizes the structure of the system circuit board 4, reduces the production cost of the process, simplifies the process flow, and improves the manufacturing yield.

[0042] In order to connect the test display device to the chip performance test and function verification dual-purpose test system 1000, a radio frequency connector 3 is arranged on the upper end of the test adapter circuit board 2, the radio frequency connector 3 is electrically connected to the test adapter circuit board 2, the radio frequency connector 3 is used to test the chip performance by connecting to a network analyzer, when the test signal is transmitted to the crimp connector 1, the test signal is transmitted from the crimp connector 1 to the test adapter circuit board 2 on the upper end, the test adapter circuit board 2 transmits the signal to the radio frequency connector 3 arranged on the upper end of the test adapter circuit board 2, and the radio frequency connector 3 transmits the test signal to the external device to analyze the chip performance.

[0043] In order to facilitate the test personnel to observe the performance test results of the chip to be tested, the radio frequency connector 3 is connected to an oscilloscope, the oscilloscope can convert the test electrical signal of the chip to be tested into a visible image, so as to facilitate the test personnel to study the change process of the test signal, and then judge the performance of the chip to be tested through the change process of the test signal.

[0044] In order to perform function verification on the chip to be tested, the crimping pin 5 can be inserted into the upper signal via hole 41 and the lower signal via hole 42 at the same time, the crimping pin 5 includes a pin column 53 and two abutting protrusions protruding from the side surface of the pin column 53, specifically, please further refer to Figure 3 , the first contact part 52 and the second contact part 51 respectively include a first abutting protrusion 511 and a second abutting protrusion 521, when the chip to be tested is subjected to function verification, the first abutting protrusion 521 of the first contact part 52 is inserted into the lower signal via hole 42, and the second abutting protrusion 511 of the second contact part 51 is inserted into the upper signal via hole 41, so as to realize interconnection of the chip to be tested and the detection chip, and then perform function verification on the chip to be tested.

[0045] In order to protect the system circuit board 4, a plurality of ground via holes 43 are arranged in the system circuit board 4, the plurality of ground via holes 43 are arranged close to the plurality of signal via holes, and the plurality of ground via holes 43 are used to dissipate heat of the system circuit board 4 and eliminate damage of static electricity to the system circuit board 4, so that the plurality of ground via holes 43 are arranged to protect the system circuit board 4.

[0046] It should be noted that the material of the crimping pin 5 can be copper material, and can also be full steel material with nickel plating treatment, and the present application does not limit this, in an embodiment of the present application, the material of the crimping pin 5 is copper material, which has good conductivity and good corrosion resistance, and is very stable on the circuit board, which is a good conductive material.

[0047] The above merely describes the preferred embodiments of the present application, and is not intended to limit the patent scope of the present application. Any equivalent structural changes made according to the content of the present application specification and drawings, or direct / indirect application in other related technical fields, are included in the patent protection scope of the present application.

Claims

1. A dual-purpose test system for both performance testing and functional verification of a chip, characterized by, The utility model relates to a test system, which comprises: a compression connector, a test adapter circuit board is installed on the upper end of the compression connector, a plurality of compression pins are installed on the lower end of the compression connector, each compression pin has a first contact part and a second contact part distributed along the length direction of the compression pin, and the test adapter circuit board is electrically connected with the plurality of compression pins; and a system circuit board, a plurality of through holes are formed on the system circuit board corresponding to the plurality of compression pins, an upper signal through hole and a lower signal through hole are arranged in each through hole and are spaced from each other, the upper signal through hole is used to electrically connect a chip to be tested, and the lower signal through hole is used to electrically connect a detection chip. Wherein, each compression pin can move relative to the system circuit board, each compression pin has a first position and a second position on the moving stroke of the compression pin, only the first contact part of the compression pin can be plugged into the upper signal through hole to be electrically connected at the first position, the first contact part of the compression pin can be plugged into the lower signal through hole to be electrically connected, and the second contact part of the compression pin can be plugged into the upper signal through hole to be electrically connected at the second position.

2. The dual-purpose test system for chip performance testing and functional verification of claim 1, wherein, The compression connector is plugged into the lower end of the test adapter circuit board.

3. The dual-purpose test system for both chip performance testing and functional verification according to claim 1, wherein, The compression connector comprises a male compression connector and a female compression connector, the female compression connector is plugged into the lower end of the male compression connector; The test adapter circuit board is installed on the upper end of the male compression connector, and the plurality of compression pins are installed on the lower end of the female compression connector.

4. The dual-purpose test system for both chip performance testing and functional verification according to claim 3, wherein, The female compression connector and the male compression connector are electrically connected through a plug connector.

5. The dual-purpose test system for chip performance testing and functional verification of claim 1, wherein, The system circuit board comprises an upper PCB and a lower PCB, and the upper PCB and the lower PCB are pressed together; The upper signal through hole is arranged in the upper PCB, and the lower signal through hole is arranged in the lower PCB.

6. The dual-purpose test system for chip performance testing and functional verification of claim 1, wherein, A radio frequency connector is installed on the upper end of the test adapter circuit board, the radio frequency connector is electrically connected with the test adapter circuit board, and the radio frequency connector is used to test the performance of the chip by externally connecting a network analyzer.

7. The dual-purpose test system for both chip performance testing and functional verification according to claim 6, wherein, The radio frequency connector is electrically connected with an oscilloscope to observe the performance of the chip to be tested.

8. The dual-purpose test system for both chip performance testing and functional verification of claim 1, wherein, The compression pin comprises a pin column and two abutting protrusions protruding from the side surface of the pin column, the first contact part is provided with a first abutting protrusion, and the second contact part is provided with a second abutting protrusion.

9. The dual-purpose test system for both chip performance testing and functional verification of claim 1, wherein, The system circuit board is provided with a plurality of ground through holes close to the plurality of signal through holes.

10. The dual-purpose test system for chip performance testing and functional verification of claim 1, wherein, The material of the compression pin comprises copper.

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