Code generation method and device, equipment and storage medium

Abstract

The application provides a code generation method, device and equipment and a storage medium. The method comprises the following steps: obtaining configuration parameters corresponding to a target algorithm to be processed, wherein the configuration parameters comprise a generating polynomial of the target algorithm and an input data bit width; generating encoded data matched with the input data bit width according to the configuration parameters; and performing bit-by-bit calculation on the encoded data according to the generating polynomial to determine a circuit structure expression corresponding to each bit of the encoded data. The application is based on a bit-type algorithm, and the encoded data encoded by the algorithm is obtained according to the configuration parameters. The encoded data is calculated bit by bit, the circuit structure expression of the algorithm is generated, the circuit structure corresponding to the algorithm is automatically derived, and the circuit design efficiency is improved.

Description

Technical Field

[0001] This application relates to the field of communication technology, and more specifically, to a code generation method, apparatus, device, and storage medium. Background Technology

[0002] CRC (Cyclic Redundancy Check) is a commonly used checksum with error detection and correction capabilities. It is widely used for data verification in external storage and computer synchronous communication. The principle of CRC verification is to establish a pre-defined relationship between data bits and check bits using specific mathematical operations. Using this mathematical operation, a CRC checksum is generated at the sending end and appended to the data to be sent to the receiving end. The receiving end uses the same mathematical operation to perform a CRC check on the received data, thereby determining whether any errors occurred during transmission.

[0003] In ASIC (Application-Specific Integrated Circuit) chip design, CRC checksums are often performed to ensure data transmission correctness. To achieve higher speeds, CRC checksums are not generated through software calculations but are implemented directly through hardware circuits. A common scenario in the hardware implementation of CRC checksum circuits involves deriving the circuit structure expression for a data block with a fixed bit width and then implementing the circuit design using a hardware description language. The implementation of CRC checksum circuits varies depending on the CRC algorithm and the data length. Manually deriving the CRC circuit is extremely tedious, time-consuming, and labor-intensive. Summary of the Invention

[0004] The purpose of this application is to provide a code generation method, apparatus, device, and storage medium based on a bit-type algorithm. The encoded data is obtained according to the configuration parameters, and the encoded data is calculated bit by bit to generate the circuit structure expression of the algorithm. This realizes the automatic derivation of the circuit structure corresponding to the algorithm and improves the efficiency of circuit design.

[0005] The first aspect of this application provides a code generation method, comprising: obtaining configuration parameters corresponding to a target algorithm to be processed, wherein the configuration parameters include a generator polynomial of the target algorithm and an input data bit width; generating encoded data matching the input data bit width according to the configuration parameters; and performing bit-by-bit calculations on the encoded data according to the generator polynomial to determine the circuit structure expression corresponding to each bit of the encoded data.

[0006] In one embodiment, obtaining the configuration parameters corresponding to the target algorithm to be processed includes: when the target algorithm to be processed is received, determining whether the target algorithm exists in the database; when the target algorithm exists in the database, obtaining the first parameter of the target algorithm entered by the user, and extracting the preset parameter corresponding to the target algorithm pre-stored in the database, and using the first parameter and the preset parameter as the configuration parameters.

[0007] In one embodiment, the first parameter includes one or more of the following: the input data bit width of the target algorithm, the target algorithm identifier, and the verification data.

[0008] In one embodiment, the preset parameters include one or more of the following: the generator polynomial of the target algorithm, the initial value, the input inversion flag, the output inversion flag, and the output XOR value.

[0009] In one embodiment, obtaining the configuration parameters corresponding to the target algorithm to be processed further includes: when the target algorithm does not exist in the database, obtaining the user-entered custom parameters of the target algorithm, and using the custom parameters as the configuration parameters of the target algorithm.

[0010] In one embodiment, the custom parameters include one or more of the following: the input data bit width of the target algorithm, the check data, the generator polynomial of the target algorithm, the initial value, the input inversion flag, the output inversion flag, and the output XOR value.

[0011] In one embodiment, generating encoded data matching the input data bit width according to the configuration parameters includes: generating input data corresponding to the target algorithm according to the input data bit width; processing the input data according to the input inversion flag; adding a preset encoding value to the end of the processed input data; and performing an XOR operation between the input data with the added encoding value and the initial value to obtain the encoded data.

[0012] In one embodiment, the step of performing bit-by-bit calculations on the encoded data according to the generator polynomial to determine the circuit structure expression corresponding to each bit of the encoded data includes: shifting the data in the encoded data to the left by a specified number of bits to obtain a shifted-out data group; if the highest bit in the shifted-out data group is 0, shifting the entire shifted-out data group one bit to the left and shifting it one bit from the remaining encoded data into the shifted-out data group; if the highest bit in the shifted-out data group is not 0, performing a bitwise XOR operation between the data in the shifted-out data group and the generator polynomial of the target algorithm, shifting the result of the XOR operation one bit to the left and storing it in the shifted-out data group, and shifting it one bit from the remaining encoded data into the shifted-out data group; determining the circuit structure expression corresponding to the target algorithm in this round based on the shifted-out data group, and using the above method to participate in the calculation of each bit of the encoded data to obtain multiple circuit structure expressions corresponding to the target algorithm.

[0013] In one embodiment, determining the circuit structure expression corresponding to the current round of the target algorithm based on the shifted-out data group includes: simplifying the shifted-out data group using a Karnaugh map to obtain the circuit structure expression corresponding to the target algorithm.

[0014] In one embodiment, the method further includes: performing output processing on the circuit structure expression according to the configuration parameters, and outputting the final circuit structure expression corresponding to the target algorithm.

[0015] In one embodiment, the configuration parameters further include verification data of the target algorithm; the method further includes: substituting the verification data into the plurality of circuit structure expressions to obtain verification values ​​output by the plurality of circuit structure expressions, and comparing the verification values ​​with preset standard values ​​to verify the accuracy of the plurality of circuit structure expressions.

[0016] In one embodiment, the method further includes: generating a code file for the target algorithm based on the circuit structure expression.

[0017] A second aspect of this application provides a code generation apparatus, comprising: a parameter acquisition module for acquiring configuration parameters corresponding to a target algorithm to be processed, wherein the configuration parameters include a generator polynomial of the target algorithm and an input data bit width; a data generation module for generating encoded data matching the input data bit width according to the configuration parameters; and an expression determination module for performing bit-by-bit calculations on the encoded data according to the generator polynomial to determine the circuit structure expression corresponding to each bit of the encoded data.

[0018] In one embodiment, the parameter acquisition module is configured to: upon receiving the target algorithm to be processed, determine whether the target algorithm exists in the database; when the target algorithm exists in the database, acquire the first parameter of the target algorithm entered by the user, extract the preset parameter corresponding to the target algorithm pre-stored in the database, and use the first parameter and the preset parameter as the configuration parameter.

[0019] In one embodiment, the first parameter includes one or more of the following: the input data bit width of the target algorithm, the target algorithm identifier, and the verification data;

[0020] In one embodiment, the preset parameters include one or more of the following: the generator polynomial of the target algorithm, the initial value, the input inversion flag, the output inversion flag, and the output XOR value.

[0021] In one embodiment, the parameter acquisition module is used to: when the target algorithm does not exist in the database, acquire the user-inputted custom parameters of the target algorithm, and use the custom parameters as the configuration parameters of the target algorithm;

[0022] In one embodiment, the custom parameters include one or more of the following: the input data bit width of the target algorithm, the check data, the generator polynomial of the target algorithm, the initial value, the input inversion flag, the output inversion flag, and the output XOR value.

[0023] In one embodiment, the data generation module is configured to: generate input data corresponding to the target algorithm based on the input data bit width; process the input data based on the input inversion flag; add a preset encoding value to the end of the processed input data; and perform an XOR operation between the input data with the added encoding value and the initial value to obtain the encoded data.

[0024] In one embodiment, the expression determination module is used to: shift the data in the encoded data to the left by a specified number of bits to obtain a shifted-out data group; if the highest bit in the shifted-out data group is 0, shift the entire shifted-out data group one bit to the left and shift the remaining encoded data one bit to the shifted-out data group; if the highest bit in the shifted-out data group is not 0, perform a bitwise XOR operation between the data in the shifted-out data group and the generator polynomial of the target algorithm, shift the result of the XOR operation one bit to the left and store it in the shifted-out data group, and shift the remaining encoded data one bit to the shifted-out data group; determine the circuit structure expression corresponding to the current round of the target algorithm based on the shifted-out data group, and use the above method to participate in the calculation of each bit of the encoded data to obtain multiple circuit structure expressions corresponding to the target algorithm.

[0025] In one embodiment, determining the circuit structure expression corresponding to the current round of the target algorithm based on the shifted-out data group includes: simplifying the shifted-out data group using a Karnaugh map to obtain the circuit structure expression corresponding to the target algorithm.

[0026] In one embodiment, the system further includes an expression output module, configured to process the circuit structure expression according to the configuration parameters and output the final circuit structure expression corresponding to the target algorithm.

[0027] In one embodiment, the configuration parameters further include verification data of the target algorithm; the device further includes: an expression verification module, used to input the verification data into the plurality of circuit structure expressions to obtain verification values ​​output by the plurality of circuit structure expressions, and to compare the verification values ​​with preset standard values ​​to verify the accuracy of the plurality of circuit structure expressions.

[0028] In one embodiment, the apparatus further includes a code generation module, configured to generate a code file for the target algorithm based on the plurality of circuit structure expressions.

[0029] A third aspect of this application provides an electronic device, including: a memory for storing a computer program; and a processor for executing the computer program to implement the method of the first aspect of this application and any of its embodiments.

[0030] A fourth aspect of this application provides a non-transitory electronic device readable storage medium, comprising: a program, which, when run by an electronic device, causes the electronic device to execute the method of the first aspect of this application and any of its embodiments.

[0031] The code generation method, apparatus, device, and storage medium provided in this application are based on bit-type algorithms. They obtain encoded data encoded by the target algorithm according to configuration parameters, and perform bit-by-bit calculations on the encoded data based on the generator polynomial of the target algorithm to generate the circuit structure expression of the target algorithm. This realizes the automatic derivation of the circuit structure corresponding to the target algorithm, greatly reducing the cost of manual derivation and improving the efficiency of circuit design. Attached Figure Description

[0032] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1This is a schematic diagram of an electronic device according to an embodiment of this application;

[0034] Figure 2 This is a flowchart illustrating a code generation method according to an embodiment of this application;

[0035] Figure 3 This is a flowchart illustrating a code generation method according to an embodiment of this application;

[0036] Figures 4A-4B This is a schematic diagram illustrating the process of shifting out a data set and generating a polynomial in accordance with an embodiment of this application.

[0037] Figure 5 This is a schematic diagram of a code generation apparatus according to an embodiment of this application. Detailed Implementation

[0038] The technical solutions of the embodiments of this application will now be described with reference to the accompanying drawings. In the description of this application, the terms "first," "second," etc., are used only for distinguishing descriptions and should not be construed as indicating or implying relative importance.

[0039] like Figure 1 As shown, this embodiment provides an electronic device 1, including: at least one processor 11 and a memory 12. Figure 1 Taking a processor as an example, processor 11 and memory 12 are connected via bus 10. Memory 12 stores instructions that can be executed by processor 11. The instructions are executed by processor 11 to enable electronic device 1 to perform all or part of the process of the method in the following embodiments, so as to automatically derive the circuit structure corresponding to the target algorithm and improve circuit design efficiency.

[0040] In one embodiment, the electronic device 1 may be a bus device, a mobile phone, a tablet computer, a laptop computer, a desktop computer, or a large computing system composed of multiple computers.

[0041] To clearly describe the solution in this embodiment, the terms used are defined as follows:

[0042] CRC: Cyclic Redundancy Check, is a commonly used check code with error detection and correction capabilities.

[0043] ASIC: Application-Specific Integrated Circuit.

[0044] RTL: Register Transfer Level.

[0045] POLY: CRC-Polynomial, the generator polynomial of the CRC algorithm.

[0046] INIT: CRC Initial Value, the default value for initializing the CRC algorithm register. The number of bits in INIT is the same as that in POLY.

[0047] REFIN: Flag indicating whether the CRC input data needs to be reversed byte by byte.

[0048] REFOUT: Flag indicating whether the CRC output result is inverted.

[0049] XOROUT: Outputs the XOR value of the CRC checksum. The CRC checksum is XORed with XOROUT and then output. Its bit width is equal to the CRC checksum bit width CRC_WIDTH.

[0050] CRC_NUM: The number value of the CRC algorithm in the CRC algorithm-number lookup table in this scheme.

[0051] WIDTH: Input data bit width.

[0052] HEX_DATA: A hexadecimal number used to verify the correctness of the CRC checksum expression; its length does not exceed WIDTH.

[0053] CRC_WIDTH: The number of bits in the CRC checksum width.

[0054] In ASIC (Application-Specific Integrated Circuit) chip design, CRC checksums are often required to ensure data transmission correctness. To achieve higher speeds, CRC checksums are not generated through software calculations but are implemented directly through hardware circuits. A common scenario in the hardware implementation of CRC checksum circuits is deriving the circuit structure expression for a data block with a fixed bit width and then implementing the circuit design using a hardware description language. However, the implementation of CRC checksum circuits varies depending on the CRC algorithm and data length. Manually deriving the CRC circuit is tedious, time-consuming, and laborious. This embodiment provides a solution that allows for the derivation of the CRC checksum circuit structure expression for data blocks of arbitrary bit width based on different CRC algorithms during the ASIC design process, and then implementing the circuit design using a hardware description language. This significantly saves design time and is highly efficient.

[0055] The technical content of the embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0056] Please refer to Figure 2This is a code generation method according to an embodiment of this application, which can be generated by... Figure 1 The method is executed by the electronic device 1 shown and can be applied in ASIC design scenarios to automatically derive the circuit structure corresponding to the algorithm, thereby improving circuit design efficiency. The method includes the following steps:

[0057] Step 201: Obtain the configuration parameters corresponding to the target algorithm to be processed.

[0058] In this step, the target algorithm can be the CRC algorithm. The configuration parameters include at least the generator polynomial POLY of the target algorithm and the input data bit width WIDTH. The configuration parameters can be obtained by user input or directly retrieved from the pre-stored database.

[0059] Step 202: Generate encoded data that matches the bit width of the input data according to the configuration parameters.

[0060] In this step, taking the CRC algorithm as an example, the encoded data can be a data column formed by adding a CRC checksum to the input data. In the actual CRC verification process, if a piece of data needs to be transmitted, the CRC checksum is first added to the end of the data to be transmitted before sending the data, forming an encoded data column to be sent. Here, we borrow this method and directly generate encoded data using CRC encoding based on the configuration parameters of the target algorithm. This encoded data matches the input data width (WIDTH) in the configuration parameters. In this way, a circuit structure can be generated for any configured width parameter.

[0061] Step 203: Perform bit-by-bit calculations on the encoded data based on the generator polynomial to determine the circuit structure expression corresponding to each bit of the encoded data.

[0062] In this step, based on a bit-based algorithm, a bit-by-bit CRC calculation is performed on the encoded data to obtain the circuit structure expression corresponding to each bit of the encoded data. In practical scenarios, for a specific CRC algorithm, its CRC generator polynomial POLY is determined. For example, in the CRC-4 / ITU algorithm mentioned above, its generator polynomial is X⁴ + X¹ + 1, so POLY is (1, 0, 0, 1, 1). By using a cyclic solution method, the circuit structure expression corresponding to each bit of the encoded data can be obtained, and finally, multiple circuit structure expressions corresponding to the target algorithm can be obtained.

[0063] Step 204: Generate the code file for the target algorithm based on the circuit structure expression.

[0064] In this step, based on the circuit structure expression of the CRC checksum generated in step 203, a Perl script can be used to generate the corresponding RTL Verilog file for the current CRC algorithm. (RTL, Register Transfer Level, refers to a method of describing the data flow of a circuit using registers. Verilog, or Verilog HDL, is a hardware description language that describes the structure and behavior of digital system hardware in text form.) The input data bit width of this RTL Verilog is equal to the input data bit width parameter WIDTH, and the output CRC checksum bit width is equal to the number of CRC checksum bits, CRC_WIDTH. The circuit structure expression for each bit of the CRC checksum is the XOR logic of different signal bits of the input data.

[0065] The above code generation method is based on a bit-type algorithm. It obtains the encoded data of the target algorithm according to the configuration parameters, performs bit-by-bit calculations on the encoded data based on the generator polynomial of the target algorithm, generates the circuit structure expression of the target algorithm, and then generates the code file of the algorithm based on the circuit structure expression. This realizes the automatic derivation of the circuit structure corresponding to the target algorithm, which greatly reduces the cost of manual derivation and improves the efficiency of circuit design.

[0066] Please refer to Figure 3 This is a code generation method according to an embodiment of this application, which can be generated by... Figure 1 The method is executed by the electronic device 1 shown and can be applied in ASIC design scenarios to automatically derive the circuit structure corresponding to the algorithm, thereby improving circuit design efficiency. The method includes the following steps:

[0067] Step 301: Upon receiving the target algorithm to be processed, determine whether the target algorithm exists in the database. If yes, proceed to step 302; otherwise, proceed to step 303.

[0068] In this step, the target algorithm is the CRC algorithm. The database pre-stores common CRC algorithm names and their corresponding preset parameters. By pre-stored specific parameters of some commonly used algorithms in the database, they can be directly called when used without user input, simplifying the user's operation process.

[0069] A table showing the names and numbers (CRC_NUM) of commonly used CRC algorithms is shown in Table 1:

[0070] Table 1. CRC Algorithms and Corresponding Numbers in the Database

[0071] CRC algorithm name CRC_NUM CRC algorithm name CRC_NUM CRC-4 / ITU 1 CRC-16 / MODBUS 14 CRC-5 / EPC 2 CRC-16 / CCITT 15 CRC-5 / ITU 3 CRC-16 / CCITT-FALSE 16 CRC-5 / USB 4 CRC-16 / X5 17 CRC-6 / ITU 5 CRC-16 / XMODEN 18 CRC-7 / MMC 6 CRC-16 / DNP 19 CRC-8 7 CRC-32 20 CRC-8 / ITU 8 CRC-32 / BZIP2 21 CRC-8 / ROHC 9 CRC-32 / MPEG-2 22 CRC-8 / MAXIM 10 CRC-32 / POSIX 23 CRC-16 / IBM 11 CRC-32 / JAMCRC 24 CRC-16 / MAXIM 12 CRC-8 / CDMA2000 25 CRC-16 / USB 13 CRC-8 / WCDMA 26

[0072] The target algorithm can be a specific type of algorithm that the user needs to design, such as the CRC-5 / ITU algorithm. The user can enter the identifier of the target algorithm through an interactive tool, such as the number CRC_NUM value, and then query the database to see if the target algorithm exists. If it exists, proceed to step 302; otherwise, proceed to step 303.

[0073] Step 302: Obtain the first parameter of the target algorithm entered by the user, and extract the preset parameters corresponding to the target algorithm pre-stored in the database. Use the first parameter and the preset parameters as configuration parameters. Then proceed to step 304.

[0074] In this step, when the target algorithm exists in the database, the user-entered parameters are first retrieved. The first parameter here includes, but is not limited to, one or more of the following: the input data bit width of the target algorithm, the target algorithm identifier, and the checksum data. The first parameter is the one that needs to be entered by the user. That is, if the required target algorithm is included in the CRC algorithm-number lookup table 1 above, for example, if the target algorithm's number CRC_NUM value is 3 and the corresponding algorithm name is CRC-5 / ITU, then parameter input mode A can be used. In this mode, the following three parameters can be entered:

[0075] Parameter 1, WIDTH, is the input data bit width, which is a decimal integer.

[0076] Parameter 2, HEX_DATA, is a hexadecimal number with a length not exceeding WIDTH. After the script obtains the circuit structure expression of the CRC check code, HEX_DATA will be substituted into the expression to obtain the corresponding CRC check value. This check value can be used to compare with the check values ​​of other algorithms to verify the correctness of the CRC check code expression.

[0077] Parameter 3 is the target algorithm identifier, used to characterize the uniqueness of the target algorithm. For example, it can be the number CRC_NUM corresponding to the target CRC algorithm. CRC_NUM is the internal encoding of the Perl script. The correspondence between the CRC algorithm and the encoding CRC_NUM can be obtained through the help information of the Perl script.

[0078] In one embodiment, in parameter input mode A, the preset parameters of the target algorithm stored in the database can be directly called. The preset parameters include, but are not limited to, one or more of the following: the generator polynomial of the target algorithm, the initial value, the input inversion flag, the output inversion flag, and the output XOR value.

[0079] Assuming the target algorithm is CRC-5 / ITU, then based on the CRC_NUM value 3 corresponding to the CRC-5 / ITU algorithm, the corresponding preset parameters are automatically retrieved and the following parameters are automatically assigned:

[0080] a. The generator polynomial POLY of the CRC-5 / ITU algorithm is determined for a specific CRC algorithm. For example, the generator polynomial of the CRC-4 / ITU algorithm mentioned above is X4+X1+1.

[0081] b. The initial value INIT of CRC-5 / ITU.

[0082] c. Input the inversion flag REFIN.

[0083] d. Output the inverted flag REFOUT.

[0084] e. Output the XOR value (XOROUT).

[0085] Thus, by introducing parameters such as initial value, input / output inversion flag, and XOR value of output, the method of this embodiment can support CRC algorithms with non-zero initial value, CRC algorithms with inverted input and output, and CRC algorithms with XOR operation of output. This enables support for multiple CRC algorithms and increases the flexibility of circuit design.

[0086] Step 303: Obtain the user-entered custom parameters of the target algorithm and use these custom parameters as the configuration parameters of the target algorithm. Then proceed to step 304.

[0087] In this step, if the target algorithm does not exist in the database, the user needs to enter relevant custom parameters. These custom parameters include, but are not limited to, one or more of the following: the input data bit width of the target algorithm, the check data, the generator polynomial of the target algorithm, the initial value, the input inversion flag, the output inversion flag, and the output XOR value.

[0088] In other words, if the desired target algorithm is not included in CRC Algorithm-Number Lookup Table 1, the user can specify the parameters via parameter input mode B. The custom parameters that can be entered in mode B are as follows:

[0089] Parameter 1 is the input data width WIDTH for the target algorithm. This parameter is a decimal integer.

[0090] Parameter 2, the verification data HEX_DATA is a hexadecimal number with a length not exceeding WIDTH.

[0091] Parameter 3 is the generator polynomial POLY of the target algorithm. For example, for the CRC-4 / ITU algorithm, its generator polynomial is X4+X1+1, and POLY is (1, 0, 0, 1, 1).

[0092] Parameter 4 is the initial value INIT of the target algorithm. For example, for the target algorithm CRC-4 / ITU, the value of INIT is (0, 0, 0, 0).

[0093] Parameter 5 is the input inversion flag REFIN. For example, for the CRC-4 / ITU algorithm, REFIN equals 1.

[0094] Parameter 6 is the output inversion flag REFOUT. For example, for the CRC-4 / ITU algorithm, REFOUT equals 1.

[0095] Parameter 7 is the output XOR value, for example, for the CRC-4 / ITU algorithm, XOROUT is (0, 0, 0, 0, 0).

[0096] This embodiment introduces a custom mode B to address potential new CRC algorithms in the future. By specifying five parameters—CRC polynomial POLY, initial data value INIT, input data reversal flag REFIN, output data reversal flag REFOUT, and output data XOROUT value—the CRC algorithm can be customized, improving the scalability of the solution.

[0097] Step 304: Generate the input data corresponding to the target algorithm based on the input data bit width.

[0098] In this step, the input data for the target algorithm can be generated based on the parameter WIDTH. The generated input data can be arranged in big-endian byte order, with the most significant byte on the leftmost side and the least significant byte on the rightmost side.

[0099] Step 305: Process the input data according to the input inversion flag.

[0100] In this step, if the REFIN flag parameter of the target algorithm is 1, the input data generated in step 304 is reversed byte by byte. If the REFIN parameter is 0, no reversal is performed.

[0101] Step 306: Add a preset encoding value to the end of the processed input data.

[0102] In this step, the preset encoding value can be 0 or other specified characters. Taking the CRC algorithm as an example, in the actual CRC verification process, if a piece of data needs to be transmitted, the CRC checksum is first added to the end of the data to be transmitted before sending the data, forming an encoded data column to be sent. Here, we borrow this method and take 0 as an example. We can add 0 to the end of the input data processed in step 305. The number of 0s added is equal to the number of checksum bits generated by the target algorithm CRC_WIDTH.

[0103] Step 307: Perform an XOR operation between the input data with the added encoded value and the initial value to obtain the encoded data.

[0104] In this step, the input data after adding the encoded value in step 306 can be XORed with the highest CRC_WIDTH bit and the initial value INIT. For ease of description, the encoded data obtained in this step is represented by array D.

[0105] Step 308: Shift the data in the encoded data to the left by a specified number of positions to obtain the shifted-out data group.

[0106] In this step, to obtain the CRC check expression bit by bit from the encoded data D after the input XOR operation in step 307, the data in array D is first shifted to the left by (CRC_WIDTH+1) bits. For ease of description, the shifted-out data group from array D is represented by array A, where the leftmost data in array A is the most significant bit.

[0107] Step 309: If the highest bit in the shifted-out data group is 0, shift the entire shifted-out data group one bit to the left, and shift the remaining encoded data one bit to the left into the shifted-out data group. Then proceed to step 311.

[0108] In this step, if the highest bit of the data in array A is 0, then the data in array A is shifted left by one bit, the shifted-out data in array A is discarded, and array D is also shifted left by one bit and the shifted-out data is placed in the lower bit of array A. The new value in array A is used as the result of this round of calculation.

[0109] Step 310: If the highest bit in the shifted-out data group is not 0, perform a bitwise XOR operation between the data in the shifted-out data group and the generator polynomial of the target algorithm. Shift the result of the XOR operation left by one bit and store it in the shifted-out data group. Then shift the remaining encoded data left by one bit into the shifted-out data group. Then proceed to step 311.

[0110] In this step, if the highest bit of the data in array A is 1, perform a bitwise XOR operation between the data in array A and the generator polynomial POLY of the target algorithm. Shift the result of the XOR operation one bit to the left and store it in array A. Discard the highest bit that was shifted out of the XOR operation result. At the same time, array D is also shifted one bit to the left, and the data shifted out of array D is placed in the lower bits of array A. The new value in array A at this time is the result of this round of calculation.

[0111] Step 311: Based on the shifted-out data group, determine the circuit structure expression corresponding to the target algorithm in this round.

[0112] In this step, after each round of calculation in step 309 or step 310, a new array A is obtained, and the circuit structure expression corresponding to the target algorithm in this round is determined based on the new array A.

[0113] In one embodiment, a Karnaugh map can be used to simplify the shifted data group to obtain the circuit structure expression corresponding to the target algorithm.

[0114] like Figure 4A As shown, the XOR expression of the current array A and the generator polynomial of the target algorithm is obtained by using the Karnaugh map simplification method. Taking the target algorithm CRC-4 / ITU as an example, assume that the 5 bits of data shifted out from array D are the shifted-out data group A (A5, A4, A3, A2, A1), and the corresponding generator polynomial is POLY (P4, P3, P2, P1, P0).

[0115] like Figure 4B As shown, when A5 equals 0, no XOR operation is performed, and the result is array A(A4, A2, A2, A1, A0), where A5 is removed from array A and A0 is a bit removed from array D and added to array A.

[0116] When A5 equals 1, array A needs to be XORed with the CRC-4 / ITU generator polynomial POLY. The result is array A(A4^P43 A3^P2,A2^P1,A1^P0,A0). The highest bit of the XOR result is removed, and the lowest bit is filled with A0, which is the bit that was shifted out from data D.

[0117] According to the above calculation rules, the results can be simplified using Karnaugh maps to obtain logical expressions, as shown in Tables 2 and 3 below:

[0118] Table 2. Simplification of bit4 Karnaugh map

[0119]

[0120] From Table 2, the simplified circuit structure expression after calculating bit4 Karnaugh map in this round is: (!A5)&A4+A4&(!P3)+(!A4)&A5&P3.

[0121] Table 3. Simplification of bit3 Karnaugh map

[0122]

[0123] From Table 3, we can obtain the simplified circuit structure expression of the bit3 Karnaugh map in this round of calculation: (!A5)&A3+A3&(!P2)+(!A3)&A5&P2.

[0124] Table 4. Simplification of bit2 Karnaugh map

[0125]

[0126] From Table 4, we can obtain the simplified circuit structure expression of bit2 Karnaugh map in this round of calculation: (!A5)&A2+A2&(!P1)+(!A2)&A5&P1.

[0127] Table 5. Simplification of bit1 Karnaugh map

[0128]

[0129] From Table 5, we can obtain the simplified Karnaugh map expression for bit1 in this round of calculation: (!A5)&A1+A1&(!P0)+(!A1)&A5&P0.

[0130] In summary, taking the target algorithm CRC-4 / ITU as an example, assuming the 5 bits of data shifted out from array D are shifted-out data group A (A5, A4, A3, A2, A1), the corresponding generator polynomial is POLY (P4, P3, P2, P1, P0). Following the Karnaugh map simplification method described above, the circuit structure expression for the result of this round of 5-bit data operation is:

[0131] ((!A5)&A4+A4&(!P3)+(!A4)&P3&A5,

[0132] (!A5)&A3+A3&(!P2)+(!A3)&P2&A5,

[0133] (!A5)&A2+A2&(!P1)+(!A2)&P1&A5,

[0134] (!A5)&A1+A1&(!P0)+(!A1)&P0&A5,

[0135] A0).

[0136] Step 312: Determine whether every bit of the encoded data is involved in the calculation. If yes, proceed to step 313; otherwise, return to step 308.

[0137] In this step, following steps 308 to 311, after obtaining a new array A in each round, the calculation of array A and the generator polynomial POLY of the target algorithm is continued according to the above rules. After each round of calculation, it is determined whether each bit in array D has been CRC calculated. If not, return to step 308. If each bit in array D has been calculated, multiple circuit structure expressions corresponding to the target algorithm can be obtained. Then proceed to step 313.

[0138] For a specific CRC algorithm, its CRC generator polynomial POLY is fixed. For example, in the CRC-4 / ITU algorithm mentioned above, its generator polynomial is X4 + X1 + 1, so POLY is (1, 0, 0, 1, 1), that is, P4 = 1, P3 = 0, P2 = 0, P1 = 1, P0 = 1. Substituting these values ​​into the above expression and simplifying, we get array A (A4, A3, A5^A2, A5^A1, A0). This result is stored in array A to continue the next round of calculation until all data in array D has participated in the CRC calculation. Using this pattern and a iterative solution method, the circuit structure expressions for different CRC checksums can be obtained.

[0139] In one embodiment, before step 312, the circuit structure expression of each bit in the result of array A obtained in step 311 can be uniquely processed, that is, if there are two identical data in the XOR expression, the duplicate data is removed from the result.

[0140] Step 313: Process the circuit structure expression according to the configuration parameters and output the final circuit structure expression corresponding to the target algorithm.

[0141] In this step, the output inversion flag REFOUT can be used to determine whether to invert the results of multiple circuit structure expressions corresponding to the target algorithm obtained in step 312. Specifically, if the output inversion flag REFOUT = 1, the results of multiple circuit structure expressions are inverted as a whole, that is, the least significant bit of the results becomes the most significant bit, and the most significant bit becomes the least significant bit. If the output inversion flag REFOUT = 0, the results of multiple circuit structure expressions are not inverted.

[0142] Then, the results of the multiple circuit structure expressions processed above are bitwise XORed with the output XOR value parameter XOROUT. For the result obtained after the output XOR operation, the expression of each bit is uniquely processed to obtain the final circuit structure expression of the CRC checksum. Thus, the derivation process is based on a bit-type algorithm, performing bit-by-bit CRC calculation on the data. Using Karnaugh maps, a general expression for the XOR result of the data and the CRC polynomial in each step is obtained, and finally, the CRC checksum expression is generated. This expression can greatly reduce the computational load of the bit-type algorithm and improve computational efficiency.

[0143] Step 314: Generate the code file for the target algorithm based on the circuit structure expression. See the description of step 204 in the above embodiments for details.

[0144] In one embodiment, the configuration parameters further include verification data for the target algorithm. The method further includes: substituting the verification data into multiple circuit structure expressions to obtain verification values ​​output by the multiple circuit structure expressions; and comparing the verification values ​​with preset standard values ​​to verify the accuracy of the multiple circuit structure expressions.

[0145] Substitute the verification data HEX_DATA into the final CRC checksum expression obtained in step 313 to obtain the CRC checksum value. Compare the checksum value with a preset standard value to verify the correctness of the generated CRC checksum expression. If the checksum value is different from the preset standard value, the final CRC checksum expression is considered incorrect; otherwise, it is correct. If the final CRC checksum expression is incorrect, it is necessary to check the target algorithm and the algorithm for calculating the preset standard value to determine which side made a mistake.

[0146] The code generation method described above firstly achieves full support for current mainstream CRC algorithms by introducing multiple parameters. During parameter transmission, two CRC parameter input modes are provided. In Mode A, the automatic transmission of parameters is conveniently achieved through a CRC algorithm-number lookup table. In Mode B, user-defined CRC parameters are supported, improving the scalability and flexibility of the solution and greatly enhancing its adaptability.

[0147] Second, this embodiment is based on a bit-type algorithm. The XOR result of each step is derived to obtain a general expression with regularity. Based on this, the final CRC check code expression is obtained. Each bit in this CRC check code expression is calculated independently, which can easily obtain the corresponding circuit expression. Moreover, this expression can also be used in software to calculate CRC check values. Compared with the traditional bit-type algorithm, this scheme can greatly reduce computing resources and improve computing speed.

[0148] Third, the solution in this embodiment can convert the generated CRC checksum expression into a circuit structure in the form of an RTL Verilog file, which facilitates ASIC design and integration and greatly improves ASIC design efficiency.

[0149] Fourth, a verification method is provided to verify the generated CRC checksum expression. By inputting a specific hexadecimal number, the CRC checksum value of that number in the CRC checksum expression can be obtained, providing a very intuitive verification of the correctness of the CRC checksum expression.

[0150] Please refer to Figure 5 This is a code generation apparatus 500 according to an embodiment of this application, which can be applied to... Figure 1The electronic device 1 shown can be applied in ASIC design scenarios to automatically derive the circuit structure corresponding to the algorithm, thereby improving circuit design efficiency. The device includes: a parameter acquisition module 501, a data generation module 502, an expression determination module 503, and a code generation module 504. The principle relationship between each module is as follows:

[0151] The parameter acquisition module 501 is used to acquire the configuration parameters corresponding to the target algorithm to be processed. The configuration parameters include the generator polynomial of the target algorithm and the input data bit width.

[0152] The data generation module 502 is used to generate encoded data that matches the bit width of the input data according to the configuration parameters.

[0153] The expression determination module 503 is used to perform bit-by-bit calculations on the encoded data based on the generator polynomial to determine the circuit structure expression corresponding to each bit of the encoded data.

[0154] In one embodiment, the device further includes a code generation module 504, used to generate a code file for a target algorithm based on multiple circuit structure expressions.

[0155] In one embodiment, the parameter acquisition module 501 is used to: upon receiving a target algorithm to be processed, determine whether the target algorithm exists in the database. If the target algorithm exists in the database, acquire the first parameter of the target algorithm entered by the user, extract the preset parameter corresponding to the target algorithm stored in the database, and use the first parameter and the preset parameter as configuration parameters.

[0156] In one embodiment, the first parameter includes one or more of the following: the input data bit width of the target algorithm, the target algorithm identifier, and the verification data.

[0157] In one embodiment, the preset parameters include one or more of the following: the generator polynomial of the target algorithm, the initial value, the input inversion flag, the output inversion flag, and the output XOR value.

[0158] In one embodiment, the parameter acquisition module 501 is used to: when the target algorithm does not exist in the database, acquire the user-entered custom parameters of the target algorithm, and use the custom parameters as the configuration parameters of the target algorithm.

[0159] In one embodiment, the custom parameters include one or more of the following: the input data bit width of the target algorithm, the check data, the generator polynomial of the target algorithm, the initial value, the input inversion flag, the output inversion flag, and the output XOR value.

[0160] In one embodiment, the data generation module 502 is configured to: generate input data corresponding to the target algorithm based on the input data bit width; process the input data based on the input inversion flag; add a preset encoding value to the end of the processed input data; and perform an XOR operation between the input data with the added encoding value and the initial value to obtain encoded data.

[0161] In one embodiment, the expression determination module 503 is used to: shift the data in the encoded data left by a specified number of bits to obtain a shifted-out data group. If the highest bit in the shifted-out data group is 0, the entire shifted-out data group is shifted left by one bit, and the remaining encoded data is shifted left by one bit into the shifted-out data group. If the highest bit in the shifted-out data group is not 0, the data in the shifted-out data group is XORed bitwise with the generator polynomial of the target algorithm, the result of the XOR operation is shifted left by one bit and stored in the shifted-out data group, and the remaining encoded data is shifted left by one bit into the shifted-out data group. Based on the shifted-out data group obtained after shifting, the circuit structure expression corresponding to the target algorithm in this round is determined. By using the above method, each bit of the encoded data is used in the calculation to obtain multiple circuit structure expressions corresponding to the target algorithm.

[0162] In one embodiment, the circuit structure expression corresponding to the target algorithm in this round is determined based on the shifted-out data group obtained after shifting, including: simplifying the shifted-out data group using a Karnaugh map to obtain the circuit structure expression corresponding to the target algorithm.

[0163] In one embodiment, it further includes: an expression output module 505, used to process the circuit structure expression according to the configuration parameters and output the final circuit structure expression corresponding to the target algorithm.

[0164] In one embodiment, the configuration parameters further include verification data for the target algorithm. The apparatus also includes an expression verification module 506, configured to input the verification data into multiple circuit structure expressions to obtain verification values ​​output by the multiple circuit structure expressions, and compare the verification values ​​with preset standard values ​​to verify the accuracy of the multiple circuit structure expressions.

[0165] For a detailed description of the code generation device 500 described above, please refer to the description of the relevant method steps in the above embodiments.

[0166] This invention also provides a non-transitory electronic device readable storage medium, comprising: a program, which, when run on the electronic device, enables the electronic device to execute all or part of the processes of the methods described in the above embodiments. The storage medium may be a disk, optical disk, read-only memory (ROM), random access memory (RAM), flash memory, hard disk drive (HDD), or solid-state drive (SSD), etc. The storage medium may also include combinations of the above types of memory.

[0167] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A code generation method, characterized in that, include: Obtain the configuration parameters corresponding to the target algorithm to be processed. The configuration parameters include the generator polynomial of the target algorithm, the input data bit width, the input inversion flag, and the initial value. Generate encoded data that matches the bit width of the input data based on the configuration parameters; The encoded data is calculated bit by bit according to the generator polynomial to determine the circuit structure expression corresponding to each bit of the encoded data. The process of generating encoded data that matches the bit width of the input data according to the configuration parameters includes: Based on the input data bit width, the input data corresponding to the target algorithm is generated; The input data is processed according to the input inversion flag bit, wherein if the input inversion flag bit is 1, the input data is inverted byte by byte; Add a preset encoding value to the end of the processed input data; The input data with the added encoded value is XORed with the initial value to obtain the encoded data.

2. The method according to claim 1, characterized in that, The process of obtaining the configuration parameters corresponding to the target algorithm to be processed includes: Upon receiving the target algorithm to be processed, determine whether the target algorithm exists in the database; When the target algorithm exists in the database, the first parameter of the target algorithm entered by the user is obtained, and the preset parameter corresponding to the target algorithm pre-stored in the database is extracted. The first parameter and the preset parameter are used as the configuration parameter.

3. The method according to claim 2, characterized in that, The first parameter includes one or more of the following: the input data bit width of the target algorithm, the target algorithm identifier, and the verification data.

4. The method according to claim 3, characterized in that, The preset parameters include one or more of the following: the generator polynomial of the target algorithm, the initial value, the input inversion flag, the output inversion flag, and the output XOR value.

5. The method according to claim 2, characterized in that, The step of obtaining the configuration parameters corresponding to the target algorithm to be processed also includes: When the target algorithm does not exist in the database, the user-entered custom parameters of the target algorithm are obtained, and the custom parameters are used as the configuration parameters of the target algorithm.

6. The method according to claim 5, characterized in that, The custom parameters include: The target algorithm comprises one or more of the following: input data bit width, check data, generator polynomial, initial value, input inversion flag, output inversion flag, and output XOR value.

7. The method according to claim 1, characterized in that, The step of performing bit-by-bit calculations on the encoded data based on the generator polynomial to determine the circuit structure expression corresponding to each bit of the encoded data includes: Shift the data in the encoded data to the left by a specified number of positions to obtain the shifted-out data group; If the highest bit in the shifted-out data group is 0, then the entire shifted-out data group is shifted left by one bit, and the remaining encoded data is shifted left by one bit into the shifted-out data group. If the highest bit in the shifted-out data group is not 0, the data in the shifted-out data group is XORed with the generator polynomial of the target algorithm bitwise, the result of the XOR operation is shifted left by one bit and stored in the shifted-out data group, and the remaining encoded data is shifted left by one bit into the shifted-out data group. Based on the shifted-out data group, the circuit structure expression corresponding to the target algorithm in this round is determined. The above method is used to participate in the calculation of each bit of the encoded data to obtain multiple circuit structure expressions corresponding to the target algorithm.

8. The method according to claim 7, characterized in that, The step of determining the circuit structure expression corresponding to the current round of the target algorithm based on the shifted-out data group includes: The shifted-out data group obtained after the shift is simplified using a Karnaugh map to obtain the circuit structure expression corresponding to the target algorithm.

9. The method according to claim 7, characterized in that, Also includes: The circuit structure expression is processed according to the configuration parameters to output the final circuit structure expression corresponding to the target algorithm.

10. The method according to claim 1, characterized in that, The configuration parameters also include the verification data of the target algorithm; the method further includes: The verification data is substituted into multiple circuit structure expressions to obtain the verification values ​​output by the multiple circuit structure expressions. The verification values ​​are then compared with preset standard values ​​to verify the accuracy of the multiple circuit structure expressions.

11. The method according to claim 1, characterized in that, Also includes: Based on the circuit structure expression, generate the code file for the target algorithm.

12. A code generation device, characterized in that, include: The parameter acquisition module is used to acquire the configuration parameters corresponding to the target algorithm to be processed. The configuration parameters include the generator polynomial, input data bit width, input inversion flag, and initial value of the target algorithm. The data generation module is used to generate encoded data that matches the bit width of the input data according to the configuration parameters; An expression determination module is used to perform bit-by-bit calculations on the encoded data according to the generator polynomial to determine the circuit structure expression corresponding to each bit of the encoded data. The data generation module is used for: Based on the input data bit width, the input data corresponding to the target algorithm is generated; The input data is processed according to the input inversion flag bit, wherein if the input inversion flag bit is 1, the input data is inverted byte by byte; Add a preset encoding value to the end of the processed input data; The input data with the added encoded value is XORed with the initial value to obtain the encoded data.

13. The apparatus according to claim 12, characterized in that, The parameter acquisition module is used for: Upon receiving the target algorithm to be processed, determine whether the target algorithm exists in the database; When the target algorithm exists in the database, the first parameter of the target algorithm entered by the user is obtained, and the preset parameter corresponding to the target algorithm pre-stored in the database is extracted. The first parameter and the preset parameter are used as the configuration parameter. The first parameter includes one or more of the following: the input data bit width of the target algorithm, the target algorithm identifier, and the verification data; The preset parameters include one or more of the following: the generator polynomial of the target algorithm, the initial value, the input inversion flag, the output inversion flag, and the output XOR value.

14. The apparatus according to claim 13, characterized in that, The parameter acquisition module is used for: When the target algorithm does not exist in the database, the user-entered custom parameters of the target algorithm are obtained, and the custom parameters are used as the configuration parameters of the target algorithm. The custom parameters include one or more of the following: the input data bit width of the target algorithm, the check data, the generator polynomial of the target algorithm, the initial value, the input inversion flag, the output inversion flag, and the output XOR value.

15. The apparatus according to claim 12, characterized in that, The expression determination module is used for: Shift the data in the encoded data to the left by a specified number of positions to obtain the shifted-out data group; If the highest bit in the shifted-out data group is 0, then the entire shifted-out data group is shifted left by one bit, and the remaining encoded data is shifted left by one bit into the shifted-out data group. If the highest bit in the shifted-out data group is not 0, the data in the shifted-out data group is XORed with the generator polynomial of the target algorithm bitwise, the result of the XOR operation is shifted left by one bit and stored in the shifted-out data group, and the remaining encoded data is shifted left by one bit into the shifted-out data group. Based on the shifted-out data group, the circuit structure expression corresponding to the target algorithm in this round is determined. The above method is used to participate in the calculation of each bit of the encoded data to obtain multiple circuit structure expressions corresponding to the target algorithm.

16. The apparatus according to claim 12, characterized in that, The configuration parameters also include the verification data of the target algorithm; the device further includes: The expression verification module is used to input the verification data into multiple circuit structure expressions to obtain the verification values ​​output by the multiple circuit structure expressions, and compare the verification values ​​with preset standard values ​​to verify the accuracy of the multiple circuit structure expressions.

17. The apparatus according to claim 12, characterized in that, The device further includes: The code generation module is used to generate the code file of the target algorithm based on the circuit structure expression.

18. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the method as described in any one of claims 1 to 11.

19. A non-transitory electronic device readable storage medium, characterized in that, Includes: a program, when executed by an electronic device, causing the electronic device to perform the method of any one of claims 1 to 11.

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