Data output circuit

Abstract

An embodiment of the present disclosure discloses a data output circuit. The data output circuit includes: a selection circuit configured to select and output a first control signal or a second control signal according to a received first code; a driving circuit connected to the selection circuit, the driving circuit being configured to receive a first data signal and output a first level according to the first control signal, or output a second level according to the second control signal; the first level includes a power supply voltage; the second level is greater than the first level. The embodiment of the present disclosure uses a first code to select and output an appropriate control signal, and the driving circuit generates an appropriate output voltage according to the control signal.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductor technology, and relate to, but are not limited to, a data output circuit. Background Art

[0002] Data (DATA) in a storage unit can be transmitted to a data output terminal (OUTPUT) through a data output circuit, and then an output voltage is transmitted to an external data port (DQ pad) through the data output terminal. On the one hand, the transmission path between the data output terminal and the external data port is too long. On the other hand, the transmission medium between the data output terminal and the external data port will absorb signals. Both of these will cause attenuation of the transmitted output voltage, that is, the output data. At this time, the data transmitted to the external data port may not be full-scale data. When such data is collected by the external data port, the data in the storage unit may be misjudged, which will seriously affect the performance of the memory. How to enable the external data port to collect the correct stored data has become an urgent problem to be solved. Summary of the Invention

[0003] In view of this, embodiments of the present disclosure provide a data output circuit. The data output circuit includes:

[0004] A selection circuit, configured to select and output a first control signal or a second control signal according to a received first code;

[0005] A driving circuit, connected to the selection circuit, the driving circuit is configured to receive a first data signal and output a first level according to the first control signal, or output a second level according to the second control signal; the first level includes a power supply voltage; the second level is greater than the first level.

[0006] In some embodiments, the selection circuit includes a first selector;

[0007] A control end of the first selector is configured to receive the first code; a first input end of the first selector is configured to receive the first control signal, and a second input end of the first selector is configured to receive the second control signal;

[0008] When the first code is a first value, the first selector correspondingly outputs the first control signal, and when the first code is a second value, the first selector correspondingly outputs the second control signal.

[0009] In some embodiments, the driving circuit includes a first pull-up driving unit and a second pull-up driving unit;

[0010] A first end of the first pull-up driving unit is connected to a power supply voltage, and a control end of the first pull-up driving unit is connected to an output end of the selection circuit for receiving the first control signal or the second control signal;

[0011] A first end of the second pull-up driving unit is connected to a second end of the first pull-up driving unit, a second end of the second pull-up driving unit is a data output end, and a control end of the second pull-up driving unit is for receiving a third control signal;

[0012] Under the condition that the second pull-up driving unit is turned on, the driving circuit is configured to output the first level through the data output end according to the first control signal, or to output the second level through the data output end according to the second control signal.

[0013] In some embodiments, the first pull-up driving unit includes: a first P-type transistor and a capacitor; the second pull-up driving unit includes: a second P-type transistor and a first resistor connected in series;

[0014] The capacitor is connected between a gate of the first P-type transistor and a second pole of the first P-type transistor; a first pole of the first P-type transistor is connected to the power supply voltage, and the gate of the first P-type transistor is for receiving the first control signal or the second control signal;

[0015] A first pole of the second P-type transistor is connected to the second pole of the first P-type transistor; a second pole of the second P-type transistor is connected to a first end of the first resistor; a gate of the second P-type transistor is for receiving the third control signal; a second end of the first resistor is the data output end.

[0016] In some embodiments, the data output circuit further includes: a control signal generation circuit connecting the selection circuit and the driving circuit;

[0017] The control signal generation circuit includes:

[0018] a first generation circuit for generating the first control signal;

[0019] a second generation circuit for generating the second control signal;

[0020] a third generation circuit for generating the third control signal.

[0021] In some embodiments, the first generation circuit includes: a NAND gate;

[0022] The first input terminal of the NAND gate is used to receive the second code, the second input terminal of the NAND gate is used to receive the first power gating signal, and the output terminal of the NAND gate is used to output the first control signal; wherein, when the first power gating signal is valid, the first pull-up driving unit is disconnected from the power supply voltage.

[0023] In some embodiments, the second generating circuit includes: a first NOR gate and a first NOT gate;

[0024] The input terminal of the first NOT gate receives the first data signal, and the output terminal of the first NOT gate outputs a fourth control signal;

[0025] The first input terminal of the first NOR gate receives the first data signal;

[0026] The second input terminal of the first NOR gate is connected to the output terminal of the first NOT gate for receiving the fourth control signal;

[0027] The output terminal of the first NOR gate is used to output the second control signal.

[0028] In some embodiments, the third generating circuit includes: a second NOT gate;

[0029] The input terminal of the second NOT gate is used to receive the first data signal, and the output terminal of the second NOT gate is used to output the third control signal.

[0030] In some embodiments, the driving circuit is used to receive the first data signal and output a third level according to a fifth control signal; the third level includes a ground voltage; the driving circuit further includes a first pull-down driving unit and a second pull-down driving unit:

[0031] The first end of the first pull-down driving unit is connected to the ground voltage, and the control end of the first pull-down driving unit is used to receive the fifth control signal;

[0032] The first end of the second pull-down driving unit is connected to the second end of the first pull-down driving unit, the second end of the second pull-down driving unit is the data output terminal, and the control end of the second pull-down driving unit is used to receive a sixth control signal;

[0033] Under the condition that the second pull-down driving unit is turned on, the first pull-down driving unit is used to receive the fifth control signal and correspondingly output the third level.

[0034] In some embodiments, the first pull-down driving unit includes: a first N-type transistor; the second pull-down driving unit includes: a second N-type transistor and a second resistor connected in series;

[0035] A first pole of the first N-type transistor is connected to the ground voltage, a second pole of the first N-type transistor is connected to the data output terminal, and a gate of the first N-type transistor is configured to receive the fifth control signal;

[0036] A first pole of the second N-type transistor is connected to the second pole of the first N-type transistor, a second pole of the second N-type transistor is connected to a first end of the second resistor, a gate of the second N-type transistor is configured to receive the sixth control signal, and a second end of the second resistor is connected to the data output terminal.

[0037] In some embodiments, the control signal generation circuit further includes:

[0038] A fourth generation circuit for generating the fifth control signal;

[0039] A fifth generation circuit for generating the sixth control signal.

[0040] In some embodiments, the fourth generation circuit includes: a second NOR gate;

[0041] A first input terminal of the second NOR gate is configured to receive a second power gating signal; a second input terminal of the second NOR gate is configured to receive a third code; an output terminal of the second NOR gate is connected to a control terminal of the first pull-down driving unit; wherein, when the second power gating signal is valid, the second pull-down driving unit is disconnected from the ground voltage.

[0042] In some embodiments, the fifth generation circuit includes: a third NOT gate;

[0043] An input terminal of the third NOT gate is configured to receive the first data signal, and an output terminal of the third NOT gate is configured to output the sixth control signal.

[0044] In some embodiments, the data output circuit further includes: a sampling circuit connected to the control signal generation circuit;

[0045] The sampling circuit is configured to sample an initial data signal;

[0046] The sampling circuit is connected to the control signal generation circuit and outputs the first data signal.

[0047] In some embodiments, the sampling circuit includes: a second selector;

[0048] An input terminal of the second selector is configured to receive the initial data signal, a control terminal of the second selector is configured to receive a clock signal, and the second selector is configured to sample the initial data signal based on the clock signal and output the first data signal.

[0049] The data output circuit according to the embodiments of the present disclosure can determine a first code based on the attenuation of the output data from the data output terminal to the external data port, so as to select and output an appropriate control signal. The driving circuit generates an appropriate output voltage according to the control signal, so as to reduce the influence caused by possible subsequent signal attenuation and ensure the accuracy of the data collected by the external data port. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Figure 1 It is a schematic diagram of a data output circuit in some embodiments;

[0051] Figures 2 to 12 It is a schematic diagram of the data output circuit provided by the embodiments of the present disclosure;

[0052] Figures 13 to 15 It is a schematic diagram of a sampling circuit in the data output circuit provided by the embodiments of the present disclosure;

[0053] Figure 16 It is a schematic diagram of the data output circuit provided by the embodiments of the present disclosure. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0054] To facilitate the understanding of the present disclosure, the present disclosure will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present disclosure more thorough and comprehensive.

[0055] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present disclosure belongs. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0056] The memory includes a plurality of storage units, and the data in the storage units can be "0" or "1". In some embodiments, the data in the storage units can be transmitted to the data output terminal OUTPUT through Figure 1 the data output circuit 100 shown. The data output circuit 100 shown includes:

[0057] The pull-up driving circuit 210 includes N parallel pull-up units. The first end of each pull-up unit is connected to the power supply voltage, the second end of each pull-up unit is connected to the data output terminal, and each pull-up unit includes a first NMOS transistor and a first resistor connected in series. The gate of the first NMOS transistor is the control end of each pull-up unit, and it responds to the pull-up signal.

[0058] The pull - down driving circuit 310 includes N parallel pull - down units. The first end of each pull - down unit is connected to the ground voltage, the second end of each pull - down unit is connected to the data output terminal, and each pull - down unit includes a second NMOS transistor and a second resistor connected in series. The gate of the second NMOS transistor is the control end of each pull - down unit, which responds to the pull - down signal.

[0059] The pull - up signal generation circuit 220 includes N first NOR gates. Each first NOR gate is used to receive the input data DATA and the corresponding pull - up calibration code ZQPU and output a pull - up signal. The pull - up calibration code ZQPU is generated by a terminal resistor calibration circuit (not shown).

[0060] The pull - down signal generation circuit 320 includes N second NOR gates. Each second NOR gate is used to receive the input data DATA and the corresponding pull - down calibration code ZQPD and output a pull - down signal. The pull - down calibration code ZQPU is generated by a terminal resistor calibration circuit (not shown).

[0061] The N pull - up calibration codes ZQPU and the N pull - down calibration codes ZQPD can be used to adjust the opening degrees of the respective first NMOS transistors and second NMOS transistors, so that their corresponding output voltage values are different.

[0062] Then, the output voltage is transmitted to the external data port through the data output terminal. On the one hand, the transmission path between the data output terminal and the external data port is too long. On the other hand, the transmission medium between the data output terminal and the external data port will absorb the signal. Both of these will cause the transmitted output voltage, that is, the output data, to attenuate. For example, the voltage of the output data attenuates from 1V to 0.6V. At this time, the data transmitted to the external data port may not be full - amplitude data. When such data is collected by the external data port, the data in the storage unit may be misjudged, which will seriously affect the performance of the memory. How to enable the external data port to collect the correct stored data has become an urgent problem to be solved.

[0063] An embodiment of the present disclosure provides a data output circuit 1000, as Figure 2 shown. The data output circuit includes:

[0064] A selection circuit 400, configured to select and output a first control signal SIG1 or select and output a second control signal SIG2 according to the received first code CODE1;

[0065] The driving circuit 500 is connected to the selection circuit 400. The driving circuit 500 is configured to receive a first data signal DATA and output a first level V1 according to the first control signal SIG1, or output a second level V2 according to the second control signal SIG2. The first level V1 includes a power supply voltage VDD. The second level V2 is greater than the first level V1.

[0066] For the case where the output voltage decays from the data output terminal OUTPUT to the external data port DQ PAD, the driving circuit 500 can be made to receive the second control signal SIG2, so that the data output terminal of the driving circuit 500 can output a second voltage V2 greater than the power supply voltage, to make up for the attenuation loss of the output voltage, so that the voltage collected by the external data port can still correctly represent the value of the received first data signal DATA.

[0067] For the case where the output voltage from the data output terminal OUTPUT to the external data terminal DQ PAD does not decay, or the decay is very small and does not affect subsequent judgment, the driving circuit 500 can be made to receive the first control signal SIG1, so that the data output terminal of the driving circuit 500 can output a first voltage V1, that is, the power supply voltage. At this time, the voltage collected by the external data port can still correctly represent the value of the received first data signal DATA.

[0068] The data output circuit according to the embodiments of the present disclosure can determine the first code CODE1 based on the attenuation of the output data from the data output terminal OUTPUT to the external data port DQ PAD, so as to select and output an appropriate control signal. The driving circuit 500 generates an appropriate output voltage according to the control signal, so as to reduce the influence caused by possible subsequent signal attenuation and ensure the accuracy of the data collected by the external data port DQ PAD.

[0069] In some embodiments, if the attenuation rate of the output data from the data output terminal OUTPUT to the external data port DQ PAD (attenuation rate = ((voltage output by the data output terminal - voltage collected by the external data) / voltage output by the data output terminal * 100%)) is greater than a first preset value, the first code CODE1 is used to select and output the second control signal SIG2 to output the second voltage V2 to increase the voltage value of the output data. Conversely, the first code CODE1 is used to select and output the first control signal SIG1 to output the first voltage V1 without increasing the voltage value of the output data.

[0070] In some embodiments, if it is measured that the output impedance from the data output terminal OUTPUT to the external data port DQ PAD is greater than a second preset value, the first code CODE1 is used to select and output a second control signal SIG2 to output a second voltage V2 to increase the voltage value of the output data. Conversely, the first code CODE1 is used to select and output a first control signal SIG1 to output a first voltage V1 without increasing the voltage value of the output data.

[0071] In some embodiments, as Figure 3 shown, the selection circuit 1000 includes a first selector 410;

[0072] The control terminal of the first selector 410 is used to receive the first code CODE1; the first input terminal 411 of the first selector 410 is used to receive the first control signal SIG1, and the second input terminal 412 of the first selector is used to receive the second control signal SIG2;

[0073] When the first code CODE1 is a first value, the first selector correspondingly outputs the first control signal, and when the first code CODE1 is a second value, the first selector correspondingly outputs the second control signal.

[0074] The first code CODE1 may be an impedance calibration code. The impedance calibration code can be used to calibrate the internal impedance and is used to calibrate the offset of the internal impedance caused by temperature, time, etc. For example, the impedance calibration code may be a ZQ calibration code provided by a ZQ calibration circuit. The impedance calibration code can be used to calibrate the external impedance, and the external impedance includes the impedance between the data output terminal and the external data port.

[0075] The first selector 410 correspondingly outputs the first control signal SIG1 or the second control signal SIG2 according to different values of the first code CODE1.

[0076] In some embodiments, when the first value is the binary data "0" (abbreviation "0") representing a low level, the first selector 410 selects and outputs the first control signal SIG1. When the second value is the binary data "1" (abbreviation "1") representing a high level, the first selector 410 selects and outputs the second control signal SIG2.

[0077] In some other embodiments, when the first value is "0", the first selector 410 selects and outputs the second control signal SIG2. When the second value is "1", the first selector 410 selects and outputs the first control signal SIG1.

[0078] In some embodiments, as Figure 4As shown, the driving circuit 500 includes a first pull-up driving unit 510 and a second pull-up driving unit 520;

[0079] A first end of the first pull-up driving unit 510 is connected to a power supply voltage VDD, and a control end of the first pull-up driving unit 510 is connected to an output end of the selection circuit 400 for receiving the first control signal SIG1 or the second control signal SIG2;

[0080] A first end of the second pull-up driving unit 520 is connected to a second end of the first pull-up driving unit 510, a second end of the second pull-up driving unit 520 is a data output end OUTPUT, and a control end of the second pull-up driving unit 520 is for receiving a third control signal SIG3;

[0081] Under the condition that the second pull-up driving unit 520 is turned on, the driving circuit 500 is configured to output the first level V1 through the data output end OUTPUT according to the first control signal SIG1, or to output the second level V2 through the data output end OUTPUT according to the second control signal SIG2.

[0082] As Figure 4 shown, when the second pull-up driving unit 520 is turned on, the voltage at the second end of the first pull-up driving unit 510 can be transferred to the data output end OUTPUT.

[0083] The second pull-up driving unit 520 is turned on or off based on the third control signal SIG3.

[0084] In some embodiments, as Figure 5 shown, the first pull-up driving unit 510 includes: a first P-type transistor P1 and a capacitor C1; the second pull-up driving unit 520 includes: a second P-type transistor P2 and a first resistor R1 connected in series;

[0085] The capacitor C1 is connected between a gate of the first P-type transistor P1 and a second pole of the first P-type transistor P1; a first pole of the first P-type transistor P1 is connected to the power supply voltage VDD, and a gate of the first P-type transistor P1 is for receiving the first control signal SIG1 or the second control signal SIG2;

[0086] A first pole of the second P-type transistor P2 is connected to the second pole of the first P-type transistor P1; a second pole of the second P-type transistor P2 is connected to a first end of the first resistor R1; a gate of the second P-type transistor P2 is for receiving the third control signal SIG3; a second end of the first resistor R1 is the data output end OUTPUT.

[0087] The first and second poles of the first P-type transistor P1 can be the source or the drain respectively. The first and second poles of the second P-type transistor P1 can also be the source or the drain respectively.

[0088] In some embodiments, the second control signal SIG2 can be a pulse signal. When the first P-type transistor P1 receives this pulse signal, since the capacitor C1 is coupled between the gate and the drain of the first P-type transistor P1, by utilizing the principle that the voltage difference across the capacitor C1 cannot change abruptly, the goal of outputting a second voltage (greater than the power supply voltage VDD) at the node NODE1 is achieved.

[0089] This pulse signal can be as Figure 6 shown. Specifically, this pulse signal is at a low level during the first time period T1. For the first P-type transistor P1, it is in the conducting state at this time. If the second P-type transistor is conducting at this time, the voltage of the data output terminal OUTPUT is the first voltage V1.

[0090] The pulse signal is at a high level during the second time period T2. For the first P-type transistor P1, it is in the cut-off state at this time. At this time, the first P-type transistor P1 can be equivalent to a second capacitor C2, and the capacitance value of the second capacitor C2 is the gate capacitance c2 of the first P-type transistor P1. The capacitance value of the first capacitor C1 is c1. If the second P-type transistor P2 is conducting at this time, the voltage of the data output terminal OUTPUT is Vdd + c1 / (c1 + c2) * Vdd. The value range of Vdd + c1 / (c1 + c2) * Vdd is: Vdd < Vdd + c1 / (c1 + c2) * Vdd < 2Vdd.

[0091] In this way, an output voltage greater than the power supply voltage VDD is obtained. In the embodiments of the present disclosure, by selecting appropriate the first P-type transistor P1 and the first capacitor C1, the required second voltage V2 can be obtained.

[0092] For example, when the ratio of the gate capacitance c2 of the first P-type transistor P1 to the capacitance value of the first capacitor C1 is 1:1, the output voltage of the data output terminal OUTPUT is 1.5VDD.

[0093] When the ratio of the gate capacitance c2 of the first P-type transistor P1 to the capacitance value of the first capacitor C1 is 1:2, the output voltage of the data output terminal OUTPUT is 1.67VDD.

[0094] Furthermore, in the embodiments of the present disclosure, by adjusting the ratio of the gate capacitance c2 of the first P-type transistor P1 to the capacitance value of the first capacitor C1, the required second voltage V2 can be obtained.

[0095] The first control signal SIG1 can be a low-level signal or a high-level signal. When the gate of the first P-type transistor P1 is used to receive the first control signal SIG1 which is a low-level signal, the first P-type transistor P1 conducts and outputs the power supply voltage.

[0096] The gate of the second P-type transistor P2 is used to receive the third control signal SIG3. The second P-type transistor P2 is used to control whether to allow the voltage at the node NODE1 to be transferred to the data output terminal OUTPUT. When the third control signal is a low-level signal, when the second P-type transistor P2 is made to conduct, the voltage at the node NODE1 is allowed to be transferred to the data output terminal OUTPUT. When the third control signal SIG3 is a high-level signal, when the second P-type transistor P2 is made to cut off, the voltage at the node NODE1 is not allowed to be transferred to the data output terminal OUTPUT.

[0097] In some embodiments, as Figure 7 shown, the data output circuit 1000 further includes: a control signal generation circuit 600 connecting the selection circuit 400 and the drive circuit 500;

[0098] The control signal generation circuit 600 includes:

[0099] a first generation circuit 610 for generating the first control signal SIG1;

[0100] a second generation circuit 620 for generating the second control signal SIG2;

[0101] a third generation circuit 630 for generating the third control signal SIG3.

[0102] In some embodiments, as Figure 8 shown, the first generation circuit 610 includes: a NAND gate 611;

[0103] The first input terminal of the NAND gate 611 is used to receive the second code CODE2, the second input terminal of the NAND gate 611 is used to receive the first power gating signal PG1, and the output terminal of the NAND gate 611 is used to output the first control signal SIG1; wherein, when the first power gating signal PG1 is valid, the first pull-up driving unit 510 is disconnected from the power supply voltage VDD.

[0104] In some embodiments, the second code CODE2 can be a fixed signal, for example, a high signal "1".

[0105] In some embodiments, the second code CODE2 can also be an impedance calibration code (for example, a ZQ calibration code), that is, the second code CODE2 can be provided by a ZQ calibration circuit.

[0106] In some embodiments, the second code CODE2 is equal to the first code COED1. That is, when the first code COED1 is "1", the second code CODE2 is also "1". When the first code COED1 is "0", the second code CODE2 is also "0".

[0107] The first power gating signal PG1 being valid means that when the first power gating signal PG1 is a low-level signal "0", regardless of the value of the second code CODE2, the output signal of the first NAND gate 611 is a high-level signal, so that the first pull-up driving unit 510 is in a cut-off state, playing a role in turning off the current path of the power supply voltage VDD to the data output terminal OUTPUT. That is, when the first power gating signal PG1 is valid, the driving circuit 500 (including the first pull-up driving unit 510 and the second pull-up driving unit 520) is in a power-saving mode.

[0108] When the first power gating signal PG1 is valid, the value of the second code CODE2 does not affect the first generating circuit 610 from generating a signal to turn off the first pull-up driving unit 510. When the first power gating signal PG1 is invalid, the value of the second code CODE2 is "1" so that the first generating circuit 610 generates a signal to turn on the first pull-up driving unit 510.

[0109] In some embodiments, as Figure 8 shown, the second generating circuit includes: a first NOR gate 622 and a first NOT gate 621;

[0110] The input terminal of the first NOT gate 621 receives the first data signal DATA, and the output terminal of the first NOT gate 621 outputs a fourth control signal SIG4;

[0111] The first input terminal of the first NOR gate 622 receives the first data signal DATA;

[0112] The second input terminal of the first NOR gate 622 is connected to the output terminal of the first NOT gate 621 for receiving the fourth control signal SIG4;

[0113] The output terminal of the first NOR gate 622 is used to output the second control signal SIG2.

[0114] It can be understood that when any one end of the first NOR gate 622 inputs "1", its output signal is "0", and only when the input signals at both ends of the first NOR gate 622 are both "0", its output signal is "1". The fourth control signal SIG4 received by the second input terminal of the first NOR gate 622 is an inverted delay signal of the first data signal DATA.

[0115] Therefore, the first NOT gate 621 and the first NOR gate 622 can generate a short high-level pulse signal as the second control signal SIG2 by using the first data signal DATA.

[0116] In some embodiments, as Figure 8 shown, the third generation circuit 630 includes: a second NOT gate 631;

[0117] The input terminal of the second NOT gate 631 is used to receive the first data signal DATA, and the output terminal of the second NOT gate 631 is used to output the third control signal SIG3.

[0118] The third control signal SIG3 is an inverted delay signal of the first data signal DATA.

[0119] In some embodiments, the second NOT gate 631 and the first NOT gate 621 can also be the same NOT gate. That is, the fourth control signal SIG4 can be used as the third control signal SIG3.

[0120] When the first data signal DATA is "1", the third control signal SIG3 is a low-level signal, and the second P-type transistor receives this low-level signal and conducts.

[0121] When the first data signal DATA is "0", the third control signal SIG3 is a high-level signal, and the second P-type transistor receives this high-level signal and cuts off.

[0122] Therefore Figure 8 the first pull-up driving unit 510 and the second pull-up driving unit 520 shown can only be used to drive high-level signals and cannot drive low-level signals.

[0123] Compared with directly outputting the first data signal DATA as the third control signal SIG3 to the second pull-up driving unit 520, adding the second NOT gate 631 between the second pull-up driving unit 520 and the first data signal can enhance the data driving ability. Avoid a large attenuation of the first data signal DATA before it is input to the second pull-up driving unit 520.

[0124] In some embodiments, a repeater can also be connected between the second NOT gate 631 and the second pull-up driving unit 520 to further improve the driving ability of the signal output by the second NOT gate 631.

[0125] In some embodiments, as Figure 9 shown, the driving circuit 500 is used to receive the first data signal DATA and output a third level according to the fifth control signal SIG5; the third level includes the ground voltage VSS; the driving circuit 500 further includes a first pull-down driving unit 530 and a second pull-down driving unit 540:

[0126] The first end of the first pull - down driving unit 530 is connected to the ground voltage VSS, and the control end of the first pull - down driving unit 530 is used to receive the fifth control signal SIG5;

[0127] The first end of the second pull - down driving unit 540 is connected to the second end of the first pull - down driving unit, the second end of the second pull - down driving unit is the data output terminal OUTPUT, and the control end of the second pull - down driving unit is used to receive the sixth control signal SIG6;

[0128] Under the condition that the second pull - down driving unit 540 is turned on, the first pull - down driving unit 530 is used to receive the fifth control signal SIG5 and correspondingly output the third level.

[0129] As Figure 9 shown, when the second pull - down driving unit 540 is turned on, the voltage VSS at the second end of the first pull - down driving unit 530 can be transferred to the data output terminal OUTPUT. It can be understood that at this time, at least one of the first pull - up driving unit 510 and the second pull - up driving unit 520 is cut off.

[0130] The second pull - down driving unit 540 is turned on or off based on the sixth control signal SIG6. The second pull - down driving unit 540 includes an NMOS transistor. At this time, when the sixth control signal SIG6 is a high - level signal, the second pull - down driving unit 540 is turned on; when the sixth control signal SIG6 is a low - level signal, the second pull - down driving unit 540 is cut off.

[0131] Also, for example, the second pull - down driving unit 540 includes a PMOS transistor. At this time, when the sixth control signal SIG6 is a low - level signal, the second pull - down driving unit 540 is turned on; when the sixth control signal SIG6 is a high - level signal, the second pull - down driving unit 540 is cut off.

[0132] The first pull - down driving unit 530 is turned on or off based on the fifth control signal SIG5. The first pull - down driving unit 530 includes an NMOS transistor. At this time, when the fifth control signal SIG5 is a high - level signal, the first pull - down driving unit 530 is turned on; when the fifth control signal SIG5 is a low - level signal, the first pull - down driving unit 530 is cut off.

[0133] Also, for example, the first pull - down driving unit 530 includes a PMOS transistor. At this time, when the fifth control signal SIG5 is a low - level signal, the first pull - down driving unit 530 is turned on; when the fifth control signal SIG5 is a high - level signal, the first pull - down driving unit 530 is cut off.

[0134] When the voltage output from the data output terminal OUTPUT is used to reflect the level of the first data signal DATA, that is, when used as a data output circuit, when the first pull-up driving unit 510 and the second pull-up driving unit 520 are turned on, at least one of the first pull-down driving unit 510 and the second pull-down driving unit 520 is turned off to output the power supply voltage VDD and a voltage greater than the power supply voltage VDD. When the first pull-down driving unit 510 and the second pull-down driving unit 520 are turned on, at least one of the first pull-up driving unit 510 and the second pull-up driving unit 520 is turned off to output the ground voltage VSS.

[0135] In some embodiments, as Figure 10 shown, the first pull-down driving unit 530 includes: a first N-type transistor N1; the second pull-down driving unit 540 includes: a second N-type transistor N2 and a second resistor R2 connected in series;

[0136] A first pole of the first N-type transistor N1 is connected to the ground voltage VSS, a second pole of the first N-type transistor is connected to the data output terminal OUTPUT, and a gate of the first N-type transistor N1 is used to receive the fifth control signal SIG5;

[0137] A first pole of the second N-type transistor N2 is connected to the second pole of the first N-type transistor N1, a second pole of the second N-type transistor N2 is connected to a first end of the second resistor R2, a gate of the second N-type transistor N2 is used to receive the sixth control signal SIG6, and a second end of the second resistor R2 is connected to the data output terminal OUTPUT.

[0138] When the fifth control signal SIG5 is a low-level signal, the gate of the first N-type transistor N1 receives this signal and is turned off.

[0139] When the fifth control signal SIG5 is a high-level signal, the gate of the first N-type transistor N1 receives this signal and is turned on.

[0140] When the sixth control signal SIG6 is a low-level signal, the gate of the second N-type transistor N2 receives this signal and is turned off.

[0141] When the sixth control signal SIG6 is a high-level signal, the gate of the second N-type transistor N2 receives this signal and is turned on.

[0142] In some embodiments, as Figure 11 shown, the control signal generation circuit further includes:

[0143] a fourth generation circuit 640 for generating the fifth control signal SIG5;

[0144] The fifth generation circuit 650 for generating the sixth control signal SIG6.

[0145] In some embodiments, as Figure 12 shown, the fourth generation circuit 640 includes: a second NOR gate 641;

[0146] The first input terminal of the second NOR gate 641 is used to receive the second power gating signal PG2; the second input terminal of the second NOR gate 641 is used to receive the third code CODE3; the output terminal of the second NOR gate 641 is connected to the control terminal of the first pull-down driving unit 530; wherein, when the second power gating signal PG2 is valid, the second pull-down driving unit 530 is disconnected from the ground voltage VSS.

[0147] It can be understood that when any one end of the second NOR gate 641 inputs "1", its output signal is "0", and only when the input signals at both ends of the second NOR gate 641 are both "0", its output signal is "1".

[0148] The second power gating signal PG2 being valid means that when the second power gating signal PG2 is a high-level signal "1", regardless of the value of the third code CODE3, the output signal of the second NOR gate 641 is a low-level signal, so that the first pull-down driving unit 530 is in a cut-off state, playing a role in turning off the current path from the ground voltage VSS to the data output terminal OUTPUT. That is, when the second power gating signal PG2 is valid, the lower half of the driving circuit 500 (including the first pull-down driving unit 530 and the second pull-down driving unit 540) is in a power-saving mode.

[0149] In some embodiments, as Figure 12 shown, the fifth generation circuit 650 includes: a third NOT gate 651;

[0150] The input terminal of the third NOT gate 651 is used to receive the first data signal DATA, and the output terminal of the third NOT gate 651 is used to output the sixth control signal SIG6.

[0151] The sixth control signal SIG6 is an inverted delay signal of the first data signal DATA.

[0152] When the first data signal DATA is "1", the sixth control signal SIG6 is a low-level signal, and the second N-type transistor N2 receives this low-level signal and is cut off.

[0153] When the first data signal DATA is "0", the sixth control signal SIG6 is a high-level signal, and the second N-type transistor N2 receives this high-level signal and is turned on.

[0154] Therefore Figure 12The first pull-down driving unit and the second pull-down driving unit shown can only be used to drive low-level data signals and cannot drive high-level data signals.

[0155] Compared with directly outputting the first data signal DATA as the sixth control signal SIG6 to the second pull-down driving unit 540, adding a third NOT gate 641 between the second pull-down driving unit 540 and the first data signal can enhance the data driving ability and prevent a large attenuation of the first data signal DATA before it is input to the second pull-down driving unit 540.

[0156] In some embodiments, a repeater can also be connected between the third NOT gate 641 and the second pull-down driving unit 540 to further improve the driving ability of the signal output by the third NOT gate 641.

[0157] In some embodiments, as Figure 13 shown, the data output circuit further includes: a sampling circuit 700 connected to the control signal generation circuit;

[0158] The sampling circuit 700 is used to sample the initial data signal DATA1;

[0159] The sampling circuit 700 is connected to the control signal generation circuit and outputs the first data signal DATA.

[0160] For example, the initial data signal includes a set of data signals, such as "11100000". The sampling circuit 700 can sample this signal to increase or decrease the data frequency. For example, by retaining the odd-numbered data, the sampled signal is "1100", which is the first data signal.

[0161] The sampling circuit 700 can also perform grouped sampling on this signal. For example, sampling the odd-numbered signals at the rising edge of the signal and / or sampling the even-numbered signals at the falling edge of the signal. The sampled signal is "1100" or "1000" or "11100000", which is the first data signal.

[0162] In some embodiments, as Figure 14 shown, the sampling circuit 700 includes: a second selector 710;

[0163] The second selector 710 can be a data selector. Its input terminal is used to receive the initial data signal DATA1, and the control terminal of the second selector 710 is used to receive the clock signal WCK. The second selector is used to sample the initial data signal DATA1 based on the clock signal WCK and output the first data signal DATA.

[0164] In some embodiments, as Figure 15As shown, the second selector 710 can be a two-to-one data selector, and the clock signal WCK includes a first clock signal WCK1 and a second clock signal WCK2. The phases of the first clock signal WCK1 and the second clock signal WCK2 can be opposite. The second selector 710 has a first input terminal and a second input terminal. When the first clock signal WCK1 is valid, for example, the initial data signal DATA1 corresponding to the rising edge of the first clock signal WCK1 at the first input terminal can be output as the first data signal DATA. When the second clock signal WCK2 is valid, for example, the initial data signal DATA1 corresponding to the rising edge of the second clock signal WCK2 at the second input terminal can be output as the first data signal DATA. Compared with using one clock signal, in this way, the sampling frequency of the data can be increased.

[0165] In summary, in the embodiments of the present disclosure, in the first aspect, by using a selection circuit, the first pull-up driving unit can accept one of two control signals, so that the data driver can output at least the power supply voltage and a voltage greater than the power supply voltage.

[0166] In the second aspect, the first data signal is directly connected to the second pull-up driving unit through a NOT gate (the third NOT gate) instead of through the NOR gate in Figure 1 , which can reduce the delay time caused by the first data signal passing through the first driving unit. The second pull-up driving unit is used to transmit the high-level data in the first data signal. And functions such as ZQ coding and power gating are embodied by the first pull-up driving unit.

[0167] There are also the following examples in the embodiments of the present disclosure, as Figure 16 shown, the data output circuit includes (N + 1) selection circuits 400, (N + 1) driving circuits 500, and (N + 1) control signal generation circuits 600.

[0168] In the embodiments of the present disclosure, the first code is (N + 1) ZQ pull-up calibration codes (ZQPU[n:0]) stored in the ZQ calibration circuit. The second code in the embodiments of the present disclosure is also the ZQ pull-up calibration code (ZQPU[n:0]). The third code is (N + 1) ZQ pull-down calibration codes (ZQPD[n:0]) stored in the ZQ calibration circuit.

[0169] The first selection circuit 400 is used to receive ZQPU[0] and ZQPD[0], and the first control signal generation circuit is used to receive ZQPU[0]; the second selection circuit 400 is used to receive ZQPU[1] and ZQPD[1], and the second control signal generation circuit is used to receive ZQPU[1]; and so on.

[0170] Each driving circuit includes a first pull-up driving unit, and the first pull-up driving unit includes a first P-type transistor P1. The gates of each first P-type transistor P1 are connected together. Each driving circuit includes a second pull-up driving unit, and the second pull-up driving unit includes a second P-type transistor P2 and a first resistor R1. The gates of each second P-type transistor P2 are connected together. Each driving circuit includes a first pull-down driving unit 530, and the first pull-down driving unit includes a first N-type transistor N1. The gates of each first N-type transistor N1 are connected together. Each driving circuit includes a second pull-down driving unit 540, and the second pull-down driving unit 540 includes a second N-type transistor N2 and a second resistor R2. The gates of each second N-type transistor N2 are connected together.

[0171] In some embodiments, a first repeater 810 is further included between the output terminal of the first NOT gate 622 and the second P-type transistor P2, for holding the output third control signal SIG3.

[0172] In some embodiments, a second repeater 820 is further included between the output terminal of the third NOT gate 641 and the second N-type transistor N2, for holding the output sixth control signal SIG6.

[0173] In the embodiments of the present disclosure, when the first data signal DATA is a high-level data "1", the second P-type transistor P2 is turned on and the second N-type transistor N2 is turned off.

[0174] The data output circuit includes (N + 1) selection circuits, which sequentially receive one of ZQPU[n:0].

[0175] When the corresponding pull-up calibration code ZQPU code received by the selection circuit 400 is "1", the first control signal SIG1 output by the first generating circuit is received, and the power supply voltage is output at the data output terminal OUTPUT.

[0176] When the corresponding pull-up calibration code ZQPU code received by the selection circuit is "0", the second control signal SIG2 output by the second generating circuit is received. The second voltage greater than the power supply voltage is output at the data output terminal OUTPUT.

[0177] When the first data signal DATA is a high-level data "0", the second P-type transistor P2 is turned off and the second N-type transistor N2 is turned on.

[0178] (N + 1) fourth generation circuits sequentially receive one of ZQPD[n:0]. When the second power gating signal is "1", the fourth generation circuit outputs the signal "1", and all the first N-type transistors N1 are turned off. When the second power gating signal is "0", and when the corresponding pull-down calibration code ZQPD code received by the fourth generation circuit is "0", the corresponding first N-type transistor N1 is turned on, and the data output terminal OUTPUT outputs the ground voltage. When the second power gating signal is "0", and when the corresponding pull-down calibration code ZQPD code received by the fourth generation circuit is "1", the corresponding first N-type transistor N1 is turned off.

[0179] Embodiments of the present disclosure utilize the pull-up calibration code ZQPU[n:0], the pull-down calibration code ZQPD[n:0], and a selection circuit to adjust the states of transistors in the corresponding driving circuit, so that their corresponding output voltage values are different to obtain the target voltage.

[0180] It should be understood that "some embodiments", "an embodiment", or "one embodiment" mentioned throughout the specification means that specific features, structures, or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, the appearances of "in an embodiment" or "in one embodiment" throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures, or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present disclosure, the magnitudes of the sequence numbers of the above processes do not mean the order of execution, and the order of execution of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present disclosure. The sequence numbers of the embodiments of the present disclosure above are only for description and do not represent the advantages or disadvantages of the embodiments.

[0181] It should be noted that in this article, the term "comprising", "including" or any other variant thereof is intended to cover a non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including a..." does not exclude the existence of additional identical elements in the process, method, article or device including the element.

[0182] The above is only the implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present disclosure, and all of them should be covered by the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A data output circuit, characterized in that, The data output circuit includes: a selection circuit configured to select and output a first control signal or a second control signal according to a received first code; a driving circuit connected to the selection circuit, the driving circuit being configured to receive a first data signal and output a first level according to the first control signal, or output a second level according to the second control signal; the first level includes a power supply voltage; the second level is greater than the first level; the selection circuit includes a first selector; a control terminal of the first selector is configured to receive the first code; a first input terminal of the first selector is configured to receive the first control signal, and a second input terminal of the first selector is configured to receive the second control signal; If the attenuation rate of the output data of the data output circuit from the data output terminal to the external data port is greater than a first preset value, the second control signal is selected and output by using the first code; otherwise, the first control signal is selected and output by using the first code.

2. The data output circuit according to claim 1, wherein When the first code is a first value, the first selector correspondingly outputs the first control signal; when the first code is a second value, the first selector correspondingly outputs the second control signal.

3. The data output circuit according to claim 1, wherein the driving circuit includes a first pull-up driving unit and a second pull-up driving unit; a first end of the first pull-up driving unit is connected to the power supply voltage, and a control terminal of the first pull-up driving unit is connected to an output terminal of the selection circuit for receiving the first control signal or the second control signal; a first end of the second pull-up driving unit is connected to a second end of the first pull-up driving unit, a second end of the second pull-up driving unit is the data output terminal, and a control terminal of the second pull-up driving unit is configured to receive a third control signal; Under the condition that the second pull-up driving unit is turned on, the driving circuit is configured to output the first level through the data output terminal according to the first control signal, or output the second level through the data output terminal according to the second control signal.

4. The data output circuit according to claim 3, wherein the first pull-up driving unit includes: a first P-type transistor and a capacitor; the second pull-up driving unit includes: a second P-type transistor and a first resistor connected in series; the capacitor is connected between a gate of the first P-type transistor and a second pole of the first P-type transistor; a first pole of the first P-type transistor is connected to the power supply voltage, and the gate of the first P-type transistor is configured to receive the first control signal or the second control signal; a first pole of the second P-type transistor is connected to the second pole of the first P-type transistor; a second pole of the second P-type transistor is connected to a first end of the first resistor; a gate of the second P-type transistor is configured to receive the third control signal; a second end of the first resistor is the data output terminal.

5. The data output circuit according to claim 3, wherein the data output circuit further includes: a control signal generation circuit connected to the selection circuit and the driving circuit; the control signal generation circuit includes: a first generation circuit for generating the first control signal; a second generation circuit for generating the second control signal; a third generation circuit for generating the third control signal.

6. The data output circuit according to claim 5, wherein the first generation circuit includes: a NAND gate; The first input terminal of the NAND gate is used to receive the second code, the second input terminal of the NAND gate is used to receive the first power gating signal, and the output terminal of the NAND gate is used to output the first control signal; wherein, when the first power gating signal is valid, the first pull-up driving unit is disconnected from the power supply voltage.

7. The data output circuit according to claim 5, wherein The second generating circuit includes: a first NOR gate and a first NOT gate; The input terminal of the first NOT gate receives the first data signal, and the output terminal of the first NOT gate outputs a fourth control signal; The first input terminal of the first NOR gate receives the first data signal; The second input terminal of the first NOR gate is connected to the output terminal of the first NOT gate for receiving the fourth control signal; The output terminal of the first NOR gate is used to output the second control signal.

8. The data output circuit according to claim 5, wherein The third generating circuit includes: a second NOT gate; The input terminal of the second NOT gate is used to receive the first data signal, and the output terminal of the second NOT gate is used to output the third control signal.

9. The data output circuit according to claim 5, wherein The driving circuit is used to receive the first data signal and output a third level according to a fifth control signal; the third level includes a ground voltage; the driving circuit further includes a first pull-down driving unit and a second pull-down driving unit: The first end of the first pull-down driving unit is connected to the ground voltage, and the control terminal of the first pull-down driving unit is used to receive the fifth control signal; The first end of the second pull-down driving unit is connected to the second end of the first pull-down driving unit, the second end of the second pull-down driving unit is the data output terminal, and the control terminal of the second pull-down driving unit is used to receive a sixth control signal; Under the condition that the second pull-down driving unit is turned on, the first pull-down driving unit is used to receive the fifth control signal and correspondingly output the third level.

10. The data output circuit according to claim 9, wherein The first pull-down driving unit includes: a first N-type transistor; the second pull-down driving unit includes: a second N-type transistor and a second resistor connected in series; The first pole of the first N-type transistor is connected to the ground voltage, the second pole of the first N-type transistor is connected to the data output terminal, and the gate of the first N-type transistor is used to receive the fifth control signal; The first pole of the second N-type transistor is connected to the second pole of the first N-type transistor, the second pole of the second N-type transistor is connected to the first end of the second resistor, the gate of the second N-type transistor is used to receive the sixth control signal, and the second end of the second resistor is connected to the data output terminal.

11. The data output circuit according to claim 10, wherein The control signal generating circuit further includes: A fourth generating circuit for generating the fifth control signal; A fifth generating circuit for generating the sixth control signal.

12. The data output circuit according to claim 11, wherein The fourth generating circuit includes: a second NOR gate; The first input terminal of the second NOR gate is used to receive a second power gating signal; the second input terminal of the second NOR gate is used to receive a third code; the output terminal of the second NOR gate is connected to the control terminal of the first pull-down driving unit; wherein, when the second power gating signal is valid, the second pull-down driving unit is disconnected from the ground voltage.

13. The data output circuit according to claim 11, characterized in that The fifth generating circuit includes: a third NOT gate; The input terminal of the third NOT gate is used to receive the first data signal, and the output terminal of the third NOT gate is used to output the sixth control signal.

14. The data output circuit according to claim 9, wherein The data output circuit further includes: a sampling circuit connected to the control signal generation circuit; The sampling circuit is used to sample the initial data signal; The sampling circuit is connected to the control signal generation circuit and outputs the first data signal.

15. The data output circuit according to claim 14, wherein The sampling circuit includes: a second selector; The input terminal of the second selector is used to receive the initial data signal, the control terminal of the second selector is used to receive the clock signal, and the second selector is used to sample the initial data signal based on the clock signal and output the first data signal.

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