Ghost command suppression in half-frequency memory devices

Abstract

The present application relates to ghost command suppression in a half-frequency memory device. The memory device includes a command interface configured to receive a dual-cycle command from a host device via a plurality of command address bits. The memory device also includes a command decoder configured to decode a first portion of the plurality of command address bits in a first cycle of the dual-cycle command. The command decoder includes a mask circuit system. The mask circuit system includes a mask generation circuit system configured to generate a mask signal. The mask circuit system also includes a multiplexer circuit system configured to apply the mask signal to prevent the command decoder from decoding a second portion of the plurality of command address bits in a second cycle of the dual-cycle command.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to the field of semiconductor devices. More specifically, embodiments of the present disclosure relate to mask circuitry that masks command address bits that are not decoded as commands from being decoded in half-frequency circuits of a memory device. Background Art

[0002] Semiconductor devices (e.g., memory devices) utilize timing with shifts of data signals, data strobes, commands, and / or other signals to perform operations. Commands are decoded and captured using command address bits. Some memory devices that utilize addresses for their operations (e.g., write (WR), write mode (WRP), activate, and read commands) use command address bits that will be captured in a second cycle based on the decoded command. These second cycle command address bits may not need to be decoded and should not be decoded. However, some command address bits in the second cycle may appear as a first cycle of a ghost command when decoded incorrectly, even though they are not actually part of the first cycle of the command to be decoded to initiate the command. In other words, without some masking techniques, the memory device may not be able to distinguish whether the data on the command address bits is to be decoded as part of a newly received command.

[0003] Embodiments of the present disclosure may address one or more of the issues set forth above. Summary of the invention

[0004] According to aspects of the present application, a memory device is provided. The memory device includes: a command interface configured to receive a dual-cycle command from a host device via a plurality of command address bits; and a command decoder configured to decode a first portion of the plurality of command address bits in a first cycle of the dual-cycle command, and includes a mask circuit system including: a mask generation circuit system configured to generate a mask signal; and a multiplexer circuit system configured to apply the mask signal to prevent the command decoder from decoding a second portion of the plurality of command address bits in a second cycle of the dual-cycle command.

[0005] According to another aspect of the present application, a memory device is provided. The memory device includes: a command interface configured to receive a dual-cycle command from a host device via a plurality of command address bits; and a command decoder configured to decode a first portion of the plurality of command address bits in a first cycle of the dual-cycle command, comprising: a first pipeline including: a first mask generation circuit system configured to generate a first mask signal; a first multiplexer circuit system configured to apply the first mask signal when the first cycle is received in the first pipeline to prevent the command decoder from decoding a second portion of the plurality of command address bits in a second cycle of the dual-cycle command; row decoding, wherein the first pipeline operates using an even clock oscillating at half the frequency of a system clock containing the first and second cycles; and a second pipeline comprising: a second mask generation circuit system configured to generate a second mask signal; and a second multiplexer circuit system configured to apply the second mask signal when the first cycle is received in the second pipeline to prevent the command decoder from decoding the second portion of the plurality of command address bits in the second cycle of the two-cycle command, wherein the second pipeline operates using an odd clock oscillating at half the frequency of the system clock.

[0006] According to another aspect of the present application, a method is provided. The method includes: receiving a first portion of a plurality of command address bits at a command interface in a first cycle of a system clock; determining, using a mask generation circuit system of a memory device, whether a command corresponding to the plurality of command address bits is a valid two-cycle command or a second cycle of a two-cycle command; and based on the determination that the command is a valid two-cycle command, asserting a mask signal in the mask generation circuit system, wherein the assertion of the mask signal is configured to prevent decoding of a second portion of the plurality of command address bits received during a second cycle of the system clock corresponding to the two-cycle command. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a simplified block diagram illustrating certain features of a memory device with mask circuitry according to an embodiment of the present disclosure;

[0008] Figure 2 In 1N mode according to the embodiment Figure 1 A timing diagram of a half-frequency mode of a memory device;

[0009] Figure 3 In the 2N mode according to the embodiment Figure 1 A timing diagram of a half-frequency mode of a memory device;

[0010] Figure 4A method of manufacturing a mask generator circuit and a multiplexer circuit according to an embodiment of the present invention Figure 1 A block diagram of a mask circuit system;

[0011] Figure 5 According to the embodiment in 1N mode Figure 1 A timing diagram of a dual cycle command in a memory device;

[0012] Figure 6 According to the embodiment Figure 1 A timing diagram for a memory device that uses a dual cycle history to determine whether a cycle corresponds to a valid command or a ghost command in 1N mode; and

[0013] Figure 7 According to the embodiment Figure 1 A timing diagram for a memory device that uses a dual cycle history to determine whether a cycle corresponds to a valid command or a ghost command in a 1N mode with continuous commands;

[0014] Figure 8 According to the embodiment Figure 1 A timing diagram of a memory device receiving consecutive commands in a 2N mode;

[0015] Fig. 9 According to the embodiment Figure 1 A timing diagram of a memory device receiving a plurality of commands in a 2N mode;

[0016] Fig.10 According to the embodiment Figure 4 a circuit diagram of a mask-generating circuit system;

[0017] Fig.11 is an even-numbered pipeline according to an embodiment Figure 4 a circuit diagram of a multiplexer circuit system; and

[0018] Fig.12 is an odd-numbered pipeline according to an embodiment Figure 4 Circuit diagram of the multiplexer circuit system. DETAILED DESCRIPTION

[0019] One or more specific embodiments will be described below. In order to provide a brief description of these embodiments, not all features of the actual implementation are described in the specification. It should be understood that in the development of any such actual implementation, as in any engineering or design project, many implementation-specific decisions must be made to achieve the developer's specific goals, such as complying with system-related and business-related constraints, which may vary from implementation to implementation. In addition, it should be understood that this development work may be complex and time-consuming, but it will still be a routine task of design, fabrication, and manufacturing for those of ordinary skill who benefit from the present invention.

[0020] As previously described, the command address bits of the dual-cycle command may be captured in a continuous cycle of the system clock. For example, the bits in the second cycle may correspond to options and / or memory addresses to be used to execute a command (e.g., write, read, etc.). However, the bits captured in the second cycle may look like bits from the first cycle indicating a new command. If these ghost commands are not suppressed, they may be decoded incorrectly. In addition, suppressing or masking these ghost commands may become more complicated due to the use of a half-frequency mode of a masked memory device. The half-frequency mode means that the memory device includes two pipelines, each of which operates at a frequency that is half the frequency of the system clock. In addition, the half-frequency mode may include a 1N mode or a 2N mode. In the 1N mode, a dual cycle of the dual-cycle command is received in different pipelines on a continuous cycle of the system clock. In 2N mode, a double cycle of a double cycle command is received in the same pipeline on non-consecutive cycles of a system clock corresponding to a first pipeline (e.g., an even pipeline following an even cycle of the system clock), wherein the cycle is separated from another cycle of the system clock corresponding to a second pipeline (e.g., an odd pipeline following an odd cycle of the system clock).

[0021] Now turning to the graph, Figure 1 1 is a simplified block diagram illustrating certain features of memory device 10. Specifically, Figure 1 The block diagram of FIG. 1 is a functional block diagram illustrating certain functionality of the memory device 10. According to one embodiment, the memory device 10 may be a DDR5 SDRAM device. Various features of the DDR5 SDRAM allow for reduced power consumption, greater bandwidth, and greater storage capacity compared to previous generations of DDR SDRAM.

[0022] The memory device 10 may include a plurality of memory banks 12. For example, the memory banks 12 may be DDR5 SDRAM memory banks. The memory banks 12 may be provided on one or more chips (e.g., SDRAM chips) arranged on dual in-line memory modules (DIMMS). As will be appreciated, each DIMM may include a plurality of SDRAM memory chips (e.g., x8 or x16 memory chips). Each SDRAM memory chip may include one or more memory banks 12. The memory device 10 represents a portion of a single memory chip (e.g., SDRAM chip) having a plurality of memory banks 12. For DDR5, the memory banks 12 may be further arranged to form memory bank groups. For example, for an 8-gigabit (Gb) DDR5 SDRAM, the memory chip may include 16 memory banks 12 arranged into 8 memory bank groups, each memory bank group including 2 memory banks. For example, for a 16Gb DDR5 SDRAM, the memory chip may include 32 memory banks 12 arranged into 8 memory bank groups, each memory bank group including 4 memory banks. Various other configurations, arrangements, and sizes of banks 12 on memory device 10 may be utilized depending on the application and design of the overall system.

[0023] The memory device 10 may include a command interface 14 and an input / output (I / O) interface 16. The command interface 14 is configured to provide a plurality of signals (e.g., signals 15) from an external host device, such as a controller 17 that may be embodied as a processor and / or other host device. The processor or controller may provide various signals 15 to the memory device 10 to facilitate the transmission and receipt of data to be written to or read from the memory device 10.

[0024] As will be appreciated, the command interface 14 may include a plurality of circuits, such as a clock input circuit 18 and a command address input circuit 20, for example, to ensure proper handling of the signal 15. The command interface 14 may receive one or more clock signals from an external device. Typically, double data rate (DDR) memory utilizes a differentiated pair of system clock signals, referred to herein as a true clock signal (Clk_t) and a complementary or bar clock signal (Clk_c). The positive clock edge of DDR refers to the point where the rising true clock signal Clk_t intersects the falling bar clock signal Clk_c, while the negative clock edge indicates the transition of the falling true clock signal Clk_t and the rising of the bar clock signal Clk_c. Commands (e.g., read commands, write commands, etc.) are typically input on the positive edge of the clock signal, and data is transmitted or received on both the positive and negative clock edges.

[0025] The clock input circuit 18 receives the real clock signal (Clk_t) and the bar clock signal (Clk_c), and generates an internal clock signal CLK. The internal clock signal CLK is supplied to an internal clock generator, such as a delay locked loop (DLL) 30. The DLL 30 generates a phase-controlled internal clock signal LCLK based on the received internal clock signal CLK. The phase-controlled internal clock signal LCLK is supplied to, for example, the I / O interface 16, and is used as a timing signal for determining the output timing of read data.

[0026] The internal clock signal / phase CLK may also be provided to various other components within the memory device 10 and may be used to generate various additional internal clock signals. For example, the internal clock signal CLK may be provided to a command decoder 32. The command decoder 32 may receive command signals from a command bus 34 and may decode the command signals to provide various internal commands. For example, the command decoder 32 may provide the command signal to the DLL 30 via the bus 36 to coordinate the generation of the phase-controlled internal clock signal LCLK. For example, the phase-controlled internal clock signal LCLK may be used to clock data passing through the IO interface 16.

[0027] Furthermore, the command decoder 32 may decode commands such as read commands, write commands, mode register set commands, activate commands, and the like, and provide access to a particular memory bank 12 corresponding to the command via the bus path 40. Additionally or alternatively, the command decoder may send an internal write signal 41 to the IO interface 16. As will be appreciated, the memory device 10 may include various other decoders, such as row decoders and column decoders, to facilitate access to the memory banks 12. In one embodiment, each memory bank 12 includes a bank control block 22 that provides the necessary decoding (e.g., row decoders and column decoders), as well as other features such as timing control and data control to facilitate execution of commands to and from the memory banks 12.

[0028] The memory device 10 performs operations, such as read commands and write commands, based on command / address signals received from an external device, such as a processor. In one embodiment, the command / address bus may be a 14-bit bus to accommodate the command / address signals (CA<13:0>). The command / address signals are clocked to the command interface 14 using clock signals (Clk_t and Clk_c). The command interface may include a command address input circuit 20 configured to receive and transmit commands, such as through a command decoder 32, to provide access to the memory bank 12. In addition, the command interface 14 may receive a chip select signal (CS_n). The CS_n signal enables the memory device 10 to process commands on the incoming CA<13:0> bus. Access to a particular memory bank 12 within the memory device 10 is encoded with a command on the CA<13:0> bus. As previously discussed, command decoder 32 may include at least one mask circuitry 50 that determines and / or masks whether the data on the CA<13:0> bits corresponds to a valid incoming command or a "ghost" command in which the incoming data on CA<13:0> looks like a command but is actually an address or other data. Mask circuitry 50 may utilize historical commands to determine whether the data is a valid command or a ghost command.

[0029] In addition, the command interface 14 may be configured to receive a plurality of other command signals. For example, a command / address (CA_ODT) signal on the die terminal may be provided to facilitate proper impedance matching within the memory device 10. A reset command (RESET_n) may be used to reset the command interface 14, a status register, a state machine, etc., for example, during power-on. The command interface 14 may also receive a command / address inversion (CAI) signal, which may be provided to invert the state of the command / address signal CA<13:0> on the command / address bus, for example, depending on the command / address routed for a particular memory device 10. A mirror (MIR) signal may also be provided to facilitate mirroring functionality. Based on the configuration of multiple memory devices in a particular application, the MIR signal may be used to multiplex the signal so that it may be swapped to achieve a particular routing of the signal to the memory device 10. Various signals that facilitate testing of the memory device 10, such as a test enable (TEN) signal, may also be provided. For example, the TEN signal may be used to place the memory device 10 in a test mode for connectivity testing.

[0030] The command interface 14 may also be used to provide an alert signal (ALERT_n) to the system processor or controller for certain errors that may be detected. For example, if a cyclic redundancy check (CRC) error is detected, an alert signal (ALERT_n) may be transmitted from the memory device 10. Other alert signals may also be generated. In addition, as described above, the bus and pins used to transmit the alert signal (ALERT_n) from the memory device 10 may be used as input pins during certain operations, such as a connectivity test mode performed using the TEN signal.

[0031] By transmitting and receiving signals 44 (e.g., data and / or a strobe to capture data) via the IO interface 16, data can be sent to the memory device 10 using the command and clock signals discussed above. More specifically, data can be sent to or retrieved from the memory bank 12 via a data path 46, which includes a plurality of bidirectional data buses. Data IO signals, commonly referred to as DQ signals, are typically transmitted and received in one or more bidirectional data buses. For some memory devices, such as DDR5 SDRAM memory devices, IO signals can be divided into high bytes and low bytes. For example, for a x16 memory device, IO signals can be divided into upper and lower IO signals (e.g., DQ<15:8> and DQ<7:0>) corresponding to, for example, the high and low bytes of the data signals.

[0032] In order to allow higher data rates within the memory device 10, some memory devices, such as DDR memory devices, may utilize a data strobe signal (commonly referred to as DQS). DQS is driven by an external processor or controller that sends data (e.g., for a write command) or by the memory device 10 (e.g., for a read command). For a read command, DQS is actually an additional data output (DQ) signal with a predetermined pattern. For a write command, DQS is used as a clock signal to capture the corresponding input data. Like the clock signal (Clk_t and Clk_c), DQS can be provided as a pair of data strobe signals (DQS_t and DQS_c) with differences to provide differentiated paired signaling during reading and writing. For some memory devices, such as DDR5 SDRAM memory devices, the differentiated paired DQS can be divided into upper and lower data strobe signals (e.g., UDQS_t and UDQS_c; LDQS_t and LDQS_c) corresponding to, for example, the high byte and low byte of data sent to and from the memory device 10.

[0033] An impedance (ZQ) calibration signal may also be provided to the memory device 10 through the IO interface 16. The ZQ calibration signal may be provided to a reference pin and used to tune the output driver and ODT values ​​by adjusting the pull-up and pull-down resistors of the memory device 10 across changes in process, voltage, and temperature (PVT) values. Because PVT characteristics may affect the ZQ resistance value, a ZQ calibration signal may be provided to a ZQ reference pin for adjusting the resistance to calibrate the input impedance to a known value. As will be appreciated, a precision resistor is typically coupled between the ZQ pin on the memory device 10 and GND / VSS external to the memory device 10. This resistor acts as a reference for adjusting the internal ODT and drive strength of the IO pins.

[0034] Additionally, a loopback signal (LOOPBACK) may be provided to the memory device 10 through the IO interface 16. The loopback signal may be used during a test or debug phase to set the memory device 10 to a mode in which a signal is looped back throughout the memory device 10 through the same pin. For example, the loopback signal may be used to set up the memory device 10 to test the data output (DQ) of the memory device 10. The loopback may include both data and strobes, or perhaps only the data pin. This is typically intended for monitoring data captured by the memory device 10 at the IO interface 16.

[0035] As will be appreciated, various other components, such as power supply circuits (for receiving external VDD and VSS signals), mode registers (for defining various modes of programmable operation and configuration), read / write amplifiers (for amplifying signals during read / write operations), temperature sensors (for sensing the temperature of the memory device 10), etc., may also be incorporated into the memory device 10. Therefore, it should be understood that Figure 1 The block diagram is provided only to highlight certain functional features of the memory device 10 to assist in the subsequent detailed description.

[0036] Figure 21 is an example timing diagram 100 of a half-frequency mode of a memory device in 1N mode. The timing diagram 100 includes a chip select signal 102, a system clock (Clk_t) 104, an even clock (ClkE) 106 for driving an even pipeline, and an odd clock (ClkO) 108 for driving an odd pipeline. When a command is issued, the chip select signal 102 may be asserted low (or high in some embodiments). The even clock 106 and the odd clock 108 are derived from alternating pulses of Clk_t 104 to form a clock having half the frequency of Clk_t 104. The chip select signal 102 is asserted in a pulse 110 corresponding to a command (e.g., an activate, read, or write command). Since the memory device 10 is in 1N mode, a received command is sent within a continuous cycle of Clk_t 104. The command may be a dual cycle command in which the chip select signal 102 is asserted within a dual cycle of Clk_t 104. The first cycle of Clk_t 104 corresponds to pulse 112 of even clock 106 in the even pipeline, and the second cycle of Clk_t 104 corresponds to pulse 114 of odd clock 108 in the odd pipeline. The third cycle of Clk_t 104 corresponds to pulse 116 of even clock 106, and the fourth cycle of Clk_t 104 corresponds to pulse 118 of odd clock 108.

[0037] The command may be decoded from some CA bits (e.g., CA<5:0>) in the first cycle. If the command corresponds to a valid dual-cycle command, then the CA bits (e.g., CA<4:0>, CA<13:0>, or CA<13:6>) received in the second cycle of Clk_t 104 will not be decoded. If the CA bits are decoded incorrectly, the decoded command is a ghost command, which is not actually a command but may only appear to be a command. In order to stop the improper decoding of ghost commands, when a command is received in a pipeline (e.g., an even pipeline), a mask signal may be generated in the mask circuit system 50 to prevent the decoding of the ghost command when a dual-cycle command is received. The mask circuit system 50 may use a common pattern of dual-cycle commands to determine whether a command is a dual-cycle command. For example, in some embodiments, all dual-cycle commands may have a low chip select signal 102 and one or more CA bits (e.g., CA<4:0>) that can be used to decode whether the command is a dual-cycle command. <1> ). In 1N mode, the mask circuitry 50 may generate a mask signal on an even clock 106 cycle to block a command on the next odd cycle, or vice versa.

[0038] Figure 3130 is an example timing diagram of half frequency of a memory device in 2N mode for a dual cycle command that utilizes a mask signal to prevent decoding of the CA bit in the second cycle. Since the memory device is in 2N mode, the received command is sent in alternate / non-consecutive cycles of Clk_t 104 that skip at least one cycle corresponding to another pipeline. Therefore, since the command is processed in a single pipeline (e.g., an even pipeline), the chip select signal 102 can be asserted in alternate cycles of Clk_t 104, as illustrated by pulses 132 and 134. The first CA bit (e.g., CA<13:0>) is decoded using the first cycle corresponding to pulse 136 after the falling edge of pulse 132. The mask signal is used to skip the next cycle of the odd clock 108 corresponding to pulse 138. The next CA bit (e.g., CA<13:0>) is captured in the third cycle corresponding to pulse 140 (the second cycle of the even clock 106 after receiving the command). In the 2N mode, the mask circuitry 50 may generate a mask signal on an even clock 106 cycle to block commands on the next even cycle, or may generate a mask signal on an odd clock 108 cycle to block commands on the next odd cycle.

[0039] Figure 4 1 is a block diagram of mask circuitry 50. As illustrated, mask circuitry 50 is divided into an even pipeline 150 and an odd pipeline 152. Mask circuitry 50 is used to mask ghost commands from being decoded in command decoder 32. Even pipeline 150 receives an even chip select signal 154 and an even command address bit 156 (e.g., CA ) at a mask generation circuit 158 ​​in even pipeline 150. <1> As previously described, mask generation circuit 158 ​​uses even chip select signal 154 and even command address bit 156 to determine whether the received command is a double cycle command. If both even chip select signal 154 and even command address bit 156 are asserted, mask generation circuit 158 ​​may output an even mask signal (Stop2cDecE) 160 to prevent a ghost command from being decoded.

[0040] The odd pipeline 152 receives the odd chip select signal 162 and the odd command bit 164 (eg, CA ) at the mask generation circuit 166 in the odd pipeline 152. <1> As previously described, the mask generation circuit 166 uses the odd chip select signal 162 and the odd command bit 164 to determine whether the received command is a double cycle command. If both the odd chip select signal 162 and the odd command bit 164 are asserted, the mask generation circuit 166 may output an odd mask signal (Stop2cDecE) 168 to prevent the ghost command from being decoded.

[0041] Since the memory device 10 can operate in either 1N or 2N mode, the even pipeline 150 utilizes both by receiving the even mask signal 160 and the odd mask signal 168 at the multiplexer circuit 170. The appropriate mask signal to be used is determined based on the mode selection signal 172 indicating whether the memory device 10 is operating in the 1N mode or the 2N mode. For example, in the 1N mode, the even pipeline 150 can be masked (e.g., the odd mask signal 168) to prevent ghost commands in the even pipeline 150 after the odd pipeline 152 received a valid command in the previous cycle. However, in the 2N mode, the even pipeline 150 can be masked (e.g., the even mask signal 160) to prevent ghost commands in the even pipeline 150 after the even pipeline has received a valid command in the previous cycle of the even clock 106. If the mask signal is not generated, the command decoder 32 completes decoding the commands in the even pipeline as command decode even 174 .

[0042] Since the memory device 10 can operate in either 1N or 2N mode, the odd pipeline 152 utilizes both by receiving the odd mask signal 168 and the even mask signal 160 at the multiplexer circuit 176. The appropriate mask signal is used based on the mode selection signal 178 indicating whether the memory device 10 is operating in the 1N mode or the 2N mode. The mode selection signal 172 and the mode selection signal 178 can be the same signal or separate signals. In the 1N mode, the odd pipeline 152 can be masked (e.g., the even mask signal 160) to prevent ghost commands in the odd pipeline 152 after the even pipeline 150 received a valid command in the previous cycle. However, in the 2N mode, the odd pipeline 152 can be masked (e.g., the odd mask signal 168) to prevent ghost commands in the odd pipeline 152 after the even pipeline has received a valid command in the previous cycle of the even clock 106. If the mask signal is not generated, the command decoder 32 completes decoding the commands in the odd pipeline 152 into command decode odd 180 .

[0043] Furthermore, when a ghost command is detected, the ghost command can be prevented from generating a new mask signal. Figure 51 is a timing diagram 190 of an active cancel command (or other dual cycle command) in 1N mode. The timing diagram 190 includes the even chip select signal 154, the odd chip select signal 162, the even mask signal 160, and the odd mask signal 168. The pulses of the chip select signal 102 correspond to dual cycle commands (e.g., active cancel commands). In addition, assuming that one or more CA bits (e.g., CA <1> ) is held at a value (e.g., 0) corresponding to a two-cycle command for the duration of the command. The first cycle 194 (of the even clock) is used to capture the chip select signal into the command decoder 32 and generate a pulse 196 of the even chip select signal 154. Since the one or more CA bits are held at that value and the even chip select signal 154 is asserted, the mask circuitry 50 generates a pulse 198 on the odd mask signal 168 to prevent the ghost command from being decoded in the next clock cycle 200, even though the odd chip select signal 162 is asserted with a pulse 202. In addition, although the odd chip select signal 162 and the one or more CA bits may be asserted, the odd mask signal 168 has a pulse 204 suppressed by checking the single cycle history indicating that the previous cycle was a valid cycle and the current cycle is a ghost command.

[0044] In some cases, a single cycle history may not be sufficient to confirm that the current cycle may correspond to a ghosted command. Figure 6 2 is a timing diagram 210 that uses a dual cycle history to determine whether a cycle corresponds to a valid command or a ghost command in the memory device 10 in 1N mode. The chip select signal 102 is asserted in pulse 212 for the corresponding activation cancellation and read command. In the next pulse 214 of the even clock 106, at least a portion of the bits of the valid command are captured and the even chip select signal 216 is asserted. Since the one or more CA bits are maintained at the value and the even chip select signal 154 is asserted, the mask circuit system 50 generates a pulse 218 on the even mask signal 160 to prevent the ghost command from being decoded in the next clock cycle 220. In addition, although the odd chip select signal 162 and one or more CA bits can be asserted, the odd mask signal 168 has a pulse 224 suppressed by checking the single cycle history indicating that the previous cycle was a valid cycle and the current cycle is a ghost command.

[0045] In the next cycle 226 of the even clock 106, a second valid command (e.g., a read command) is received. Reviewing the one or more CA bits and the chip select signal from the previous cycle of the odd clock 108 may cause the second valid command to appear as a ghost command. In contrast, by examining the even mask signal 160 from two previous cycles (e.g., the previous cycle of the even clock 106), the mask circuitry 50 may confirm that the second valid command is valid, rather than being inappropriately identified as a ghost command. In other words, by looking at the chip select signal 222 from the previous cycle and the even mask signal 160 generated by the earlier two cycles, the mask circuitry 50 may infer whether the current cycle contains a valid command or a ghost command.

[0046] Likewise, Figure 7 2 is a timing diagram 230 that uses a dual cycle history to determine whether a cycle corresponds to a valid command or a ghost command in 1N mode. The chip select signal 102 is asserted in pulse 232 for a consecutive activation cancel command. In the next pulse 234 of the even clock 106, at least a portion of the bits of the valid command are captured and the even chip select signal 236 is asserted. Since the one or more CA bits are maintained at the value and the even chip select signal 154 is asserted, the mask circuit system 50 generates a pulse 238 on the even mask signal 160 to prevent the ghost command from being decoded in the next clock cycle 240, even though the odd chip select signal 162 is asserted with pulse 242. In addition, although the odd chip select signal 162 and one or more CA bits may be asserted, the odd mask signal 168 has a pulse 244 suppressed by checking the dual cycle history indicating that the previous cycle was a valid cycle and the current cycle is a ghost command.

[0047] In the next cycle 246 of the even clock 106, a second valid deactivate command is received. Reviewing the one or more CA bits and chip select signals of the previous cycle of the odd clock 108 may cause the second valid command to appear as a ghost command. In contrast, by checking the even mask signal 160 from two previous cycles (e.g., the previous cycle of the even clock 106), the mask circuitry 50 may confirm that the second valid command is valid, rather than being inappropriately identified as a ghost command.

[0048] In 2N mode, the mask generation differs in that a pipeline (eg, even pipeline 150) generates the mask for the next cycle in the pipeline. The other pipeline (eg, odd pipeline 152) is skipped between cycles. Figure 82 is a timing diagram 250 of consecutive commands received in 2N mode. When the chip select signal 102 is asserted via pulse 252, a valid dual cycle command is received at loop 1 254 in the even pipeline 150. Due to the 2N mode of the memory device 10, loop 2 256 in the odd pipeline 152 is skipped. Loop 3 258 may contain a ghost command. Therefore, the mask generated from loop 1 254 can be used to prevent the decoding of the ghost command in loop 2 256. Since the first valid command has been completed, the chip select signal 102 returns to being unasserted at point 259. After point 259, no valid command is received at loop 4 260. Instead, the next valid dual cycle command is received with loop 5 262, resulting in loop 6 264 being skipped and the data of loop 7 266 being blocked from decoding due to the mask signal occurring from the next valid dual cycle command.

[0049] Fig. 9 3 is a timing diagram 300 for the memory device 10 to receive multiple commands in 2N mode. The chip select signal 102 is asserted in pulse 302 for activating the cancel command. In the next pulse 304 of the even clock 106, at least a portion of the bits of the valid command are captured and the even chip select signal 154 is asserted. Since one or more CA bits are maintained at the value and the even chip select signal 154 is asserted, the mask circuit system 50 generates a pulse 308 on the even mask signal 160 to prevent the ghost command from being decoded in the next even clock cycle 312, even if the even chip select signal 154 remains asserted. Due to the 2N mode, the middle cycle 310 of the odd clock 108 is skipped. After the ghost command has been suppressed, the even mask signal 160 is reset using deassertion 314. Deassertion 314 is used to clear the even mask signal 160 in preparation for the next valid signal. The chip select signal 102 may transition high during this reset as part of a deselect command 316 followed by a pulse 318 of the chip select signal 102 corresponding to a read command. Pulse 318 is received at pulse 320 of the even clock 106 and used to maintain pulse 306. The even mask signal 160 is re-asserted via pulse 322 to prevent decoding of a ghost command in cycle 2 326 of the read command. The next cycle 324 of the odd clock 108 is skipped due to the 2N mode. After generating the mask signal to suppress the ghost command, the even mask signal 160 may be reset for the next valid command.

[0050] Fig.10 yes Figure 41 and 166. As illustrated, the mask generation circuit 158 ​​of the even pipeline 150 includes a 1N mode history circuit system 350 and a 2N mode history circuit system 352. The mask generation circuit 158 ​​receives a feedback value 353, a delayed odd chip select signal 354, one or more delayed odd CA bits 356, and an inverted even chip select signal 358 from the 1N mode history circuit system 350 at the selection circuit system 360. The output of the selection circuit system 360 is transmitted to a "NOR" gate 362. The "NOR" gate 362 also receives one or more even command address bits 156. The "NOR" gate 362 also receives a feedback value 364 from the 2N mode history circuit system 352. The output 366 (StopGhostCmdE) of the "NOR" gate 362 is transmitted to the input of the flip-flop 368. The flip-flop 368 also receives a delayed or undelayed even clock 370 and a delayed or undelayed inverted even clock 372. The flip-flop 368 may also receive a reset signal 374 when the memory device 10 is restarted.

[0051] The output 376 of the flip-flop 368 is fed back to the 1N mode history circuit system 350 and the 2N mode history circuit system 352. The 2N mode history circuit system 352 also receives a mode2N selection signal 378 at a NAND gate 380. The mode2N selection signal 378 is used to indicate whether the memory device 10 is in the 1N mode or the 2N mode. The output of the NAND gate 380 is inverted in an inverter 382 to generate the feedback value 364.

[0052] The output 376 is also fed back to the NOR gate 384 of the 1N mode history circuit system 350 along with the mode2N selection signal 378. The output of the NOR gate 384 is inverted via the inverter 386 to generate the feedback value 353. The output 376 may also be inverted and / or amplified in the inverter 388 to generate the even mask signal 160.

[0053] The mask generation circuit 158 ​​of the even pipeline 150 includes a 1N mode history circuit system 350 and a 2N mode history circuit system 352. The mask generation circuit 158 ​​receives a feedback value 353, a delayed odd chip select signal 354, one or more delayed odd CA bits 356, and an inverted even chip select signal 358 from the 1N mode history circuit system 350 at a selection circuit system 360. The output of the selection circuit system 360 is transmitted to a NOR gate 362. The NOR gate 362 also receives one or more even command address bits 156. The NOR gate 362 also receives a feedback value 364 from the 2N mode history circuit system 352. The output 366 (StopGhostCmdE) of the NOR gate 362 is transmitted to the input of a flip-flop 368. The flip-flop 368 also receives a delayed or undelayed even clock 370 and a delayed or undelayed inverted even clock 372. The flip-flop 368 may also receive a reset signal 374 when the memory device 10 is restarted.

[0054] The output 376 of the flip-flop 368 is fed back to the 1N mode history circuit system 350 and the 2N mode history circuit system 352. The 2N mode history circuit system 352 also receives a mode2N selection signal 378 at a NAND gate 380. The mode2N selection signal 378 is used to indicate whether the memory device 10 is in the 1N mode or the 2N mode. The output of the NAND gate 380 is inverted in an inverter 382 to generate the feedback value 364.

[0055] The output 376 is also fed back to the NOR gate 384 of the 1N mode history circuit system 350 along with the mode2N selection signal 378. The output of the NOR gate 384 is inverted via the inverter 386 to generate the feedback value 353. The output 376 may also be inverted and / or amplified in the inverter 388 to generate the even mask signal 160.

[0056] The mask generation circuit 166 of the odd pipeline 152 includes a 1N mode history circuit system 390 and a 2N mode history circuit system 392. The mask generation circuit 166 receives a feedback value 393, a delayed even chip select signal 394, one or more delayed even CA bits 396, and an inverted odd chip select signal 398 from the 1N mode history circuit system 390 at the selection circuit system 400. The output of the selection circuit system 400 is transmitted to a "NOR" gate 402. The "NOR" gate 402 also receives one or more even command address bits 156. The "NOR" gate 402 also receives a feedback value 404 from the 2N mode history circuit system 392. The output 406 (StopGhostCmdO) of the "NOR" gate 402 is transmitted to the input of a flip-flop 408. The flip-flop 408 also receives a delayed or undelayed odd clock 410 and a delayed or undelayed inverted odd clock 412. The flip-flop 408 may also receive a reset signal 414 when the memory device 10 is restarted.

[0057] The output 416 of the flip-flop 408 is fed back to the 1N mode history circuit system 390 and the 2N mode history circuit system 392. The 2N mode history circuit system 392 also receives the mode2N selection signal 378 at the NAND gate 420. The mode2N selection signal 378 is used to indicate whether the memory device 10 is in the 1N mode or the 2N mode. The output of the NAND gate 420 is inverted in the inverter 422 to generate the feedback value 404.

[0058] The output 416 is also fed back to the NOR gate 424 of the 1N mode history circuit system 390 along with the mode2N selection signal 378. The output of the NOR gate 424 is inverted via an inverter 426 to generate the feedback value 393. The output 416 may also be inverted and / or amplified in the inverter 428 to generate the odd mask signal 168.

[0059] Fig.11 yes Figure 4The multiplexer circuit 170 is a circuit diagram of the multiplexer circuit 170. The multiplexer circuit 170 receives the mode2N selection signal 378 and generates an inverted mode2N selection signal 452 using an inverter 454. The multiplexer circuit 170 also receives a signal indicating certain bits (e.g., CA <0> Bit 460, CA <1> Bit 462 and / or CA <3> The PDNF signal 456 is received at the selection circuit system 458, and the CA <0> Bit 460, CA <1> Bit 462 and CA <3> Bit 464. CA <1> Bit 462, CA <4> Bit 468 and chip select even decode signal 470 are transmitted to NOR gate 466. NOR gate 472 receives disable decode bits 474, 476, and 478 to disable decoding based on disable decode bits 474, 476, and 478. The outputs from select circuitry 458, NOR gate 466, and NOR gate 472 are transmitted to NAND gate 480.

[0060] The 2:1 multiplexer 482 receives the mask signals 160 and 168 and selects between the mask signals 160 and 168 based on whether mode N1 or mode N2 is selected as indicated by the mode2N selection signal 378 and / or the inverted mode2N selection signal 452. At least one of the mask signals (e.g., the even mask signal 160) is delayed in the delay 484. Since the multiplexer circuit 170 is disposed in the even pipeline, if the memory device 10 is in the N1 mode, the odd mask signal 168 of the odd pipeline is selected. Conversely, if the memory device 10 is in the N2 mode, the even mask signal 160 of the even pipeline is selected. The selected mask signal is output from the 2:1 multiplexer 482 to the inverter 486. The output of the inverter 486 is transmitted to the NOR gate 488 together with the output of the NAND gate 480. The output of NOR gate 488 is command decode even number 174 .

[0061] Fig.12 yes Figure 4The multiplexer circuit 176 is a circuit diagram of the multiplexer circuit 176. The multiplexer circuit 176 receives the mode2N selection signal 378 and generates the inverted mode2N selection signal 452 using the inverter 454. In some embodiments, the multiplexer circuit 176 may not be configured to locally generate the inverted mode2N selection signal 452, but rather receive the inverted mode2N selection signal 452 from outside the multiplexer circuit 176. The multiplexer circuit 176 also receives a signal indicating certain bits (e.g., CA <0> Bit 460, CA <1> Bit 462 and / or CA <3> The PDNF signal 456 is received at the selection circuit system 502, and the CA <0> Bit 460, CA <1> Bit 462 and CA <3> Bit 464. CA <1> Bit 462, CA <4> Bit 468 and chip select even decode signal 470 are transmitted to NOR gate 504. NOR gate 506 receives disable decode bits 474, 476, and 478 to disable decoding based on disable decode bits 474, 476, and 478. The outputs from select circuitry 502, NOR gate 504, and NOR gate 506 are transmitted to NAND gate 508.

[0062] The 2:1 multiplexer 510 receives the mask signals 160 and 168 and selects between the mask signals 160 and 168 based on whether mode N1 or mode N2 is selected as indicated by the mode2N selection signal 378 and / or the inverted mode2N selection signal 452. At least one of the mask signals (e.g., the odd mask signal 168) is delayed in the delay 512. Since the multiplexer circuit 176 is disposed in the odd pipeline, if the memory device 10 is in the N1 mode, the even mask signal 160 of the even pipeline is selected. Conversely, if the memory device 10 is in the N2 mode, the odd mask signal 168 of the odd pipeline is selected. The selected mask signal is output from the 2:1 multiplexer 510 to the inverter 513. The output of the inverter 513 is transmitted to the NOR gate 514 together with the output of the NAND gate 508. The output of NOR gate 514 is command decode odd number 180 .

[0063] Although the present disclosure is susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, it should be understood that the present disclosure is not intended to be limited to the specific forms disclosed. For example, the logic polarity may be reversed. Additionally or alternatively, equivalent circuits may be used. For example, a NAND gate and an inverter may be replaced by an AND gate. Alternatively, the present disclosure is intended to cover all modifications, equivalents, and alternative forms that fall within the spirit and scope of the present disclosure as defined by the appended claims.

[0064] The techniques presented and claimed herein are cited and applied to specific examples of material objects and actual properties that clearly improve the art and are therefore not abstract, intangible, or purely theoretical. In addition, if any claim attached at the end of this specification contains one or more elements designated as "means for [performing] [the function] ..." or "steps for [performing] [the function] ...", it is intended that such elements will be interpreted in accordance with the provisions of 35 U.S.C. § 112(f). However, for any claim containing elements designated in any other manner, it is intended that such elements should not be interpreted in accordance with the provisions of 35 U.S.C. § 112(f).

Claims

1. A memory device, include: a command interface configured to receive a dual cycle command from a host device via a plurality of command address bits; and a command decoder configured to decode a first portion of the plurality of command address bits in a first cycle of the two-cycle command and comprising mask circuitry comprising: mask generation circuitry configured to generate a mask signal; and Multiplexer circuitry is configured to apply the mask signal to prevent the command decoder from decoding a second portion of the plurality of command address bits in a second cycle of the two-cycle command.

2. The memory device of claim 1, wherein the command decoder comprises two pipelines, each of the two pipelines operating at a frequency corresponding to half a frequency of a system clock of the first and second cycles.

3. The memory device of claim 2, wherein a first pipeline of the two pipelines includes the mask generation circuitry and the multiplexer circuitry, and the mask signal is configured to prevent a second pipeline of the two pipelines from decoding the second portion.

4. The memory device of claim 3, wherein the two pipelines operate in a 2N mode, wherein both the first and second cycles of the two-cycle command are pipelined in the first pipeline in non-consecutive cycles of the system clock.

5. The memory device of claim 3, wherein a second pipeline of the two pipelines include: additional mask generation circuitry configured to generate additional mask signals; and Additional multiplexer circuitry is configured to apply the additional mask signal to prevent the second pipeline from decoding a plurality of command address bits in a second cycle of an additional two-cycle command.

6. The memory device of claim 5, wherein the multiplexer circuitry is configured to receive the additional mask signal and the mask signal and select the mask signal for application to the first pipeline.

7. The memory device of claim 3, wherein the two pipelines operate in 1N mode, wherein the first cycle of the two-cycle command is pipelined in the first pipeline and the second cycle of the two-cycle command is pipelined in the second pipeline in consecutive cycles of the system clock.

8. The memory device of claim 3, wherein the second pipeline of the two pipelines include: additional mask generation circuitry configured to generate additional mask signals; and Additional multiplexer circuitry is configured to apply the additional mask signal to prevent the first pipeline from decoding a plurality of command address bits in a second cycle of an additional two-cycle command.

9. The memory device of claim 8, wherein the multiplexer circuitry is configured to receive the additional mask signal and the mask signal and select the additional mask signal for application to the first pipeline.

10. The memory device of claim 1, wherein the mask generation circuitry is configured to generate the mask signal based at least in part on one of the command address bits in a previous cycle of a system clock corresponding to the first and second cycles prior to the first cycle.

11. The memory device of claim 1 , wherein the mask generation circuitry is configured to generate the mask signal based at least in part on one of the command address bits in a previous cycle of a system clock two cycles prior to the first cycle, wherein the system clock corresponds to the first and second cycles.

12. The memory device of claim 1, wherein the mask generation circuitry is configured to generate the mask signal based at least in part on a chip select signal.

13. A memory device, include: a command interface configured to receive a dual cycle command from a host device via a plurality of command address bits; and a command decoder configured to decode a first portion of the plurality of command address bits in a first cycle of the two-cycle command, comprising: The first assembly line includes: first mask generation circuitry configured to generate a first mask signal; a first multiplexer circuit system configured to apply the first mask signal to prevent the command decoder from decoding a second portion of the plurality of command address bits in a second cycle of the two-cycle command when the first cycle is received in the first pipeline, wherein the first pipeline operates using an even clock oscillating at half the frequency of a system clock containing the first and second cycles; and The second pipeline includes: second mask generation circuitry configured to generate a second mask signal; and a second multiplexer circuit system configured to apply the second mask signal to prevent the command decoder from decoding the second portion of the plurality of command address bits in a second cycle of the two-cycle command when the first cycle is received in the second pipeline, wherein the second pipeline operates using an odd clock oscillating at half the frequency of the system clock.

14. The memory device of claim 13, wherein the first multiplexer circuitry is configured to: receiving the first mask signal and the second mask signal; and The first mask signal is selected for the first pipeline when the first and second pipelines operate in a 2N mode, wherein the first and second cycles of the dual-cycle command are both pipelined in the first pipeline in non-consecutive cycles of the system clock, or both are pipelined in the second pipeline in non-consecutive cycles of the system clock.

15. The memory device of claim 14, wherein the second multiplexer circuitry is configured to: receiving the first mask signal and the second mask signal; and When the first and second pipelines operate in the 2N mode, the second mask signal is selected for the second pipeline.

16. The memory device of claim 13, wherein the first multiplexer circuitry is configured to: receiving the first mask signal and the second mask signal; and The second mask signal is selected for the first pipeline when the first and second pipelines operate in 1N mode, wherein one of the first or second cycles of the two-cycle command is pipelined in the first pipeline and the other is pipelined in the second pipeline in consecutive cycles of the system clock.

17. The memory device of claim 16, wherein the first multiplexer circuitry is configured to: receiving the first mask signal and the second mask signal; and When the first and second pipelines operate in the 1N mode, the first mask signal is selected for the second pipeline.

18. A method, wherein include: receiving a first portion of a plurality of command address bits at a command interface during a first cycle of a system clock; determining, using mask generation circuitry of the memory device, whether the command corresponding to the plurality of command address bits is a valid two-cycle command or a second cycle of a two-cycle command; and Based on the determination that the command is a valid two-cycle command, asserting a mask signal in the mask generation circuitry, wherein assertion of the mask signal is configured to prevent decoding of a second portion of the plurality of command address bits received during a second cycle of the system clock corresponding to the two-cycle command.

19. The method of claim 18, comprising selecting between the mask signal and an additional mask signal in a multiplexer circuit system, wherein the mask generation circuit system and the multiplexer circuit system are in a first pipeline of two pipelines in the memory device, and the multiplexer circuit system receives the mask signal from the first pipeline and the additional mask signal from a second pipeline.

20. The method of claim 19, wherein selecting between the mask signal and the additional mask signal comprises selecting the mask signal when the first and second pipelines operate in a 2N mode, wherein the first and second cycles of the dual-cycle command are both pipelined in the first pipeline in non-consecutive cycles of the system clock, or are both pipelined in the second pipeline in non-consecutive cycles of the system clock.

21. The method of claim 19, wherein selecting between the mask signal and the additional mask signal comprises selecting the mask signal when the first and second pipelines operate in 1N mode, wherein one of the first or second cycles of the dual-cycle command is pipelined in the first pipeline and the other is pipelined in the second pipeline in non-consecutive cycles of the system clock.

22. The method of claim 19, wherein when the command interface is configured to operate in a half-frequency design having a first pipeline and a second pipeline, determining whether the command corresponding to the plurality of command address bits is a valid two-cycle command or a second cycle of a two-cycle command comprises checking a two-cycle history.

23. The method of claim 22, wherein the first and second pipelines are in 1N mode, and checking the double cycle history of a command to be received in a first command comprises checking a single cycle history of the second pipeline and a double cycle history of the first pipeline.

24. The method of claim 22, wherein the first and second pipelines are in 2N mode, and checking the two-cycle history of a command to be received in a first command comprises checking a two-cycle history of the first pipeline.

25. A memory device, include: a command interface configured to receive a dual cycle command from a host device via a plurality of command address bits; and a command decoder configured to decode a first portion of the plurality of command address bits in a first cycle of the two-cycle command and comprising: generating circuitry configured to generate an indication based on decoding bits in the first cycle; and Blocking circuitry is configured to block the command decoder from decoding a second portion of the plurality of command address bits in a second cycle of the two-cycle command based at least in part on the indication.

26. The memory device of claim 25, wherein the command decoder comprises two pipelines, each of the two pipelines operating at a frequency corresponding to half the frequency of a system clock of the first and second cycles.

27. The memory device of claim 26, wherein a first pipeline of the two pipelines includes the generating circuitry and the blocking circuitry, and the indication is configured to prevent a second pipeline of the two pipelines from decoding the second portion.

28. The memory device of claim 27, wherein the two pipelines operate in a 2N mode, wherein both the first and second cycles of the two-cycle command are pipelined in the first pipeline in non-consecutive cycles of the system clock.

29. The memory device of claim 27, wherein the second pipeline of the two pipelines include: additional generating circuitry configured to generate additional indications; and Additional blocking circuitry is configured to block the second pipeline from decoding a plurality of command address bits in a second cycle of an additional two-cycle command based at least in part on the additional indication.

30. The memory device of claim 29, wherein the blocking circuitry is configured to receive the additional indication and the indication and select the indication for controlling blocking of the first pipeline.

31. The memory device of claim 27, wherein the two pipelines operate in 1N mode, wherein the first cycle of the two-cycle command is pipelined in the first pipeline and the second cycle of the two-cycle command is pipelined in the second pipeline in consecutive cycles of the system clock.

32. The memory device of claim 27, wherein the second pipeline of the two pipelines include: additional generating circuitry configured to generate additional indications; and Additional blocking circuitry is configured to block the first pipeline from decoding an additional plurality of command address bits in a second cycle of an additional two-cycle command based at least in part on the additional indication.

33. The memory device of claim 32, wherein the blocking circuitry is configured to receive the additional indication and the indication and select the additional indication for controlling blocking of the first pipeline.

34. The memory device of claim 25, wherein the generating circuitry is configured to generate the indication based at least in part on one of the plurality of command address bits in a previous cycle of a system clock corresponding to the first and second cycles prior to the first cycle.

35. The memory device of claim 25, wherein the generating circuitry is configured to generate the indication based at least in part on one of the plurality of command address bits in a previous cycle of a system clock two cycles prior to the first cycle, wherein the system clock corresponds to the first and second cycles.

36. The memory device of claim 25, wherein the generating circuitry is configured to generate the indication based at least in part on a chip select signal.

37. A memory device, include: a command interface configured to receive a dual cycle command from a host device via a plurality of command address bits; and a command decoder configured to decode a first portion of the plurality of command address bits in a first cycle of the two-cycle command, comprising: a first pipeline including a first blocking circuitry configured to block the command decoder from decoding a second portion of the plurality of command address bits in a second cycle of the two-cycle command when the first cycle is received in the first pipeline, wherein the first pipeline operates using an even clock oscillating at half the frequency of a system clock containing the first and second cycles; and a second pipeline comprising a second blocking circuit system configured to block the command decoder from decoding the second portion of the plurality of command address bits in the second cycle of the two-cycle command when the first cycle is received in the second pipeline, wherein the second pipeline operates using an odd clock oscillating at half the frequency of the system clock.

38. A memory device according to claim 37, wherein the first blocking circuit system is configured to block the first pipeline from decoding the second portion of the multiple command address bits when the first cycle is received in the first pipeline when the first and second pipelines operate in 2N mode, wherein the first and second cycles of the dual-cycle command are both pipelined in the first pipeline in non-consecutive cycles of the system clock, or both are pipelined in the second pipeline in non-consecutive cycles of the system clock, and the second blocking circuit system is configured to block the second pipeline from decoding the second portion of the multiple command address bits when the first cycle is received in the second pipeline when the first and second pipelines operate in the 2N mode.

39. A memory device according to claim 37, wherein the first blocking circuit system is configured to block the first pipeline from decoding the second portion of the plurality of command address bits when the first cycle is received in the second pipeline when the first and second pipelines operate in 1N mode, wherein one of the first and second cycles of the dual-cycle command is pipelined in the first pipeline and the other is pipelined in the second pipeline in a continuous cycle of the system clock, and the second blocking circuit system is configured to block the second pipeline from decoding the second portion of the plurality of command address bits when the first cycle is received in the first pipeline and when the first and second pipelines operate in the 1N mode.

40. A method wherein include: receiving a first portion of a plurality of command address bits at a command interface of a memory device in a first cycle of a system clock; determining, using the memory device, whether a command corresponding to the plurality of command address bits is a valid two-cycle command or a second cycle of a two-cycle command; and Based on the determination that the command is a valid two-cycle command, decoding of a second portion of the plurality of command address bits received during a second cycle of the system clock corresponding to the two-cycle command is blocked.

41. The method of claim 40, operating the memory device using a half-frequency design of a first pipeline and a second pipeline, wherein determining whether the command corresponding to the plurality of command address bits is a valid two-cycle command or a second cycle of a two-cycle command comprises checking a two-cycle history.

42. The method of claim 41, wherein the first and second pipelines are in 1N mode and checking the two-cycle history of a command to be received comprises checking a single-cycle history of the second pipeline and a two-cycle history of the first pipeline.

43. The method of claim 41, wherein the first and second pipelines are in 2N mode and checking the two-cycle history of a command to be received comprises checking a two-cycle history of the first pipeline.

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