Semiconductor structure and method of manufacturing the same

Abstract

The application provides a semiconductor structure and a preparation method thereof, which comprises the following steps: forming a structure layer, which comprises a first region and a second region; forming channel through holes in the structure layer, the density of the channel through holes in the first region is greater than that in the second region; forming a gate gap in the structure layer, which comprises a first groove, a second groove and a third groove; the first groove is located in the first region, the third groove is located in the second region, the second groove is located at the junction of the first region and the second region, and the depth of the second groove is less than that of the first groove and the third groove. In the semiconductor structure, the depth of the second groove of the gate gap at the junction of the first region and the second region with different channel through hole densities is less than that of the first groove and the third groove in the first region and the second region, which can avoid the extension of the gate gap to the channel through hole, thereby avoiding the leakage after filling the gate gap.

Description

[0001] This application is a divisional application of the Chinese Patent Application No. 202010036998.6, filed on January 14, 2020, and entitled "Semiconductor Structure and Preparation Method Thereof". TECHNICAL FIELD

[0002] The present application belongs to the technical field of integrated circuit design and manufacturing, and particularly relates to a semiconductor structure and a preparation method thereof. BACKGROUND

[0003] In the prior art, with the development of technology, the number of sacrificial layers and inter-gate dielectric layers in the stack structure in 3D NAND (three-dimensional memory) is increasing. For three-dimensional memory including the stack structure with a large number of layers, since the density of channel through holes formed in the core area and the step area of the stack structure is different (for example, the core area is arranged in 9 rows of channel through holes, and the density of the channel through holes is large, while the step area is arranged in 3 rows of channel through holes, and the density of the channel through holes is small), this will cause a local stress difference at the junction of the core area and the step area (i.e., the junction of the two areas with different densities of trench through holes). The sacrificial layer in the stack structure is generally a silicon nitride layer, and the inter-gate dielectric layer is generally a silicon oxide layer. The bond energy of Si-N bond in the silicon nitride layer is lower than that of Si-O bond. The Si-N bond in the silicon nitride layer at the junction of the core area and the step area is stretched longer. The Si-N bond with longer bond length is more easily broken by positive ions generated and accelerated on the electrode of the etching machine when forming the inter-gate gap by using a dry etching process, thereby causing damage at the junction of the core area and the step area and forming a protrusion of the inter-gate gap in the direction of the channel through hole (i.e., the inter-gate gap at the junction of the core area and the step area extends in the direction of the channel through hole). With the increase of the depth of the inter-gate gap, the damage at the junction of the core area and the step area is more obvious, and even the inter-gate gap can extend into the channel through hole. The channel through hole is formed with a functional sidewall and a channel layer. If the inter-gate gap extends into the channel through hole, it is easy to cause a leakage problem after forming a common source line in the inter-gate gap. SUMMARY

[0004] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a semiconductor structure and a preparation method thereof, which can solve the above-mentioned problems in the prior art.

[0005] To achieve the above-mentioned purposes and other related purposes, the present application provides a preparation method of a semiconductor structure, which comprises the following steps:

[0006] forming a structure layer, the structure layer comprising a first region and a second region; forming a channel via in the structure layer, the channel via being located in the first region and the second region, and a density of the channel via in the first region being greater than a density of the channel via in the second region; and

[0007] forming a gate gap in the structure layer, the gate gap comprising a first trench, a second trench and a third trench; wherein the first trench is located in the first region, the third trench is located in the second region, the second trench is located at a boundary between the first region and the second region, one end of the second trench is connected with the first trench, and the other end of the second trench is connected with the third trench, and a depth of the second trench is less than depths of the first trench and the third trench.

[0008] In the semiconductor structure formed in the above embodiment, the depth of the second trench of the gate gap located at the boundary between the first region and the second region where the density of the channel via is different is less than the depths of the first trench and the third trench located in the first region and the second region, and there is no trench with a greater depth at the boundary between the first region and the second region, which can avoid the extension of the gate gap to the channel via due to the stress difference at the boundary between the first region and the second region, thereby avoiding the leakage after filling the gate gap.

[0009] Optionally, forming the structure layer comprises the following steps:

[0010] forming a stack structure comprising sacrificial layers and gate dielectric layers alternately stacked in sequence, the stack structure comprising a core region and a step region located at an edge of the stack structure, wherein the core region is the first region, and the step region is the second region;

[0011] forming the channel via in the stack structure, the channel via penetrating through the stack structure along a thickness direction; and

[0012] forming a covering dielectric layer on an upper surface of the stack structure.

[0013] Optionally, before forming the covering dielectric layer on the upper surface of the stack structure, the method further comprises the following steps:

[0014] forming a functional sidewall in the channel via; and

[0015] forming a channel layer on a surface of the functional sidewall.

[0016] Optionally, the sacrificial layers comprise silicon nitride layers, and the gate dielectric layers comprise silicon oxide layers.

[0017] Optionally, forming the gate gap in the stack structure comprises the following steps:

[0018] forming the first trench in the first region and forming the third trench in the second region; the first trench and the third trench both penetrate the cover dielectric layer and the stack structure along the thickness direction; and

[0019] forming a second trench in the structure layer, the second trench penetrating the cover dielectric layer along the thickness direction to expose the stack structure.

[0020] Optionally, after forming the gate gap, the method further comprises the step of forming a common source line in the gate gap.

[0021] Optionally, before forming the common source line in the gate gap, the method further comprises the step of forming an insulating isolation layer on the sidewall of the gate gap.

[0022] Optionally, before forming the insulating isolation layer on the sidewall of the gate gap, the method further comprises the following steps:

[0023] removing the sacrificial layer based on the gate gap to form a sacrificial gap; and

[0024] forming a gate layer in the sacrificial gap.

[0025] Optionally, before forming the second trench in the structure layer, the method further comprises the following steps:

[0026] removing the sacrificial layer based on the first trench and the third trench to form a sacrificial gap;

[0027] forming a gate layer in the sacrificial gap; and

[0028] forming a first conductive layer in the first trench and the third trench.

[0029] Optionally, after forming the second trench, the method further comprises the step of forming a second conductive layer in the second trench, the second conductive layer being connected with the first conductive layer located in the first trench and the third trench to form a common source line.

[0030] Optionally, before forming the first conductive layer in the first trench and the third trench, the method comprises the step of forming a first insulating isolation layer on the sidewall of the first trench and the sidewall of the third trench; and before forming the second conductive layer in the second trench, the method further comprises the step of forming a second insulating isolation layer on the sidewall of the second trench.

[0031] The present application also provides a semiconductor structure, which comprises:

[0032] a structure layer, the structure layer comprising a first region and a second region;

[0033] channel vias, located in the first region and the second region, and the density of the channel vias in the first region is greater than the density of the channel vias in the second region; and

[0034] a gate gap, located in the structure layer; the gate gap comprises a first trench, a second trench and a third trench, the first trench is located in the first region, the third trench is located in the second region, the second trench is located at the junction of the first region and the second region, one end of the second trench is connected with the first trench, the other end of the second trench is connected with the third trench, and the depth of the second trench is less than the depth of the first trench and the depth of the third trench.

[0035] In the semiconductor structure in the above embodiment, the depth of the second trench of the gate gap at the junction of the first region and the second region where the density of the channel vias is different is less than the depth of the first trench and the depth of the third trench in the first region and the second region, and there is no trench with a greater depth at the junction of the first region and the second region, which can avoid the extension of the gate gap to the channel via due to the stress difference at the junction of the first region and the second region, thereby avoiding the leakage after filling the gate gap.

[0036] Optionally, the semiconductor structure further comprises:

[0037] a functional sidewall, located in the channel via; and

[0038] a channel layer, located on the surface of the functional sidewall.

[0039] Optionally, the semiconductor structure further comprises a common source line, the common source line being located in the gate gap.

[0040] Optionally, the semiconductor structure further comprises an insulating isolation layer, the insulating isolation layer being located on the sidewall of the gate gap and between the common source line and the structure layer.

[0041] Optionally, the structure layer comprises:

[0042] a stack structure, the stack structure comprising sacrificial layers and gate dielectric layers which are alternately and sequentially stacked, the stack structure comprising a core region and a step region located at the edge of the stack structure, wherein the core region is the first region, and the step region is the second region; the channel via is located in the stack structure and penetrates the stack structure along the thickness direction; and

[0043] a covering dielectric layer, located on the upper surface of the stack structure.

[0044] The first trench and the third trench both penetrate the cover dielectric layer and the stack structure along the thickness direction; and the second trench penetrates the cover dielectric layer along the thickness direction to expose the stack structure.

[0045] Optionally, the sacrificial layer comprises a silicon nitride layer, and the inter-gate dielectric layer comprises a silicon oxide layer.

[0046] Optionally, the structure layer comprises:

[0047] a stack structure comprising gate layers and inter-gate dielectric layers alternately stacked in sequence, the stack structure comprising a core region and a step region located at an edge of the stack structure, wherein the core region is the first region, and the step region is the second region; the channel via is located in the stack structure and penetrates the stack structure along the thickness direction; and

[0048] a cover dielectric layer located on an upper surface of the stack structure;

[0049] The first trench and the third trench both penetrate the cover dielectric layer and the stack structure along the thickness direction; and the second trench penetrates the cover dielectric layer along the thickness direction to expose the stack structure. BRIEF DESCRIPTION OF DRAWINGS

[0050] Figure 1 A flow chart showing a preparation method of a semiconductor structure provided in an embodiment of the present application.

[0051] Figure 2 A cross-sectional structure schematic diagram of a structure obtained after forming a stack structure in a structure layer in the preparation method of a semiconductor structure provided in an embodiment of the present application.

[0052] Figure 3 A top view structure schematic diagram of a structure obtained after forming a channel via in a stack structure in the preparation method of a semiconductor structure provided in an embodiment of the present application.

[0053] Figure 4 A cross-sectional structure schematic diagram along the AA direction in FIG. Figure 3 .

[0054] Figure 5 A top view structure schematic diagram of a structure obtained after forming a functional sidewall and a channel layer in the preparation method of a semiconductor structure provided in an embodiment of the present application.

[0055] Figure 6 A cross-sectional structure schematic diagram along the AA direction in FIG. Figure 5 .

[0056] Figure 7The diagram shown is a cross-sectional view of the structure obtained after forming a covering dielectric layer in the semiconductor structure fabrication method provided in Embodiment 1 of the present invention.

[0057] Figure 8 The diagram shown is a top view of the structure obtained after forming the first trench and the third trench in a semiconductor structure fabrication method provided in an embodiment of the present invention.

[0058] Figure 9 The diagram shown is a top view of the structure obtained after forming a second trench in a semiconductor structure fabrication method provided in an embodiment of the present invention.

[0059] Figure 10 Displayed as along Figure 9 A schematic diagram of the cross-sectional structure along the AA direction.

[0060] Figure 11 Displayed as along Figure 9 Schematic diagram of the cross-sectional structure in the BB direction.

[0061] Figure 12 The diagram shown is a top view of the structure obtained after forming a common source line in a semiconductor structure fabrication method provided in an embodiment of the present invention; wherein... Figure 12 This is also a top view schematic diagram of a semiconductor structure provided in Embodiment 2 of the present invention.

[0062] Figure 13 Displayed as along Figure 12 A schematic diagram of the cross-sectional structure along the AA direction.

[0063] Figure 14 Displayed as along Figure 12 Schematic diagram of the cross-sectional structure in the BB direction.

[0064] Figure 15 Displayed as along Figure 12 A schematic diagram of the cross-sectional structure in the CC direction.

[0065] Figure 16 The diagram shown is a cross-sectional view of the structure obtained after removing the sacrificial layer to form a sacrificial gap in the semiconductor structure fabrication method provided in Embodiment 1 of the present invention.

[0066] Figure 17 The diagram shown is a cross-sectional view of the structure obtained after forming the gate layer in the semiconductor structure fabrication method provided in Embodiment 1 of the present invention.

[0067] Figure 18 The diagram shown is a top view of the structure obtained after forming an insulating isolation layer and a common source line in a semiconductor structure fabrication method provided in an embodiment of the present invention; wherein... Figure 18This is also a top view schematic diagram of a semiconductor structure provided in Embodiment 2 of the present invention.

[0068] Figure 19 Displayed as along Figure 18 A schematic diagram of the cross-sectional structure along the AA direction.

[0069] Figure 20 Displayed as along Figure 18 Schematic diagram of the cross-sectional structure in the BB direction.

[0070] Component designation explanation

[0071] 10 and 17 structural layers

[0072] 101, 102 Stacked Structure

[0073] 1011 Sacrificial Layer

[0074] 1012 Inter-gate dielectric layer

[0075] 1013 Sacrifice Interval

[0076] 1021 gate layer

[0077] 103 Covering dielectric layer

[0078] 104 First District

[0079] 105 Second Area

[0080] 11. Channel through hole

[0081] 12 Functional sidewalls

[0082] 13. Channel layer

[0083] 14 Gate gap

[0084] 141 First trench

[0085] 142 Second trench

[0086] 143 Third trench

[0087] 15 Insulation layer

[0088] 16 Common Source Lines Detailed Implementation

[0089] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0090] It should be noted that the diagrams provided in the embodiments only schematically illustrate the basic concepts of the present application, and the diagrams only show the components related to the present application, rather than the number, shape and size of the components in actual implementation. The shapes, number and proportions of the components in actual implementation can be arbitrarily changed, and the layout of the components can be more complex.

[0091] Embodiment One

[0092] Referring to Figure 1 The embodiments also provide a semiconductor structure preparation method, which comprises the following steps:

[0093] 1) forming a structure layer, the structure layer comprising a first region and a second region; a channel via is formed in the structure layer, the channel via being located in the first region and the second region, and the density of the channel via in the first region being greater than the density of the channel via in the second region; and

[0094] 2) forming a gate gap in the structure layer, the gate gap comprising a first trench, a second trench and a third trench; wherein the first trench is located in the first region, the third trench is located in the second region, the second trench is located at the junction of the first region and the second region, one end of the second trench being connected with the first trench and the other end of the second trench being connected with the third trench, and the depth of the second trench being less than the depth of the first trench and the depth of the third trench.

[0095] For example, the structure layer 10 can be formed on a substrate (not shown), which can comprise a silicon substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate, etc. Preferably, in the embodiments, the substrate 10 comprises a silicon substrate.

[0096] For example, in step 1), forming the structure layer 10 can comprise the following steps:

[0097] 11) forming a stack structure 101 comprising sacrificial layers 1011 and gate dielectric layers 1012 which are alternately and sequentially stacked, the stack structure 101 comprising a core region and a step region located at the edge of the stack structure 101, wherein the core region is the first region 104, and the step region is the second region 105, as shown in Figures 2 to 3 .

[0098] 12) forming the channel via 11 in the stack structure 101, the channel via 11 penetrates the stack structure 101 along the thickness direction, as shown in Figure 3 and Figure 4 .

[0099] 13) forming a covering dielectric layer 103 on the upper surface of the stack structure 101, as shown in Figure 7 .

[0100] As an example, the number of layers of the stack structure 101 can be set according to actual needs. In the embodiment, the number of layers of the stack structure 13 can include, but is not limited to, 32 layers, 64 layers, or 128 layers, and the like.

[0101] As an example, under the same etching conditions, the sacrificial layer 1011 has a higher etching selectivity than the inter-gate dielectric layer 1012, so as to ensure that the inter-gate dielectric layer 1012 is hardly removed when the sacrificial layer 1011 is removed. Specifically, the inter-gate dielectric layer 1012 can include, but is not limited to, a silicon oxide layer, and the sacrificial layer 1011 can include a silicon nitride layer. The bond energy of the Si-N bond in the sacrificial layer 1011 is lower than the bond energy of the Si-O bond in the inter-gate dielectric layer 1012. The Si-N bond in the sacrificial layer 1011 at the junction of the first region 104 and the second region 105 is pulled longer. The Si-N bond with a longer bond length is more likely to be broken and reacted by the positive ions generated and accelerated on the electrode of the etching machine when the gate gap 14 is formed by using a dry etching process, thereby causing damage at the junction of the first region 104 and the second region 105 and forming a protrusion of the gate gap 14 in the direction of the channel via 11 (i.e., the gate gap 14 at the junction of the first region 104 and the second region 105 extends in the direction of the channel via 11). As the depth of the gate gap 14 increases, the damage at the junction of the first region 104 and the second region 105 becomes more obvious, and even the gate gap 14 can extend into the channel via 11. In the embodiment, the depth of the second groove 142 at the junction of the first region 104 and the second region 105 where the density of the channel via 11 is different is less than the depth of the first groove 141 and the third groove 143 at the first region 104 and the second region 105. There is no deep groove at the junction of the first region 104 and the second region 105, which can avoid the extension of the gate gap 14 to the channel via 11 due to the stress difference at the junction of the first region 104 and the second region 105, thereby avoiding the leakage after filling the gate gap 14.

[0102] As an example, the covering medium layer 103 can include but is not limited to a silicon oxide layer or a silicon nitride layer. Preferably, in the present embodiment, the material of the covering medium layer 103 can be the same as that of the inter-gate medium layer 1012.

[0103] As an example, as shown in Figures 5 to 6 , the step 12) and the step 13) can further include the following step of forming a channel structure:

[0104] 121) forming a functional sidewall 12 in the channel through hole 11; and

[0105] 122) forming a channel layer 13 on the surface of the functional sidewall 12.

[0106] As an example, the functional sidewall 12 can include, in sequence, a blocking layer (not shown), a storage layer (not shown) and a tunneling layer (not shown); wherein the blocking layer can include but is not limited to a silicon oxide layer, the storage layer can include but is not limited to a silicon nitride layer, and the tunneling layer can include but is not limited to a silicon oxide layer.

[0107] As an example, the channel layer 13 can include but is not limited to a polysilicon layer.

[0108] As an example, after forming the channel layer 13, the channel layer 13 can fill the channel through hole 11; of course, there can also be a gap on the side away from the functional sidewall 12 after forming the channel layer 13, i.e. the channel layer 13 does not fill the channel through hole 11, at this time, further including the step of forming a filling insulating layer (not shown) on the surface of the channel layer 13, the filling insulating layer filling the channel through hole 11.

[0109] As an example, the filling insulating layer can include but is not limited to a silicon oxide layer.

[0110] In one example, as shown in Figures 8 to 11 , the step 2) can include the following steps:

[0111] 21) forming the first trench 141 in the first region 104 and forming the third trench 143 in the second region 105; the first trench 141 and the third trench 143 both penetrate the covering medium layer 103 and the stack structure 101 in the thickness direction, as shown in Figure 8 and Figure 11 ; and

[0112] 22) forming a second trench 142 in the structure layer 10, the second trench 142 penetrating the covering medium layer 103 in the thickness direction to expose the stack structure 101, as shown in Figure 9 and Figure 10 .

[0113] Specifically, in step 21), the first trench 141 and the second trench 142 can be formed simultaneously by using the same photolithography process and the same etching process.

[0114] Specifically, in step 22), the second trench 142 can extend through the covering dielectric layer 103 and into the stack structure 101 to a certain depth, for example, as shown in FIG. 2B, the depth of the second trench 142 extending into the stack structure 101 can be greater than the sum of the thickness of one layer of the sacrificial layer 1011 and one layer of the gate dielectric layer 1012, and less than the sum of the thickness of one layer of the sacrificial layer 1011 and two layers of the gate dielectric layer 1012. Of course, in other examples, the depth of the second trench 142 extending into the stack structure 101 can be set according to actual needs, and is not limited thereto. Figure 10 As an example, one end of the second trench 142 extends into the first region 104 and connects with the first trench 141, and the other end of the second trench 142 extends into the second region 105 and connects with the third trench 143. The length of the second trench 142 extending into the first region 104 and the second region 105 can be set according to actual needs, for example, the length of the second trench 142 extending into the first region 104 can be 2-10 times the distance between two adjacent columns of the channel via 11 in the first region 104, specifically, 2 times, 3 times, 4 times, 5 times, 6 times, 7 times, 8 times, 9 times, or 10 times; the length of the second trench 142 extending into the second region 105 can be 2-10 times the distance between two adjacent columns of the channel via 11 in the second region 105, specifically, 2 times, 3 times, 4 times, 5 times, 6 times, 7 times, 8 times, 9 times, or 10 times.

[0115] In one example, as shown in FIG. 2C, after step 2), the following step of forming a common source line 16 in the gate gap 14 is further included:

[0116] Figures 12 to 15 As an example, as shown in FIG. 2C, after step 2), the following step of forming a common source line 16 in the gate gap 14 is further included:

[0117] 3) the step of forming a common source line 16 in the gate gap 14.

[0118] As an example, a conductive layer can be formed in the gate gap 14 as the common source line 16, and the material of the common source line 16 can include but is not limited to copper, aluminum, nickel, or doped polysilicon, etc.

[0119] In an optional example, before forming the common source line 16, the following steps are further included:

[0120] ​The sacrificial layer 1011 is removed based on the gate gap 14 to form a sacrificial gap 1013, as shown in Figure 16 ; and

[0121] A gate layer 1021 is formed in the sacrificial gap 1013; at this time, the stack structure is a stack structure 102 including the gate layer 1021 and the gate medium layer 1012 alternately stacked in sequence, and the structure layer is a structure layer 17 including the stack structure 102 and the cover medium layer 103 on the upper surface of the stack structure 102, as shown in Figure 17 .

[0122] In one example, as shown in Figures 18 to 20 , after the gate layer 1021 is formed in the sacrificial gap 1013, the following step of forming an insulating isolation layer 15 of the gate gap structure is further included: forming an insulating isolation layer 15 on the sidewall of the gate gap 14, which can include but is not limited to a silicon oxide layer or a silicon nitride layer.

[0123] In another optional embodiment, in step 2), before the second trench 142 is formed in the structure layer 10, the following steps are further included:

[0124] 211) The sacrificial layer 1011 is removed based on the first trench 141 and the third trench 143 to form a sacrificial gap 1013;

[0125] 212) A gate layer 1021 is formed in the sacrificial gap 1013; and

[0126] 213) A first conductive layer (not shown) is formed in the first trench 141 and the third trench 143; it should be noted that the first conductive layer here is the part of the common source line 16 located in the first trench 141 and the third trench 143 in Figure 12 or Figure 18 , and the first conductive layer constitutes the part of the first filling structure (located in the first trench 141) and the third filling structure (located in the third trench 143) of the gate gap structure.

[0127] As an example, before the first conductive layer is formed in the first trench 141 and the third trench 143, the step of forming a first insulating isolation layer (not shown) on the sidewall of the first trench 141 and the sidewall of the third trench 143 is included. It should be noted that the first insulating isolation layer is the insulating isolation layer 15 in Figure 18The first insulating isolation layer of the insulating isolation layer 15 is located in the first trench 141 and the third trench 143, and the first insulating isolation layer constitutes a part of the first filling structure (located in the first trench 141) and the third filling structure (located in the third trench 143) of the gate gap structure.

[0128] As an example, after forming the second trench 142, the following steps are further included:

[0129] 23) Forming a second conductive layer (not shown) in the second trench 142. It should be noted that the second conductive layer here is the second conductive layer 17 of the gate gap structure. Figure 12 Or Figure 18 The common source line 16 of the gate gap structure is located in the second trench 142, and the second conductive layer constitutes a part of the second filling structure (located in the second trench 142) of the common source line 16. The second conductive layer is connected with the first conductive layer located in the first trench 141 and the third trench 143 to form the common source line 16.

[0130] As an example, before forming the second conductive layer in the second trench 142, the following step of forming a second insulating isolation layer (not shown) on the sidewall of the second trench 142 is further included. It should be noted that the second insulating isolation layer is a part of the insulating isolation layer 15 located in the second trench 142, and the second insulating isolation layer constitutes a part of the second filling structure (located in the second trench 142) of the insulating isolation layer 15 of the gate gap structure.

[0131] In the semiconductor structure formed in the above embodiment, the depth of the second trench 142 of the gate gap 14 located at the junction of the first region 104 and the second region 105 with different densities of the channel through hole 11 is less than the depth of the first trench 141 and the third trench 143 of the first region 104 and the second region 105. There is no trench with greater depth at the junction of the first region 104 and the second region 105, which can avoid the extension of the gate gap 14 to the channel through hole 11 due to the stress difference at the junction of the first region 104 and the second region 105, thereby avoiding the leakage after filling the gate gap 14.

[0132] Embodiment two

[0133] Please refer to Figures 2 to 11 Please refer to Figures 12 to 15In the embodiment, a semiconductor structure is also provided, which comprises: a structure layer 10, the structure layer 10 comprising a first region 104 and a second region 105; a channel via 11, the channel via 11 being located in the first region 104 and the second region 105, and the density of the channel via 11 in the first region 104 being greater than the density of the channel via 11 in the second region 105; and a gate gap 14, the gate gap 14 being located in the structure layer 10; the gate gap 14 comprising a first trench 141, a second trench 142 and a third trench 143, the first trench 141 being located in the first region 104, the third trench 143 being located in the second region 105, the second trench 142 being located between the first trench 141 and the third trench 143, one end of the second trench 142 being connected with the first trench 141, and the other end of the second trench 142 being connected with the third trench 143, the depth of the second trench 142 being less than the depth of the first trench 141 and the depth of the third trench 143.

[0134] For example, the structure layer 10 can be formed on a substrate (not shown), which can include a silicon substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, an SOI (Silicon-on-insulator) substrate, a GOI (Germanium-on-Insulator) substrate, or the like. Preferably, in the embodiment, the substrate 10 comprises a silicon substrate.

[0135] For example, the structure layer 10 can comprise: a stack structure 101, the stack structure 101 comprising sacrificial layers 1011 and gate dielectric layers 1012 which are alternately stacked in sequence, the stack structure 101 comprising a core region and a step region located at the edge of the stack structure, wherein the core region is the first region 104, and the step region is the second region 105; the channel via 11 being located in the stack structure 101 and penetrating the stack structure 101 in the thickness direction; and a covering dielectric layer 103, the covering dielectric layer 103 being located on the upper surface of the stack structure 101; the first trench 141 and the third trench 143 both penetrating the covering dielectric layer 103 and the stack structure 101 in the thickness direction; and the second trench 142 penetrating the covering dielectric layer 103 in the thickness direction to expose the stack structure 101.

[0136] For example, the number of layers of the stack structure 101 can be set according to actual needs. In the embodiment, the number of layers of the stack structure 13 can include, but is not limited to, 32 layers, 64 layers, 128 layers, or the like.

[0137] As an example, the sacrificial layer 1011 has a higher etching selectivity than the inter-gate dielectric layer 1012 under the same etching condition, so as to ensure that the inter-gate dielectric layer 1012 is hardly removed when the sacrificial layer 1011 is removed; specifically, the sacrificial layer 1011 can include but is not limited to a silicon nitride layer, and the inter-gate dielectric layer 1012 can include a silicon oxide layer. The bond energy of Si-N bond in the sacrificial layer 1011 is lower than the bond energy of Si-O bond in the inter-gate dielectric layer 1012, and the Si-N bond in the sacrificial layer 1011 at the junction of the first region 104 and the second region 105 is pulled longer, and the Si-N bond with the longer bond length is more likely to be broken by the positive ions accelerated by the electrode of the etching machine and react when the gate gap 14 is formed by using a dry etching process, so as to cause damage at the junction of the first region 104 and the second region 105 and form a protrusion of the gate gap 14 in the direction of the channel via 11 (i.e., the gate gap 14 at the junction of the first region 104 and the second region 105 extends in the direction of the channel via 11); as the depth of the gate gap 14 increases, the damage at the junction of the first region 104 and the second region 105 becomes more obvious, and even the gate gap 14 can extend into the channel via 11. In the embodiment, the depth of the second trench 142 at the junction of the first region 104 and the second region 105 where the density of the channel via 11 is different is less than the depth of the first trench 141 and the third trench 143 in the first region 104 and the second region 105, and there is no deep trench at the junction of the first region 104 and the second region 105, which can avoid the extension of the gate gap 14 to the channel via 11 due to the stress difference at the junction of the first region 104 and the second region 105, so as to avoid the leakage after the gate gap 14 is filled.

[0138] As an example, the cover dielectric layer 103 can include but is not limited to a silicon oxide layer or a silicon nitride layer, and preferably, the material of the cover dielectric layer 103 can be the same as the material of the inter-gate dielectric layer 1012 in the embodiment.

[0139] As an example, the semiconductor structure further includes a channel structure, including a functional sidewall 12 located in the channel via 11, and a channel layer 13 located on the surface of the functional sidewall 12.

[0140] As an example, the functional sidewall 12 can include, in sequence, a blocking layer (not shown), a storage layer (not shown), and a tunneling layer (not shown); wherein the blocking layer can include, but is not limited to, a silicon oxide layer, the storage layer can include, but is not limited to, a silicon nitride layer, and the tunneling layer can include, but is not limited to, a silicon oxide layer.

[0141] As an example, the channel layer 13 can include, but is not limited to, a polysilicon layer.

[0142] As an example, after the channel layer 13 is formed, the channel layer 13 can fill the channel via 11; of course, there can also be a gap on the side away from the functional sidewall 12 after the channel layer 13 is formed, i.e., the channel layer 13 does not fill the channel via 11, in which case, a step of forming a filling insulating layer (not shown) on the surface of the channel layer 13 is further included, and the filling insulating layer fills the channel via 11.

[0143] As an example, the filling insulating layer can include, but is not limited to, a silicon oxide layer. As an example, the first trench 141 and the third trench 143 both extend through the cover dielectric layer 103 and the stack structure 101 in the thickness direction; the second trench 142 extends through the cover dielectric layer 103 in the thickness direction to expose the stack structure 101, and the second trench 142 can extend to a certain depth in the stack structure 101 after extending through the cover dielectric layer 103, for example, as shown in Figure 10 the second trench 142 can extend to a depth in the stack structure 101 that is greater than the sum of the thicknesses of one layer of the sacrificial layer 1011 and one layer of the gate dielectric layer 1012, and less than the sum of the thicknesses of one layer of the sacrificial layer 1011 and two layers of the gate dielectric layer 1012. Of course, in other examples, the depth to which the second trench 142 extends into the stack structure 101 can be set according to actual needs, and is not limited thereto.

[0144] As an example, the second trench 142 extends into the first region 104 to connect with the first trench 141 at one end and extends into the second region 105 to connect with the third trench 143 at the other end. The length of the second trench 142 extending into the first region 104 and the second region 105 can be set according to actual needs. For example, the length of the second trench 142 extending into the first region 104 can be 2-10 times the distance between two adjacent rows of the channel via holes 11 in the first region 104. Specifically, the length can be 2 times, 3 times, 4 times, 5 times, 6 times, 7 times, 8 times, 9 times, or 10 times. The length of the second trench 142 extending into the second region 105 can be 2-10 times the distance between two adjacent rows of the channel via holes 11 in the second region 105. Specifically, the length can be 2 times, 3 times, 4 times, 5 times, 6 times, 7 times, 8 times, 9 times, or 10 times.

[0145] As an example, the semiconductor structure further includes a gate gap structure including the common source line 16 located in the gate gap 14. The gate gap structure includes a first filling structure located in the first trench 141, a second filling structure located in the second trench 142, and a third filling structure located in the third trench 143. The first filling structure includes the portion of the common source line 16 located in the first trench 141 (first conductive layer), the second filling structure includes the portion of the common source line 16 located in the second trench 142 (second conductive layer), and the third filling structure includes the portion of the common source line 16 located in the third trench 143 (first conductive layer).

[0146] Please continue to refer to Figures 18 to 20 In another embodiment, the present application also provides a semiconductor structure. The semiconductor structure in this embodiment is substantially the same as the semiconductor structure shown in Figures 12 to 15 the differences between the two are that, Figures 12 to 15The stack structure 101 in the structure layer 10 described in the above embodiment comprises the sacrificial layer 1011 and the gate dielectric layer 1012 which are alternately stacked in sequence, and the common source line 16 is formed in the gate gap 14. The stack structure 102 in the structure layer 17 described in the semiconductor structure of the embodiment comprises the gate layer 1021 and the gate dielectric layer 1012 which are alternately stacked in sequence, and the insulating isolation layer 15 is formed on the sidewall of the gate gap 14, i.e. the insulating isolation layer 15 is formed between the common source line 16 and the stack structure 102. The gate gap structure comprises the common source line 16 and the insulating isolation layer 15. The gate gap structure comprises a first filling structure in the first trench 141, a second filling structure in the second trench 142, and a third filling structure in the third trench 143. The first filling structure comprises the part of the common source line 16 in the first trench 141 (first conductive layer) and the part of the insulating isolation layer 15 in the first trench 141 (first insulating isolation layer). The second filling structure comprises the part of the common source line 16 in the second trench 142 (second conductive layer) and the part of the insulating isolation layer 15 in the second trench 142 (second insulating isolation layer). The third filling structure comprises the part of the common source line 16 in the third trench 143 (first conductive layer) and the part of the insulating isolation layer 15 in the third trench 143 (first insulating isolation layer).

[0147] As an example, the material of the common source line 16 can include but is not limited to copper, aluminum, nickel, or doped polysilicon, etc.

[0148] As an example, the insulating isolation layer 15 can include but is not limited to a silicon oxide layer or a silicon nitride layer. In the semiconductor structure of the above embodiment, the depth of the second trench 142 at the junction of the first region 104 and the second region 105 where the density of the channel via 11 is different is less than the depth of the first trench 141 and the third trench 143 in the first region 104 and the second region 105. There is no trench with large depth at the junction of the first region 104 and the second region 105, which can avoid the extension of the gate gap 14 to the channel via 11 due to the stress difference at the junction of the first region 104 and the second region 105, thereby avoiding the leakage after filling the gate gap 14.

[0149] As described above, the semiconductor structure and the preparation method thereof, the preparation method of the semiconductor structure comprises the following steps: forming a structure layer, the structure layer comprises a first region and a second region; a channel via is formed in the structure layer, the channel via is located in the first region and the second region, and the density of the channel via in the first region is greater than that in the second region; and a gate gap is formed in the structure layer, the gate gap comprises a first groove, a second groove and a third groove; wherein the first groove is located in the first region, the third groove is located in the second region, the second groove is located at the junction of the first region and the second region, one end of the second groove is connected with the first groove, and the other end of the second groove is connected with the third groove, and the depth of the second groove is less than the depth of the first groove and the depth of the third groove. In the semiconductor structure formed in the above embodiment, the depth of the second groove of the gate gap located at the junction of the first region and the second region where the density of the channel via is different is less than the depth of the first groove and the third groove located in the first region and the second region, and there is no groove with large depth at the junction of the first region and the second region, which can avoid the extension of the gate gap to the channel via due to the stress difference at the junction of the first region and the second region, thereby avoiding the leakage after filling the gate gap.

[0150] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes completed by those skilled in the art without departing from the spirit and technical thought disclosed by the present application should be covered by the claims of the present application.

Claims

1. A method of fabricating a semiconductor structure, characterized by, The method comprises: forming a stack structure comprising sacrificial layers and gate dielectric layers alternately arranged in sequence, the stack structure comprising a first region and a second region; forming channel vias penetrating through the stack structure along a thickness direction of the stack structure, the density of the channel vias in the first region being greater than that in the second region; forming a gate gap comprising a first trench, a second trench and a third trench; the first trench is located in the first region; the third trench is located in the second region; the second trench is located between the first trench and the third trench, one end of the second trench is connected with the first trench, and the other end of the second trench is connected with the third trench; along the thickness direction, the depth of the second trench is less than the depth of the first trench and the depth of the third trench.

2. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: After forming the channel vias penetrating through the stack structure along the thickness direction of the stack structure, the method further comprises: forming a covering dielectric layer on the stack structure.

3. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: The sacrificial layers comprise silicon nitride, and the gate dielectric layers comprise silicon oxide.

4. The method according to claim 2, wherein the first trench and the third trench both penetrate through the covering dielectric layer and the stack structure along the thickness direction, and the second trench penetrates through the covering dielectric layer along the thickness direction.

5. The method of claim 4, wherein the semiconductor structure is prepared by a method comprising: The second trench penetrates through at least one of the sacrificial layers and at least one of the gate dielectric layers along the thickness direction.

6. The method of claim 5, wherein the semiconductor structure is prepared by a method comprising: The depth of the second trench in the stack structure is less than the sum of the thickness of one of the sacrificial layers and the thickness of two of the gate dielectric layers.

7. The method of claim 4, wherein the semiconductor structure is formed by a method comprising: The method further comprises: removing the sacrificial layers based on the gate gap to form a sacrificial gap; forming a gate layer in the sacrificial gap; forming an insulating isolation layer on the sidewall of the gate gap; forming a common source line on the surface of the insulating isolation layer in the gate gap.

8. The method of claim 4, wherein the semiconductor structure is prepared by a method comprising: Before forming the second trench, the method further comprises: removing the sacrificial layers based on the first trench and the third trench to form a sacrificial gap; forming a gate layer in the sacrificial gap; forming a first conductive layer in the first trench and the third trench.

9. The method of claim 8, wherein the semiconductor structure is prepared by a method comprising: After forming the second trench, the method further comprises: forming a second conductive layer in the second trench, the second conductive layer and the first conductive layer located in the first trench and the third trench are connected to form a common source line.

10. The method according to claim 9, wherein before forming the first conductive layer in the first trench and the third trench, the method further comprises forming a first insulating isolation layer on the sidewall of the first trench and the sidewall of the third trench; and before forming the second conductive layer in the second trench, the method further comprises forming a second insulating isolation layer on the sidewall of the second trench.

11. The method of claim 1, wherein One end of the second trench extends into the first region to connect with the first trench, and the second trench extends into the first region to a length of 2-10 times the spacing between two adjacent columns of the channel holes in the first region.

12. The method of claim 1, wherein The other end of the second trench extends into the second region to connect with the third trench, and the second trench extends into the second region to a length of 2-10 times the spacing between two adjacent columns of the channel holes in the second region.

13. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: After forming the channel holes penetrating through the stack structure along the thickness direction of the stack structure, the preparation method further comprises: forming functional side walls in the channel holes; forming a channel layer on the surface of the functional side walls.

14. A semiconductor structure, characterized by comprises: a stack structure comprising gate layers and gate dielectric layers alternately arranged in sequence, the stack structure comprising a first region and a second region; a channel structure penetrating through the stack structure along the thickness direction of the stack structure, the density of the channel structure in the first region being greater than the density of the channel structure in the second region; and a gate gap structure comprising a first filling structure, a second filling structure and a third filling structure, the first filling structure being located in the first region; the third filling structure being located in the second region; the second filling structure being located between the first filling structure and the third filling structure, one end of the second filling structure being connected with the first filling structure, the other end of the second filling structure being connected with the third filling structure, the depth of the second filling structure being less than the depth of the first filling structure and the depth of the third filling structure along the thickness direction. One end of the second filling structure extends into the first region to connect with the first filling structure, and the second filling structure extends into the first region to a length of 2-10 times the spacing between two adjacent columns of the channel structures in the first region.

15. The semiconductor structure of claim 14, wherein, The other end of the second filling structure extends into the second region to connect with the third filling structure, and the second filling structure extends into the second region to a length of 2-10 times the spacing between two adjacent columns of the channel structures in the second region.

16. The semiconductor structure of claim 14, wherein, The channel structure comprises:

17. The semiconductor structure of claim 14, wherein, functional side walls; and a channel layer on the surface of the functional side walls. The gate gap structure further comprises a common source line, the common source line comprising a first conductive layer located in the first region and the second region, and a second conductive layer located between the first conductive layer in the first region and the first conductive layer in the second region, the second conductive layer being connected with the first conductive layer.

18. The semiconductor structure of claim 14, wherein, The gate gap structure further comprises an insulating isolation layer located between the common source line and the stack structure.

19. The semiconductor structure of claim 18, wherein, 20. The semiconductor structure of claim 14, wherein: the semiconductor structure further comprises a covering dielectric layer located on the stack structure; the first filling structure and the third filling structure both penetrate through the covering dielectric layer and the stack structure along the thickness direction; and the second filling structure penetrates through the covering dielectric layer along the thickness direction. ​ 21. The semiconductor structure of claim 20, wherein, The second filling structure penetrates at least one of the gate layers and at least one of the interlayer dielectric layers in the thickness direction.

22. The semiconductor structure of claim 21, wherein, The second filling structure has a depth in the stack structure that is less than the sum of the thickness of one of the gate layers and two of the interlayer dielectric layers.

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