Display panel and its manufacturing method, display device

Abstract

The application provides a display panel, a manufacturing method thereof and a display device. The display panel comprises a substrate and N conductive layers, the N conductive layers are sequentially arranged on the substrate in a direction away from the substrate, each of the N conductive layers comprises at least one conductive line extending along a first direction, and N is an integer greater than or equal to 3; the part of the at least one conductive line in each conductive layer extending along the first direction is staggered with the part of the at least one conductive line in the remaining conductive layers extending along the first direction in a second direction, and the parts of the at least one conductive line in each conductive layer extending along the first direction and the parts of the at least one conductive line in the remaining conductive layers extending along the first direction overlap.

Description

Technical Field

[0001] This article relates to, but is not limited to, the field of display technology, and in particular to a display panel and its manufacturing method, and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. Under-display camera technology is a novel technology proposed to increase the screen-to-body ratio of display devices. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] This disclosure provides a display panel, a method for manufacturing the same, and a display device.

[0005] This disclosure provides a display panel. The display panel includes:

[0006] Substrate;

[0007] N conductive layers are sequentially disposed on the substrate along a direction away from the substrate, and each of the N conductive layers includes at least one conductive line extending along a first direction, where N is an integer greater than or equal to 3;

[0008] The portion of at least one conductive line in each conductive layer extending along the first direction and the portion of at least one conductive line in the remaining conductive layers extending along the first direction are misaligned and overlapped in the second direction when projected onto the substrate, and the second direction intersects the first direction.

[0009] In an exemplary embodiment, the orthographic projections of a conductive line located in the nth conductive layer, a conductive line located in the (n-1)th conductive layer, and a conductive line located in the (n+1)th conductive layer on the substrate all overlap, while the orthographic projections of the conductive line located in the (n-1)th conductive layer and the conductive line located in the (n+1)th conductive layer on the substrate do not overlap, where n is an integer greater than or equal to 2 and less than or equal to N-1.

[0010] In an exemplary embodiment, the overlap length of the orthographic projections of the conductive line located in the nth conductive layer and the conductive line located in the (n-1)th conductive layer on the substrate along the second direction is equal to the overlap length of the orthographic projections of the conductive line located in the nth conductive layer and the conductive line located in the (n+1)th conductive layer on the substrate along the second direction.

[0011] In an exemplary embodiment, the overlap length of the conductive line located in the nth conductive layer and the conductive line located in the (n-1)th conductive layer along the second direction when projected onto the substrate is k1× Where k1 is the first process parameter, W is the line width parameter, and S is the line spacing parameter.

[0012] In an exemplary embodiment, the orthographic projections of a conductive line located in the m-th conductive layer, a conductive line located in the (m-1)-th conductive layer, and a conductive line located in the (m-2)-th conductive layer on the substrate all overlap, and the orthographic projections of the conductive line located in the (m-1)-th conductive layer and the conductive line located in the (m-2)-th conductive layer on the substrate do not overlap, where m is an integer greater than or equal to 3 and less than or equal to N.

[0013] In an exemplary embodiment, the overlap length of the orthographic projection of the conductive line located in the m-th conductive layer and the conductive line located in the (m-1)-th conductive layer on the substrate along the second direction is less than the overlap length of the orthographic projection of the conductive line located in the m-th conductive layer and the conductive line located in the (m-2)-th conductive layer on the substrate along the second direction.

[0014] In an exemplary embodiment, the overlap length of the orthographic projection of the conductive line located in the m-th conductive layer and the conductive line located in the (m-1)-th conductive layer on the substrate along the second direction is equal to half the overlap length of the orthographic projection of the conductive line located in the m-th conductive layer and the conductive line located in the (m-2)-th conductive layer on the substrate along the second direction.

[0015] In an exemplary embodiment, the overlap length of the conductive line located in the m-th conductive layer and the conductive line located in the (m-1)-th conductive layer along the second direction on the substrate is: Where k2 is the second process parameter, W is the line width parameter, and S is the line spacing parameter.

[0016] In one exemplary embodiment, the line widths of multiple conductive lines within at least one conductive layer are equal, and the spacing between adjacent conductive lines is equal.

[0017] In one exemplary embodiment, the linewidth of multiple conductive lines within at least one conductive layer is equal to the line spacing between adjacent conductive lines.

[0018] In one exemplary embodiment, the linewidths of the conductive lines in different conductive layers are equal, and the spacing between adjacent conductive lines in different conductive layers is equal.

[0019] In one exemplary embodiment, the display panel further includes an insulating layer located between two adjacent conductive layers, wherein the plurality of insulating layers have equal thickness.

[0020] In one exemplary embodiment, the thickness of the conductive layer is less than the thickness of the insulating layer adjacent to it.

[0021] In one exemplary embodiment, the display panel includes a display area; the display area includes a first region and a second region; the orthographic projections of the first region and the second region onto the substrate do not overlap;

[0022] The display panel further includes: a circuit structure layer and a light-emitting structure layer disposed on the substrate, wherein the light-emitting structure layer is located on the side of the circuit structure layer away from the substrate, and the N conductive layers are located between the circuit structure layer and the light-emitting structure layer; the circuit structure layer includes: a plurality of first pixel driving circuits and a plurality of second pixel driving circuits located in the first region, and the light-emitting structure layer includes: a plurality of first light-emitting devices located in the first region and a plurality of second light-emitting devices located in the second region;

[0023] At least one first pixel driving circuit among the plurality of first pixel circuits is electrically connected to at least one first light-emitting device among the plurality of first light-emitting devices, and at least one second pixel driving circuit among the plurality of second pixel driving circuits is electrically connected to at least one second light-emitting device among the plurality of second light-emitting devices through at least one conductive line among the N conductive layers.

[0024] In one exemplary embodiment, the value of N is 3;

[0025] A conductive line located in the second conductive layer overlaps with the orthographic projections of a conductive line located in the first conductive layer and a conductive line located in the third conductive layer on the substrate. The orthographic projections of the conductive line located in the first conductive layer and the conductive line located in the third conductive layer do not overlap. The orthographic projection of the conductive line located in the third conductive layer overlaps with the orthographic projection of another conductive line located in the first conductive layer on the substrate. The conductive line located in the first conductive layer and the other conductive line are adjacent in the second direction.

[0026] In an exemplary embodiment, the overlap length of the orthographic projection of the conductive line located in the second conductive layer and the conductive line located in the first conductive layer on the substrate along the second direction is equal to the overlap length of the orthographic projection of the conductive line located in the second conductive layer and the conductive line located in the third conductive layer on the substrate along the second direction.

[0027] The overlap length of the orthographic projection of the conductive line located in the third conductive layer and the other conductive line located in the first conductive layer onto the substrate along the second direction is twice the overlap length of the orthographic projection of the conductive line located in the second conductive layer and the conductive line located in the first conductive layer onto the substrate along the second direction.

[0028] In an exemplary embodiment, the overlap length of the orthographic projections of the conductive line located in the second conductive layer and the conductive line located in the first conductive layer on the substrate along the second direction is denoted as O1; the overlap length of the orthographic projections of the conductive line located in the second conductive layer and the conductive line located in the third conductive layer on the substrate along the second direction is denoted as O2; the overlap length of the orthographic projections of the conductive line located in the third conductive layer and the other conductive line located in the first conductive layer on the substrate along the second direction is denoted as O3; the thickness of the insulating layer between the first conductive layer and the second conductive layer is denoted as D1; ​​the thickness of the insulating layer between the second conductive layer and the third conductive layer is denoted as D2; the thickness of the insulating layer between the first conductive layer and the third conductive layer is denoted as D3; then O1, O2, O3, D1, D2, and D3 satisfy the following formula:

[0029]

[0030] A display device includes the display panel described in any of the above embodiments.

[0031] A method for fabricating a display panel, used to fabricate the display panel described in any of the above embodiments. The fabrication method includes: sequentially forming N conductive layers on one side of a substrate; wherein each of the N conductive layers includes at least one conductive line extending along a first direction, and N is an integer greater than or equal to 3; the portion of at least one conductive line in each conductive layer extending along the first direction and the portion of at least one conductive line in the remaining conductive layers extending along the first direction are misaligned and overlapped in a second direction when projected onto the substrate, and the second direction intersects the first direction.

[0032] The display panel provided in this embodiment improves the display quality by offsetting and overlapping the orthogonal projections of at least one conductive line in each of the N conductive layers extending along a first direction with the portions of at least one conductive line in the remaining conductive layers extending along the first direction in a second direction.

[0033] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0034] The accompanying drawings are provided to further illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure. The shape and size of one or more components in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0035] Figure 1 This is a perspective view of a display device according to an embodiment of the present disclosure;

[0036] Figure 2 This is a front view schematic diagram of the display panel according to an embodiment of the present disclosure;

[0037] Figure 3 This is a partial schematic diagram of the display panel according to an embodiment of the present disclosure;

[0038] Figure 4 This is a partial top view of a display panel;

[0039] Figure 5 for Figure 4 A cross-sectional view of the display panel along the AA direction;

[0040] Figure 6 This is a partial top view of the display panel according to an embodiment of the present disclosure;

[0041] Figure 7 for Figure 6 A cross-sectional view of the display panel along the BB direction. Detailed Implementation

[0042] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be changed to one or more forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0043] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shape and size of one or more parts in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0044] The ordinal numbers such as "first," "second," and "third" in this disclosure are used to avoid confusion among the constituent elements, not to limit the quantity. "Multiple" in this disclosure includes two or more quantities.

[0045] In this disclosure, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of the specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately changed depending on the direction in which the constituent elements are described. Therefore, the description is not limited to the terms used in the specification and may be appropriately replaced as appropriate.

[0046] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection or an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate.

[0047] In this disclosure, "electrical connection" includes the situation where constituent elements are connected together by a component having a certain electrical function. There are no particular limitations on the "component having a certain electrical function," as long as it enables the transmission of electrical signals between the connected constituent elements. Examples of "component having a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components having one or more functions.

[0048] In this disclosure, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain) and the source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0049] In this disclosure, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this disclosure, the "source electrode" and the "drain electrode" can be interchanged.

[0050] In this disclosure, "parallel" refers to a state in which the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore can include a state in which the angle is greater than or equal to -5° and less than 5°. Furthermore, "perpendicular" refers to a state in which the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore can include a state in which the angle is greater than or equal to 85° and less than 95°.

[0051] In this disclosure, the terms "film" and "layer" can be interchanged. For example, sometimes "conductive layer" can be replaced with "conductive film". Similarly, sometimes "insulating film" can be replaced with "insulating layer".

[0052] In this disclosure, "about" or "approximately" means values ​​that are not strictly defined and are within the allowable range of process and measurement errors.

[0053] In this disclosure, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined, but can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, and chamfers, curved edges, and other deformations are possible.

[0054] In this disclosure, "light transmittance" refers to the ability of light to pass through a medium, and is the percentage of light flux passing through a transparent or translucent body relative to the incident light flux.

[0055] This disclosure provides at least one embodiment of a display device, including a display panel. The display device can be a product with image display capabilities (including static images or dynamic images, where dynamic images can be video). For example, the display device can be any of the following products: monitor, television set, billboard, digital photo frame, laser printer with display function, telephone, mobile phone, drawing screen, personal digital assistant (PDA), digital camera, portable camcorder, viewfinder, navigator, vehicle, large-area wall, information query equipment (such as business query equipment for e-government, banks, hospitals, power companies, etc.), monitor, etc. Furthermore, the display device can also be any of the following products: microdisplay, virtual reality (VR) device including a microdisplay, or augmented reality (AR) device, etc.

[0056] Figure 1 This is a perspective view of a display device according to an embodiment of the present disclosure. Figure 1 As shown, the display device may include a display panel 100 and a sensor 200. The display panel 100 may be a flat panel for displaying images. The display panel 100 may be referred to as a screen, such as a liquid crystal display panel, an organic light-emitting diode (OLED) display panel, etc. For example, the sensor 200 may be an infrared sensor, an ultrasonic sensor, a LiDAR (Light Detection and Ranging) sensor, a radar sensor, a camera sensor, etc.

[0057] In one exemplary embodiment, such as Figure 1 As shown, the display panel 100 may have a display side 100A and a non-display side 100B. The display side 100A is the side of the display panel 100 capable of displaying images. When the human eye is on the display side 100A, the image displayed on the display panel 100 can be viewed. The non-display side 100B is opposite to the display side 100A. The sensor 200 may be disposed on the non-display side 100B of the display panel 100; therefore, the sensor 200 can be called an under-display sensor. Since the sensor 200 needs to receive light signals transmitted through the display panel 100 from the outside, the display panel 100 needs to have high light transmittance in the area corresponding to the sensor 200. The display panel in this embodiment is not limited to display devices with an under-display camera (Full Display with Camera, FDC), but can also be applied to other display panels with multiple conductive layer cables.

[0058] In one exemplary embodiment, such as Figure 1 As shown, the display panel 100 may have a display area AA and a peripheral area SA. For example... Figure 1 As shown, the X direction can be the extension direction of one side of the display area AA, such as the extension direction of the long side. The Y direction can be the extension direction of the other side of the display area AA, such as the extension direction of the short side. The Z direction can be the vertical direction of the display area AA. In this embodiment of the present disclosure, the Z direction is also the thickness direction of the display panel.

[0059] Figure 2 This is a front view schematic diagram of a display panel according to an embodiment of this disclosure. Figure 2 As shown, the peripheral area SA can be located on at least one side outside the display area AA. For example, the peripheral area SA can be located on one side outside the display area AA. Alternatively, the peripheral area SA can be located around the display area AA, including the top and bottom sides and the left and right sides.

[0060] like Figure 2 As shown, the display area AA may include a first area AA1 and a second area AA2 that do not overlap. The first area AA1 may be referred to as the sensor non-corresponding area. The second area AA2 may be referred to as the sensor corresponding area. The light transmittance of the second area AA2 is higher than that of the first area AA1. The orthographic projection of the sensor 200 onto the display panel 100 overlaps with the second area AA2 at least partially, so that more light can pass through the display panel 100 and be received by the sensor 200. For example, a portion of the orthographic projection of the sensor 200 onto the display panel 100 is located within the second area AA2. Alternatively, the entire orthographic projection of the sensor 200 onto the display panel 100 is located within the second area AA2. Alternatively, the photosensitive window of the sensor 200 is located within the second area AA2 in the orthographic projection of the sensor 200 onto the display panel 100.

[0061] In an exemplary embodiment, the first region AA1 may be a region in the display area AA other than the second region AA2.

[0062] In an exemplary embodiment, the first region AA1 may surround at least one side of the second region AA2. For example, the second region AA2 may be located at the top center of the display area AA, and the first region AA1 may surround the second region AA2. For example, the second region AA2 may be located at other positions such as the upper left or upper right corner of the display area AA, and this disclosure is not limited thereto.

[0063] In one exemplary embodiment, the display area AA can be a rectangle, such as a rounded rectangle. The second area AA2 can be a circle, an ellipse, a rectangle, a pentagon, a hexagon, etc., and this disclosure does not limit it.

[0064] In an exemplary embodiment, the display area AA may be provided with multiple sub-pixels. A sub-pixel may be the smallest portion with controllable brightness. At least one sub-pixel may include a pixel driving circuit and a light-emitting device. The pixel driving circuit may be electrically connected to the light-emitting device and configured to drive the electrically connected light-emitting device to emit light. The pixel circuit may include multiple transistors and at least one capacitor. For example, the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. In the above circuit structures, T refers to a thin-film transistor, C refers to a capacitor, the number before T represents the number of thin-film transistors in the circuit, and the number before C represents the number of capacitors in the circuit.

[0065] In one exemplary embodiment, the multiple transistors in the pixel circuit can be either P-type transistors or N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the manufacturing difficulty of the display substrate, and improve product yield. In other examples, the multiple transistors in the pixel circuit may include both P-type and N-type transistors.

[0066] In one exemplary embodiment, the multiple transistors in the pixel circuit can be low-temperature polysilicon (LTPS) thin-film transistors (TFTs), oxide thin-film transistors (OPTs), or a combination of both. The active layer of the LTPS TFT is made of low-temperature polysilicon (LTPS), while the active layer of the OPT TFT is made of oxide semiconductor. LTPS TFTs offer advantages such as high mobility and fast charging, while OPTs offer advantages such as low leakage current. Integrating LTPS and OPTs onto a single display substrate, i.e., an LTPS+Oxide (LTPO) display substrate, leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0067] In an exemplary embodiment, the light-emitting device can be any one of a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), or a micro-LED. For example, the light-emitting device can be an OLED, which emits red, green, blue, or white light under the drive of its corresponding pixel driving circuit. The color of the emitted light can be determined as needed. For example, the light-emitting device can include an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting device can be electrically connected to the corresponding pixel driving circuit, which is not limited in this disclosure.

[0068] In one exemplary embodiment, a pixel unit of the display area AA may include three sub-pixels, which may be a red sub-pixel, a green sub-pixel, and a blue sub-pixel, respectively. This disclosure does not limit this.

[0069] In one exemplary embodiment, a pixel unit may include four sub-pixels, which may be a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, respectively.

[0070] In an exemplary embodiment, the shape of the light-emitting device can be rectangular, rhomboid, pentagonal, or hexagonal. When a pixel unit includes three sub-pixels, the light-emitting devices of the three sub-pixels can be arranged horizontally, vertically, or in a triangular arrangement. When a pixel unit includes four sub-pixels, the light-emitting devices of the four sub-pixels can be arranged horizontally, vertically, or in a square arrangement; this disclosure does not limit this arrangement.

[0071] Figure 3 This is a partial schematic diagram of a display panel according to an embodiment of the present disclosure. Figure 3 As shown, the area occupied by a pixel driving circuit can be referred to as a sub-pixel region. The first region AA1 may include multiple sub-pixel regions arranged in an array. The sub-pixel regions within the first region AA1 may include a normal sub-pixel region 101 and a dummy sub-pixel region 102. The normal sub-pixel region 101 may house a first pixel driving circuit. A first light-emitting device electrically connected to the first pixel driving circuit may be located within the first region AA1, and all or part of the first light-emitting device may be located within the normal sub-pixel region 101. The dummy sub-pixel region 102 may house a second pixel driving circuit or an invalid pixel driving circuit. A second light-emitting device electrically connected to the second pixel driving circuit may be located in the second region AA2. Setting up an invalid pixel circuit can improve the uniformity of components across multiple film layers during the etching process. For example, the invalid pixel circuit may have a structure substantially the same as the first and second pixel driving circuits in its row or column, except that it is not electrically connected to any light-emitting device.

[0072] In one exemplary embodiment, such as Figure 3 As shown, the second region AA2 may include a plurality of second light-emitting devices arranged in an array. At least one of the second light-emitting devices in the second region AA2 may be electrically connected to the second pixel driving circuit in the virtual sub-pixel area 102 in the first region AA1, and driven to emit light by the circuit.

[0073] like Figure 3 As shown, at least one second pixel driving circuit in the virtual sub-pixel area 102 within the first region AA1 can be electrically connected to at least one second light-emitting device in the second region AA2 via at least one conductive line 110. For example, each second light-emitting device in the second region AA2 can be electrically connected to a second pixel driving circuit in a virtual sub-pixel area 102 within the first region AA1 via at least one conductive line 110. By placing the second pixel driving circuit driving the second light-emitting device in the first region AA1, the occlusion of light by the pixel driving circuit is reduced, increasing the light transmittance of the second region AA2.

[0074] In one exemplary embodiment, such as Figure 3As shown, the second region AA2 may include multiple second light-emitting devices, and the first region AA1 may include multiple first light-emitting devices and multiple pixel driving circuits. The multiple pixel driving circuits may include multiple first pixel driving circuits, multiple second pixel driving circuits, and multiple invalid pixel driving circuits, etc. At least one of the multiple second pixel driving circuits may be electrically connected to at least one of the multiple second light-emitting devices via at least one conductive line 110, and the orthographic projection of at least one second pixel driving circuit on the substrate does not overlap with the orthographic projection of at least one second light-emitting device on the substrate. At least one second pixel driving circuit may be configured to provide a driving signal to the electrically connected second light-emitting device to drive the second light-emitting device to emit light. At least one of the multiple first pixel driving circuits may be electrically connected to at least one of the multiple first light-emitting devices. The orthographic projection of at least one first pixel driving circuit on the substrate and the orthographic projection of at least one first light-emitting device on the substrate at least partially overlap. One end of the conductive line 110 may be electrically connected to a second pixel driving circuit, and the other end may be electrically connected to a second light-emitting device. The conductive line 110 may extend from the first region AA1 to the second region AA2, which is not limited in this disclosure.

[0075] In one exemplary embodiment, such as Figure 3 As shown, since the first region AA1 not only has a first pixel driving circuit electrically connected to the first light-emitting device, but also a second pixel driving circuit electrically connected to the second light-emitting device, the number of pixel driving circuits in the first region AA1 can be greater than the number of first light-emitting devices. In the disclosed embodiment, as... Figure 3 As shown, the area where the second pixel driving circuit is disposed can be obtained by reducing the size of the first pixel driving circuit in the Y direction. For example, the size of the pixel driving circuit in the Y direction can be smaller than the size of the first light-emitting device in the Y direction. In the disclosed embodiment, as... Figure 3 As shown, the original 'a' column pixel driving circuits can be compressed along the Y direction, thereby adding space for one more column of pixel driving circuits. The space occupied by the original 'a' column pixel driving circuits and the compressed 'a+1' column pixel driving circuits can be the same. Here, 'a' can be an integer greater than 1. For example, 'a' can be equal to 2, 3, 4, 7, etc.

[0076] In one exemplary embodiment, the original b-row pixel driving circuit can be compressed along the X direction to add space for a new row of pixel driving circuits, and the space occupied by the b-row pixel driving circuit before compression and the b+1-row pixel driving circuit after compression is the same. Here, b can be an integer greater than 1. Alternatively, the area for setting the second pixel driving circuit can be obtained by reducing the size of the first pixel driving circuit in the X and Y directions.

[0077] In one exemplary embodiment, a row of light-emitting devices may refer to a row of pixel driving circuits all connected to the same gate line (e.g., a scan line). A row of pixel driving circuits may refer to a row of pixel driving circuits all connected to the same gate line; this disclosure does not limit this.

[0078] In one exemplary embodiment, the display panel includes a substrate and a circuit structure layer located on one side of the substrate. The circuit structure layer may include at least one first pixel driving circuit and at least one second pixel driving circuit. The circuit structure layer may be located between the substrate and conductive lines.

[0079] In one exemplary embodiment, the display panel may further include a light-emitting structure layer located on the side of the plurality of conductive lines away from the substrate. The light-emitting structure layer may include at least one first light-emitting device and at least one second light-emitting device.

[0080] Figure 4 This is a partial top view of a display panel. Figure 5 for Figure 4 The diagram shows a cross-sectional view of the display panel along the AA direction. Figure 4 and Figure 5 The diagram illustrates one design and arrangement of multiple conductive lines. For example, the multiple conductive lines of a display panel can be located in three conductive layers (e.g., a first conductive layer, a second conductive layer, and a third conductive layer arranged sequentially along a direction away from the substrate). The first conductive layer may include at least one first connecting line 10, the second conductive layer may include at least one second connecting line 20, and the third conductive layer may include at least one third connecting line 30. The orthographic projection of the extension of the second connecting line 20 along the Y direction onto the substrate can cover the orthographic projection of the extension of the first connecting line 10 along the Y direction onto the substrate. The orthographic projection of the extension of the third connecting line 30 along the Y direction onto the substrate does not overlap with the orthographic projections of the extensions of the first connecting line 10 and the second connecting line 20 along the Y direction onto the substrate.

[0081] In some implementations, since the second light-emitting device in the second region is electrically connected to the second pixel driving circuit in the first region via conductive lines, the display uniformity of the second region is affected by the capacitance of the conductive lines. In some examples, by adjusting the compression ratio of the pixel driving circuit in the first region and adjusting the priority order of connecting the second light-emitting devices of different colors to the second pixel driving circuit in the second region, the length of the conductive lines electrically connected to the second light-emitting devices can be controlled, thereby reducing the impact of the capacitance of the conductive lines on display quality. However, when the lengths of the conductive lines in different conductive layers are approximately the same, Figure 4 and Figure 5Taking the conductive line structure shown as an example, the extension portions of the conductive lines of the first and second conductive layers along the Y direction overlap, while the extension portions of the conductive lines of the third conductive layer along the Y direction do not overlap with the extension portions of the conductive lines of the first and second conductive layers along the Y direction. The overlapping areas between the conductive lines of different conductive layers are different, which leads to differences in capacitance between different conductive lines and can easily cause problems such as uneven display.

[0082] This disclosure provides a display panel. The display panel includes a substrate and N conductive layers. The N conductive layers are sequentially disposed on the substrate along a direction away from the substrate. Each of the N conductive layers includes at least one conductive line extending along a first direction, where N is an integer greater than or equal to 3. The portion of at least one conductive line in each conductive layer extending along the first direction overlaps with the portion of at least one conductive line in the remaining conductive layers extending along the first direction in a second direction, where the projection of the conductive line onto the substrate is offset in a second direction and intersects the first direction.

[0083] The display panel provided in this embodiment improves the display quality by offsetting and overlapping the orthogonal projections of at least one conductive line in each of the N conductive layers extending along a first direction with the portions of at least one conductive line in the remaining conductive layers extending along the first direction in a second direction.

[0084] In some exemplary embodiments, the substrate may be a flexible substrate or a rigid substrate, such as a glass substrate, and this disclosure does not limit it.

[0085] In one exemplary embodiment, the orthographic projections of a conductive line located in the nth conductive layer overlap with those of a conductive line located in the (n-1)th conductive layer and a conductive line located in the (n+1)th conductive layer on the substrate. However, the orthographic projections of the conductive line located in the (n-1)th conductive layer and the conductive line located in the (n+1)th conductive layer do not overlap. Here, n is an integer greater than or equal to 2 and less than or equal to N-1. In some examples, N can be 3 and n can be 2. The orthographic projections of a conductive line located in the second conductive layer overlap with those of a conductive line located in the first conductive layer and a conductive line located in the third conductive layer on the substrate. However, the orthographic projections of the conductive line located in the first conductive layer and the conductive line located in the third conductive layer may not overlap.

[0086] In an exemplary embodiment, the overlap length of the orthographic projections of the conductive line located in the nth conductive layer and the conductive line located in the (n-1)th conductive layer onto the substrate along the second direction is equal to the overlap length of the orthographic projections of the conductive line located in the nth conductive layer and the conductive line located in the (n+1)th conductive layer onto the substrate along the second direction.

[0087] In an exemplary embodiment, the overlap length of the orthographic projection of the conductive line located in the nth conductive layer and the conductive line located in the (n-1)th conductive layer onto the substrate along the second direction is k1× Where k1 is the first process parameter, W is the line width parameter, and S is the line spacing parameter.

[0088] In one exemplary embodiment, k1 is 0.7 to 1.3.

[0089] In one exemplary embodiment, the orthographic projections of a conductive line located in the m-th conductive layer overlap with those of a conductive line located in the (m-1)-th and (m-2)-th conductive layers on the substrate, but the orthographic projections of the conductive line located in the (m-1)-th and (m-2)-th conductive layers do not overlap. Here, m is an integer greater than or equal to 3 and less than or equal to N. In some examples, N can be 3, and m can be 3. The orthographic projections of a conductive line located in the third conductive layer overlap with those of a conductive line located in the first and second conductive layers on the substrate, but the orthographic projections of the conductive line located in the first and second conductive layers may not overlap.

[0090] In an exemplary embodiment, the overlap length of the orthographic projection of the conductive line located in the m-th conductive layer and the conductive line located in the (m-1)-th conductive layer onto the substrate along the second direction is less than the overlap length of the orthographic projection of the conductive line located in the m-th conductive layer and the conductive line located in the (m-2)-th conductive layer onto the substrate along the second direction.

[0091] In an exemplary embodiment, the overlap length of the orthographic projection of the conductive line located in the m-th conductive layer and the conductive line located in the (m-1)-th conductive layer onto the substrate along the second direction is equal to half the overlap length of the orthographic projection of the conductive line located in the m-th conductive layer and the conductive line located in the (m-2)-th conductive layer onto the substrate along the second direction.

[0092] In an exemplary embodiment, the overlap length of the conductive line located in the m-th conductive layer and the conductive line located in the (m-1)-th conductive layer on the substrate along the second direction is k2×(W-12S), where k2 is the second process parameter, W is the line width parameter, and S is the line spacing parameter.

[0093] In one exemplary embodiment, k2 is 0.7 to 1.3.

[0094] In one exemplary embodiment, k2 is equal to k1.

[0095] In one exemplary embodiment, the line widths of multiple conductive lines within at least one conductive layer are equal, and the spacing between adjacent conductive lines is equal.

[0096] In one exemplary embodiment, the linewidth of multiple conductive lines within at least one conductive layer is equal to the line spacing between adjacent conductive lines.

[0097] In one exemplary embodiment, the linewidths of the conductive lines in different conductive layers are equal, and the spacing between adjacent conductive lines in different conductive layers is equal.

[0098] In an exemplary embodiment, the overlap length of the conductive line located in the m-th conductive layer and the conductive line located in the (m-1)-th conductive layer along the second direction on the substrate is denoted as O. m-1 Let O be the overlap length of the orthographic projection of the conductive line located in the m-th conductive layer and the conductive line located in the (m-2)-th conductive layer onto the substrate along the second direction. m And so on, where m is an integer greater than or equal to 3 and less than or equal to N, then O1 + O2 + ... + O m = (m-1)WS. Where W is the linewidth of the conductive lines located in different conductive layers and whose orthogonal projections on the substrate overlap, and S is the line spacing of the conductive lines located in different conductive layers and whose orthogonal projections on the substrate overlap. The linewidths and line spacings of the conductive lines located in different conductive layers and whose orthogonal projections on the substrate overlap are equal.

[0099] Figure 6 This is a partial top view of the display panel according to an embodiment of the present disclosure. Figure 7 for Figure 6 A cross-sectional view of the display panel along the BB direction. (See diagram below.) Figure 6 and Figure 7 As shown, the technical solution is illustrated using a display panel comprising three conductive layers as an example. Along the direction away from the substrate, the three conductive layers may include a first conductive layer, a second conductive layer, and a third conductive layer sequentially disposed along the direction away from the substrate.

[0100] like Figure 6 and Figure 7 As shown, the first conductive layer includes at least one first conductive line 111 extending along a first direction D1. The second conductive layer may include at least one second conductive line 112 extending along the first direction D1. The third conductive layer may include at least one third conductive line 113 extending along the first direction D1. In this embodiment of the present disclosure, the first direction D1 may be parallel to the Y direction.

[0101] In one exemplary embodiment, such as Figure 6 and Figure 7 As shown, the three conductive layers may include multiple spaced-apart wire groups 10a. Each wire group 10a may include three conductive lines located in different conductive layers. Along the thickness direction (Z-direction) of the display panel, each wire group 10a may include a first conductive line 111, a second conductive line 112, and a third conductive line 113 stacked sequentially. The three conductive lines within a wire group 10a are staggered sequentially along the second direction D2.

[0102] In one exemplary embodiment, such as Figure 6 As shown, the portion of at least one conductive line in each conductive layer extending along the first direction D1 and the portion of at least one conductive line in the remaining conductive layers extending along the first direction D1 are misaligned and overlapped in the second direction D2 when projected onto the substrate. In this embodiment, the second direction D2 may be parallel to the X direction.

[0103] like Figure 6 As shown, the portions of the first conductive line 111 extending along the first direction and the portions of the second conductive line 112 extending along the first direction within the same conductive line group 10a overlap in the second direction when projected onto the substrate. This overlap is denoted as the first overlap 121, indicating overlapping traces. Similarly, the portions of the second conductive line 112 extending along the first direction and the portions of the third conductive line 113 extending along the first direction within the same conductive line group 10a overlap in the second direction when projected onto the substrate. This overlap is denoted as the second overlap 122, indicating overlapping traces. Figure 6 As shown, there is a misalignment along the second direction between the first overlap 121 and the second overlap 122, that is, the first overlap 121 and the second overlap 122 do not intersect.

[0104] In one exemplary embodiment, such as Figure 6 As shown, the portion of the third conductive line 113 of conductor group 10a extending in the first direction overlaps with the portion of the first conductive line 111 of another adjacent conductor group 10a extending in the first direction in the orthographic projection onto the substrate in the second direction. This overlap is denoted as the third overlap 123, indicating overlapping traces. The portion of the second conductive line 112, located in the same conductor group 10a as the third conductive line 113, extending in the first direction in the orthographic projection onto the substrate does not overlap with the portion of the first conductive line 111 of another adjacent conductor group 10a extending in the first direction in the orthographic projection onto the substrate in the second direction. Figure 7 As shown.

[0105] In an exemplary embodiment, the first conductive line 111, the second conductive line 112, and the third conductive line 113 may all be made of a transparent conductive material. For example, the transparent conductive material may be a conductive oxide material, such as indium tin oxide (ITO), but this disclosure is not limited thereto.

[0106] In one exemplary embodiment, the thickness of the first conductive layer may be set to less than 0.1 micrometers. The thickness of the second conductive layer may be set to less than 0.1 micrometers. The thickness of the third conductive layer may be set to less than 0.1 micrometers.

[0107] In one exemplary embodiment, such as Figure 7 As shown, only two conductor groups 10a are illustrated as an example. In this embodiment, the length of the first overlap 121 is denoted as O1, the length of the second overlap 122 is denoted as O2, and the length of the third overlap 123 is denoted as O3. For example, O1, O2, and O3 may each be different.

[0108] In one exemplary embodiment, such as Figure 7 As shown, O1 can be equal to O2.

[0109] In one exemplary embodiment, such as Figure 7 As shown, O3 can be greater than O1 and greater than O2. For example, O1 can be equal to O2, and O3 can be equal to 2O1.

[0110] In one exemplary embodiment, such as Figure 7 As shown, the linewidth of the first conductive line 111 is denoted as W1, the spacing between two adjacent first conductive lines 111 within the first conductive layer is denoted as S1, and the occupied width of the first conductive line 111 within the first conductive layer is denoted as P1. P1 is equal to the sum of W1 and S1. The linewidth of the second conductive line 112 is denoted as W2, the spacing between two adjacent second conductive lines 112 within the second conductive layer is denoted as S2, and the occupied width of the second conductive line 112 within the second conductive layer is denoted as P2. P2 is equal to the sum of W2 and S2. The linewidth of the third conductive line 113 is denoted as W3, the spacing between two adjacent third conductive lines 113 within the third conductive layer is denoted as S3, and the occupied width of the third conductive line 113 within the third conductive layer is denoted as P3. P3 is equal to the sum of W3 and S3. For example, P1, P2, and P3 are equal.

[0111] In an exemplary embodiment, the linewidth W1 and line spacing S1 of the first conductive line 111 can be determined according to actual process capabilities, and this disclosure does not limit this. Generally, S1 is less than 2W1, depending on conventional process capabilities and design requirements. For example, the linewidth W2 and line spacing S2 of the second conductive line 112 can be set with reference to the linewidth W1 and line spacing S1 of the first conductive line 111. For example, W2 and W3 can be set to be the same as W1, and both are denoted as W, where W is also called the linewidth parameter. S2 and S3 can be set to be the same as S1, and both are denoted as S, where S is also called the line spacing parameter. Setting the linewidth and line spacing of the first conductive line 111, the second conductive line 112, and the third conductive line 113 to be the same can reduce the complexity of the conductive line manufacturing process and lower the manufacturing cost of the display panel.

[0112] In one exemplary embodiment, such as Figure 7 As shown, the display panel may further include a first insulating layer 131 located on the side of the first conductive layer away from the substrate. The first insulating layer 131 may be located between the first conductive layer and the second conductive layer. The orthographic projection of the first insulating layer 131 onto the substrate covers the orthographic projection of the portion of the first conductive line 111 extending along the first direction onto the substrate, thereby preventing signal crosstalk between the first conductive line 111 and the second conductive line 112. Figure 7 As shown, the thickness of the first insulating layer 131 is denoted as D1.

[0113] In an exemplary embodiment, the thickness of the first insulating layer 131 may be set from 1.0 micrometer to 3.0 micrometer.

[0114] In an exemplary embodiment, the thickness of the first conductive layer may be less than the thickness of the first insulating layer 131.

[0115] In one exemplary embodiment, the first insulating layer 131 may be made of an inorganic material. The inorganic material may include silicon oxynitride (SiO2). x N y It can be any one or more of the following: silicon nitride (SiN), silicon oxide (SiO), silicon dioxide (SiO2), aluminum oxide (Al2O3), titanium dioxide (TiO2), and niobium pentoxide (Nb2O5).

[0116] In an exemplary embodiment, the first insulating layer 131 may be made of an organic material. The organic material may include one or a mixture of polymers such as polyimide (PI), polyacrylate, polyphenylene sulfide, polyarylate, cellulose acetate propionate, polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyethersulfone resin (PES), polycarbonate (PC), polyetherimide (PEI), cyclic olefin polymer (COP), silicone resin, polyaryl compound (PAR), or glass fiber reinforced plastic (FRP).

[0117] In an exemplary embodiment, the first insulating layer 131 may be configured as a single-layer film or a composite film, etc.

[0118] In one exemplary embodiment, such as Figure 7 As shown, the display panel may further include a second insulating layer 132 located on the side of the second conductive layer away from the substrate. The second insulating layer 132 may be located between the second conductive layer and the third conductive layer. The orthographic projection of the second insulating layer 132 onto the substrate covers the orthographic projection of the portion of the second conductive line 112 extending along the first direction onto the substrate, thereby preventing signal crosstalk between the second conductive line 112 and the third conductive line 113. Figure 7 As shown, the thickness of the second insulating layer 132 is denoted as D2. Figure 7 As shown, the thickness of the insulating layer between the first conductive layer and the third conductive layer is denoted as D3. For example, D2 can be equal to D1, and both can be denoted as D. D3 can be equal to the sum of D1 and D2, that is, D3 can be equal to 2D.

[0119] In an exemplary embodiment, the thickness and material of the second insulating layer 132 may be set with reference to the first insulating layer 131, and this disclosure does not limit it.

[0120] In an exemplary embodiment, the thicknesses of the first insulating layer 131 and the second insulating layer 132 may be different.

[0121] In an exemplary embodiment, the thickness of the second conductive layer may be less than the thickness of the second insulating layer 132.

[0122] In one exemplary embodiment, the thickness of the conductive layer is less than the thickness of the adjacent insulating layer. The adjacent insulating layer may be located on the side of the conductive layer closer to the substrate or on the side of the conductive layer farther from the substrate.

[0123] In one exemplary embodiment, such as Figure 7 As shown, in a direction perpendicular to the display panel, the display panel may include: a substrate 300, a circuit structure layer 400 disposed on one side of the substrate 300, a first conductive layer, a second conductive layer, a third conductive layer, and a light-emitting structure layer. The circuit structure layer 400 may include multiple pixel driving circuits. A first insulating layer 131 may be disposed between the first conductive layer and the second conductive layer, and a second insulating layer 132 may be disposed between the second conductive layer and the third conductive layer. A third insulating layer may be disposed between the third conductive layer and the light-emitting structure layer. The light-emitting structure layer may include: an anode layer, a pixel definition layer, an organic light-emitting layer, and a cathode layer.

[0124] In an exemplary embodiment, the coupling capacitance between the first conductive line 111 in the first conductive layer and the second conductive line 112 in the second conductive layer and the third conductive line 113 in the third conductive layer can be denoted as C1; the coupling capacitance between the second conductive line 112 in the second conductive layer and the first conductive line 111 in the first conductive layer and the third conductive line 113 in the third conductive layer can be denoted as C2; and the coupling capacitance between the third conductive line 113 in the third conductive layer and the first conductive line 111 in the first conductive layer and the second conductive line 112 in the second conductive layer can be denoted as C3. The relevant parameters can satisfy the following formulas: P1 = W1 + S1, P2 = W2 + S2, P3 = W3 + S3.

[0125] Let W1 = W2 = W3, and denote them all as W. S1 = S2 = S3, and denote them all as S, and W1 + W2 + W3 - O1 - O2 - O3 = P1 = W1 + S1, that is, 3W - O1 - O2 - O3 = W + S.

[0126] Based on the above relationship, formula (1) can be derived:

[0127] 2W-S=O1+O2+O3 (1)

[0128] Normally, if the first insulating layer 131 and the second insulating layer 132 are prepared using the same materials and the same process conditions, then the dielectric constant of the interlayer capacitance will be the same. Assuming that the thicknesses of the first insulating layer 131 and the second insulating layer 132 are the same, that is: D1 = D2, D3 = D1 + D2 = 2D1.

[0129] To make C1 = C2 = C3, the following equation (2) must be satisfied:

[0130]

[0131] Based on D1 = D2 and D3 = D1 + D2 = 2D1, we can derive formula (3):

[0132] O1 = O2, O3 = 2O1 (3)

[0133] Substituting equation (3) into equation (1) yields:

[0134] O1=O2=1 / 2W-1 / 4S, O3=2O1=W-1 / 2S.

[0135] In the aforementioned derivation process, D1 = D2 and D3 = D1 + D2 = 2D1 is only one application scenario in actual application. According to the actual structural design needs of the display panel, the numerical relationship between D1, D2 and D3 can be any combination. O1, O2 and O3 can be calculated by combining the aforementioned formula (2). This disclosure does not limit this.

[0136] Taking a certain display panel as an example, given that P1 is 3.8 micrometers, W1 and S1 are both 1.9 micrometers, then O1 is 0.475 micrometers, O2 is 0.475 micrometers, and O3 is 0.95 micrometers, meaning O3 equals 2O1. Since the thickness and manufacturing process of the first insulating layer 131 and the second insulating layer 132 are the same, based on the above relationship between O1, O2, and O3, it can be concluded that C1, C2, and C3 are all equal.

[0137] Taking another display panel as an example, given that P1 is 3.8 micrometers, W1 is 2.0 micrometers, and S1 is 1.8 micrometers, then O1 is 0.55 micrometers, O2 is 0.55 micrometers, and O3 is 1.1 micrometers, meaning O3 equals 2O1. Since the thickness and manufacturing process of the first insulating layer 131 and the second insulating layer 132 are the same, based on the aforementioned relationship between O1, O2, and O3, it can still be concluded that C1, C2, and C3 are all equal.

[0138] In an exemplary embodiment, O1, O2, and O3 obtained from the above calculations are their respective theoretical values, which can be multiplied by process parameters to obtain their actual values. For example, Wherein, k2 is the second process parameter, and k2 ranges from 0.7 to 1.3. W is the line width parameter, and S is the line spacing parameter. The actual values ​​are used to guide the actual production of the display panel. Since the actual values ​​fully consider the processing accuracy and dimensional fluctuations of the display panel in the actual production process based on the theoretical values, the product design is more reasonable, which helps to reduce the manufacturing cost of the display panel.

[0139] The structure of a display panel is illustrated below using an example of the fabrication process. The "patterning process" described in this disclosure, for metallic, inorganic, or transparent conductive materials, includes processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film of a certain material fabricated on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. A "layer" after the patterning process contains at least one "pattern."

[0140] The manufacturing process of a display panel may include the following steps:

[0141] (1) Provide a substrate.

[0142] (2) Forming a semiconductor layer.

[0143] A semiconductor thin film is deposited on a substrate, and then patterned using a patterning process to form a semiconductor layer.

[0144] (3) Form the first gate metal layer.

[0145] On the substrate forming the aforementioned structure, a first insulating film and a first metal film are sequentially deposited. The first metal film is patterned using a patterning process to form a first insulating layer covering the semiconductor layer and a first gate metal layer disposed on the first insulating layer.

[0146] (4) Form a second gate metal layer.

[0147] On the substrate forming the aforementioned structure, a second insulating film and a second metal film are sequentially deposited. The second metal film is patterned using a patterning process to form a second insulating layer covering the first gate metal layer, and a second gate metal layer disposed on the second insulating layer.

[0148] (5) Form the third insulating layer and the first source / drain metal layer.

[0149] On the substrate with the aforementioned structure, a third insulating film is deposited, and a third insulating layer is formed by a patterning process. The third insulating layer has multiple pixel vias. Subsequently, a third metal film is deposited, and the third metal film is patterned by a patterning process to form a first source / drain metal layer disposed on the third insulating layer.

[0150] (6) Form a second source / drain metal layer.

[0151] On the substrate forming the aforementioned structure, a fourth insulating film and a fourth metal film are sequentially deposited. The fourth metal film is patterned using a patterning process to form a fourth insulating layer covering the first source / drain metal layer, and a second source / drain metal layer disposed on the fourth insulating layer.

[0152] In some exemplary embodiments, a fifth insulating film is coated on the substrate on which the aforementioned structure is formed, and the fifth insulating layer is formed by a patterning process.

[0153] (7) Form the first conductive layer.

[0154] A first transparent conductive film is deposited on the substrate forming the aforementioned structure, and the first transparent conductive film is patterned by a patterning process to form a first conductive layer disposed on the fifth insulating layer.

[0155] (8) Form the sixth insulating layer and the second conductive layer.

[0156] On the substrate forming the aforementioned structure, a sixth insulating film is coated, and a sixth insulating layer (i.e., the aforementioned first insulating layer 131) is formed by a patterning process. Subsequently, a second transparent conductive film is deposited, and the second transparent conductive film is patterned by a patterning process to form a second conductive layer disposed on the sixth insulating layer.

[0157] (9) Form the seventh insulating layer and the third conductive layer.

[0158] On the substrate with the aforementioned structure, a seventh insulating film is coated, and a seventh insulating layer (i.e., the aforementioned second insulating layer 132) is formed by a patterning process. Subsequently, a third transparent conductive film is deposited, and the third transparent conductive film is patterned by a patterning process to form a third conductive layer disposed on the seventh insulating layer.

[0159] (10) Forming a light-emitting structural layer.

[0160] On the substrate forming the aforementioned structure, an eighth insulating film is coated, and an eighth insulating layer is formed through a patterning process. Subsequently, an anode conductive film is deposited, and the anode conductive film is patterned through a patterning process to form an anode layer disposed on the eighth insulating layer. Next, a pixel definition film is coated on the substrate with the aforementioned pattern, and a pixel definition layer (PDL) is formed through a masking, exposure, and development process. The pixel definition layer has multiple pixel openings exposing the anode layer. An organic light-emitting layer is formed within the aforementioned pixel openings, and the organic light-emitting layer is connected to the anode. Subsequently, a cathode film is deposited, and the cathode film is patterned through a patterning process to form a cathode pattern. Finally, an encapsulation layer is formed on the cathode.

[0161] This disclosure provides a method for fabricating a display panel. This method is applied to fabricating a display panel according to any of the above embodiments. The method includes: sequentially forming N conductive layers on one side of a substrate. Each of the N conductive layers includes at least one conductive line extending along a first direction, where N is an integer greater than or equal to 3. The portion of at least one conductive line in each conductive layer extending along the first direction overlaps with the portion of at least one conductive line in the remaining conductive layers extending along the first direction, whose projections onto the substrate are misaligned in a second direction and intersect.

[0162] This disclosure also provides a display device, including the display panel of any of the foregoing embodiments. In some examples, the display panel may include an OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display device may be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. However, this embodiment is not limited thereto.

[0163] While the embodiments disclosed in this invention are as described above, the content is merely for the purpose of facilitating understanding of the invention and is not intended to limit the invention. Any person skilled in the art to which this invention pertains may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this invention shall still be determined by the scope defined in the appended claims.

Claims

1. A display panel, characterized by, The display panel comprises: a substrate; N conductive layers arranged on the substrate in sequence in a direction away from the substrate, each of the N conductive layers comprising at least one conductive line extending in a first direction, N being an integer greater than or equal to 3; a portion of the at least one conductive line in each of the conductive layers extending in the first direction and a portion of the at least one conductive line in each of the remaining conductive layers extending in the first direction are misaligned in a second direction and overlap in a projection of the substrate on a plane, the second direction intersecting the first direction; The overlapped length of the strip conductive line located at the n-th conductive layer and the strip conductive line located at the (n-1)-th conductive layer in the orthographic projection of the substrate along the second direction is k1x(W+S) ), wherein k1 is a first process parameter, W is a line width parameter, and S is a line spacing parameter.

2. The display panel of claim 1, wherein, a projection of one conductive line in an nth conductive layer and one conductive line in an (n-1)th conductive layer and one conductive line in an (n+1)th conductive layer on the substrate overlap, a projection of the one conductive line in the (n-1)th conductive layer and the one conductive line in the (n+1)th conductive layer on the substrate do not overlap, wherein n is an integer greater than or equal to 2 and less than or equal to N-1.

3. The display panel of claim 2, wherein, an overlapping length of the projection of the one conductive line in the nth conductive layer and the one conductive line in the (n-1)th conductive layer on the substrate in the second direction is equal to an overlapping length of the projection of the one conductive line in the nth conductive layer and the one conductive line in the (n+1)th conductive layer on the substrate in the second direction.

4. The display panel of any one of claims 1-3, wherein, a projection of one conductive line in an mth conductive layer and one conductive line in an (m-1)th conductive layer and one conductive line in an (m-2)th conductive layer on the substrate overlap, a projection of the one conductive line in the (m-1)th conductive layer and the one conductive line in the (m-2)th conductive layer on the substrate do not overlap, wherein m is an integer greater than or equal to 3 and less than or equal to N.

5. The display panel of claim 4, wherein, an overlapping length of the projection of the one conductive line in the mth conductive layer and the one conductive line in the (m-1)th conductive layer on the substrate in the second direction is less than an overlapping length of the projection of the one conductive line in the mth conductive layer and the one conductive line in the (m-2)th conductive layer on the substrate in the second direction.

6. The display panel of claim 5, wherein, an overlapping length of the projection of the one conductive line in the mth conductive layer and the one conductive line in the (m-1)th conductive layer on the substrate in the second direction is equal to half of an overlapping length of the projection of the one conductive line in the mth conductive layer and the one conductive line in the (m-2)th conductive layer on the substrate in the second direction.

7. The display panel of claim 6, wherein, The overlapping length of the strip of conductive lines located at the mth conductive layer and the strip of conductive lines located at the (m-1)th conductive layer in the orthographic projection of the substrate along the second direction is k2×(W- ); wherein k2 is a second process parameter, W is a line width parameter, and S is a line spacing parameter.

8. The display panel of any of claims 1-3, wherein, line widths of the plurality of conductive lines in at least one conductive layer are equal, and line-to-line spacings of adjacent conductive lines are equal.

9. The display panel of claim 8, wherein, line widths of the plurality of conductive lines in at least one conductive layer are equal, and line-to-line spacings of adjacent conductive lines are equal.

10. The display panel of claim 8, wherein, line widths of the plurality of conductive lines in different conductive layers are equal, and line-to-line spacings of adjacent conductive lines in different conductive layers are equal.

11. The display panel of any of claims 1-3, wherein, the display panel further comprises insulating layers between adjacent two of the conductive layers, thicknesses of the plurality of insulating layers are equal.

12. The display panel of claim 11, wherein, thicknesses of the conductive layers are less than thicknesses of the insulating layers adjacent to the conductive layers.

13. The display panel of any of claims 1-3, wherein, the display panel comprises a display area; the display area comprises a first region and a second region; the first region and the second region do not overlap in a projection of the substrate on a plane. The display panel further comprises a circuit structure layer and a light emitting structure layer disposed on the substrate, the light emitting structure layer is located on a side of the circuit structure layer away from the substrate, and the N conductive layers are located between the circuit structure layer and the light emitting structure layer; the circuit structure layer comprises a plurality of first pixel driving circuits and a plurality of second pixel driving circuits located in the first region, and the light emitting structure layer comprises a plurality of first light emitting devices located in the first region and a plurality of second light emitting devices located in the second region; At least one first pixel driving circuit in the plurality of first pixel driving circuits is electrically connected with at least one first light emitting device in the plurality of first light emitting devices, and at least one second pixel driving circuit in the plurality of second pixel driving circuits is electrically connected with at least one second light emitting device in the plurality of second light emitting devices through at least one conductive line in the N conductive layers.

14. The display panel of claim 1, wherein, N is 3; The orthographic projection of one conductive line located in the second conductive layer on the substrate overlaps with the orthographic projection of one conductive line located in the first conductive layer and the orthographic projection of one conductive line located in the third conductive layer, the orthographic projection of the conductive line located in the first conductive layer on the substrate does not overlap with the orthographic projection of the conductive line located in the third conductive layer, the orthographic projection of the conductive line located in the third conductive layer on the substrate overlaps with the orthographic projection of another conductive line located in the first conductive layer, and the conductive line located in the first conductive layer and the another conductive line are adjacent in the second direction.

15. The display panel of claim 14, wherein, The overlapping length of the orthographic projection of the conductive line located in the second conductive layer on the substrate along the second direction with the orthographic projection of the conductive line located in the first conductive layer is equal to the overlapping length of the orthographic projection of the conductive line located in the second conductive layer on the substrate along the second direction with the orthographic projection of the conductive line located in the third conductive layer. The overlapping length of the orthographic projection of the conductive line located in the third conductive layer on the substrate along the second direction with the another conductive line located in the first conductive layer is twice the overlapping length of the orthographic projection of the conductive line located in the second conductive layer on the substrate along the second direction with the conductive line located in the first conductive layer.

16. The display panel of claim 14, wherein, The overlapping length of the orthographic projection of the conductive line located in the second conductive layer on the substrate along the second direction with the conductive line located in the first conductive layer is denoted as O1, the overlapping length of the orthographic projection of the conductive line located in the second conductive layer on the substrate along the second direction with the conductive line located in the third conductive layer is denoted as O2, the overlapping length of the orthographic projection of the conductive line located in the third conductive layer on the substrate along the second direction with the another conductive line located in the first conductive layer is denoted as O3, the thickness of the insulating layer between the first conductive layer and the second conductive layer is denoted as D1, the thickness of the insulating layer between the second conductive layer and the third conductive layer is denoted as D2, and the thickness of the insulating layer between the first conductive layer and the third conductive layer is denoted as D3; O1, O2, O3, D1, D2 and D3 satisfy the following formula: 。 17. A display device comprising: The display panel comprises the display panel according to any one of claims 1 to 16.

18. A method for manufacturing a display panel, characterized by, A method for manufacturing a display panel as claimed in any one of claims 1 to 16, the manufacturing method comprising: forming N conductive layers on one side of a substrate in sequence; wherein each of the N conductive layers comprises at least one conductive line extending along a first direction, and N is an integer greater than or equal to 3; the portion of the at least one conductive line in each conductive layer extending along the first direction and the portion of the at least one conductive line in the remaining conductive layers extending along the first direction are offset in a second direction and overlap in orthographic projection on the substrate, the second direction being transverse to the first direction.

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