Light emitting element, method for manufacturing light emitting element, and display device

Abstract

A light emitting device, a manufacturing method therefor, and a display apparatus are provided. The light emitting device includes a light emitting device core including a first semiconductor layer, a second semiconductor layer disposed on the first semiconductor layer, and a device active layer disposed between the first semiconductor layer and the second semiconductor layer; a first insulating film formed on a side surface of the light emitting device core to surround the side surface of the light emitting device core and having a first fixed charge; and a second insulating film disposed to surround an outer side surface of the first insulating film and including a material having a second fixed charge different from the first fixed charge.

Description

[0001] This application claims priority to and all the benefits of Korean Patent Application No. 10-2020-0113657, filed on September 7, 2020, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0002] The present disclosure relates to a light emitting element, a method of manufacturing a light emitting element, and a display device. BACKGROUND

[0003] With the development of multimedia, display devices have become increasingly important, and various types of display devices, such as organic light emitting diode (OLED) display devices, liquid crystal display (LCD) devices, etc., have been used.

[0004] A display device, which is a device for displaying an image, includes a display panel such as an OLED display panel or an LCD panel. The display panel can include a light emitting element such as a light emitting diode (LED), and the LED can be classified into an OLED using an organic material as a light emitting material and an inorganic LED using an inorganic material as a light emitting material. SUMMARY

[0005] TECHNICAL PROBLEM

[0006] Aspects of the present disclosure provide a light emitting element including a first insulating layer and a second insulating layer having different fixed charges from each other on side surfaces of a first semiconductor layer, an element active layer, and a second semiconductor layer of the light emitting element.

[0007] Aspects of the present disclosure also provide a display device including the light emitting element.

[0008] Aspects of the present disclosure also provide a method of manufacturing a light emitting element having improved film characteristics by forming a first insulating layer using a plasma enhanced atomic layer deposition method.

[0009] It should be noted that the disclosed aspects are not limited to this, and other aspects not mentioned here will be apparent to those of ordinary skill in the art in light of the following description.

[0010] TECHNICAL SOLUTION

[0011] According to the disclosed embodiment, a light emitting element includes: a light emitting element core including a first semiconductor layer, a second semiconductor layer disposed on the first semiconductor layer, and an element active layer disposed between the first semiconductor layer and the second semiconductor layer; a first insulating layer formed on a side surface of the light emitting element core to surround the side surface of the light emitting element core and having a first fixed charge; and a second insulating layer disposed to surround an outer surface of the first insulating layer and including a material having a second fixed charge different from the first fixed charge.

[0012] The polarity of the first fixed charge is the same as the polarity of the second fixed charge.

[0013] Each of the first fixed charge and the second fixed charge is a positive fixed charge, and the magnitude of the first fixed charge is smaller than the magnitude of the second fixed charge.

[0014] Each of the first fixed charge and the second fixed charge is a negative fixed charge, and the magnitude of the first fixed charge is greater than the magnitude of the second fixed charge.

[0015] The polarity of the first fixed charge is different from the polarity of the second fixed charge.

[0016] The first fixed charge is a negative fixed charge, and the second fixed charge is a positive fixed charge.

[0017] The first insulating layer includes at least one of silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN), aluminum oxide (Al x O y ), hafnium oxide (HfO x ), and zirconium oxide (ZrO x ), and the second insulating layer includes at least one of silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN), and aluminum oxide (Al x O y ).

[0018] The first insulating layer includes silicon oxide (SiO x ), and the second insulating layer includes aluminum oxide (Al x O y ).

[0019] The first fixed charge of silicon oxide (SiO x ) and the second fixed charge of aluminum oxide (Al x O yeach of the second fixed charges is a positive fixed charge, and the first fixed charge is smaller in size than the second fixed charge.

[0020] The first fixed charge of the silicon oxide (SiO x The first fixed charge of the silicon oxide (SiO x O y The second fixed charge of the aluminum oxide (Al

[0021] The first insulating layer is directly disposed on side surfaces of the first semiconductor layer, the second semiconductor layer, and the element active layer.

[0022] According to the disclosed embodiments, a display device includes: a substrate; a first electrode disposed on the substrate; a second electrode disposed on the substrate and spaced apart from the first electrode; and a light emitting element disposed on the substrate and having both ends disposed on the first electrode and the second electrode, respectively; wherein the light emitting element includes: a light emitting element core including a first semiconductor layer, a second semiconductor layer disposed on the first semiconductor layer, and an element active layer disposed between the first semiconductor layer and the second semiconductor layer; a first insulating layer formed on side surfaces of the light emitting element core to surround the side surfaces of the light emitting element core and having a first fixed charge; and a second insulating layer disposed to surround an outer surface of the first insulating layer and including a material having a second fixed charge different from the first fixed charge.

[0023] The first fixed charge has the same polarity as the second fixed charge.

[0024] Each of the first fixed charge and the second fixed charge is a positive fixed charge, and the first fixed charge is smaller in size than the second fixed charge.

[0025] Each of the first fixed charge and the second fixed charge is a negative fixed charge, and the first fixed charge is larger in size than the second fixed charge.

[0026] The first fixed charge has a different polarity from the second fixed charge.

[0027] The first fixed charge is a negative fixed charge, and the second fixed charge is a positive fixed charge.

[0028] The display device further includes: a third insulating layer disposed on the light emitting element to expose both ends of the light emitting element; a first contact electrode disposed on the first electrode and in contact with one end of the light emitting element exposed by the first electrode and the third insulating layer; and a second contact electrode disposed on the second electrode and in contact with the other end of the light emitting element exposed by the second electrode and the third insulating layer.

[0029] The thickness of the second insulating layer exposed by the third insulating layer is smaller than the thickness of the second insulating layer not exposed by the third insulating layer.

[0030] The second insulating layer exposes a portion of the first insulating layer at both ends of the light emitting element.

[0031] According to the disclosed embodiment, a method of manufacturing a light emitting element includes the steps of forming a core structure on one surface of a bulk substrate; forming a first insulating material layer on an outer surface of the core structure using plasma atomic layer deposition (PEALD), the first insulating material layer including a material having a first fixed charge; forming a second insulating material layer on one surface of the first insulating material layer, the second insulating material layer including a material having a second fixed charge different from the first fixed charge; forming an element rod by partially removing the first insulating material layer and the second insulating material layer to expose a top surface of the core structure; and separating the element rod from the bulk substrate.

[0032] The step of forming the first insulating material layer includes providing a precursor onto the core structure; providing a reactive gas onto the core structure; and generating a plasma of the reactive gas on the core structure.

[0033] The first insulating material layer includes silicon oxide (SiO x ), the second insulating material layer includes aluminum oxide (Al x O y ), the precursor includes a silicon-containing precursor, and the reactive gas includes oxygen.

[0034] The step of forming the core structure includes forming a first stack structure including a first semiconductor material layer on a bulk substrate, an element active material layer on the first semiconductor material layer, and a second semiconductor material layer on the element active material layer; and vertically etching the first stack structure in a direction perpendicular to a top surface of the bulk substrate.

[0035] Details of other embodiments are included in the detailed description and the accompanying drawings.

[0036] Advantageous effects

[0037] According to the light emitting element according to one embodiment, since the first insulating layer and the second insulating layer of the light emitting element include materials having fixed charges different from each other, it is possible to improve the luminance deterioration of the light emitting element. In addition, since the second insulating layer including a material having a fixed charge different from the fixed charge of the material of the first insulating layer is disposed to surround the first insulating layer, the second insulating layer can protect the first insulating layer, and thus it is possible to provide a light emitting element having high reliability.

[0038] In addition, according to the method of manufacturing a light emitting element according to an embodiment, a deposition process for forming a first insulating layer of a light emitting element can be performed using plasma-enhanced atomic layer deposition (PEALD). The first insulating layer formed by plasma-enhanced atomic layer deposition (PEALD) can have improved film properties compared to the first insulating layer formed by thermal atomic layer deposition (thermal ALD). Accordingly, by forming the first insulating layer using plasma-enhanced atomic layer deposition (PEALD), a light emitting element having high reliability can be provided.

[0039] Effects according to embodiments are not limited to what has been exemplified above, and more various effects are included in the disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0040] Figure 1 is a plan view of a display device according to an embodiment.

[0041] Figure 2 is a schematic plan view of one pixel of a display device according to an embodiment.

[0042] Figure 3 is a cross-sectional view taken along lines Qa-Qa', Qb-Qb', and Qc-Qc' of Figure 2 .

[0043] Figure 4 is a schematic perspective view of a light emitting element according to an embodiment.

[0044] Figure 5 is a cross-sectional view taken along line V-V' of Figure 4 .

[0045] Figure 6 is an enlarged view showing an example of portion Q of Figure 3 .

[0046] Figure 7 is a flowchart showing a method of manufacturing a light emitting element according to an embodiment.

[0047] Figures 8 to 14 is a cross-sectional view showing a manufacturing process of a light emitting element according to an embodiment.

[0048] Figure 15 is a graph comparing light emitting characteristics of light emitting elements according to first insulating layers formed by plasma-enhanced atomic layer deposition (PEALD) and thermal atomic layer deposition (thermal ALD), respectively, when the first insulating layer includes silicon oxide (SiO x ).

[0049] Figure 16 is an enlarged view showing another example of portion Q of Figure 3 .

[0050] Figure 17 is an enlarged view of another example of the portion Q of Figure 3 .

[0051] Figure 18 is an enlarged view of another example of the portion Q of Figure 3 .

[0052] Figure 19 is a cross-sectional view of a light emitting element according to another embodiment.

[0053] Figure 20 is a cross-sectional view of a light emitting element according to another embodiment.

[0054] Figure 21 is a cross-sectional view of a light emitting element according to another embodiment. DETAILED DESCRIPTION

[0055] The advantages and features of the present disclosure and a method for achieving the same can be more readily understood through the following detailed description of the preferred embodiments and the accompanying drawings. However, the present disclosure is not limited to the embodiments disclosed herein but can be implemented in other forms. That is, the present disclosure will be defined only by the appended claims.

[0056] It will also be understood that when a layer is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers can also be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present.

[0057] Throughout the specification, like drawing reference numerals refer to like components.

[0058] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0059] Figure 1 is a plan view of a display device according to one embodiment.

[0060] Referring to Figure 1 , a display device 10 displays a moving image or a still image. The display device 10 can refer to any electronic device that provides a display screen. Examples of the display device 10 can include a television, a laptop computer, a monitor, a billboard, an Internet of Things device, a mobile phone, a smart phone, a tablet Personal Computer (PC), an electronic watch, a smart watch, a watch phone, a head-mounted display, a mobile communication terminal, an electronic notebook, an electronic book, a Portable Multimedia Player (PMP), a navigation device, a game machine, a digital camera, a camcorder, etc. that provide a display screen.

[0061] The display device 10 includes a display panel that provides a display screen. Examples of the display panel can include an inorganic light emitting diode display panel, an organic light emitting display panel, a quantum dot light emitting display panel, a plasma display panel, and a field emission display panel. In the following description, a case where an inorganic light emitting diode display panel is applied as the display panel will be exemplified, but the present disclosure is not limited thereto, and other display panels can be applied within the same technical spirit.

[0062] Hereinafter, a first direction DR1, a second direction DR2, and a third direction DR3 are defined in the drawings in which embodiments of the display device 10 are described. The first direction DR1 and the second direction DR2 can be directions perpendicular to each other in one plane. The third direction DR3 can be a direction perpendicular to the plane on which the first direction DR1 and the second direction DR2 are positioned. The third direction DR3 is perpendicular to each of the first direction DR1 and the second direction DR2. In describing embodiments of the display device 10, the third direction DR3 indicates a thickness direction of the display device 10.

[0063] The display device 10 can have a rectangular shape including a long side and a short side such that a side in the first direction DR1 is longer than a side in the second direction DR2 in a plan view. A corner portion where the long side and the short side of the display device 10 meet can be a right angle in a plan view. However, the present disclosure is not limited thereto, and it can be rounded to have a curved shape. The planar shape of the display device 10 is not limited to the example shown, and can be other shapes such as a square shape, a quadrilateral shape having rounded corners (vertices), other polygonal shapes, and a circular shape.

[0064] A display surface of the display device 10 can be provided on one side in the third direction DR3 that is a thickness direction. In describing embodiments of the display device 10, unless otherwise specified, the term "upward" refers to one side of the third direction DR3 that is a display direction, and the term "top surface" refers to a surface facing the one side of the third direction DR3. Also, the term "downward" refers to the other side of the third direction DR3 that is a direction opposite to the display direction, and the term "bottom surface" refers to a surface facing the other side of the third direction DR3. Also, "left", "right", "up", and "down" indicate directions when the display device 10 is viewed from above. For example, "right side" indicates one side in the first direction DR1, "left side" indicates the other side in the first direction DR1, "upper side" indicates one side in the second direction DR2, and "lower side" indicates the other side in the second direction DR2.

[0065] The display device 10 can include a display area DA and a non-display area NDA. The display area DA is an area capable of displaying a picture, and the non-display area NDA is an area that does not display a picture.

[0066] The shape of the display area DA can follow the shape of the display device 10. For example, the shape of the display area DA can have a rectangular shape similar to the overall shape of the display device 10 in a plan view. The display area DA can substantially occupy the center of the display device 10.

[0067] The display area DA can include a plurality of pixels PX. The plurality of pixels PX can be arranged in a matrix. In a plan view, the shape of each pixel PX can be a rectangular shape or a square shape. However, the shape of each pixel PX is not limited thereto, and can be a rhombic shape in which each side is inclined with respect to one direction. The pixels PX can be alternately arranged in a stripe type or a mosaic type. The display area DA can include a plurality of pixels PX. The plurality of pixels PX can be arranged in a matrix. In a plan view, the shape of each pixel PX can be a rectangular shape or a square shape. However, the shape of each pixel PX is not limited thereto, and can be a rhombic shape in which each side is inclined with respect to one direction. The pixels PX can be alternately arranged in a stripe type or a mosaic type.

[0068] The non-display area NDA can be disposed around the display area DA. The non-display area NDA can completely or partially surround the display area DA. In an exemplary embodiment, the display area DA can have a rectangular shape, and the non-display area NDA can be disposed adjacent to the four sides of the display area DA. The non-display area NDA can form a bezel of the display device 10. In the non-display area NDA, a wiring and a circuit driver belonging to the display device 10 or a pad (also referred to as a "land" or a "solder pad") portion on which an external device is mounted can be disposed.

[0069] Figure 2 is a schematic plan view of one pixel of a display device according to one embodiment.

[0070] Referring to Figure 2 , each pixel PX can include a plurality of sub-pixels SPX (SPX1, SPX2, and SPX3). For example, one pixel PX can include a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3. The first sub-pixel SPX1 can emit light of a first color, the second sub-pixel SPX2 can emit light of a second color, and the third sub-pixel SPX3 can emit light of a third color. The first color can be blue, the second color can be green, and the third color can be red. However, the disclosure is not limited thereto, and the sub-pixels SPX1, SPX2, and SPX3 can emit light of the same color. Figure 2 Although one pixel PX is shown to include three sub-pixels SPX1, SPX2, and SPX3, the disclosure is not limited thereto, and each pixel PX can include a greater number of sub-pixels SPX.

[0071] Each sub-pixel SPX of the display device 10 can include an emission area EMA and a non-emission area (not shown). The emission area EMA is an area that emits light emitted from a light emitting element ED, and the non-emission area is an area that does not emit light because light emitted from the light emitting element ED does not reach there.

[0072] The emission area EMA can include an area in which the light emitting element ED is disposed and an area adjacent thereto. The emission area EMA can also include an area in which light emitted from the light emitting element ED is reflected or refracted by another member and emitted.

[0073] Each sub-pixel SPX can also include a first area CBA disposed in the non-emission area. The first area CBA can be disposed at a side (e.g., an upper side in Figure 2

[0074] The emission areas EMA of the respective sub-pixels SPX included in one pixel PX can be arranged to be spaced apart from each other in the first direction DR1. Similarly, the first areas CBA of the respective sub-pixels SPX included in one pixel PX can be arranged to be spaced apart from each other in the first direction DR1. The emission areas EMA and the first areas CBA can each be arranged to be spaced apart from each other in the first direction DR1, and the emission areas EMA and the first areas CBA can be alternately arranged in the second direction DR2.

[0075] The first area CBA can be an area in which the electrodes 21 and 22 to be described later are separated from each other. Each of the sub-pixels SPX adjacent to each other in the second direction DR2 can include a first electrode 21 and a second electrode 22 extending in the second direction DR2. Each of the first electrode 21 and the second electrode 22 can be separated from a corresponding electrode of the first electrode 21 and the second electrode 22 in the other sub-pixel SPX in the first area CBA. Accordingly, a portion of the first electrode 21 and the second electrode 22 disposed in each sub-pixel SPX can be disposed in the first area CBA. The arrangement of the first electrode 21 and the second electrode 22 will be described in detail later.

[0076] Figure 3 is a cross-sectional view taken along lines Qa-Qa', Qb-Qb', and Qc-Qc' of Figure 2 .

[0077] Referring to Figure 3 , the display device 10 can include a first base 11, a circuit element layer CCL disposed on the first base 11, and a light emitting element layer disposed on the circuit element layer CCL. Hereinafter, the cross-sectional structure of the circuit element layer CCL of the display device 10 will be described with reference to Figure 3 .

[0078] ​The first substrate 11 can be an insulating substrate. The first substrate 11 can be made of an insulating material such as glass, quartz, or a polymer resin. Also, the first substrate 11 can be a rigid substrate, but can be a flexible substrate that can be bent, folded, or rolled.

[0079] A lower metal layer BML can be disposed on the first substrate 11. The lower metal layer BML can be a light blocking layer for protecting the active material layer ACT of the transistor TR from external light. The lower metal layer BML can include a material for blocking light. For example, the lower metal layer BML can be formed of an opaque metal material that blocks transmission of light.

[0080] The lower metal layer BML has a patterned shape. The lower metal layer BML can be disposed to cover at least a channel region of the active material layer ACT of the transistor TR from the bottom, and can also be disposed to cover the entire active material layer ACT of the transistor TR from the bottom. However, the disclosure is not limited thereto, and the lower metal layer BML can be omitted.

[0081] A buffer layer 12 can be disposed on the lower metal layer BML. The buffer layer 12 can be disposed to cover the entire surface of the first substrate 11 on which the lower metal layer BML is disposed. The buffer layer 12 can function to protect the transistor TR from moisture that permeates through the first substrate 11 that is susceptible to moisture permeation. The buffer layer 12 can be formed of a plurality of inorganic layers that are alternately stacked. For example, the buffer layer 12 can be formed of a plurality of layers that are alternately stacked with inorganic layers including at least one of silicon oxide (SiO x ), silicon nitride (SiN x ), and silicon oxynitride (SiON).

[0082] A semiconductor layer can be disposed on the buffer layer 12. The semiconductor layer can include the active material layer ACT of the transistor TR. The active material layer ACT can be disposed to be superposed with the lower metal layer BML.

[0083] Although only one of the transistors included in one sub-pixel SPX of the display device 10 is illustrated in the accompanying drawings, the disclosure is not limited thereto. For example, each sub-pixel SPX of the display device 10 can include two or three transistors. For example, the display device 10 can include two or three transistors for each sub-pixel SPX.

[0084] The semiconductor layer can include polysilicon, single-crystal silicon, an oxide semiconductor, etc.

[0085] In an example embodiment, when the semiconductor layer includes polysilicon, the polysilicon can be formed by crystallizing amorphous silicon. When the semiconductor layer includes polysilicon, the active material layer ACT can include a plurality of doped regions doped with impurities and a channel region provided therebetween. In another example embodiment, the semiconductor layer can include an oxide semiconductor. The oxide semiconductor can be, for example, indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), indium zinc tin oxide (IZTO), indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium gallium zinc tin oxide (IGZTO), or the like.

[0086] A gate insulating layer 13 can be provided over the semiconductor layer. The gate insulating layer 13 can function as a gate insulating layer of the transistor TR. The gate insulating layer 13 can be formed of an inorganic layer including an inorganic material such as silicon oxide (SiO x ), silicon nitride (SiN x ), or silicon oxynitride (SiON), or a stacked structure thereof.

[0087] A first conductive layer 14 can be provided over the gate insulating layer 13. The first conductive layer 14 can include a gate electrode GE of the transistor TR and a first capacitor electrode CSE of the storage capacitor.

[0088] The gate electrode GE can be provided to overlap with the channel region of the active material layer ACT in a third direction DR3. The first capacitor electrode CSE can be provided to overlap with a second source / drain electrode SD2 of the transistor TR, which will be described later, in the third direction DR3. Since the first capacitor electrode CSE is provided to overlap with the second source / drain electrode SD2 in the third direction DR3, a storage capacitor can be formed therebetween. In some embodiments, the first capacitor electrode CSE and the gate electrode GE can be integrated into one layer. A portion of the integrated layer can include the gate electrode GE, and another portion thereof can include the first capacitor electrode CSE.

[0089] The first conductive layer 14 can be formed as a single layer or a plurality of layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. However, the disclosure is not limited thereto.

[0090] An interlayer insulating layer 15 is provided over the first conductive layer 14. The interlayer insulating layer 15 can be provided to cover the first conductive layer 14. The interlayer insulating layer 15 can include an inorganic insulating material such as silicon oxide (SiO x ), silicon nitride (SiN x ), and silicon oxynitride (SiON).

[0091] The second conductive layer 16 is disposed on the interlayer insulating layer 15. The second conductive layer 16 can include the first source / drain electrode SD1 and the second source / drain electrode SD2 of the transistor TR and the data line DTL.

[0092] The first source / drain electrode SD1 and the second source / drain electrode SD2 can be electrically connected to two end regions (e.g., each doped region of the active material layer ACT of the transistor TR) of the active material layer ACT of the transistor TR, respectively, through contact holes that penetrate the interlayer insulating layer 15 and the gate insulating layer 13. In addition, the second source / drain electrode SD2 of the transistor TR can be electrically connected to the lower metal layer BML through another contact hole that penetrates the interlayer insulating layer 15, the gate insulating layer 13, and the buffer layer 12.

[0093] The data line DTL can apply a data signal to another transistor (not shown) included in the display device 10. Although not shown in the drawings, the data line DTL can be connected to a source / drain electrode of the other transistor.

[0094] The second conductive layer 16 can be formed as a single layer or a plurality of layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. However, the present disclosure is not limited thereto.

[0095] The passivation layer 17 is disposed on the second conductive layer 16. The passivation layer 17 serves to cover and protect the second conductive layer 16. The passivation layer 17 can include an inorganic insulating material such as silicon oxide (SiO x ), silicon nitride (SiN x ), and silicon oxynitride (SiON).

[0096] The third conductive layer 18 is disposed on the passivation layer 17. The third conductive layer 18 can include the first power line VL1, the second power line VL2, and the first conductive pattern CDP.

[0097] A high potential voltage (or a first source voltage) can be supplied to the first power line VL1, and a low potential voltage (or a second source voltage) lower than the high potential voltage supplied to the first power line VL1 can be supplied to the second power line VL2. The second power line VL2 can be electrically connected to the second electrode 22 to supply the low potential voltage (second source power) to the second electrode 22. In addition, an alignment signal for aligning the light emitting element ED can be applied to the second power line VL2 during a manufacturing process of the display device 10.

[0098] The first conductive pattern CDP can be electrically connected to the second source / drain electrode SD2 of the transistor TR through a contact hole that penetrates the passivation layer 17. The first conductive pattern CDP can be electrically connected to the first electrode 21 through a first contact hole CT1 to be described later to transmit a first source voltage applied from the first power supply line VL1 to the first electrode 21.

[0099] The third conductive layer 18 can be formed as a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. However, the present disclosure is not limited thereto.

[0100] The via layer 19 is disposed on the third conductive layer 18. The via layer 19 can be disposed on the passivation layer 17 on which the third conductive layer 18 is disposed. The via layer 19 can serve to planarize the surface. The via layer 19 can include an organic insulating material, for example, an organic material such as polyimide (PI).

[0101] Hereinafter, the structure of a light emitting element layer disposed on the via layer 19 will be described with reference to Figure 2 and Figure 3

[0102] The light emitting element layer can be disposed on the via layer 19 of the circuit element layer CCL. The light emitting element layer can include a plurality of light emitting elements ED, a first bank IBK, a second bank OBK, a first electrode 21 and a second electrode 22, a first contact electrode 41 and a second contact electrode 42, and a plurality of insulating layers 51, 52, 53, and 54.

[0103] The first bank IBK can be disposed on the via layer 19. The first bank IBK can have a shape extending in the second direction DR2 within each sub-pixel SPX in a plan view. The first bank IBK can terminate while being separated within the emission area EMA that is separated by the second bank OBK, such that the first bank IBK does not extend to an adjacent sub-pixel SPX in the second direction DR2.

[0104] The first bank IBK can include a first sub-bank IBK1 and a second sub-bank IBK2. The first sub-bank IBK1 and the second sub-bank IBK2 can face each other and be spaced apart from each other in the first direction DR1. For example, the first sub-bank IBK1 can be disposed on the left side of the emission area EMA in a plan view, and the second sub-bank IBK2 can be disposed on the right side of the emission area EMA in a plan view. A separation space formed between the first sub-bank IBK1 and the second sub-bank IBK2 spaced apart from each other can provide an area in which a plurality of light emitting elements ED are disposed.

[0105] ​The first bank IBK (IBK1 and IBK2) can have a structure in which at least a portion of the first bank IBK protrudes upward (e.g., on one side in the third direction DR3) with respect to a top surface of the via layer 19. The protruding portion of the first bank IBK can have an inclined side surface.

[0106] The first bank IBK can serve to change a traveling direction of light emitted from the light emitting element ED toward the inclined side surface of the first bank IBK to an upward direction (e.g., a display direction). In other words, the first bank IBK can serve as a reflection partition wall that provides a space in which the light emitting element ED is disposed and changes a traveling direction of light emitted from the light emitting element ED to a display direction.

[0107] On the other hand, although the side surface of the first bank IBK is illustrated to be inclined in a straight line shape in the drawings, the present disclosure is not limited thereto. For example, the side surface (or outer surface) of the first bank IBK can have a curved semicircular shape or a semioval shape. In an exemplary embodiment, the first bank IBK can include an organic insulating material such as polyimide (PI), but is not limited thereto.

[0108] The first electrode 21 and the second electrode 22 can be disposed on the first bank IBK and the via layer 19 exposed by the first bank IBK. Specifically, the first electrode 21 can be disposed on the first sub-bank IBK1, and the second electrode 22 can be disposed on the second sub-bank IBK2.

[0109] Each of the first electrode 21 and the second electrode 22 can have a shape extending in the second direction DR2 in a plan view. The first electrode 21 and the second electrode 22 can be spaced apart from each other and disposed to face each other in the first direction DR1. In a plan view, the shapes of the first electrode 21 and the second electrode 22 can be substantially similar to those of the first sub-bank IBK1 and the second sub-bank IBK2, respectively, but the areas of the first electrode 21 and the second electrode 22 can be greater than those of the first sub-bank IBK1 and the second sub-bank IBK2, respectively.

[0110] The first electrode 21 can extend in the second direction DR2 in a plan view to overlap with a portion of the second bank OBK extending in the first direction DR1. The first electrode 21 can be in contact with the first conductive pattern CDP through a first contact hole CT1 that penetrates the via layer 19. The first electrode 21 can be electrically connected to the transistor TR through the first conductive pattern CDP.

[0111] The second electrode 22 can extend in the second direction DR2 in a plan view to overlap with a portion of the second bank OBK extending in the first direction DR1. The second electrode 22 can be in contact with the second power supply line VL2 through a second contact hole CT2 that penetrates the via layer 19.

[0112] Although the drawings show that the first contact hole CT1 and the second contact hole CT2 are superposed with the second bank OBK, the present disclosure is not limited thereto. For example, the first contact hole CT1 and the second contact hole CT2 can be disposed in the emission area EMA surrounded by the second bank OBK so as not to be superposed with the second bank OBK.

[0113] In the first region CBA of the sub-pixel SPX, the first electrode 21 and the second electrode 22 can be separated from the other electrodes 21 and 22 included in the sub-pixel SPX adjacent in the second direction DR2, respectively. Such a shape of the first electrode 21 and the second electrode 22 can be formed in a process of disconnecting the electrodes 21 and 22 in the first region CBA after a process of arranging the light emitting element ED during a manufacturing process of the display device 10. However, the present disclosure is not limited thereto. In some embodiments, each of the first electrode 21 and the second electrode 22 can extend to the sub-pixel SPX adjacent in the second direction DR2 to be disposed continuously, or can divide only one of the first electrode 21 and the second electrode 22.

[0114] The shape and arrangement of the first electrode 21 and the second electrode 22 arranged in each sub-pixel SPX are not particularly limited as long as at least a part of the first electrode 21 and the second electrode 22 are spaced apart from each other to form a space in which the light emitting element ED is disposed. In Figure 2 and Figure 3 In the first region CBA of the sub-pixel SPX, the first electrode 21 and the second electrode 22 can be separated from the other electrodes 21 and 22 included in the sub-pixel SPX adjacent in the second direction DR2, respectively. Such a shape of the first electrode 21 and the second electrode 22 can be formed in a process of disconnecting the electrodes 21 and 22 in the first region CBA after a process of arranging the light emitting element ED during a manufacturing process of the display device 10. However, the present disclosure is not limited thereto. In some embodiments, each of the first electrode 21 and the second electrode 22 can extend to the sub-pixel SPX adjacent in the second direction DR2 to be disposed continuously, or can divide only one of the first electrode 21 and the second electrode 22.

[0115] The first electrode 21 can be disposed on the first sub-bank IBK1 to cover an outer surface of the first sub-bank IBK1. The first electrode 21 can extend outward from a side surface of the first sub-bank IBK1 to be disposed on a part of a top surface of the via layer 19 exposed by the first sub-bank IBK1 and the second sub-bank IBK2 in a region between the first sub-bank IBK1 and the second sub-bank IBK2.

[0116] The second electrode 22 can be disposed on the second subbank IBK2 to cover the outer surface of the second subbank IBK2. The second electrode 22 can extend outward from the side surface of the second subbank IBK2 to be disposed on the portion of the top surface of the via layer 19 exposed by the first subbank IBK1 and the second subbank IBK2 in the region between the first subbank IBK1 and the second subbank IBK2. The first electrode 21 and the second electrode 22 can be spaced apart from each other in the first direction DR1 such that a portion of the via layer 19 is exposed in the region between the first subbank IBK1 and the second subbank IBK2.

[0117] The first electrode 21 and the second electrode 22 can be electrically connected to the light emitting element ED, and a predetermined voltage can be applied to the first electrode 21 and the second electrode 22 such that the light emitting element ED emits light. For example, the first electrode 21 and the second electrode 22 can be electrically connected to the light emitting element ED disposed between the first electrode 21 and the second electrode 22 through the first contact electrode 41 and the second contact electrode 42, which will be described later, respectively, and an electrical signal applied to the first electrode 21 and the second electrode 22 can be transmitted to the light emitting element ED through the first contact electrode 41 and the second contact electrode 42, respectively.

[0118] The first electrode 21 and the second electrode 22 can be used to form an electric field in the sub-pixel SPX to align the light emitting element ED. The light emitting element ED can be disposed between the first electrode 21 and the second electrode 22 by the electric field formed on the first electrode 21 and the second electrode 22. In an exemplary embodiment, the light emitting element ED of the display device 10 can be injected onto the electrodes 21 and 22 by an inkjet printing process. When ink including the light emitting element ED is injected onto the electrodes 21 and 22, an alignment signal is applied to the electrodes 21 and 22 to generate an electric field. The light emitting element ED dispersed in the ink can be aligned on the electrodes 21 and 22 by receiving a dielectrophoretic force generated by the electric field on the electrodes 21 and 22.

[0119] The first and second electrodes 21 and 22 can include a transparent conductive material. For example, each of the first and second electrodes 21 and 22 can include a material such as indium tin oxide (ITO), indium zinc oxide (IZO), and indium tin zinc oxide (ITZO), but is not limited thereto. In some other embodiments, the first and second electrodes 21 and 22 can include a conductive material having high reflectivity. For example, the first and second electrodes 21 and 22 can include a metal such as silver (Ag), copper (Cu), or aluminum (Al) as a material having high reflectivity. In this case, the first and second electrodes 21 and 22 can reflect light emitted from the light emitting element ED and traveling toward the side surface of the first bank IBK (the first and second sub-banks IBK1 and IBK2) to travel in the display direction in each sub-pixel SPX. Without being limited thereto, the first and second electrodes 21 and 22 can have a structure in which at least one transparent conductive material and at least one metal layer having high reflectivity are stacked, or can be formed to include one layer thereof. In an exemplary embodiment, the first and second electrodes 21 and 22 can have a stacked structure such as ITO / Ag / ITO, ITO / Ag / IZO, or ITO / Ag / ITZO / IZO, or can be an alloy including aluminum (Al), nickel (Ni), lanthanum (La), or the like.

[0120] The first insulating layer 51 can be disposed on the first and second electrodes 21 and 22. The first insulating layer 51 can be disposed on the first and second electrodes 21 and 22 to expose at least a portion of the first and second electrodes 21 and 22. The first insulating layer 51 can be entirely formed on a surface of the substrate 11 including an area between the first and second electrodes 21 and 22 to expose a portion of the first and second electrodes 21 and 22.

[0121] The first insulating layer 51 can be formed to have a step such that a portion of its top surface is recessed between the first and second electrodes 21 and 22. The first insulating layer 51 can be formed such that a portion of its top surface is recessed due to a step formed by a member disposed thereunder (e.g., the first and / or second electrodes 21 and 22). In some embodiments, an empty space can be formed between the light emitting element ED and the top surface of the first insulating layer 51, a portion of which is recessed due to a step formed between the first and second electrodes 21 and 22. A material forming the second insulating layer 52, which will be described later, can fill the empty space between the first insulating layer 51 and the light emitting element ED. However, the present disclosure is not limited thereto, and the first insulating layer 51 can not have a step between the first and second electrodes 21 and 22. For example, the first insulating layer 51 can include a flat top surface to dispose the light emitting element ED between the first and second electrodes 21 and 22.

[0122] The first insulating layer 51 can protect the first and second electrodes 21 and 22 while insulating the first and second electrodes 21 and 22 from each other. Further, it is possible to prevent the light emitting element ED disposed on the first insulating layer 51 from being damaged due to direct contact with other components.

[0123] The second bank OBK can be disposed on the first insulating layer 51. Portions of the second bank OBK extending in the first and second directions DR1 and DR2 in a plan view can be arranged in a grid pattern. The second bank OBK can be disposed across a boundary of each sub-pixel SPX to delimit adjacent sub-pixels SPX.

[0124] The second bank OBK can be formed to have a height greater than that of the first bank IBK. The second bank OBK can serve to prevent ink from spilling to an adjacent sub-pixel SPX during an inkjet printing process for aligning the light emitting element ED in a manufacturing process of the display device 10. In an exemplary embodiment, the second bank OBK can include an organic insulating material such as polyimide (PI), but is not limited thereto.

[0125] The light emitting element ED can be disposed on the first insulating layer 51 between the first and second electrodes 21 and 22 such that one end of the light emitting element ED is positioned on the first electrode 21 and the other end of the light emitting element ED is positioned on the second electrode 22.

[0126] The light emitting element ED can have a shape extending in one direction. The extending direction of the light emitting element ED disposed on the first and second electrodes 21 and 22 can be substantially perpendicular to the extending direction of the first and second electrodes 21 and 22. However, the disclosure is not limited thereto. Some of the plurality of light emitting elements ED can be arranged such that their extending direction is substantially perpendicular to the extending direction of the first and second electrodes 21 and 22, and some other of the plurality of light emitting elements ED can be arranged such that their extending direction is inclined to the extending direction of the first and second electrodes 21 and 22.

[0127] The second insulating layer 52 can be partially disposed on the light emitting element ED. The second insulating layer 52 can be disposed on the light emitting element ED disposed between the first and second electrodes 21 and 22 to expose both ends of the light emitting element ED. The second insulating layer 52 can be disposed to partially surround an outer surface of the light emitting element ED. The second insulating layer 52 can serve to protect the light emitting element ED and also to fix the light emitting element ED in a manufacturing process of the display device 10.

[0128] The portion of the second insulating layer 52 disposed on the light emitting element ED can have a shape extending in the second direction DR2 between the first and second electrodes 21 and 22 in a plan view. For example, the second insulating layer 52 can form a linear or island-shaped pattern in each sub-pixel SPX.

[0129] Although not shown in the drawings, a material constituting the second insulating layer 52 can be provided between the first electrode 21 and the second electrode 22 and fill the empty space formed by the recess as described above between the light emitting element ED and the first insulating layer 51.

[0130] The first contact electrode 41 and the second contact electrode 42 can be provided on the second insulating layer 52. The first contact electrode 41 and the second contact electrode 42 can have a shape extending in one direction in a plan view. Each of the first contact electrode 41 and the second contact electrode 42 can have a shape extending in a second direction DR2. The first contact electrode 41 and the second contact electrode 42 can be spaced apart from each other and provided to face each other in the first direction DR1.

[0131] The first contact electrode 41 can be provided on the first electrode 21. The first contact electrode 41 can be in contact with the first electrode 21 exposed by the first insulating layer 51 and can be in contact with one end of the light emitting element ED exposed by the second insulating layer 52. Since the first contact electrode 41 is in contact with the first electrode 21 and one end of the light emitting element ED, it can be used to electrically connect the light emitting element ED to the first electrode 21.

[0132] The third insulating layer 53 is provided on the first contact electrode 41. The third insulating layer 53 can be used to electrically insulate the first contact electrode 41 and the second contact electrode 42 from each other. The third insulating layer 53 can be provided to cover the first contact electrode 41, but can not be provided on the other end of the light emitting element ED so that the light emitting element ED can be in contact with the second contact electrode 42.

[0133] The second contact electrode 42 can be provided on the second electrode 22. The second contact electrode 42 can be in contact with the second electrode 22 exposed by the first insulating layer 51 and can be in contact with the other end of the light emitting element ED exposed by the second insulating layer 52 and the third insulating layer 53. The second contact electrode 42 can be in contact with the other end of the light emitting element ED and the second electrode 22 to electrically connect the light emitting element ED to the second electrode 22.

[0134] In other words, one end of the light emitting element ED exposed by the second insulating layer 52 can be electrically connected to the first electrode 21 through the first contact electrode 41, and the other end of the light emitting element ED can be electrically connected to the second electrode 22 through the second contact electrode 42.

[0135] The first contact electrode 41 and the second contact electrode 42 can include a conductive material. For example, they can include ITO, IZO, ITZO, aluminum (Al), etc. As one example, the first contact electrode 41 and the second contact electrode 42 can each include a transparent conductive material, but are not limited thereto.

[0136] The fourth insulating layer 54 can be provided entirely on the first substrate 11. The fourth insulating layer 54 can serve to protect the components provided on the first substrate 11 from the external environment.

[0137] The first to fourth insulating layers 51, 52, 53, and 54 described above can include an inorganic insulating material or an organic insulating material. In an exemplary embodiment, the first to fourth insulating layers 51, 52, 53, and 54 can include an inorganic insulating material such as silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (Al x O y ), aluminum nitride (AlN), or the like. Alternatively, they can include an organic insulating material such as acrylic resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, unsaturated polyester resin, polystyrene resin, polyphenylene sulfide resin, benzocyclobutene, cardo resin, siloxane resin, silsesquioxane resin, polymethyl methacrylate, polycarbonate, polymethyl methacrylate-polycarbonate synthetic resin, or the like. However, the present disclosure is not limited thereto.

[0138] Figure 4 is a schematic perspective view of a light emitting element according to an embodiment. Figure 5 is a cross-sectional view taken along the line V-V' of Figure 4 .

[0139] The light emitting element ED as a particle element can have a shape extending in one direction X. The light emitting element ED can have a rod shape, a tube shape, or a cylindrical shape having a predetermined aspect ratio. The length of the light emitting element ED can be greater than the diameter of the light emitting element ED, and the aspect ratio can be 1.2:1 to 100:1, but the present disclosure is not limited thereto.

[0140] The light emitting element ED can have a size of a nanoscale (equal to or greater than 1 nm and less than 1 µm) to a microscale (equal to or greater than 1 µm and less than 1 mm). In an embodiment, both the diameter and the length of the light emitting element ED can be nanoscale or microscale. In some other embodiments, the diameter of the light emitting element ED can be nanoscale, while the length of the light emitting element ED can be microscale. In some embodiments, some of the light emitting elements ED can have a diameter and / or a length of nanoscale, while some other light emitting elements ED can have a diameter and / or a length of microscale.

[0141] The light emitting element ED can include an inorganic light emitting diode. The inorganic light emitting diode can include a plurality of semiconductor layers. For example, the inorganic light emitting diode can include a first conductive type (e.g., n-type) semiconductor layer, a second conductive type (e.g., p-type) semiconductor layer, and an active semiconductor layer interposed therebetween. The active semiconductor layer can receive holes and electrons from the first conductive type semiconductor layer and the second conductive type semiconductor layer, respectively, and the holes and the electrons that have reached the active semiconductor layer can recombine to emit light.

[0142] Referring to Figure 4 and Figure 5 The light emitting element ED according to one embodiment includes a light emitting element core 300 having the plurality of semiconductor layers described above, and a plurality of insulating layers 380 (381 and 382) surrounding an outer circumferential surface of the light emitting element core 300.

[0143] The light emitting element core 300 can have a shape extending in one direction X. The shape of the light emitting element core 300 can follow the shape of the light emitting element ED. The shape of the light emitting element core 300 can be a rod shape or a cylindrical shape similar to the shape of the light emitting element ED.

[0144] The light emitting element core 300 can include a first semiconductor layer 310, an element active layer 330, and a second semiconductor layer 320 sequentially stacked in one direction X that is a longitudinal direction of the light emitting element ED. The first semiconductor layer 310, the element active layer 330, and the second semiconductor layer 320 can be the first conductive type semiconductor layer, the active semiconductor layer, and the second conductive type semiconductor layer, respectively, described above.

[0145] Hereinafter, in the structure description of the light emitting element ED, for simplicity of description, the term "upward" or "upper side" refers to one side of one direction X that is an extension direction of the light emitting element ED or the light emitting element core 300, and the term "top surface" refers to a surface facing one side of one direction X. Also, the terms "downward" and "lower side" refer to the other side of one direction X that is an extension direction of the light emitting element ED, and the term "bottom surface" refers to a surface facing the other side of one direction X.

[0146] The first semiconductor layer 310 can be a semiconductor layer doped with a dopant of a first conductive type. The dopant of the first conductive type can be Si, Ge, Sn, Se, or the like. In an exemplary embodiment, the first semiconductor layer 310 can be n-GaN doped with n-type Si.

[0147] The second semiconductor layer 320 can be disposed on the first semiconductor layer 310 with the element active layer 330 interposed therebetween. The second semiconductor layer 320 can be spaced apart from the first semiconductor layer 310 in one direction X.

[0148] The second semiconductor layer 320 can be a semiconductor layer doped with a second conductivity type dopant. The second conductivity type dopant can be Mg, Zn, Ca, Ba, or the like. In an exemplary embodiment, the second semiconductor layer 320 can be p-GaN doped with p-type Mg.

[0149] Meanwhile, although it is illustrated in the drawings that the first semiconductor layer 310 and the second semiconductor layer 320 are configured as a single layer, the present disclosure is not limited thereto. According to some embodiments, the first semiconductor layer 310 and the second semiconductor layer 320 can further include a greater number of layers, such as a cladding layer or a tensile-strained barrier reduction (TSBR) layer, depending on the material of the element active layer 330.

[0150] The element active layer 330 can be disposed between the first semiconductor layer 310 and the second semiconductor layer 320. The element active layer 330 can include a material having a single quantum well structure or a multi-quantum well structure. As described above, the element active layer 330 can emit light through recombination of electron-hole pairs according to an electrical signal applied through the first semiconductor layer 310 and the second semiconductor layer 320.

[0151] In some embodiments, the element active layer 330 can have a structure in which a semiconductor material having a large energy bandgap and a semiconductor material having a small energy bandgap are alternately stacked, and can include other group III to group V semiconductor materials according to a wavelength band of emitted light.

[0152] Light emitted from the element active layer 330 can be projected through both side surfaces of the light emitting element ED and an outer surface in a longitudinal direction. That is, the directionality of light emitted from the element active layer 330 is not limited to one direction.

[0153] The light emitting element core 300 can further include an electrode layer 370 disposed on the second semiconductor layer 320. The electrode layer 370 can be in contact with the second semiconductor layer 320. The electrode layer 370 can be an ohmic contact electrode. However, the electrode layer 370 is not limited thereto and can be a Schottky contact electrode. Meanwhile, although the drawings illustrate that a top surface of the electrode layer 370 has a flat surface, the present disclosure is not limited thereto. For example, the top surface of the electrode layer 370 can include surface roughness. A description of an embodiment in which the top surface of the electrode layer 370 includes predetermined surface roughness will be described later with reference to another drawing.

[0154] When both ends of the light emitting element ED are electrically connected to the first electrode 21 and the second electrode 22 (or the first contact electrode 41 and the second contact electrode 42) to apply an electrical signal to the first semiconductor layer 310 and the second semiconductor layer 320, since the electrode layer 370 is disposed between the second semiconductor layer 320 and the electrode, the electrode layer 370 can serve to reduce electrical resistance.

[0155] The electrode layer 370 can include an electrically conductive metal. For example, the electrode layer 370 can include at least one of aluminum (Al), titanium (Ti), indium (In), gold (Au), silver (Ag), indium tin oxide (ITO), indium zinc oxide (IZO), and indium tin zinc oxide (ITZO). Also, the electrode layer 370 can include an n-type or p-type doped semiconductor material.

[0156] The insulating layer 380 can be disposed to surround the outer circumferential surface of the light emitting element core 300. The insulating layer 380 can include a first insulating layer 381 and a second insulating layer 382.

[0157] The first insulating layer 381 can be disposed to surround the outer circumferential surface (or side surface) of the light emitting element core 300. Specifically, the first insulating layer 381 can be disposed to surround the outer circumferential surface (or side surface) of the first semiconductor layer 310, the element active layer 330, and the second semiconductor layer 320 of the light emitting element core 300. The first insulating layer 381 can be disposed in direct contact with the side surface of the first semiconductor layer 310, the element active layer 330, and the second semiconductor layer 320. A portion of the first insulating layer 381 can also be disposed on the side surface of the electrode layer 370 of the light emitting element core 300. The first insulating layer 381 can be formed to surround the side surface of the member and extend in one direction X along which the light emitting element ED extends.

[0158] The first insulating layer 381 can serve to protect the member (e.g., the first semiconductor layer 310, the element active layer 330, the second semiconductor layer 320, and the electrode layer 370). Also, since the first insulating layer 381 is disposed to surround the side surface of the element active layer 330 and includes a material capable of minimizing the loss of carriers that can occur at the interface between the element active layer 330 and the first insulating layer 381, the first insulating layer 381 can serve to prevent a decrease in the light efficiency of the light emitting element ED.

[0159] The first insulating layer 381 can include a material having a first fixed charge and insulating properties (e.g., SiO x , SiN x , SiON, SiO x N y , Al x O yat least one of SiO2, HfO2, TiO2, SrTiO3, Ta2O5, Gd2O3, ZrO2, Ga2O3, V2O5, Co3O4, ZnO, ZnO:Al, ZnO:B, In2O3:H, WO3, MoO3, Nb2O5, NiO, MgO, RuO2, MgF2, AlF3, Alucone, TiN, TaN, Si3N4, AlN, GaN, WN, HfN, NbN, GdN, VN, and ZrN. Since the first insulating layer 381 surrounding the member includes an insulating material, it is possible to prevent an electrical short that can occur when the element active layer 330 is in direct contact with the first electrode 21 or the second electrode 22. Also, since the first insulating layer 381 protects the outer peripheral surface of the light emitting element ED and the element active layer 330, it is possible to prevent a decrease in light emitting efficiency due to damage to the light emitting element ED that can occur in a manufacturing process of the display device 10, which will be described later.

[0160] The thickness d1 of the first insulating layer 381 can be in the range of 5 nm to 100 nm, but is not limited thereto.

[0161] The second insulating layer 382 can be provided to surround the outer peripheral surface of the first insulating layer 381. The second insulating layer 382 can be provided to surround the outer peripheral surface of the first insulating layer 381 to perform a function of protecting the first insulating layer 381. For example, the second insulating layer 382 can be provided to surround the first insulating layer 381, and thus the second insulating layer 382 can be used to prevent the first insulating layer 381 of the light emitting element ED from being damaged in a process of forming the second insulating layer 52 and / or the third insulating layer 53 during a manufacturing process of the display device 10, which will be described later. Figure 4 and Figure 5 It is shown that the second insulating layer 382 is provided to completely cover the outer peripheral surface of the first insulating layer 381, but the present disclosure is not limited thereto. For example, the second insulating layer 382 can expose a portion of the outer peripheral surface of the first insulating layer 381 at one end of the light emitting element ED where the electrode layer 370 is provided. A description thereof will be given later with reference to other drawings.

[0162] According to one embodiment, the second insulating layer 382 can have insulating properties and further include a material having a second fixed charge different from a first fixed charge (Qf) included in the material of the first insulating layer 381. The relative relationship between the fixed charges of the first insulating layer 381 and the second insulating layer 382 will be described in detail later. For example, the second insulating layer 382 can include at least one of the insulating materials listed as the material that the first insulating layer 381 can include.

[0163] In an exemplary embodiment, when the first insulating layer 381 includes silicon oxide (SiOx ) When the second insulating layer 382 includes aluminum oxide (Al2O3) having a second fixed charge different from the first fixed charge, the second fixed charge can be a positive (+) value. In this case, the second insulating layer 382 can include aluminum oxide (Al2O3) having a second fixed charge different from the first fixed charge. x O y ) However, the present disclosure is not limited thereto, and the first insulating layer 381 and the second insulating layer 382 can include materials having fixed charges different from each other among materials listed as materials having insulating properties.

[0164] The thickness d2 of the second insulating layer 382 can be in the range of 5 nm to 100 nm, but is not limited thereto.

[0165] Although the drawings show that the thickness d1 of the first insulating layer 381 and the thickness d2 of the second insulating layer 382 are the same, the present disclosure is not limited thereto. In some embodiments, the thickness d1 of the first insulating layer 381 can be different from the thickness d2 of the second insulating layer 382. For example, the thickness d1 of the first insulating layer 381 can be greater than the thickness d2 of the second insulating layer 382. Alternatively, the thickness d1 of the first insulating layer 381 can be less than the thickness d2 of the second insulating layer 382.

[0166] Hereinafter, the relative relationship between the fixed charges of the materials included in the first insulating layer 381 and the second insulating layer 382 and the relationship between the element active layer 330 and the first insulating layer 381 will be described. In the following description, the term "fixed charge" does not refer to the total amount of the charge contained in each of the insulating layers 381 and 382, but refers to the density of the fixed charge in the region adjacent to the interface (surface) of each insulating layer 381, 382. The unit of the fixed charge can be "cm -2 ". When the fixed charge has a positive (+) value, it can have a positive fixed charge, and when it has a negative (-) value, it can have a negative fixed charge.

[0167] On the other hand, the efficiency of the light emitting element ED can depend on the characteristics of the interface (or surface) at which the element active layer 330 emitting light and the first insulating layer 381 come into contact with each other. For example, due to the movement of carriers from the element active layer 330 to the first insulating layer 381, the efficiency of the light emitting element ED can be affected by the loss at the interface (or surface) at which the element active layer 330 emitting light and the first insulating layer 381 come into contact with each other. Therefore, in order to prevent the loss due to the movement of carriers or electron-hole recombination at the interface at which the element active layer 330 and the first insulating layer 381 come into contact with each other, the material included in the first insulating layer 381 disposed to surround the side surface of the element active layer 330 can be a material having a first fixed charge and having a property that it is difficult for carriers to move from the element active layer 330 to the first insulating layer 381.

[0168] The first fixed charge of the first insulating layer 381 can be a negative fixed charge or a positive fixed charge. In an exemplary embodiment, when the first fixed charge is a negative fixed charge, a negative fixed charge layer can be formed at the interface between the first insulating layer 381 and the element active layer 330. Thus, since the interface of the first insulating layer 381 has a negative charge property, it is possible to prevent carriers (e.g., electrons) from moving from the element active layer 330 to the first insulating layer 381. Thus, since the loss of carriers due to the movement of carriers from the element active layer 330 to the first insulating layer 381 at the interface between the element active layer 330 and the first insulating layer 381 is reduced, it is possible to improve the light emitting efficiency of the light emitting element ED. However, the present disclosure is not limited thereto, and the first fixed charge can have a positive fixed charge.

[0169] As described above, the second insulating layer 382 can include a material having a second fixed charge different from the first fixed charge. That is, the fixed charge of the material included in the first insulating layer 381 can be different from the fixed charge of the material included in the second insulating layer 382.

[0170] In an exemplary embodiment, the polarity of the first fixed charge can be the same as the polarity of the second fixed charge. For example, when the first fixed charge and the second fixed charge have a positive (+) fixed charge, the absolute value of the first fixed charge can be smaller than the absolute value of the second fixed charge. In some other embodiments, when the first fixed charge and the second fixed charge have a negative (-) fixed charge, the absolute value of the first fixed charge can be greater than the absolute value of the second fixed charge. However, the present disclosure is not limited thereto. In the following description, the fact that the "size of the fixed charge is large" can mean that the absolute value of the fixed charge is large.

[0171] In some embodiments, the polarity of the first fixed charge can be different from the polarity of the second fixed charge. For example, the polarity of the first fixed charge can be negative (-), and the polarity of the second fixed charge can be positive (+). That is, the first fixed charge can have a negative fixed charge, and the second fixed charge can have a positive fixed charge. The first insulating layer 381 surrounding the element active layer 330 while contacting the side surface of the element active layer 330 includes a material having a negative fixed charge or a material having a positive fixed charge with a small absolute value, and thus it is possible to prevent carriers from moving from the element active layer 330 to the first insulating layer 381. Thus, it is possible to prevent a decrease in the efficiency of the light emitting element ED due to the loss of carriers that can occur at the interface between the first insulating layer 381 and the element active layer 330.

[0172] As described above, when the first insulating layer 381 includes silicon oxide (SiO x ) having a first fixed charge and the second insulating layer 382 includes aluminum oxide (Al x Oy ) When the first fixed charge and the second fixed charge have positive fixed charges, the size of the first fixed charge can be smaller than the size of the second fixed charge. Alternatively, the first fixed charge can have a negative fixed charge, and the second fixed charge can have a positive fixed charge. Similarly, the first fixed charge and the second fixed charge can have negative fixed charges, and the size of the first fixed charge can be greater than the size of the second fixed charge.

[0173] The second insulating layer 382 can include a material having a fixed charge different from that of the material of the first insulating layer 381, thereby improving the light emitting characteristics of the light emitting element ED included in the display device 10. Also, the second insulating layer 382 can include a material having an etching selectivity different from that of the first insulating layer 381 with respect to the same etchant. Since the second insulating layer 382 includes a material having an etching selectivity different from that of the first insulating layer 381 with respect to the same etchant, the second insulating layer 382 can prevent the first insulating layer 381 from being damaged by an etchant used in a process for forming a plurality of insulating layers (e.g., the second insulating layer 52 / the third insulating layer 53, and the fourth insulating layer 54 (see Figure 3 )) disposed on the light emitting element ED during a manufacturing process of the display device 10. A detailed description thereof will be given later with reference to Figure 6 .

[0174] Figure 4 and Figure 5 It is shown that the first insulating layer 381 and the second insulating layer 382 are formed to cover the area from the side surface of the first semiconductor layer 310 to the side surface of the electrode layer 370, but the present disclosure is not limited thereto. The first insulating layer 381 and / or the second insulating layer 382 can be disposed to cover the side surfaces of the first semiconductor layer 310, the second semiconductor layer 320, and the element active layer 330 while exposing at least a portion of the side surface of the electrode layer 370. Also, the first insulating layer 381 and / or the second insulating layer 382 can be formed to have a rounded top surface in a cross-sectional view in an area adjacent to at least one end of the light emitting element ED.

[0175] Also, in some embodiments, the outer peripheral surface of the second insulating layer 382 can be surface-treated. As described above, the light emitting element ED can be applied in a state of being dispersed in a solution to be aligned between the first electrode 21 and the second electrode 22. In this case, in order to keep the light emitting element ED in a dispersed state without being aggregated with other light emitting elements ED adjacent thereto in the solution, the surface of the second insulating layer 382 is treated to have a hydrophobicity or a hydrophilicity so that the light emitting elements ED can be kept dispersed from each other in the solution. Accordingly, when the light emitting elements ED are aligned, the light emitting elements ED can be aligned between the first electrode 21 and the second electrode 22 without being aggregated with each other.

[0176] Figure 6 is an enlarged view showing an example of the portion Q of Figure 3

[0177] Referring to Figure 3 and Figure 6 , the light emitting element ED can be disposed on the first substrate 11. The light emitting element ED can be disposed on the first insulating layer 51 between the first electrode 21 and the second electrode 22. In a cross section passing through both ends of the light emitting element ED, the first semiconductor layer 310, the element active layer 330, the second semiconductor layer 320, and the electrode layer 370 can be sequentially formed in a direction parallel to one surface of the first substrate 11, and the first insulating layer 381 and the second insulating layer 382 can be formed in a direction perpendicular to one surface of the first substrate 11.

[0178] The first insulating layer 381 of the light emitting element ED can be disposed to surround side surfaces of the first semiconductor layer 310, the element active layer 330, the second semiconductor layer 320, and the electrode layer 370, and the second insulating layer 382 can be disposed to surround the first insulating layer 381. Accordingly, an outer surface of the light emitting element ED disposed between the first electrode 21 and the second electrode 22 while both ends thereof are positioned above the first electrode 21 and the second electrode 22, respectively, can be the second insulating layer 382. A portion of the second insulating layer 382 can be in contact with the first insulating layer 51 disposed thereunder and the second insulating layer 52 disposed thereover, respectively.

[0179] Both ends of the light emitting element ED exposed by the second insulating layer 52 can be in contact with the first contact electrode 41 and the second contact electrode 42. Specifically, the second insulating layer 382 and the electrode layer 370 of the light emitting element ED exposed by the second insulating layer 52 can be in contact with the first contact electrode 41, and the second insulating layer 382 and the first semiconductor layer 310 of the light emitting element ED exposed by the second insulating layer 52 can be in contact with the second contact electrode 42. Accordingly, in regions in which the first contact electrode 41 and the second contact electrode 42 are in contact with the second insulating layer 382, the second insulating layer 382 can be interposed between the first contact electrode 41 and the second contact electrode 42 and the first insulating layer 381.

[0180] ​The first insulating layer 381 of the light-emitting element ED can be configured to surround the side surfaces of the first semiconductor layer 310, the active layer 330, the second semiconductor layer 320, and the electrode layer 370 to protect the component. Furthermore, since the first insulating layer 381 of the light-emitting element ED comprises a material having a first fixed charge, losses due to carrier migration from the active layer 330 to the first insulating layer 381 or electron-hole recombination can be prevented. Therefore, the first insulating layer 381 comprising a material having a first fixed charge is formed to surround the side surfaces of the first semiconductor layer 310, the active layer 330, the second semiconductor layer 320, and the electrode layer 370, thereby insulating the component from external components and protecting the component from their influence, and preventing a decrease in the luminous efficiency of the light-emitting element ED.

[0181] The second insulating layer 382 of the light-emitting element ED can be configured to surround the first insulating layer 381, thus the second insulating layer 382 can be used to protect the first insulating layer 381. For example, during the manufacturing process of the display device 10, the outer surface of the light-emitting element ED can be exposed to the etchant used in the process of forming the second insulating layer 52 and / or the third insulating layer 53. Specifically, the second insulating layer 382 of the light-emitting element ED can be exposed to the etchant used in the process of forming the second insulating layer 52 and / or the third insulating layer 53. The second insulating layer 382 may include a material having a second fixed charge that is different from the first fixed charge of the material included in the first insulating layer 381. Therefore, since the second insulating layer 382 includes a material different from the material of the first insulating layer 381, for example, a material having a second fixed charge that is different from the first fixed charge, the second insulating layer 382 can protect the first insulating layer 381 from the etchant.

[0182] In this embodiment, since the display device 10 includes a light-emitting element ED comprising a first insulating layer 381 having the aforementioned first fixed charge, the brightness degradation of the light-emitting element ED can be improved. Furthermore, since the light-emitting element ED includes a second insulating layer 382 surrounding the first insulating layer 381 and having a second fixed charge different from the first fixed charge, the second insulating layer 382 can protect the first insulating layer 381 during the process of forming the multiple insulating layers of the display device 10. Therefore, in this case, even when the etchant used in the process of patterning the second insulating layer 52 (or the third insulating layer 53) has an etch selectivity relative to the second insulating layer 52 (or the third insulating layer 53) similar to its etch selectivity relative to the first insulating layer 381, the second insulating layer 382, ​​comprising a material different from the material of the first insulating layer 381, can protect the first insulating layer 381 during the manufacturing process of the display device 10. Therefore, since the display device 10 includes a light-emitting element ED with improved brightness efficiency, the light output efficiency of the display device 10 can be improved.

[0183] Figure 7 is a flowchart illustrating a method of manufacturing a light emitting element according to an embodiment.

[0184] Referring to Figure 7 , a method of manufacturing a light emitting element ED according to an embodiment can include forming a core structure on one surface of a bulk substrate (step S100), forming a first insulating material layer including a material having a first fixed charge on the core structure using plasma-enhanced atomic layer deposition (PEALD) (step S200), forming a second insulating material layer including a material having a second fixed charge different from the first fixed charge on the first insulating material layer (step S300), forming an element rod by partially removing the first insulating material layer and the second insulating material layer to expose a top surface of the core structure (step S400), and separating the element rod from the bulk substrate (step S500).

[0185] In this embodiment, the first insulating layer 381 surrounding the side surface of the light emitting element core 300 can be formed by forming a first insulating material layer using plasma-enhanced atomic layer deposition (PEALD), forming a second insulating material layer on the first insulating material layer, and vertically etching the first insulating material layer and the second insulating material layer to partially remove them and expose the top surface of the light emitting element core 300 in a subsequent process. Hereinafter, a manufacturing process of a light emitting element ED according to an embodiment will be described with reference to Figures 8 to 14

[0186] Figures 8 to 14 is a cross-sectional view illustrating a manufacturing process of a light emitting element according to an embodiment.

[0187] First, a core structure 300' is formed on one surface of a bulk substrate 1100 (step S100). Figure 7 of FIG. 1.

[0188] The step S100 of forming the core structure 300' on one surface of the bulk substrate 1100 can include preparing the bulk substrate 1100, forming a first stack structure 3000 on the bulk substrate 1100, and forming a plurality of core structures 300' by etching the first stack structure 3000 in a direction perpendicular to a top surface of the bulk substrate 1100.

[0189] Specifically, referring to Figure 8 , the bulk substrate 1100 is prepared.

[0190] ​In the following, the fourth direction DR4 and the fifth direction DR5 are defined in the drawings showing embodiments of the manufacturing process of the light emitting element ED. The fourth direction DR4 and the fifth direction DR5 can be perpendicular to each other. The fifth direction DR5 can be a direction parallel to one direction X as an extending direction of the light emitting element ED formed on the base substrate 1100. In describing embodiments of the manufacturing process of the light emitting element ED, unless otherwise specified, "upward" indicates one side of the fifth direction DR5 (i.e., a direction in which the plurality of semiconductor layers of the light emitting element ED are stacked from one surface (or top surface) of the base substrate 1100), and "top surface" indicates a surface toward one side of the fifth direction DR5. Further, the term "downward" refers to the other side of the fifth direction DR5, and the term "bottom surface" refers to a surface toward the other side of the fifth direction DR5.

[0191] The base substrate 1100 can include a sapphire substrate (Al x O y ) or a transparent substrate such as glass. In an exemplary embodiment, the base substrate 1100 can be a sapphire substrate (Al x O y ).

[0192] The plurality of semiconductor layers included in the light emitting element ED can be formed on one surface of the base substrate 1100. The plurality of semiconductor layers included in the light emitting element ED can be formed by forming a seed crystal on the base substrate 1100 and growing it by an epitaxial method. The semiconductor layers can be formed by electron beam deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma laser deposition (PLD), dual-type thermal evaporation, sputtering, or metal organic chemical vapor deposition (MOCVD).

[0193] Next, a buffer material layer 1200 can be formed on one surface (or top surface) of the base substrate 1100. The buffer material layer 1200 can serve to reduce a lattice constant difference between the base substrate 1100 and a first semiconductor material layer 3100 (see Figure 9 ) to be described later. The buffer material layer 1200 can include an undoped semiconductor. The buffer material layer 1200 can include the same material as the first semiconductor material layer 3100 to be described later, but can include a material that is not doped with a first conductive type dopant or a second conductive type dopant (e.g., an n-type or a p-type dopant). Although the drawings show that the buffer material layer 1200 is formed of a single layer, the buffer material layer 1200 can be stacked as multiple layers.

[0194] The buffer material layer 1200 can be omitted depending on the type of the base substrate 1100.

[0195] Next, a first stack structure 3000 is formed over the base substrate 1100.

[0196] Referring to Figure 9 In the example embodiment in which the buffer material layer 1200 is formed on the base substrate 1100, a first stack structure 3000 including a first semiconductor material layer 3100, an element active material layer 3300, a second semiconductor material layer 3200, and an electrode material layer 3700 sequentially stacked therein is formed on the buffer material layer 1200. The plurality of material layers included in the first stack structure 3000 can be formed by performing a conventional process.

[0197] The plurality of layers included in the first stack structure 3000 can correspond to the respective layers included in the light emitting element ED according to an embodiment. Specifically, the first semiconductor material layer 3100, the element active material layer 3300, the second semiconductor material layer 3200, and the electrode material layer 3700 of the first stack structure 3000 can respectively correspond to the first semiconductor layer 310, the element active layer 330, the second semiconductor layer 320, and the electrode layer 370 of the light emitting element ED, and can include the same materials as the materials included in the respective layers.

[0198] Subsequently, the first stack structure 3000 is etched to form a plurality of core structures 300' spaced apart from each other over the base substrate 1100.

[0199] Referring to Figure 10 The plurality of core structures 300' are formed by etching the first stack structure 3000 in a direction perpendicular to one surface of the base substrate 1100, i.e., the fifth direction DR5. In the etching process for forming the core structures 300', the first semiconductor material layer 3100 of the first stack structure 3000 is etched to maintain a predetermined thickness over the base substrate 1100, so that a portion of the first semiconductor material layer 3100 can be etched to become a patterned plurality of first semiconductor layers 310, and the other portion thereof can remain unetched to become a first semiconductor connection layer 310'. Figure 9

[0200] The etching process for etching the first stack structure 3000 to form the core structures 300' can be performed by a conventional method. In the example embodiment, the core structures 300' can be formed by forming an etching mask layer on the first stack structure 3000 and etching the first stack structure 3000 along the etching mask layer in a direction perpendicular to one surface of the base substrate 1100, e.g., the fifth direction DR5.

[0201] ​For example, etching processes to form core structures 300' by etching the first stacked structure 3000 can be performed using dry etching, wet etching, reactive ion etching (RIE), inductively coupled plasma reactive ion etching (ICP-RIE), etc. In an exemplary embodiment, an etching process to form core structures 300' such that the side surfaces of core structures 300' are perpendicular to one surface of the substrate 1100 can be performed by mixing dry etching and wet etching methods. Specifically, the first stacked structure 3000 is etched in the fifth direction DR5 by a dry etching method as anisotropic etching, and then an etching process is performed by a wet etching method as isotropic etching, such that the lateral sides (or side surfaces) of the structure formed by etching the first stacked structure 3000 are arranged on a plane perpendicular to one surface of the substrate 1100, thereby forming a plurality of core structures 300'.

[0202] Multiple core structures 300' may be spaced apart from each other on the first semiconductor interconnect layer 310'. Each of the core structures 300' may include a first semiconductor layer 310, a device active layer 330, a second semiconductor layer 320 and an electrode layer 370 sequentially stacked on the first semiconductor interconnect layer 310' in the upward direction (fifth direction DR5).

[0203] The first semiconductor layer 310 may be integral with the first semiconductor interconnect layer 310'. The first semiconductor layer 310 may have a structure in which the first semiconductor interconnect layer 310' protrudes along the fifth direction DR5 from the first semiconductor interconnect layer 310' which is disposed entirely on the buffer material layer 1200. That is, the first semiconductor layer 310 and the first semiconductor interconnect layer 310' may comprise the same material and be integrally formed with each other, and may have structures with different steps. Therefore, the first semiconductor layer 310 of the core structure 300' formed on the first semiconductor interconnect layer 310' can be integrally formed with the first semiconductor interconnect layer 310' to be physically connected and / or electrically connected with each other.

[0204] Next, a first insulating material layer 3810 comprising a material having a first fixed charge is formed on the plurality of core structures 300' using plasma-enhanced atomic layer deposition (PEALD). Figure 7 Step S200).

[0205] Reference Figure 11 A first insulating material layer 3810 is formed on the outer surface of the core structure 300'. Since the first insulating material layer 3810 is formed above the entire surface of the substrate 1100, it can be formed not only on the outer surface of the core structure 300', but also on the top surface of the first semiconductor interconnect layer 310' exposed by the core structure 300'. The outer surface of the core structure 300' may include both the side surfaces and the top surface of the core structure 300'.

[0206] The first insulating material layer 3810 can correspond to the first insulating layer 381 of the light emitting element ED through a subsequent process. Accordingly, the first insulating material layer 3810 can include a material included in the first insulating layer 381, i.e., an insulating material having a first fixed charge. For example, the first insulating material layer 3810 can include at least one of the insulating materials listed as the material that the first insulating layer 381 can include. In an exemplary embodiment, the first insulating material layer 3810 can include silicon oxide (SiO x ) having a first fixed charge.

[0207] In one embodiment, the first insulating material layer 3810 can be formed using a method of coating or impregnating an insulating material on the outer surface of the core structure 300', etc. In one embodiment, the first insulating material layer 3810 can be formed using plasma-enhanced atomic layer deposition (PEALD).

[0208] In an exemplary embodiment in which the first insulating material layer 3810 includes silicon oxide (SiO x ) having a first fixed charge, the step of forming the first insulating material layer 3810 through a plasma-enhanced atomic layer deposition (PEALD) process can include: providing a precursor on the core structure 300'; purging; providing a reactive gas on the core structure 300'; generating a plasma of the reactive gas on the core structure 300'; and purging.

[0209] First, a precursor can be provided on the core structure 300'. Specifically, in an exemplary embodiment in which the first insulating material layer 3810 includes silicon oxide (SiO x ), the precursor can include a silicon-containing precursor. Then, a purge gas is provided to remove unreacted materials and byproducts that can remain in the reactor. Subsequently, a reactive gas can be provided onto the core structure 300'. The reactive gas can include oxygen. Then, power can be supplied to the core structure 300' to generate a plasma. The power for generating the plasma can be 200 W, and the process temperature can be in the range of 150°C to 250°C, but the present disclosure is not limited thereto. Thereafter, a purge gas is provided to remove unreacted materials and byproducts that can remain in the reactor.

[0210] Next, a second insulating material layer 3820 including a material having a second fixed charge different from the first fixed charge is formed on the first insulating material layer 3810 (step S300 of Figure 7 ).

[0211] Referring to Figure 12The second insulating material layer 3820 can be formed on the entire surface of the first insulating material layer 3810.

[0212] The second insulating material layer 3820 can include a material having a second fixed charge different from the first fixed charge of the first insulating material layer 3810. The second insulating material layer 3820 can be formed using a method of coating or impregnating an insulating material on the outer surface of the first insulating material layer 3810, etc. For example, the second insulating material layer 3820 can be formed by thermal atomic layer deposition (thermal ALD) or plasma-enhanced atomic layer deposition (PEALD).

[0213] Meanwhile, although the drawings show that the first insulating material layer 3810 and the second insulating material layer 3820 are formed by separate deposition processes, respectively, the present disclosure is not limited thereto. The first insulating material layer 3810 and the second insulating material layer 3820 can be formed by being simultaneously deposited in one process. In this case, similar to the first insulating material layer 3810, the second insulating material layer 3820 can be formed using plasma-enhanced atomic layer deposition (PEALD).

[0214] The second insulating material layer 3820 can correspond to the second insulating layer 382 of the light emitting element ED. Accordingly, the second insulating material layer 3820 can include a material included in the second insulating layer 382, i.e., an insulating material having a second fixed charge different from the first fixed charge. The second insulating material layer 3820 can include a material different from that of the first insulating material layer 3810. For example, the first insulating material layer 3810 can include an insulating material having a second fixed charge different from the first fixed charge among the insulating materials listed as materials that the first insulating layer 381 can include. In an exemplary embodiment, the second insulating material layer 3820 can include aluminum oxide (Al2O3) having a second fixed charge. x O y ).

[0215] Next, the first insulating material layer 3810 and the second insulating material layer 3820 are partially removed to expose the top surface of the core structure 300', thereby forming an element rod ROD( Figure 7 of step S400).

[0216] Referring to Figure 13 , the element rod ROD can include the core structure 300', the first insulating layer 381 surrounding the side surface of the core structure 300', and the second insulating layer 382 surrounding the outer circumferential surface of the first insulating layer 381.

[0217] To electrically connect the first semiconductor layer 310 and the second semiconductor layer 320 of the light emitting element ED to the above-mentioned contact electrodes 41 and 42, it is necessary to remove the insulating layers provided at both ends of the light emitting element ED to expose both end surfaces of the light emitting element ED. Therefore, the first insulating material layer 3810 and the second insulating material layer 3820 formed on the top surface of the core structure 300' as shown in FIG. 38A can be removed to expose the top surface of the core structure 300', thereby forming the element rod ROD. A process such as etch-back or dry etching as anisotropic etching can be performed to remove portions of the first insulating material layer 3810 and the second insulating material layer 3820. Figure 12 The first insulating material layer 3810 and the second insulating material layer 3820 formed on the top surface of the core structure 300' as shown in FIG. 38A can be removed to expose the top surface of the core structure 300', thereby forming the element rod ROD. A process such as etch-back or dry etching as anisotropic etching can be performed to remove portions of the first insulating material layer 3810 and the second insulating material layer 3820.

[0218] Next, the element rod ROD is separated from the base substrate 1100 (step S500). Figure 7

[0219] Referring to Figure 14 , the light emitting element ED according to one embodiment can be manufactured by removing the element rod ROD including the core structure 300', the first insulating layer 381, and the second insulating layer 382 from the base substrate 1100, the core structure 300', the first insulating layer 381, and the second insulating layer 382 corresponding to respective components of the light emitting element ED including the first insulating layer 381, the second insulating layer 382, and the light emitting element core 300 including the first semiconductor layer 310, the element active layer 330, the second semiconductor layer 320, and the electrode layer 370.

[0220] The method of separating the element rod ROD from the base substrate 1100 is not particularly limited. The process of separating the element rod ROD from the base substrate 1100 can be performed by a physical separation method or a chemical separation method.

[0221] Figure 15 is a graph comparing light emission characteristics of light emitting elements according to first insulating layers respectively formed by plasma-enhanced atomic layer deposition (PEALD) and thermal atomic layer deposition (thermal ALD) when the first insulating layer includes silicon oxide (SiO x ) when the first insulating layer includes silicon oxide (SiO

[0222] In Figure 15 , the X-axis represents time when an electrical signal is applied to the light emitting element ED, and the Y-axis represents luminance intensity of light emitted from the light emitting element ED. In the following description showing a graph of the luminance intensity of light according to time when an electrical signal is applied to the light emitting element ED for reference Figure 15 In the following description showing a graph of the luminance intensity of light according to time when an electrical signal is applied to the light emitting element ED for reference Figure 15 In Figure 15 ​Each of lines A1 and B1 shown illustrates the inclusion of silicon oxide (SiO2) according to the first insulating layer 381. x And the second insulating layer 382 includes aluminum oxide (Al). x O y The brightness distribution of light from the light-emitting element ED in an exemplary embodiment of the present invention.

[0223] Figure 15 Line A1 illustrates the formation of silicon oxide (SiO2) using plasma-enhanced atomic layer deposition (PEALD). x The first insulating layer 381 is formed using thermal atomic layer deposition (thermal ALD) to include aluminum oxide (Al). x O y In the case of the light-emitting element ED in the second insulating layer 382, ​​when an electrical signal is applied, the brightness distribution of the light varies over time. Figure 15 Line B1 illustrates the formation of silicon oxide (SiO2) using thermal atomic layer deposition (thermal ALD). x The first insulating layer 381 and the aluminum oxide (Al) x O y In the case of the light-emitting element ED in the second insulating layer 382, ​​when an electrical signal is applied, the brightness distribution of the light varies over time.

[0224] Reference Figure 15 In the case of a light-emitting element ED that uses plasma-enhanced atomic layer deposition (PEALD) to form a first insulating layer 381 and thermal atomic layer deposition (thermal ALD) to form a second insulating layer 382 (line A1), the brightness of the light emitted from the light-emitting element ED can increase over time after an electrical signal is applied to the light-emitting element ED, and can have a stable distribution after a specific time.

[0225] Reference Figure 15 In the case of a light-emitting element ED that uses thermal atomic layer deposition (thermal ALD) to form a first insulating layer 381 and a second insulating layer 382, ​​the brightness of the light emitted from the light-emitting element ED can decrease over time after an electrical signal is applied to the light-emitting element ED, and can have a stable distribution after a specific time.

[0226] The initial brightness values ​​of lines A1 and B1 (i.e., the brightness values ​​when the electrical signal is applied for 0 seconds) can be different from each other. For example... Figure 15As shown, the initial luminance value of line A1 can be greater than the initial luminance value of line B1. Therefore, since the initial luminance value of the rising line A1 is greater than the initial luminance value of the falling line B1, the luminance value of line A1 increasing over time can be greater than the luminance value of line B1. In other words, the light-emitting element ED of line A1 can have higher luminous efficiency and reliability than the light-emitting element ED of line B1.

[0227] like Figure 11 As shown, the light intensity distribution of a light-emitting element ED, which forms the second insulating layer 382 in the same manner using thermal atomic layer deposition (thermal ALD), can vary depending on whether the process for forming the first insulating layer 381 is plasma atomic layer deposition (PEALD) or thermal atomic layer deposition (thermal ALD). In other words, the light-emitting performance of the light-emitting element ED can depend on the deposition method of the first insulating layer 381.

[0228] When the process of forming the first insulating layer 381 is performed by atomic layer deposition (ALD), the thin film properties of the first insulating layer 381 can depend on whether the energy source is thermal energy or thermal and plasma. That is, the light-emitting characteristics of the light-emitting element ED can depend on whether the process for forming the first insulating layer 381 is plasma-enhanced atomic layer deposition (PEALD) or thermal atomic layer deposition (thermal ALD). For example, in the process of depositing the first insulating material layer 3810 to form the first insulating layer 381 (see...), the thin film properties of the first insulating layer 381 can be determined by... Figure 16 In this process, the first insulating layer 381 can have a high film density and / or large surface roughness because its reactivity is relatively high compared to the case using thermal atomic layer deposition (thermal ALD). Therefore, by forming the first insulating layer 381 using plasma-enhanced atomic layer deposition (PEALD) to fabricate the light-emitting element ED, it is possible to improve the thin film properties of the first insulating layer 381, such as film density and / or surface roughness, and thus improve the light-emitting properties of the light-emitting element ED.

[0229] In a method for manufacturing a light-emitting element (ED) according to one embodiment, silicon oxide (SiO2) is formed by using plasma-enhanced atomic layer deposition (PEALD) to form a material including a material having a first fixed charge. x The first insulating layer 381 improves the brightness characteristics of the light-emitting element ED. Therefore, the display quality of the display device 10, which includes the light-emitting element ED with improved brightness characteristics, can also be improved.

[0230] In the following description, other embodiments relating to a display device including a light-emitting element (ED) according to one embodiment will be described with reference to other accompanying drawings. In the following embodiments, descriptions of components identical to those in the above embodiments will be omitted or simplified, and the differences will be described primarily.

[0231] Figure 3 is an enlarged view illustrating another example of the portion Q of Figure 16

[0232] Referring to Figure 6 , the present embodiment differs from the embodiment of Figure 6 in that the third insulating layer 53 is omitted in the display device 10.

[0233] Specifically, the first contact electrode 41 and the second contact electrode 42 can be disposed directly on the second insulating layer 52. The first contact electrode 41 and the second contact electrode 42 can be spaced apart from each other on the second insulating layer 52 to expose a portion of the second insulating layer 52. The second insulating layer 52 exposed by the first contact electrode 41 and the second contact electrode 42 can contact the fourth insulating layer 54 in the exposed area.

[0234] In the present embodiment, even when the third insulating layer 53 is omitted in the display device 10, the second insulating layer 52 can include an organic insulating material to perform the function of fixing the light emitting element ED. Also, the first contact electrode 41 and the second contact electrode 42 can be simultaneously patterned and formed through a single mask process. Thus, since an additional mask process is not required to form the first contact electrode 41 and the second contact electrode 42, process efficiency can be improved. Except for the omission of the third insulating layer 53, the present embodiment is the same as the embodiment of Figure 17 , and thus redundant descriptions will be omitted.

[0235] Figure 3 is an enlarged view illustrating yet another example of the portion Q of Figure 17

[0236] Referring to Figure 6 , the present embodiment differs from the embodiment of Figure 17 in that, in the light emitting element ED_1 included in the display device 10, the second insulating layer 382_1 of the light emitting element ED_1 (together with the first insulating layer 381, collectively referred to as the insulating layer 380_1) is partially removed, and the first contact electrode 41 and the second contact electrode 42 contact the first insulating layer 381 positioned at both ends of the light emitting element ED_1.

[0237] Specifically, in the display device 10 according to the present embodiment, at least a portion of the second insulating layer 382_1 of the light emitting element ED_1 is removed so that the first insulating layer 381 positioned at both ends of the light emitting element ED_1 can be exposed in the third direction DR3. The first insulating layer 381 exposed by the removal of the second insulating layer 382_1 can be positioned at an upper portion of the display device 10 in a cross-sectional view. The first contact electrode 41 and the second contact electrode 42 can contact the first insulating layer 381 exposed by the second insulating layer 382_1. ​​

[0238] During the manufacturing process of the display device 10, a portion of the second insulating layer 382_1 of the light emitting element ED_1 can also be partially etched in a process of forming the second insulating layer 52 and / or the third insulating layer 53. Specifically, a portion of the second insulating layer 382_1 of the light emitting element ED_1 which is not overlapped with the second insulating layer 52 and is upwardly exposed can be etched. The etching selectivity (or etching rate) of the etchant used in the process for patterning the second insulating layer 52 or the third insulating layer 53 with respect to the second insulating layer 52 (or the third insulating layer 53) can be similar to or the same as the etching selectivity thereof with respect to the first insulating layer 381 of the light emitting element ED_1. In this case, in order to prevent the first insulating layer 381 from being damaged in the process of patterning the second insulating layer 52, the second insulating layer 382_1 can be disposed to surround the first insulating layer 381 to protect the first insulating layer 381. Accordingly, the second insulating layer 382_1 including a material different from that of the first insulating layer 381 (e.g., a material having a different fixed charge) can protect the first insulating layer 381 from the etchant.

[0239] In this case, as shown in FIG. 12B, the second insulating layer 382_1 can be partially etched in the process of patterning the second insulating layer 52. The first insulating layer 381 can be protected from the etchant by the second insulating layer 382_1 surrounding the outer circumferential surface of the first insulating layer 381 until the second insulating layer 382_1 exposed by the second insulating layer 52 is etched and completely removed. Accordingly, the first insulating layer 381 is prevented from being damaged in the patterning process of the second insulating layer 52 and / or the third insulating layer 53, so that the first semiconductor layer 310, the second semiconductor layer 320, and the element active layer 330 of the light emitting element ED_1 can be protected by the first insulating layer 381 surrounding the first semiconductor layer 310, the second semiconductor layer 320, and the element active layer 330. Figure 18

[0240] ​In this embodiment, since the display device 10 includes the light emitting element ED_1 including the first insulating layer 381 having the first fixed charge described above, the luminance deterioration of the light emitting element ED_1 can be improved. Further, since the light emitting element ED_1 includes the second insulating layer 382_1 surrounding the first insulating layer 381 and having a second fixed charge different from the first fixed charge, the second insulating layer 382_1 can protect the first insulating layer 381 in a process of patterning a plurality of insulating layers of the display device 10. Therefore, in this case, even when the etching selectivity of the etchant used in the process for patterning the second insulating layer 52 with respect to the second insulating layer 52 is similar to the etching selectivity thereof with respect to the first insulating layer 381, the second insulating layer 382_1 can protect the first insulating layer 381 in the manufacturing process of the display device 10. Therefore, since the display device 10 includes the light emitting element ED_1 having improved luminance efficiency, the light output efficiency of the display device 10 can be improved.

[0241] Figure 3 is an enlarged view showing Figure 18 a further example of the portion Q of

[0242] Referring Figure 17 , this embodiment differs from the embodiment of Figure 17 in that, in the light emitting element ED_2 included in the display device 10, the second insulating layer 382_2 of the light emitting element ED_2 (together with the first insulating layer 381, collectively referred to as the insulating layer 380_2) can have a different thickness for each region.

[0243] As described above, during the manufacturing process of the display device 10, in the process of forming the second insulating layer 52 and / or the third insulating layer 53, the second insulating layer 382_2 of the light emitting element ED_2 can also be partially etched. Therefore, the second insulating layer 382_2 can have a different thickness depending on the relative arrangement of the adjacent members.

[0244] In this embodiment, the etching selectivity of the etchant used in the process of patterning (forming) the second insulating layer 52 or the third insulating layer 53 with respect to the second insulating layer 52 (or the third insulating layer 53) can be different from the etching selectivity thereof with respect to the second insulating layer 382_2. For example, the etching selectivity of the etchant with respect to the second insulating layer 52 (or the third insulating layer 53) can be greater than the etching selectivity thereof with respect to the second insulating layer 382_2. Therefore, the second insulating layer 382_2 which is not superposed with the second insulating layer 52 can not be completely removed, but can be partially etched to remain on the first insulating layer 381.

[0245] The thickness of the second insulating layer 382_2 stacked on the second insulating layer 52 can be greater than the thickness of the second insulating layer 382_2 not stacked on the second insulating layer 52. In the second insulating layer 382_2 facing upward in the cross-sectional view, the thickness of the second insulating layer 382_2 stacked on the second insulating layer 52 can be greater than the thickness of the second insulating layer 382_2 not stacked on the second insulating layer 52 because the second insulating layer 382_2 stacked on the second insulating layer 52 is not etched during the manufacturing process.

[0246] Meanwhile, in the second insulating layer 382_2 facing upward in the cross-sectional view, the second insulating layer 382_2 not stacked on the second insulating layer 52 can be in contact with the first contact electrode 41 and the second contact electrode 42. Accordingly, the thickness of the second insulating layer 382_2 in contact with the first contact electrode 41 and the second contact electrode 42 can be less than the thickness of the second insulating layer 382_2 not in contact with the first contact electrode 41 and the second contact electrode 42.

[0247] In this embodiment, the thickness of the second insulating layer 382_2 stacked on the second insulating layer 52 can be greater than the thickness of the second insulating layer 382_2 not stacked on the second insulating layer 52. In the second insulating layer 382_2 facing upward in the cross-sectional view, the thickness of the second insulating layer 382_2 stacked on the second insulating layer 52 can be greater than the thickness of the second insulating layer 382_2 not stacked on the second insulating layer 52 because the second insulating layer 382_2 stacked on the second insulating layer 52 is not etched during the manufacturing process. Figure 19 In this embodiment, the thickness of the second insulating layer 382_2 stacked on the second insulating layer 52 can be greater than the thickness of the second insulating layer 382_2 not stacked on the second insulating layer 52. In the second insulating layer 382_2 facing upward in the cross-sectional view, the thickness of the second insulating layer 382_2 stacked on the second insulating layer 52 can be greater than the thickness of the second insulating layer 382_2 not stacked on the second insulating layer 52 because the second insulating layer 382_2 stacked on the second insulating layer 52 is not etched during the manufacturing process.

[0248] Figure 19 is a cross-sectional view of a light emitting element according to another embodiment.

[0249] Referring to Figure 5 In the light emitting element ED_3 according to this embodiment, the insulating layer 380_3 including the first insulating layer 381_3 and the second insulating layer 382_3 has a shape different from the shape of the insulating layer 380 of the light emitting element ED. Figure 12 In the light emitting element ED_3 according to this embodiment, the top surface or the upper cross-section of the first insulating layer 381_3 and the second insulating layer 382_3 has a partially inclined shape. The first insulating layer 381_3 and the second insulating layer 382_3 can include a region in which the thickness of the light emitting element ED_3 varies at one end of the light emitting element ED_3.

[0250] The second insulating layer 382_3 can surround the outer peripheral surface of the first insulating layer 381_3 while exposing a portion of the outer peripheral surface of the first insulating layer 381_3 at one end of the light emitting element ED_3. In this case, the length of the first insulating layer 381_3 in the extension direction X of the light emitting element ED_3 can be different from the length of the second insulating layer 382_3 in the extension direction X of the light emitting element ED_3. For example, the length of the first insulating layer 381_3 in the extension direction X of the light emitting element ED_3 can be greater than the length of the second insulating layer 382_3 in the extension direction X of the light emitting element ED_3. Although the drawings show that the second insulating layer 382_3 surrounds the outer peripheral surface of the first insulating layer 381_3 while exposing a portion of the outer peripheral surface of the first insulating layer 381_3, the present disclosure is not limited thereto. For example, the top surfaces of the first insulating layer 381_3 and the second insulating layer 382_3 are formed to be rounded, and the top surfaces of the first insulating layer 381_3 and the second insulating layer 382_3 are aligned with each other such that the second insulating layer 382_3 can be disposed to surround the outer peripheral surface of the first insulating layer 381_3 without exposing the first insulating layer 381_3.

[0251] The light emitting element ED_3 according to this embodiment can be formed based on a difference in etching selectivity of the first insulating layer 381_3 and the second insulating layer 382_3 including materials different from each other in an etching process for forming the first insulating layer 381_3 and the second insulating layer 382_3.

[0252] Specifically, referring to Figure 13 and Figure 19 , an etchant used in an etching process for forming the first insulating layer 381_3 and the second insulating layer 382_3 including materials different from each other can have different etching selectivity with respect to the first insulating layer 381_3 and the second insulating layer 382_3. Accordingly, when the etching selectivity of the etchant with respect to the second insulating layer 382_3 is higher than the etching selectivity of the etchant with respect to the first insulating layer 381_3, the etching rate of the second insulating layer 382_3 is higher than the etching rate of the first insulating layer 381_3. Accordingly, the second insulating layer 382_3 can expose a portion of the outer peripheral surface of the first insulating layer 381_3.

[0253] In addition, when portions of the first and second insulating material layers 3810 and 3820 are removed by an etch-back process without a separate etch mask in a vertical etching process for forming the first and second insulating layers 381_3 and 382_3, the upper portions of the first and second insulating layers 381_3 and 382_3 positioned on the electrode layer 370 can be formed to be rounded (as shown in Figure 20 ) due to the upper portions of the first and second insulating material layers 3810 and 3820 being exposed to an etchant for a longer time compared to the lower portions of the first and second insulating material layers 3810 and 3820.

[0254] Figure 20 is a cross-sectional view of a light emitting element according to yet another embodiment.

[0255] Referring to Figure 12 , the light emitting element core 300_1 of the light emitting element ED_4 according to this embodiment can include an electrode layer 370_1 having a surface irregularity at a top surface thereof. The surface irregularity (or surface roughness) can be formed at the top surface (e.g., the surface of the side facing the extension direction X) of the electrode layer 370_1 of the light emitting element ED_4 according to this embodiment. The surface irregularity can be randomly distributed. The surface irregularity can be formed in an etching process for removing portions of the first and second insulating material layers 3810 and 3820 to form the first and second insulating layers 381 and 382.

[0256] In particular, referring to Figure 13 and Figure 12 , the etching process for forming the first and second insulating layers 381 and 382 can be performed as an etch-back process. The first and second insulating material layers 3810 and 3820 disposed on the top surface of the electrode layer 370 (see Figure 12 ) of the core structure 300' (see Figure 20 ) are etched by an etchant used in the etching process, so that the top surface of the electrode layer 370_1 can be exposed. In this case, the exposed top surface of the electrode layer 370_1 is partially etched by the etchant, thereby forming the light emitting element ED_4 including the electrode layer 370_1 having a surface irregularity as shown in Figure 21 .

[0257] Figure 21 is a cross-sectional view of a light emitting element according to yet another embodiment.

[0258] Referring to Figure 5 , the light emitting element ED_5 according to this embodiment is similar to ​The light emitting element ED differs from the light emitting element ED_4 in that the insulating layer 380_5 includes three insulating layers 381, 382, and 383. Specifically, the insulating layer 380_5 of the light emitting element ED_5 can further include a third insulating layer 383 surrounding an outer circumferential surface of the second insulating layer 382. The third insulating layer 383 can include a material having a third fixed charge different from the second fixed charge of the second insulating layer 382. That is, the fixed charges of the materials included in the second insulating layer 382 and the third insulating layer 383 can be different from each other. For example, the third insulating layer 383 can include at least one of the insulating materials listed as the material that the first insulating layer 381 can include.

[0259] In an exemplary embodiment, when the first insulating layer 381 includes silicon oxide (SiO x ) having a first fixed charge and the second insulating layer 382 includes aluminum oxide (Al x O y ) having a second fixed charge different from the first fixed charge, the third insulating layer 383 can include silicon oxide (SiO x ) having a third fixed charge. However, the materials included in the first insulating layer 381, the second insulating layer 382, and the third insulating layer 383 are not limited thereto.

[0260] The thickness d3 of the third insulating layer 383 can be in the range of 5 nm to 100 nm, but is not limited thereto. Although the drawing shows that the thickness d3 of the third insulating layer 383 is smaller than the respective thicknesses d1 and d2 of the first insulating layer 381 and the second insulating layer 382, the relative size relationship between the thickness of the third insulating layer 383 and the thicknesses of the first insulating layer 381 and the second insulating layer 382 is not limited thereto. In a range in which the luminance of the light emitting element ED_5 is not reduced, the thickness d3 of the third insulating layer 383 can be the same as the thickness d1 of the first insulating layer 381 or the thickness d2 of the second insulating layer 382, or can be greater than the thickness d1 of the first insulating layer 381 and / or the thickness d2 of the second insulating layer 382.

[0261] In summarizing the detailed description, those skilled in the art will understand that many changes and modifications can be made to the preferred embodiments without substantially departing from the principles of the invention. Therefore, the preferred embodiments of the disclosed invention are used in a general and descriptive sense only and are not for the purpose of limitation.

Claims

1. A light-emitting element comprising: a light-emitting element core including a first semiconductor layer, a second semiconductor layer provided over the first semiconductor layer, and an element active layer provided between the first semiconductor layer and the second semiconductor layer; a first insulating layer formed on a side surface of the light-emitting element core so as to surround the side surface of the light-emitting element core, and having a first fixed charge; and a second insulating layer provided so as to surround an outer surface of the first insulating layer, and containing a material having a second fixed charge different from the first fixed charge, wherein each of the first fixed charge and the second fixed charge is a negative fixed charge, and a magnitude of the first fixed charge is larger than a magnitude of the second fixed charge. the first insulating layer contains at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum nitride, aluminum oxide, hafnium oxide, and zirconium oxide, and 2. The light-emitting element according to claim 1, wherein the second insulating layer contains at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum nitride, and aluminum oxide. the first insulating layer contains silicon oxide, and the second insulating layer contains aluminum oxide.

3. The light-emitting element according to claim 2, wherein the first insulating layer is provided directly on side surfaces of the first semiconductor layer, the second semiconductor layer, and the element active layer.

4. The light-emitting element according to claim 1, wherein 5. A display device comprising: a substrate; a first electrode provided over the substrate; a second electrode provided over the substrate and spaced apart from the first electrode; a light-emitting element provided over the substrate and having both ends provided over the first electrode and the second electrode, respectively; wherein the light-emitting element includes a light-emitting element core including a first semiconductor layer, a second semiconductor layer provided over the first semiconductor layer, and an element active layer provided between the first semiconductor layer and the second semiconductor layer; a first insulating layer formed on a side surface of the light-emitting element core so as to surround the side surface of the light-emitting element core, and having a first fixed charge; and a second insulating layer provided so as to surround an outer surface of the first insulating layer, and containing a material having a second fixed charge different from the first fixed charge, and wherein each of the first fixed charge and the second fixed charge is a negative fixed charge, and a magnitude of the first fixed charge is larger than a magnitude of the second fixed charge.

6. The display device according to claim 5, further comprising: a third insulating layer provided over the light-emitting element so as to expose the both ends of the light-emitting element; a first contact electrode provided over the first electrode and in contact with one end of the light-emitting element exposed by the first electrode and the third insulating layer; a second contact electrode provided over the second electrode and in contact with the other end of the light-emitting element exposed by the second electrode and the third insulating layer. a thickness of the second insulating layer exposed by the third insulating layer is smaller than a thickness of the second insulating layer not exposed by the third insulating layer. at the both ends of the light-emitting element, the second insulating layer exposes a part of the first insulating layer. ​ 7. The display device of claim 6, wherein, ​ 8. The display device of claim 7, wherein, ​ 9. A method of manufacturing a light-emitting element, the method comprising the steps of: forming a core structure on one surface of a base substrate; forming a first insulating material layer on an outer surface of the core structure using plasma atomic layer deposition, the first insulating material layer including a material having a first fixed charge, the first fixed charge being a negative fixed charge; forming a second insulating material layer on one surface of the first insulating material layer, the second insulating material layer including a material having a second fixed charge different from the first fixed charge, the second fixed charge being a negative fixed charge, and a magnitude of the first fixed charge being greater than a magnitude of the second fixed charge; forming an element rod by partially removing the first insulating material layer and the second insulating material layer to expose a top surface of the core structure; and separating the element rod from the base substrate. The step of forming the first insulating material layer includes:

10. The method of claim 9, wherein, providing a precursor onto the core structure; providing a reactive gas onto the core structure; and generating a plasma of the reactive gas on the core structure. The first insulating material layer includes silicon oxide, the second insulating material layer includes aluminum oxide, the precursor includes a silicon-containing precursor, and the reactive gas includes oxygen.

11. The method of claim 10, wherein, The step of forming the core structure includes:

12. The method of claim 9, wherein, forming a first stack structure including a first semiconductor material layer on the base substrate, an element active material layer on the first semiconductor material layer, and a second semiconductor material layer on the element active material layer; and vertically etching the first stack structure in a direction perpendicular to a top surface of the base substrate. ​

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