Systems, methods, devices, and data structures for digital pixel sensors

Abstract

Some embodiments relate to an imaging system comprising active pixels, a comparator, a write control circuit, and an analog-to-digital conversion (ADC) circuit. The active pixels may include a photodiode and a plurality of transistors. The comparator is operably coupled to the active pixels and configured to receive an output of the active pixels. The write control circuit is operably coupled to the comparator and configured to receive an output from the comparator. An ADC memory is operably coupled to the write control circuit. A data structure is stored in the ADC memory and is configured to store at least a first data string, wherein the first data string includes a set of flag bits for identifying each ADC operation performed and a set of ADC data bits.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 63029057, filed May 22, 2010, entitled “System, Method, Device and Data Structure for Digital Pixel Sensors,” the disclosure of which is hereby incorporated by reference in its entirety. Technical Field

[0003] The present application relates to a digital pixel sensor (DPS) imaging system and an analog-to-digital conversion circuit thereof, and in particular to an image sensor system having a write control circuit, an integrated positive feedback circuit, and an initialization circuit. Background Art

[0004] Digital pixel sensors (DPS) for image sensing applications are known. Image sensor systems utilizing complementary metal-oxide semiconductor (CMOS) photodiodes are also known, with the CMOS photodiodes being used in an active pixel configuration with multiple transfer gates in the pixel region. However, these known DPS systems are unable to achieve complete charge transfer from the pixel region when the pixel size is scaled. The lack of complete charge transfer negatively impacts noise, fill factor, hysteresis, and other properties of the DPS.

[0005] DPS systems that include a light conversion section and an application-specific integrated circuit (ASIC) section for signal processing are also known. However, since these DPS systems implement flag bits separately from analog-to-digital converter (ADC) data bits, they require independent read control signals for the flag bits during write control and read operation, necessitating a complex read process. Another technical problem with these DPS systems is that the complex read process increases the number of wires required for the DPS system, which may interfere with DPS systems with small pixel sizes. Summary of the Invention

[0006] Thus, one or more aspects of the present disclosure relate to an image sensor system. The image sensor system includes one or more active pixels, each active pixel coupled to an analog-to-digital conversion (ADC) circuit. In some embodiments, the ADC includes a comparator, a memory coupled to a data bus, and a write control circuit. Some aspects relate to a solid-state device for a DPS imaging system. In some embodiments, the solid-state device includes at least one pixel region configured for bidirectional charge transfer. The solid-state device includes: a first transfer gate and a second transfer gate having a first polysilicon layer and a first charge well layer, the first transfer gate and the second transfer gate being configured to cause an electron drift current from a first side of the pixel region to a second side of the pixel region, thereby providing bidirectional transfer based on the operation of the first and second transfer gates.

[0007] Another aspect of the present disclosure relates to a device for use in a DPS image sensor including a pixel circuit. In some embodiments, the pixel circuit includes at least two transfer gates, a photodiode region, and a floating diffusion region. In some embodiments, the pixel circuit is configured to optimize charge movement from the photodiode region to the floating diffusion region via an induced electric field of a first transfer gate and a second transfer gate.

[0008] Another aspect of the present disclosure relates to a method for forming a DPS semiconductor device. In some embodiments, the method includes providing a base layer and forming a first injection layer having a first conductive characteristic on the base layer. In some embodiments, the method includes: forming a second injection layer having a second conductive characteristic on at least a portion of the first layer; and forming at least a first transfer gate and a second transfer gate on the second injection layer. In some embodiments, operation of the first and second transfer gates induces an electron drift current from the first injection layer to the second injection layer. In some embodiments, the electron drift current corresponds to bidirectional charge transfer from the base layer to the first injection layer and from the first injection layer to the first gate or the second gate.

[0009] Yet another aspect of the present disclosure relates to a DPS device for indirect time-of-flight measurement. In some embodiments, the DPS device includes a photodiode, a first floating diffusion, a second floating diffusion, a first transfer gate, and a second transfer gate. In some embodiments, the DPS device is configured to implement a method for determining the physical distance to an object proximate to the DPS device. In some embodiments, the method includes transferring charge collected by the photodiode to the first floating diffusion or the second floating diffusion by switching the first transfer gate or the second transfer gate, and determining a delay in a received pulse based on the charge in the first or second floating diffusion. In some embodiments, determining the distance to the physical object is based on the delay.

[0010] Some aspects of the present disclosure relate to a data structure for use in an image sensor system having at least one ADC, a write control circuit, a state latch, and an ADC memory. In some embodiments, the data structure includes a flag bit and an ADC bit. In some embodiments, the flag bit is configured for state control for the at least one ADC, which utilizes the write control circuit and the data latch to transmit the data structure.

[0011] These and other objects, features, and characteristics of the present disclosure, as well as the methods of operation and functions of the related structural elements, and the economy of assembly and manufacture of the parts, will become more apparent when the following description and appended claims are considered with reference to the accompanying drawings, all of which form a part of this specification, in which like reference numerals designate corresponding parts in the different drawings. It is to be expressly understood, however, that the drawings are for purposes of illustration and description only and are not intended as a definition of the scope of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1A is a schematic diagram of an example DPS image sensing system according to one or more embodiments.

[0013] Figure 1B is a schematic diagram of another example DPS image sensing system according to one or more embodiments.

[0014] Figure 2A-2B is a schematic diagram of an example active pixel according to one or more embodiments.

[0015] Figure 3A-3B According to one or more embodiments Figure 2A-2B Circuit diagram of an example active pixel.

[0016] Figure 4A-4B is a schematic diagram of an example active pixel according to one or more embodiments.

[0017] Figure 5A-5B According to one or more embodiments Figure 4A-4B Circuit diagram of an example active pixel.

[0018] Figures 6A and 6B is a schematic diagram of an example active pixel according to one or more embodiments.

[0019] Figures 7A and 7B According to one or more embodiments Figures 6A and 6B Circuit diagram of an example active pixel.

[0020] Figures 8A and 8B is a schematic diagram of top and side views of an example active pixel according to one or more embodiments.

[0021] Figures 9A and 9B is a schematic diagram of top and side views of an example active pixel according to one or more embodiments.

[0022] Figures 10A and 10B is a charge potential diagram depicting simulation results of an example active pixel according to one or more embodiments.

[0023] Figures 11A to 11C is a schematic diagram of top and side views of an example active pixel according to one or more embodiments.

[0024] Figures 12A and 12B is a schematic diagram of an example non-shared active pixel system and an example shared active pixel system according to one or more embodiments.

[0025] Figure 13 is a schematic diagram of an example shared active pixel system according to one or more embodiments.

[0026] Figure 14 is a method according to one or more embodiments corresponding to Figures 12A and 12B and Figure 13 Example timing diagram for an active pixel system.

[0027] Figure 15 is a schematic diagram of an example back-end ADC storage circuit according to one or more embodiments.

[0028] Figure 16 is a schematic diagram of an example back-end ADC storage circuit according to one or more embodiments.

[0029] Figure 17 is a timing diagram illustrating exemplary operation of an example back-end ADC storage circuit according to one or more embodiments.

[0030] Figures 18A-18B is a diagram of an example data structure in accordance with one or more embodiments.

[0031] Figure 18C is a schematic diagram of an example memory array according to one or more embodiments.

[0032] Figure 19 is a timing diagram illustrating exemplary operation of a back-end ADC storage circuit according to one or more embodiments.

[0033] Figure 20 is a schematic diagram of an example DPS image sensing system according to one or more embodiments.

[0034] Figure 21 is a schematic diagram of an example system including read / write control circuitry and data storage according to one or more embodiments.

[0035] Figure 22 is a timing diagram illustrating exemplary operation of an ADC according to one or more embodiments.

[0036] Figures 23A-23C is a diagram of an exemplary data structure according to one or more embodiments.

[0037] Figure 24 is a timing diagram illustrating exemplary operation of an ADC according to one or more embodiments.

[0038] Figure 25 is a schematic diagram of an example system including a read / write control circuit and a status lock according to one or more embodiments.

[0039] Figure 26 is a schematic diagram of an example system including a read / write control circuit and a status lock according to one or more embodiments.

[0040] Figure 27 is a timing diagram illustrating exemplary operation of an ADC according to one or more embodiments.

[0041] Figures 28A to 28C is a diagram of an exemplary data structure according to one or more embodiments. DETAILED DESCRIPTION

[0042] The present application will now be described in detail with reference to the accompanying drawings, which are provided as illustrative examples of the present invention to enable those skilled in the art to implement the invention. It is noted that the following figures and examples are not intended to limit the scope of the present invention to a single embodiment, but other embodiments may be implemented by exchanging some or all of the elements described or illustrated.

[0043] In addition, where certain elements of the present invention can be partially or completely implemented using known components, only those parts of such known components that are necessary for understanding the present application will be described, and detailed descriptions of other parts of such known components will be omitted so as not to obscure the present invention. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. As used herein, the statement that two or more parts or components are "coupled" shall mean that the parts are joined together or operate together, directly or indirectly (i.e., through one or more intermediate parts or components, as long as a connection occurs).

[0044] Embodiments described as being implemented in hardware should not be limited thereto, but rather may include embodiments implemented in software or a combination of software and hardware, and vice versa, unless otherwise stated herein, as would be apparent to one skilled in the art. In the exemplary embodiments described herein, embodiments showing a single component should not be considered limiting; rather, other embodiments including multiple identical components are also included, and vice versa, unless otherwise expressly stated herein. In addition, no term in this specification or claims is to be considered to have an uncommon or special meaning unless expressly stated otherwise. In addition, this application covers current and future known equivalents of known components mentioned herein by way of illustration.

[0045] As used herein, "directly coupled" means that two elements are in direct contact with each other. As used herein, "fixedly coupled" or "fixed" means that two components are coupled so as to move as one while maintaining a constant orientation relative to each other. As used herein, "operably coupled" means that two elements are coupled in such a way that the two elements function together. It should be understood that two elements that are "operably coupled" do not require a direct connection or permanent connection between them.

[0046] As used herein, the word "single" means that a component is created as a single piece or single unit. That is, a component that includes multiple pieces that are created separately and then coupled together as a unit is not a "single" component or body. As used herein, a statement that two or more parts or components "engage" one another shall mean that the parts apply forces to one another directly or through one or more intermediate parts or components. As used herein, the term "number" shall refer to one or an integer greater than one (i.e., a plurality). Directional terms used herein, such as, but not limited to, top, bottom, left, right, up, down, front, back, and their derivatives, refer to the orientation of elements shown in the drawings and do not limit the claims unless expressly stated therein.

[0047] As discussed in further detail below, the methods, systems, devices, and apparatus of the embodiments described in the present disclosure may include an active pixel sensor (e.g., a complementary metal oxide semiconductor (CMOS) sensor) configured to perform charge transfer in a photodiode by generating an electric field. As discussed in further detail below, the generated electric field can be facilitated by the operation of two transfer gates. The operation of the two transfer gates can induce drift current in both directions, thereby providing bidirectional and complete charge transfer from the photodiode to the floating diffusion region. As a result, the technical effect of reducing latency can be achieved.

[0048] Figure 1AFIG2 is a schematic diagram of an example DPS image sensing system 100A according to one or more embodiments. DPS image sensing system 100A may include sensing front-end circuitry 112 operatively coupled to back-end ADC storage circuitry 115. Back-end ADC storage circuitry is referred to interchangeably herein as back-end ADC storage circuitry. In some embodiments, sensing front-end circuitry 112 may be operatively coupled to back-end ADC storage circuitry 115 via coupling capacitor Cc. In some embodiments, sensing front-end circuitry 112 may include active pixels 110. As described herein, the term "active pixel" may be referred to interchangeably with the term "pixel device." In some embodiments, back-end ADC storage circuitry 115 includes one or more instances of comparator 120, write control circuitry 130, state latch 140, ADC memory 150, coupling capacitor Cc, or other components. As described herein, the terms "pixel sensor," "pixel," "digital pixel," and "pixel portion" refer to one or more instances of one or more photodetectors, photodiodes, photovoltaic devices, solid-state transistor devices, or other image sensing components and are used interchangeably herein. Additionally, as described herein, the terms "photodiode" and "photodetector" refer to a two-terminal optoelectronic solid-state semiconductor device having photosensitive properties and may be used interchangeably herein.

[0049] In some embodiments, the DPS image sensing system 100A can be used in a 2D array of active pixels, each active pixel having dedicated signal processing circuitry (e.g., comparator 120, write control circuitry 130, ADC memory 150) coupled to a read / write data bus 160. A time code can be provided to the read / write data bus 160 from a time code generator (not shown). As understood by one of ordinary skill in the art, the time code is a count value. The time code corresponds to an ADC code, which will be further described below. In some embodiments, the 2D array of active pixels with dedicated signal processing circuitry can be packaged as an on-chip DPS. The on-chip DPS package can include bonding components, protective glass, and / or other components. For example, the on-chip DPS package can include contact pads for operably coupling the on-chip DPS to a printed circuit board (PCB).

[0050] The comparator 120 may include a 1-bit comparator coupled to a latch (eg, a state latch 140). In some embodiments, the comparator 120 may be configured to generate a voltage by dividing the input voltage (eg, V sig ) into the corresponding numeric value (for example, Figure 1AADC functionality is provided using the midpoint value of VRAMP shown in entry 107 of the back-end ADC storage circuit 115. In some embodiments, the state latch 140 and write control circuit 130 of the back-end ADC storage circuit 115 can communicate with the ADC memory 150. In some embodiments, the output of the state latch 140 is used to control ADC operation. For example, ADC operation can be controlled using a 1-bit Boolean control signal that can be latched at and output from the state latch 140. ADC operation can include one or more different modes. For example, ADC operation can include timestamp ADC operation, high conversion gain ADC (HCG ADS), and low conversion gain ADC (LCG ADC).

[0051] The following reference Figure 17 Additional details regarding status latch 140 and its functionality can be found.

[0052] ADC memory 150 can be configured to store data bits that correspond to the state data (e.g., STATE_DATA 142) held in state latch 140. In some embodiments, ADC memory 150 can include a Gray code counter. In some embodiments, ADC memory 150 includes flag bits and data bits that can utilize a DPS data structure described in further detail below.

[0053] The write control circuit 130 includes a positive feedback circuit 131 and an initialization circuit 132. In some embodiments, the positive feedback circuit 131 is a multi-input logic gate that is configured to take the output from the comparator 120 as a first input and the output from the positive feedback circuit 131 as a second input. For example, the logic gate may be a NOR gate. The positive feedback circuit 131 may also include an inverter that is configured to take the output of the logic gate (e.g., a NOR gate) as an input. In some embodiments, the initialization circuit 132 includes a pair of transistors configured to act as a NAND gate. For example, the transistor pair may be a pMOS transistor pair, which refers to Figure 15 In some embodiments, when the signal (FB) from the positive feedback circuit 131 is FB=1, the positive feedback circuit 131 is locked. The initialization circuit 132 is used to release the positive feedback circuit 131 from the lock using the control signal received from the status latch 140.

[0054] Figure 1Bis a schematic diagram of another example DPS image sensing system 100B according to one or more embodiments. In some embodiments, the active pixel 110 is formed in the first substrate 111, and each element included in the back-end ADC storage circuit 115 (e.g., comparator 120, write control circuit 130, state latch 140, ADC memory 150) can be formed in the second substrate 106. The term "active pixel" is interchangeably referred to as a "photoelectric conversion reading portion" herein. The active pixel 110 of the DPS image sensing system 100B may include a photodiode (photoelectric conversion element) and an in-pixel amplifier. More specifically, the active pixel 110 may include, for example, a photodiode PD1 as a photoelectric conversion element. For the photodiode PD1, a transfer transistor TG1-Tr is provided as a transfer element, a reset transistor RST1-Tr is provided as a reset element, a source follower transistor SF1-Tr is provided as a source follower element, a current transistor IC1-Tr is provided as a current source element, a storage transistor CG1-Tr is provided, a storage capacitor CS1 is provided as a storage capacitor element, a floating diffusion FD1 is provided as an output node ND1, and a read node ND2 is provided. As described above, the active pixel 110 may include five transistors (5Tr), namely, the transfer transistor TG1-Tr, the reset transistor RST1-Tr, the source follower transistor SF1-Tr, the current transistor IC1-Tr, and the storage transistor CG1-Tr.

[0055] In some embodiments, source follower transistors SF1-Tr, current transistors TC1-Tr, and read node ND2 together constitute output buffer portion 103. In some embodiments, storage transistors CG1-Tr and storage capacitor CS1 serving as storage capacitance elements collectively constitute charge storage portion 102.

[0056] In some embodiments, the read node ND2 of the output buffer portion 103 of the active pixel 110 is connected to the input portion of the back-end ADC storage circuit 115. In some embodiments, the active pixel 110 may convert the charge in the floating diffusion FD1 serving as the output node into a voltage signal of a level corresponding to the amount of charge, and output the voltage signal V sig Output to the back-end ADC storage circuit 115.

[0057] In the first comparison operation period of the back-end ADC storage circuit 115, the active pixel 110 outputs a voltage signal V corresponding to the overflowing charge overflowing from the photodiode PD1. sig , where the photodiode PD1 is a photoelectric conversion element, and outputs to the floating diffusion FD1 as an output node in the storage period.

[0058] In some embodiments, during the second comparison operation period of the back-end ADC storage circuit 115, the active pixel 110 outputs a voltage signal Vsig corresponding to the charge stored in the photodiode PD1, which is transferred to the floating diffusion FD1 serving as the output node during the transfer period following the storage period. During the second comparison operation period, the active pixel 110 outputs a read reset signal (signal voltage) and a read signal (signal voltage) as pixel signals to the back-end ADC storage circuit 115.

[0059] Furthermore, during the third comparison operation period of the back-end ADC storage circuit 115, the active pixel 110 outputs a voltage signal Vsig corresponding to the sum (aggregate) of the charge stored in the charge storage portion 102 and the charge stored in the photodiode PD1. The charge stored in the photodiode PD1 is transferred to the floating diffusion FD1 serving as the output node during the transfer period following the storage period. During the third comparison operation period, the active pixel 110 outputs a read reset signal (signal voltage) and a read signal (signal voltage) as pixel signals to the back-end ADC storage circuit 115.

[0060] In some embodiments, the active pixel 110 may perform a first conversion gain reset read operation during a first reset period to read a first read reset signal from the output buffer portion 103. The first read reset signal is obtained by a first conversion gain (e.g., a high conversion gain: HCG) determined by a first charge amount at the floating diffusion FD1 serving as the output node ND1. The active pixel 110 may perform a first conversion gain signal read operation during a read period following a transfer period after the first reset period to read a first read signal from the output buffer portion 103. The first read signal is obtained by conversion of the first conversion gain (HCG) determined by the first charge amount at the floating diffusion FD1 serving as the output node ND1.

[0061] Subsequently, the active pixel 110 may perform a second conversion gain signal read operation to read a second read signal from the output buffer portion 103. The second read signal is obtained by conversion using a second conversion gain (e.g., a low conversion gain: LCG). The second conversion gain is determined by a second charge amount equal to the sum of the charge at the storage capacitor CS1 and the charge at the floating diffusion FD1 as the output node ND1. Thereafter, the active pixel 110 performs a second conversion gain reset read operation in a second reset period to read a second read reset signal from the output buffer portion 103. The second read reset signal is obtained by conversion using a second conversion gain (LCG) determined by the second charge amount.

[0062] As described above, in some embodiments, the DPS image sensing system 100B can be a solid-state imaging device that operates in a timestamp (TS) mode in a first comparison operation period of the back-end ADC storage circuit 115, operates in an HCG (first conversion gain) mode in a second comparison operation period, and operates in an LCG (second conversion gain) mode in a third comparison operation period.

[0063] The photodiode PD1 generates a signal charge (electron) in an amount determined by the amount of incident light and stores the same amount of signal charge (electron). The following description will be given for the case where the signal charge is electrons and each transistor is an n-type transistor. However, the signal charge may also be a hole, or each transistor may also be a p-type transistor. Further, in some embodiments, multiple photodiodes and transfer transistors share a transistor.

[0064] In some embodiments, the photodiode (PD) in each active pixel 110 may be a pinned photodiode (PPD). On the surface of the substrate used to form the photodiode (PD), dangling bonds or other defects may exist at the surface level. Consequently, a large amount of charge (dark current) may be generated due to thermal energy, preventing the signal from being correctly read. In a pinned photodiode (PPD), the surface of the charge storage portion of the photodiode (PD) may be pinned to reduce the mixing of dark current into the signal.

[0065] The transfer transistor TG1-Tr of the active pixel 110 can be connected between the photodiode PD1 and the floating diffusion FD1 and controlled by the control signal TG applied to its gate via the control line. During the transfer period when the control signal TG is at a high (H) level, the transfer transistor TG1-Tr can remain selected and in a conductive state to transfer the charge (electrons) generated by photoelectric conversion and then stored in the photodiode PD1 to the floating diffusion FD1. After the photodiode PD1 and the floating diffusion FD1 are reset to a predetermined reset potential, the transfer transistor TG1-Tr can enter a non-conductive state, in which the control signal TG is set to a low (L) level, and the photodiode PD1 enters a storage period. In these cases, if the intensity of the incident light is very high (for example, the amount of incident light is very large), the charge exceeding the saturation charge may overflow into the floating diffusion FD1 because the overflowing charge may pass under the transfer transistor TG1-Tr. If incident light has very high illuminance, for example, charges above the saturation charge amount at the floating diffusion FD1 may overflow to the storage capacitor CS1 because the overflowing charges pass under the storage transistor CG1 -Tr.

[0066] Reset transistor RST1-Tr is connected between a supply line Vaapix for a supply voltage VAAPIX and floating diffusion FD1, and is controlled by a control signal RST applied to its gate via a control line. During a reset period in which control signal RST is at an H level, reset transistor RST1-Tr remains selected and conductive, resetting floating diffusion FD1 to the potential of supply line Vaapix for a supply voltage VAAPIX.

[0067] The storage transistor CG1-Tr is connected between the floating diffusion FD1 and the reset transistor RST1-Tr, and the storage capacitor CS1 is connected between (i) the connection node ND3 between the floating diffusion FD1 and the reset transistor RST1-Tr and (ii) the reference potential VSS. The storage transistor CG1-Tr is controlled by the control signal DCG applied to its gate via the control line. The storage transistor CG1-Tr remains in a selected state and is in a conductive state during the reset period when the control signal DCG is at an H level so as to connect the floating diffusion FD1 and the storage capacitor CS1. Here, the DPS image sensing system 100B can also be configured so that the active pixel 110 selectively connects (couples) the floating diffusion FD1 and the storage capacitor CS1 used as the output node according to the illumination of the signal.

[0068] The source follower transistor SF1-Tr used as a source follower element is connected to the read node ND2 at its source, to the power supply line Vaapix at its drain, and to the floating diffusion FD1 at its gate. The drain and source of the current transistor TC1-Tr used as a current source element are connected between the read node ND2 and the reference potential VSS (e.g., GND). The gate of the current transistor IC1-Tr is connected to the feeder of the control signal VBNPIX. The signal line LSGN1 between the read node ND2 and the input part of the back-end ADC storage circuit 115 is driven by the source follower transistor SF1-Tr used as the current source element and / or the current transistor IC1-Tr.

[0069] Figure 2A-2B are schematic diagrams of example active pixels 210 and 260 , respectively, according to one or more embodiments. Figure 2A A schematic diagram of a top view 200 of an active pixel 210 is depicted. Figure 2A A schematic diagram depicting a top view 250 of an active pixel 260 is shown. In some embodiments, the active pixel 210 may be Figure 1A Alternatively, the active pixel 210 may be the same as or similar to the active pixel 110 of FIG. 1 . Alternatively, with appropriate modifications, for example, including a single transfer gate instead of two transfer gates, the active pixel 210 may be the same as or similar to the active pixel 110 of FIG. Figure 1B1. In some embodiments, active pixel 210 corresponds to a non-shared floating diffusion structure including a bidirectional charge transfer photodiode (PD) 212. In some embodiments, active pixel 210 acts as a fixed photodiode for backside illumination. The term "non-shared" refers to the fact that floating diffusion nodes 224 and 226 are configured to receive charge transferred from a single instance of PD 212. In some embodiments, Figure 1A DPS image sensing system 100A or Figure 1B The DPS image sensing system 100B receives signals from a common floating diffusion node, which is discussed in further detail below.

[0070] Active pixel 210 may include PD 212 operatively coupled to transfer gates 214 and 216, also interchangeably referred to herein as TD 214 and 216. In some embodiments, transfer gates 214 and 216 reside asymmetrically on opposite sides of PD 212. For example, transfer gate 214 may reside at the upper right corner of PD 212, while transfer gate 216 may reside at the lower right corner of PD 212. Transfer gates 214 and 216 may include floating diffusion nodes 224 and 226, respectively. In some embodiments, transfer gates 214 and 216 may include an active layer intersecting a polysilicon layer and a charge trap layer configured as a floating diffusion layer. Figure 2B is similar to 216 except that the transfer gate 216 outputs the charge to the drain 227 instead of the floating diffusion node 226. Figure 2A Schematic diagram of active pixel 210 and active pixel 260.

[0071] In some embodiments, transfer gates 214 and 216 can facilitate complete intra-pixel charge transfer within PD 212 by enabling the generation of electron drift currents. Figure 2A and 2B, an electron flow 219 corresponding to an electron drift current is depicted. The electron flow 219 can be directed from the first side 218 of the PD 212 to the second side 220 of the PD 212 area (e.g., from point X to point X'). In this case, the drift current is directed from the second side 220 of the PD 212 to the first side 218 of the PD 212 area (e.g., from point X to point X'). The electron drift current 219 is caused by a drift electric field. The electric field applied to the active pixel 210 causes the electrons in the PD 212 to move in a particular direction based on the applied electric field. In some embodiments, the electric field is generated by an impurity concentration gradient of the PD 212, which is discussed in further detail below. Moreover, by forming an electric field in the PD 212 (e.g., via implementing an impurity concentration gradient of the PD 212), and by the operation of two (2) transfer gates (e.g., transfer gates 214 and 216), bidirectional charge transfer of electrons of the PD 212 can be achieved. As described herein, "bidirectional charge transfer" means that the number of charge transfer directions is two (2). The bidirectional charge transfer functionality, as well as the full intra-pixel charge transfer functionality of the active pixel 210, can be used in a variety of applications. Some examples of applications in which the bidirectional charge transfer functionality and the full intra-pixel charge transfer functionality can be implemented include, but are not limited to (this is not intended to be limiting), high dynamic range readout and time-of-flight (ToF) readout, which are described in further detail below.

[0072] In some embodiments, transfer gates 214 and 216 can be configured to generate an electron flow 219 corresponding to a drift current in a direction from first side 218 of PD 212 to second side 220 of PD 212 (e.g., from point X to point X'). Thus, electron flow 219 can generate bidirectional charge transfer 221. In some embodiments, the electron drift current (e.g., the electron drift current corresponding to electron flow 219) formed by the electric field applied to active pixel 210 can increase the conductivity in the area surrounding first side 218 of PD 212 and the area surrounding second side 220 of PD 212. For example, the increased conductivity can induce charge transfer of charged particles (e.g., electrons) from point X on first side 218 of PD 212 to point X' on second side 220 of PD 212. The electric field that generates electron flow 219 can attract electrons from second side 220 of PD 212. When the operation of transfer gates 214 and 216 modulates the electric field near transfer gates 214 and 216, electrons may be transferred from transfer gates 214 and 216 to floating diffusion node 224 or floating diffusion node 226, respectively. However, in active pixel 260, electrons may be transferred from transfer gates 214 and 216 to floating diffusion node 224 or drain 227, respectively.

[0073] Figure 3A-3B According to one or more embodiments Figure 2A-2B Circuit diagram of an example active pixel. Figure 3A including active pixels 310, with Figure 2A The active pixels 210 are the same or similar. Figure 3B Including Figure 2B Active pixel 260 is the same as or similar to active pixel 360 . Active pixel 210 includes PD 212 operatively coupled to floating diffusion nodes 224 and 226 . Figure 3B and Figure 3A The difference is that the transfer gate 216 is operatively coupled to the drain 227. In some embodiments, the PD 212 utilizes a backside illumination (BSI) pinned photodiode or a front illumination (FSI) pinned photodiode.

[0074] In some embodiments, the charge collected by PD 212 is transferred to floating diffusion node 224. The voltage potential of floating diffusion node 224 can be monitored by source follower (SF) 225 of active pixel 310. Floating diffusion nodes 224 and 226 can be reset or mixed by a transistor reset signal (RST) or a mixing transistor (BIN) before charge transfer (e.g., from the region of active pixel 310 or 360 to transfer gates 214 and 216 and then to floating diffusion nodes 224 and 226, respectively; or from transfer gate 214 to floating diffusion node 224, and from transfer gate 216 to drain 227). In some embodiments, pixel mixing of active pixel 310 or 360 can be implemented by BIN as part of a clocking scheme for combining charge collected by several adjacent pixels. This can have the technical effect of reducing noise and improving the signal-to-noise ratio and frame rate of DPS image sensing system 100B. In some embodiments, row select transistor (SEL) 229 can be included in active pixels 310 and 360. The row select transistor 229 can be sig The read / write data bus is operatively coupled to the source follower 225 .

[0075] Figure 4A-4B are schematic diagrams of example active pixels 410 and 460 , respectively, according to one or more embodiments. Figure 5A-5B They are Figure 4A-4B 4 and 460. Specifically, Figure 4A FIG4 is a top view 400 of an example of an active pixel 410. In some embodiments, the active pixel 410 may include Figure 1A Alternatively, active pixel 410 may be used with the DPS image sensing system 100A (e.g., in place of active pixel 110 or in addition to active pixel 110) by appropriate modifications, such as including a single transfer gate instead of two transfer gates. Figure 1B The active pixels 110 are the same or similar. Figure 4B A top view 450 of an example of an active pixel 460 that may alternatively or additionally be used as Figure 1A or Figure 1B Active pixels (eg, active pixel 110 ) in the DPS image sensing systems 100A-100B.

[0076] In some embodiments, active pixel 410 may include two (2) photodiodes (PDs) 412A and 412B. PD 412A may be operably coupled to transfer gates 414A and 416A, and PD 412B may be operably coupled to transfer gates 414B and 416B. Transfer gates 414A and 416A may reside on asymmetric opposite sides of PD 412A, and transfer gates 414B and 416B may reside on asymmetric opposite sides of PD 412B. In some embodiments, transfer gates 414A, 414B, 416A, and 416B include an active layer intersecting a polysilicon layer and a charge trap layer configured as a floating diffusion layer. Transfer gates 414A and 416A include floating diffusion nodes 424 and 426, respectively. Transfer gates 414B and 416B also include floating diffusion nodes 424 and 426, respectively. Thus, floating diffusion node 424 may be “shared” by transfer gates 414A and 414B, and floating diffusion node 426 may be “shared” by transfer gates 416A and 416B. Transfer gates 414A, 414B, 416A, and 416B may provide charge transfer to floating diffusion nodes 424 and 426 . Figure 4B is similar to the embodiment of the present invention, except that transfer gates 416A and 416B output charge to drain 427 instead of a floating diffusion node (e.g., floating diffusion node 426). Figure 4A Schematic diagram of active pixel 410 and active pixel 460.

[0077] In some embodiments, active pixels 410 and 460 can achieve bidirectional charge transfer and full intra-pixel charge transfer within PD 412A and PD 412B by having an electric field generated by or otherwise applied to PD 412A and PD 412B. Applying the electric field can cause electron drift currents to be generated within PD 412A and PD 412B, respectively. Figure 4A and 4B, an electron flow 419A corresponding to an electron drift current generated within PD 412A and an electron flow 419B corresponding to an electron drift current generated within PD 412B are depicted. For example, electron flow 419A may be generated in PD 412A in response to applying an electric field to PD 412A. Electron flow 419A may be directed from a first side 418A of PD 412A to a second side 420A of PD 412A (e.g., from point XA to point X1). Similarly, electron flow 419B may be generated in PD 412B in response to applying an electric field to PD 412B. Electron flow 419B may be directed from a first side 418B of PD 412B to a second side 420B of PD 412B (e.g., from point XB to point X2). In some embodiments, the same electric field may be applied to both PDs 412A and 412B, while in other embodiments, different electric fields may be applied to PDs 412A and 412B. The applied electric field can generate electron currents 419A and 419B with different directions. For example, the electron currents 419A and 419B corresponding to the electron drift current can have equal magnitudes but opposite directions. The electron currents 419A and 419B can be caused by an electric field applied to the active pixel 410 (or active pixel 460), which causes the electrons in PD412A and PD412B to move in a specific direction based on the applied electric field. In some embodiments, the electric field is generated by the impurity concentration gradient of PD412A and PD412B, which is discussed in further detail below. In addition, by forming an electric field in PD412A and PD412B (e.g., via the impurity concentration gradient of PD212), and by the operation of two (2) transfer gates (e.g., transfer gates 414A and 416A and transfer gates 414B and 416B), bidirectional charge transfer of electrons in each of PD412A and 412B can be achieved. The bidirectional charge transfer functionality and the full intra-pixel charge transfer functionality of the active pixels 410 and 460 can be used in a variety of applications. Some examples of applications in which the bidirectional charge transfer functionality and the full intra-pixel charge transfer functionality can be implemented include, but are not limited to (this other list is not intended to be limiting), high dynamic range readout and time-of-flight (ToF) readout, which are described in further detail below.

[0078] In some embodiments, electron flow 419A and electron flow 419B can generate bidirectional charge transfer 421A and 421B, respectively. In some embodiments, electron drift currents such as electron flow 419A and 419B, which are formed by an electric field applied to active pixel 410 or active pixel 460, can increase the conductivity in the area surrounding the first side 418A of PD 412A and the area surrounding the second side 420A of PD 412A, and increase the conductivity in the area surrounding the first side 418B of PD 412B and the area surrounding the second side 420B of PD 412B. For example, the increased conductivity can induce charge transfer of charged particles (e.g., electrons) from point XA on the first side 418A of PD 412A to point X1 on the second side 420A of PD 412A (and similarly for PD 412B). The drift electric fields that result in the generation of electron currents 419A and 419B can attract electrons from second side 420A of PD 412A and second side 420B of PD 412B, respectively. When the operation of transfer gates 414A, 414B, 416A, and 416B modulates the electric fields near transfer gates 414A, 414B, 416A, and 416B, electrons can be transferred from transfer gates 414A and 414B to floating diffusion node 424, and electrons can be transferred from transfer gates 416A and 416B to floating diffusion node 426. However, in active pixel 460, electrons can be transferred from transfer gates 414A and 414B to floating diffusion node 424, and from transfer gates 416A and 416B to drain 427.

[0079] Figure 5A-5B According to one or more embodiments Figure 4A and Figure 4B 4. Circuit diagram of active pixels 410 and 460. Figure 5A including active pixels 510, with Figure 4A The active pixels 410 are the same or similar. Figure 5B Including Figure 4B Active pixel 510 may be the same as or similar to active pixel 460. Active pixel 510 may include PDs 412A and 412B operably coupled to floating diffusion nodes 424 and 426. Figure 5B and Figure 5A The difference is that transfer gates 416A and 416B are operatively coupled to drain 427. In some embodiments, PD 412A and PD 412B utilize back-illuminated (BSI) pinned photodiodes or front-illuminated (FSI) pinned photodiodes.

[0080] In some embodiments, charge collected by PD 412A and / or 412B is transferred to floating diffusion nodes 424 and 426. The voltage potential of floating diffusion nodes 424 and 426 can be monitored by source follower (SF) 425 of active pixel 510. Floating diffusion nodes 424 and 426 can be reset or mixed by a transistor reset signal (RST) or a mixing transistor (BIN) before charge transfer (e.g., from the region of PD 412A or PD 412B to transfer gates 414A, 414B, 416A, and 416B, respectively, and then to floating diffusion nodes 424 and 426). Alternatively, as shown in FIG. Figure 5B As shown, charge can be transferred from the region of PD 412A or 412B to transfer gates 414A and 414B, then to floating diffusion node 424, and from transfer gates 416A and 416B to drain 427. In some embodiments, pixel mixing of active pixels 510 or 560 can be implemented by BIN as part of a clocking scheme for combining charge collected by several adjacent pixels. This can have the technical effect of reducing noise and improving the signal-to-noise ratio and frame rate of DPS image sensing system 100A or 100B (e.g., when active pixels 510 or 560 are used within DPS image sensing system 100).

[0081] In some embodiments, a row select transistor (SEL) 429 may be included in active pixels 510 and 560. The row select transistor 429 may be sig The read / write data bus is operatively coupled to the source follower 425 .

[0082] Figures 6A and 6B is a schematic diagram of example active pixels 610 and 660 according to one or more embodiments. Figures 7A and 7B According to one or more embodiments Figures 6A and 6B The circuit diagram of an example active pixel. Figures 6A and 6B As shown, active pixels 610 and 660 include four (4) PD / FD sharing structures that implement bidirectional and complete charge transfer of photodiodes, which is similar or identical to the bidirectional charge transfer and drift current generation of active pixels 210, 260, 410, and 460 described above. In some embodiments, Figure 6A The active pixel 610 may include Figure 1A Alternatively, the active pixel 610 may be used with the DPS image sensing system 100A (e.g., in place of or in addition to the active pixel 110) by appropriate modifications, such as including a single transfer gate instead of two transfer gates. Figure 1B The active pixels 110 are the same or similar. Figure 6B The active pixel 660 may alternatively or additionally be used as Figure 1BActive pixels (eg, active pixel 110 ) in the DPS image sensing system 100B.

[0083] In some embodiments, active pixel 610 may include four (2) photodiodes (PDs) 612A-612D. Figure 6A Only a single instance of active pixel 610 is included, however, additional instances of active pixel 610 may be operably coupled together. In some embodiments, PD 612A may be operably coupled to transfer gates 614A and 616A, PD 612B may be operably coupled to transfer gates 614B and 616B, PD 612C may be operably coupled to transfer gates 614C and 616C, and PD 612D may be operably coupled to transfer gates 614D and 616D. Transfer gates 614A and 616A may reside on asymmetrically opposite sides of PD 612A, transfer gates 614B and 616B may reside on asymmetrically opposite sides of PD 612B, transfer gates 614C and 616C may reside on asymmetrically opposite sides of PD 612C, and transfer gates 614D and 616D may reside on asymmetrically opposite sides of PD 612D. In some embodiments, each of transfer gates 614A- 614D and transfer gates 616A- 614D may include an active layer intersecting with a polysilicon layer and a charge trap layer configured as a floating diffusion layer.

[0084] In some embodiments, as Figure 6B As shown, transfer gates 614A and 616A of PD 612A and transfer gates 614C and 616C of PD 612C may include floating diffusion nodes 624 and 626, respectively. Transfer gates 614B and 616B of PD 612B and transfer gates 614D and 616D of PD 612D may include floating diffusion nodes 626 and 628, respectively. Thus, floating diffusion node 624 may be "shared" by transfer gates 614A and 614C; floating diffusion node 626 may be "shared" by transfer gates 616A and 616C and transfer gates 614B and 614D; and floating diffusion node 628 may be shared by transfer gates 616B and 616D. Transfer gates 614A-614D and 616A-616D may provide charge transfer to floating diffusion nodes 624, 626, and 628. Figure 6A is similar to the above except that transfer gates 614A-614D output charge to drain 627 instead of floating diffusion node (e.g., floating diffusion node 624). Figure 6B Schematic diagram of active pixel 610 of active pixel 660.

[0085] In some embodiments, active pixels 610 and 660 can achieve bidirectional charge transfer by having an electric field generated by or otherwise applied to PDs 612A-612D, and complete intra-pixel charge transfer within PDs 612A-612D. Applying the electric field can cause electron drift currents to be generated within PDs 612A-612D, respectively. Figure 6A and 6B , electron flows 619A, 619B, 619C, and 619D corresponding to electron drift currents generated within PDs 612A, 612B, 612C, and 612D are depicted. For example, electron flow 619A can be generated in PD 612A in response to applying an electric field to PD 612A. Electron flow 619A can be directed from a first side of PD 612A to a second side of PD 612A, and a similar effect can occur for each of PDs 612B-612D. In some embodiments, the same electric field can be applied to each of PDs 612A-612D, while in other embodiments, different electric fields can be applied to PDs 612A-612D. For example, the electric field applied to PD 612A can be different from the electric field applied to PD 612C. The applied electric field can generate electron flows 619A and 619B with different directionality than electron flows 619C and 619D. For example, electron flows 619A and 619C may have equal magnitudes but opposite directions. Electron flows 619A-619D may be caused by an electric field applied to active pixel 610 (or active pixel 660), which causes electrons in PDs 612A-612D to move in a particular direction based on the applied electric field. In some embodiments, the electric field is generated by an impurity concentration gradient of PDs 612A-612D, which is discussed in more detail below. In addition, by forming an electric field in PDs 612A-612D (e.g., via implementing an impurity concentration gradient of PDs 612A-612D), and by the operation of two (2) transfer gates (e.g., transfer gates 614A, 616A; transfer gates 614B, 616B; transfer gates 614C, 616C; and transfer gates 614D, 616D), bidirectional charge transfer of electrons in each of PDs 612A-612D may be achieved. The bidirectional charge transfer functionality and the full intra-pixel charge transfer functionality of the active pixels 610 and 660 can be used in a variety of applications. Some examples of applications in which the bidirectional charge transfer functionality and the full intra-pixel charge transfer functionality can be implemented include, but are not limited to (this is not intended to be limiting), high dynamic range readout and time-of-flight (ToF) readout, which are described in further detail below.

[0086] In some embodiments, electron flows 619A-619D can generate bidirectional charge transfer 621A-621D, respectively. In some embodiments, electron drift currents such as electron flows 619A-619D, formed by an electric field applied to active pixel 610 or active pixel 660, can increase the conductivity in the area surrounding the first side of each of PDs 612A-612D and the area surrounding the second side of PDs 612A-612D, as well as increase the conductivity in the area surrounding the first side of PDs 612A-612D and the area surrounding the second side of PDs 612A-612D. For example, the increased conductivity can induce charge transfer of charged particles (e.g., electrons) from one side of PD 612A to the other side of PD 612A. The electric field that generates electron flows 619A-619D can attract electrons from the second side of each of PDs 612A-612D. When the operation of transfer gates 614A-614D and 616A-616D modulates the electric field near transfer gates 614A-614D and 616A-616D, electrons can transfer from transfer gates 614A and 614C to floating diffusion node 624, electrons can transfer from transfer gates 616A, 616C, 614B, and 614D to floating diffusion node 626, and electrons can transfer from transfer gates 616B and 616D to floating diffusion node 628. However, in active pixel 610, electrons can transfer from transfer gates 614A, 614C, 616A, 616C, 614B, and 614D to drain 627.

[0087] In some embodiments, PDs 612A-612D correspond to a single active pixel (eg, active pixel 610). Figures 6A and 6B As shown, each PD 610A-PD 610D transfers charge to at least one common floating diffusion node (e.g., FD 624). In some embodiments, active pixel 610 and / or active pixel 660 can be operatively coupled to multiple adjacent active pixels that are identical or similar to active pixel 610 and / or 660 to form a pixel array.

[0088] Figures 7A and 7B According to one or more embodiments Figure 6A and Figure 6B Circuit diagram of active pixels 610 and 660. Figure 7A including active pixels 710, with Figure 6A The active pixels 610 are the same or similar. Figure 7B Including Figure 6B Active pixel 660 is the same as or similar to active pixel 760. Active pixel 760 includes PDs 612A-612D operatively coupled to floating diffusion nodes 624 and 626. Figure 7B and Figure 7AThe difference is that the transfer gates 616A-616D are operatively coupled to the drain 627. In some embodiments, the PDs 612A-612D utilize backside illumination (BSI) pinned photodiodes or front illumination (FSI) pinned photodiodes.

[0089] In some embodiments, the charge collected by PDs 612A-612D is transferred to floating diffusion nodes 624 and 626. The voltage potential of floating diffusion nodes 624 and 626 can be monitored by source followers (SF) 625 of active pixels 710 and 760. Floating diffusion nodes 624 and 626 can be reset or mixed by a transistor reset signal (RST) or a mixing transistor (BIN) before the charge is transferred (e.g., from the region of PD 612A to transfer gates 614A and 616B, and then to floating diffusion nodes 624 and 626). Alternatively, as Figure 7A As shown, charge can be transferred from the region of PDs 612A-612D to transfer gates 616A-616D and to drain 627. In some embodiments, pixel mixing of active pixels 710 or 760 can be implemented by BIN as part of a clocking scheme for combining charge collected by several adjacent pixels. This can have the technical effect of reducing noise and improving the signal-to-noise ratio and frame rate of DPS image sensing system 100A or DPS image sensing system 100B (e.g., when active pixels 710 or 760 are used within DPS image sensing system 100A or DPS image sensing system 100B).

[0090] In some embodiments, a row select transistor (SEL) 629 may be included in active pixels 710 and 760. The row select transistor 629 may be sig The read / write data bus is operatively coupled to the source follower 625 .

[0091] Figures 8A and 8B is a schematic diagram of a top view 800 and a side view 850 of an example active pixel 810 according to one or more embodiments. Specifically, Figure 8B The side view 850 includes a semiconductor substrate 813 of an active pixel 810. In some embodiments, the active pixel 810 may be connected to Figure 2A and Figure 2B The active pixels 210 or 260 are the same or similar. In some embodiments, the semiconductor substrate 813 may include a gradient of impurity concentration.

[0092] Active pixel 810 may include semiconductor substrate 813. Semiconductor substrate 813 may use staggered implant concentrations for each iteration of the n-layer implant region of photodiode (PD) 812. In this manner, full intra-pixel charge transfer to transfer gates 814 and 816, as well as to the floating diffusion node or drain, may be achieved. In some embodiments, the implant concentration of each n-layer of semiconductor substrate 813 may be increased compared to the previous layer, such as Figure 8B This increases the conductivity of each additional layer in the n-layer of semiconductor substrate 813 , having the technical effect of providing complete intra-pixel charge transfer from PD 812 through the operation of transfer gates 814 and 816 .

[0093] In some embodiments, the semiconductor substrate 813 includes a substrate base 811, an N1 layer 818, and an N1+N2 layer 820. As known to those skilled in the art, layers 818 and 820 may include optoelectronic materials configured to convert incident light into electrical charges. For example, the N1 layer 818 and the N1+N2 layer 820 may include materials such as silicon, gallium, arsenide, or other materials. The PD 812 includes a first electron transfer region (e.g., the N1 layer 818) having an N1 injection concentration and a second charge transfer region (e.g., the N1+N2 layer 820) having an N1+N2 injection concentration. As described herein, the injection concentration refers to the amount and type of dopant used in the substrate.

[0094] In some embodiments, the implant concentration gradient refers to varying dopant materials and varying dopant concentrations. For example, the N1 layer 818 includes N-type dopants, such as P, As, and / or Sb, which have low ionization energies at appropriate concentrations. In some embodiments, N2 may include a higher concentration of the same dopant used for N1. In some embodiments, N2 may be a different dopant at the same concentration. For example, N1 may be doped with a first dopant at a first concentration, while N2 may include a second dopant at the same concentration as the first. In some embodiments, N1 may correspond to a concentration of approximately 1×10 16～17 [per cm 3 ] of As, and relative to Si, N2 can correspond to a concentration of about 1×10 16～17 [per cm 3 ] of As. Approximation means that the above difference is negligible. In some embodiments, N1 may correspond to a concentration of 2.5 to 3.5×10 17 [per cm 3 ], and relative to Si, N2 can correspond to a concentration of about 0.5 to 1.5×10 17 [per cm 3 ] of As.

[0095] In some embodiments, the active pixel 810 may be processed using a front-end-of-line (FEOL) process for forming transistors directly on a semiconductor substrate 813. The semiconductor substrate 813 may include, for example, a wafer fabricated by growing a pure silicon layer using an epitaxial process. In some embodiments, a silicon variant may be deposited in one or more layers of the active pixel 810 (e.g., N1 layer 818, N1+N2 layer 820). In some embodiments, prior to epitaxy, further processing may be performed to improve the performance of the transistors used on the semiconductor substrate 813.

[0096] In some embodiments, the FEOL processing may include a straining step whereby silicon variants are deposited in the semiconductor substrate 813 to improve electron mobility of the substrate base 811. In some embodiments, the impurity concentration and / or material may be modified to further improve electron mobility. In some embodiments, the FEOL processing may include a gate dielectric (e.g., Figure 2A and Figure 2B The transfer gates 214 and 216 are grown. For example, this may include patterning the gates, patterning the source and drain regions, and subsequent implementation or diffusion of dopants to achieve the desired complementary electrical characteristics. For example, in some embodiments, N-type dopants such as P, As, and / or Sb are used due to their ionization energy (20-300 keV), low diffusivity, and suitable solid solubility in Si.

[0097] Figures 9A and 9B 9 is a schematic diagram of a top view 900 and a side view 950 of an example active pixel 910 according to one or more embodiments. In some embodiments, the active pixel 910 is configured for use in the DPS image sensing system 100A, or with appropriate modifications, in the DPS image sensing system 100B. In some embodiments, the active pixel 910 is Figure 2A and Figure 2B As described in further detail below, the active pixel 910 may be formed using a fabrication method that implements a concentration gradient and iterative n-implantation layer method to produce a varying impurity concentration gradient effect in various layers of the photodiode (PD) 912 of the active pixel 910.

[0098] In some embodiments, the varying impurity concentration gradient effect of active pixel 910 functions to provide increased charge conductivity in PD 912. Operation of transfer gates 914 and 916 can generate an electric field that induces an electron drift current from a first side of PD 912 to a second side of PD 912. For example, the electron drift current can be directed from point X to point X'. Including two (2) transfer gates 914 and 916 provides an electric field that causes complete intra-pixel charge transfer of electrons from N1 layer 918 to N1+N2 layer 920 and into a floating diffusion node or drain.

[0099] Active pixel 910 includes semiconductor substrate 913. Semiconductor substrate 913 can utilize staggered implant concentrations for each iteration of the n-layer implant region 912. In this way, full intra-pixel charge transfer to transfer gates 914 and 916, as well as to the floating diffusion node or drain, can be achieved. In some embodiments, as Figure 9B As shown, the implant concentration of each n-layer of semiconductor substrate 913 can be increased compared to the previous layer. This can increase the conductivity of each additional layer of the n-layer of semiconductor substrate 913, which can have the technical effect of providing complete intra-pixel charge transfer from PD 912 through the operation of transfer gates 914 and 916.

[0100] In some embodiments, the semiconductor substrate 913 includes a substrate base 911, an N1 layer 918, and an N1+N2 layer 920. As known to those skilled in the art, layers 918 and 920 may include optoelectronic materials configured to convert incident light into electrical charges. For example, the N1 layer 918 and the N1+N2 layer 920 may include materials such as silicon, gallium, arsenide, or other materials. The PD 912 includes a first electron transfer region (e.g., the N1 layer 918) having an N1 injection concentration and a second charge transfer region (e.g., the N1+N2 layer 920) having an N1+N2 injection concentration. As described herein, the injection concentration refers to the amount and type of dopant used in the substrate.

[0101] Figure 9A and Figure 9B The PD912 can be used with Figure 8A and Figure 8BPD 812 differs in that the pattern used to distinguish the N1 layer 918 from the N1+N2 layer 920 is different compared to the N1 layer 818 and the N1+N2 layer 820. For example, while the N1 layer 818 and the N1+N2 layer 820 may be arranged in a rectangular shape when viewed from the top view 800, the N1 layer 918 may increase in size approximately linearly along the axis from point X to point X'. Similarly, the N1+N2 layer 920 may decrease in size approximately linearly along the axis from point X' to point X when viewed from the top view 900. In some embodiments, the N1+N2 layer 920 may reside on a portion of the N1 layer 918, which may extend across the surface of the substrate base 911 of the semiconductor substrate 913.

[0102] In some embodiments, Figure 9A and Figure 9B The material composition and configuration of PD912 can be Figure 8A and Figure 8B The material composition and configuration of PD 812 may be the same or similar. For example, N1 layer 918 may also include ArGe doped with aluminum, and N2 may include a higher concentration of the same dopant as used for N1. As another example, N2 may include a different dopant at the same concentration.

[0103] In some embodiments, the active pixel 910 may use a front-end-of-line (FEOL) process for forming transistors directly on the semiconductor substrate 913. The semiconductor substrate 913 may include, for example, a wafer manufactured by growing a pure silicon layer using an epitaxial process. In some embodiments, a silicon variant may be deposited in one or more layers of the active pixel 910 (e.g., N1 layer 918, N1+N2 layer 920). In some embodiments, prior to epitaxy, further processing may be performed to improve the performance of the transistors used on the semiconductor substrate 913. In addition, similar to the active pixel 810, the FEOL process may include a strain step, whereby a silicon variant is deposited in the semiconductor substrate 913 to improve the electron mobility of the substrate base 911. In some embodiments, the impurity concentration and / or material may be modified to further improve the electron mobility. In some embodiments, the FEOL process may include a gate dielectric (e.g., Figure 2A and Figure 2B The transfer gates 214 and 216 are grown. For example, this may include patterning the gates, patterning the source and drain regions, and subsequent implementation or diffusion of dopants to achieve the desired complementary electrical characteristics. For example, in some embodiments, N-type dopants such as P, As, and / or Sb are used due to their ionization energy (20-300 keV), low diffusivity, and suitable solid solubility in Si.

[0104] Figures 10A and 10Bis a charge potential diagram depicting simulation results for an example active pixel according to one or more embodiments. Specifically, Figures 10A and 10B Active pixels (e.g., Figures 8A and 8B The active pixels 810 and Figures 9A and 9B Charge potential diagram of active pixel 910). Figure 10A Included is table 1000, which depicts Figures 8A to 8B The active pixels 810 and Figures 9A to 9B The operation of the active pixel 910 is similar to that of the reference active pixel 1010 (e.g. Figure 10B ). Reference active pixel 1010 includes a homogeneous photodiode region 1001 having a uniform implant composition. In contrast, active pixel 810 includes two n-layer implant regions, N1 layer 818 and N1+N2 layer 820, and active pixel 910 includes two n-layer implant regions, N1 layer 918 and N1+N2 layer 920, wherein N2 of active pixel 910 is configured to utilize a tapered n-layer implant to narrow the channeling effect, as shown. Figure 10B shown.

[0105] In the first operation, the first transfer gate TG1 of each active pixel 810, 910, and 1010 is turned on, and the second transfer gate TG2 of each active pixel 810, 910, and 1010 is turned off. Figures 10A and 10B , the first transfer gate TG1 refers to the transfer gate 814 of the active pixel 810, the transfer gate 914 of the active pixel 910, and the transfer gate 1014 of the reference active pixel 1010, and the second transfer gate TG2 refers to the transfer gate 816 of the active pixel 810, the transfer gate 916 of the active pixel 910, and the transfer gate 1016 of the reference active pixel 1010. In the second operation, the first transfer gate TG1 is turned off, and the second transfer gate TG2 is turned on. Figure 10A As shown, for both the first and second operations, a strong potential dip still exists in the photodiode region of the reference active pixel 1010. The potential dip in the reference active pixel 1010 is evidenced by the (three) thick lines near the transfer gate TG2 or TG1, depending on whether the transfer gate TG1 or the transfer gate TG2 is turned on, and represents charge accumulation in the photodiode region of the reference active pixel 1010.

[0106] As described above, active pixels 810 and 910 utilize different implant materials and doping concentrations to facilitate complete intra-pixel charge transfer to the floating diffusion nodes of those active pixels. This complete charge transfer provides the technical benefit of reducing image lag when processing an image, thereby improving the processing time of the imaging system. This complete intra-pixel charge transfer is achieved by applying a strong electric field to the photodiode region of the active pixel using two transfer gates TG1 and TG2 located on the same side of the active pixel.

[0107] As shown in Table 1000, under both operating conditions of transfer gates TG1 and TG2, active pixel 810 achieves significantly more charge transfer from the photodiode region than reference active pixel 1010. Furthermore, active pixel 910, which implements a modified injection material (e.g., a modified impurity concentration gradient) for achieving electron drift current, as discussed above, exhibits even more complete charge transfer from the photodiode region when compared to reference active pixel 1010 and active pixel 810. This is illustrated by the single bold line adjacent to the active transfer gate. In this manner, active pixels 810 and 910 achieve complete charge transfer to the floating diffusion node without a potential dip in the photodiode region of the active pixels.

[0108] Figures 11A to 11C 1 is a schematic diagram of a top view 1100, 1150 and a side view 1160 of an example active pixel according to one or more embodiments. Figure 11A and 11B As shown, in some embodiments, additional N-layer implants may be used in active pixels to achieve a strong electric field. For example, active pixel 1110A may include four (4) N-layer regions, such as Figure 11A As another example, the active pixel 1110B may also use four N-layer regions, which achieve a varying impurity concentration gradient effect through the four N-layers. Figures 8A and 8B The active pixels 810 and Figures 9A and 9B Compared to active pixel 910 of FIG. 1 , using active pixels 1110A and 1110B in DPS image sensing system 100A or DPS image sensing system 100B results in a stronger electric field due to the use of additional N-layer implant regions in active pixels 1110A and 1110B.

[0109] Figure 11BActive pixel 1110B includes a photodiode (PD) 1190, which may incorporate a structure with a varying impurity concentration gradient effect including four N-layer regions. For example, N1 layer 1118 corresponds to a first varying impurity concentration gradient region including an injection profile N1; N1+N2 layer 1119 corresponds to a second varying impurity concentration gradient region including an injection profile N1+N2; N1+N2+N3 layer 1120 corresponds to a third varying impurity concentration gradient region including an injection profile N1+N2+N3; and N1+N2+N3+N4 layer 1121 corresponds to a fourth varying impurity concentration gradient region including an injection profile N1+N2+N3+N4.

[0110] In some embodiments, the PD 1180 of the active pixel 1110A and the PD 1190 of the active pixel 1110B may include additional N layer regions, for example, five (5) N layer regions, six (6) N layer regions, seven (7) N layer regions, or more. In some embodiments, each successive N layer may have the same width, or may have varying degrees of width. Changing the shape of each region helps reduce manufacturing costs because the number of photomasks can be reduced when not only rectangular shaped masks are used. In some embodiments, the angle of incidence formed by each N layer in the narrow field effect methodology may be different from one consecutive letter to the next. For example, as Figure 11A As shown in the top view 1100 of FIG. 1 , the PD 1180 of the active pixel 1110A has four N layers whose impurity concentration increases from the least concentrated at point X to the most concentrated at point X'. In addition, the four N layers of the PD 1180 of the active pixel 1110A are distributed in approximately vertical blocks along the XX' axis. As another example, as shown from FIG. Figure 11B As seen in the top view 1150 of FIG. 1 , the PD 1190 of the active pixel 1110B further includes four N layers having increased impurity concentrations; however, these layers extend along a substantially 45-degree angle from the XX′ axis toward the edge of the PD 1190 of the active pixel 1110B.

[0111] In some embodiments, active pixels 1110A and 1110B include transfer gates 1114 and 1116, which can be located on asymmetrically opposite sides of PDs 1180 and 1190, respectively. Operation of transfer gates 1114 and 1116 of active pixel 1110A can generate an electric field that induces an electron drift current from a first side of PD 1180 to a second side of PD 1180. Operation of transfer gates 1114 and 1116 of active pixel 1110B can generate an electric field that induces an electron drift current from a first side of PD 1190 to a second side of PD 1190. For example, the electron drift current can be directed from point X to point X'. Two (2) transfer gates 1114 and 1116 are included to provide an electric field that causes complete intra-pixel charge transfer of electrons from the N1 layer 1118 to the N1+N2 layer 1119, to the N1+N2+N3 layer 1120, to the N1+N2+N3+N4 layer 1121 (and so on), and to the floating diffusion node or drain.

[0112] like Figure 11C As shown, side view 1160 depicts active pixel 1110, which can be respectively Figure 11A and Figure 11B Active pixel 1110A or 1110B is identical or similar to the active pixel 1110A or 1110B. Active pixel 1110 includes a semiconductor substrate 1113. Semiconductor substrate 1113 can utilize staggered implant concentrations for each iteration of the n-layer implant region. In this manner, full intra-pixel charge transfer to transfer gates 1114 and 1116, as well as to the floating diffusion node or drain, can be facilitated. In some embodiments, the implant concentration of each n-layer of semiconductor substrate 1113 can be increased compared to the previous layer. This can increase the conductivity of each additional layer of the n-layers of semiconductor substrate 1113, having the technical effect of providing full intra-pixel charge transfer through the operation of transfer gates 1114 and 1116.

[0113] In some embodiments, semiconductor substrate 1113 includes substrate base 1111, N1 layer 1118, N1+N2 layer 1119, N1+N2+N3 layer 1120, and N1+N2+N3+N4 layer 1121. As known to those skilled in the art, each of layers 1118-1121 may include a photoelectric material configured to convert incident light into electrical charge. For example, the layers of active pixel 1110 may include materials such as silicon, gallium, arsenide, or other materials. Active pixel 1110 may include a first charge transfer region (e.g., N1 layer 1118) having an N1 injection concentration, a second charge transfer region (e.g., N1+N2 layer 1119) having an N1+N2+N3 injection concentration, a third charge transfer region (e.g., N1+N2+N3 layer 1120) having an N1+N2+N3 injection concentration, and a fourth charge transfer region (e.g., N1+N2+N3+N4 layer 1121) having an N1+N2+N3+N4 injection concentration. As described herein, the injection concentration refers to the amount and type of dopants used in the substrate.

[0114] In some embodiments, the material composition and configuration of the PD 1180 and PD 1190 of the active pixel 1110A of the active pixel 1110B may be the same as or similar to the material composition and configuration of the PD 912 of the active pixel 910 and the PD 812 of the active pixel 810. For example, the N1 layer 1118 may further include a first concentration of an N-type dopant such as P, As, and / or Sb, the N1+N2 layer 1119 may include a higher concentration of the same dopant used for the N1 layer 1118, the N1+N2+N3 layer 1120 may include a higher concentration of the same dopant used for the N1 layer 1118 and the N1+N2 layer 1119, and the N1+N2+N3+N4 layer 1121 may further include a higher concentration of the same dopant used for the N1 layer 1118, the N1+N2 layer 1119, and the N1+N2+N3 layer 1120. As another example, the N1+N2 layer 1119 , the N1+N2+N3 layer 1120 , and / or the N1+N2+N3+N4 layer 1121 may have the same concentration of different dopants as the N1 layer 1118 .

[0115] In some embodiments, the active pixel 1110 may use a front-end-of-line (FEOL) process for forming transistors directly on the semiconductor substrate 1113. The semiconductor substrate 1113 may include, for example, a wafer manufactured by growing a pure silicon layer using an epitaxial process. In some embodiments, a silicon variant may be deposited in one or more layers of the active pixel 1110 (e.g., N1 layer 1118, N1+N2 layer 1119, N1+N2+N3 layer 1120, N1+N2+N3+N4 layer 1121). In some embodiments, prior to epitaxy, further processing may be performed to improve the performance of the transistors used on the semiconductor substrate 1113. In addition, similar to the active pixels 810 and 910, the FEOL process may include a strain step, whereby a silicon variant is deposited in the semiconductor substrate 1113 to improve the electron mobility of the substrate base 1111. In some embodiments, the impurity concentration and / or material may be modified to further improve the electron mobility. In some embodiments, the FEOL process may include a gate dielectric (e.g., Figure 2A and Figure 2B The transfer gates 214 and 216 are grown. For example, this may include patterning the gates, patterning the source and drain regions, and subsequent implementation or diffusion of dopants to achieve the desired complementary electrical characteristics. For example, in some embodiments, N-type dopants such as P, As, and / or Sb are used due to their ionization energy (e.g., between 20-300 keV), low diffusivity, and suitable solid solubility in Si.

[0116] Figures 12A and 12B is a schematic diagram of an example non-shared active pixel system 1200 and an example shared active pixel system 1250 according to one or more embodiments. Figure 12A and Figure 12B An exemplary embodiment for providing high dynamic range readout is depicted. High dynamic range readout can be achieved by an unshared active pixel system 1200 including a first active pixel 1210A or a shared active pixel system 1250 including a first active pixel 1210A and a second active pixel 1210B. In some embodiments, the unshared active pixel system 1200 including the first active pixel 1210A can be used instead of or in addition to the first active pixel 1210A. Figure 2A and 2B The shared active pixel system 1250 including the first active pixel 1210A and the second active pixel 1210B may be used instead of or in the active pixel 210 of FIG. Figure 4A and 4B The active pixel 410 is used on the basis of.

[0117] In some embodiments, the non-shared active pixel system 1200 includes a first active pixel 1210A, such as Figure 12A As shown. The first active pixel 1210A includes and is operatively coupled to a first transfer gate 1214A and a second transfer gate 1216A. Transfer gates 1214A and 1216A are operatively coupled to floating diffusion nodes 1224 and 1226, respectively. In some embodiments, application of an electric field to the first active pixel 1210A may result in generation of an electron drift current 1219A within the PD 1212A. Figure 12A and 12B , an electron flow 1219A corresponding to an electron drift current generated within PD 1212A and an electron flow 1219B corresponding to an electron drift current generated within PD 1212B are depicted. In some embodiments, transfer gates 1214A and 1216A can be configured to generate electron flow 1219A in a direction from a first side of PD 1212A to a second side of PD 1212A. Thus, electron flow 1219A can generate bidirectional charge transfer 1221A. In some embodiments, the electron drift current (e.g., electron drift current 1219A) formed by the electric field applied to the first active pixel 1210A can increase the conductivity of PD 212. For example, the increased conductivity can induce charge transfer of charged particles (e.g., electrons) from one side of PD 1212A to the other side of PD 1212A. When operation of transfer gates 1214A and 1216A modulates the electric field near transfer gates 1214A and 1216A, electrons may be transferred from transfer gates 1214A and 1216A to floating diffusion node 1224 or floating diffusion node 1226, respectively. In some embodiments, electrons may also be transferred from transfer gates 1214A and / or 1216A and to the drain.

[0118] In some embodiments, the shared active pixel system 1250 includes a first active pixel 1210A and a second active pixel 1210B. Figure 12BAs shown. First active pixel 1210A may include and be operatively coupled to first transfer gate 1214A and second transfer gate 1216A. Second active pixel 1210B may include and be operatively coupled to first transfer gate 1214B and second transfer gate 1216B. Transfer gates 1214A and 1214B may be operatively coupled to floating diffusion node 1224, and transfer gates 1216A and 1216B may be operatively coupled to floating diffusion node 1226. In some embodiments, application of an electric field to first active pixel 1210A and second active pixel 1210B may generate electron current 1219A within PD 1212A and electron current 1219B within PD 1212B. In some embodiments, transfer gates 1214A, 1214B, 1216A, and 1216B can be configured to generate electron currents 1219A and 1219B in a direction from a first side of PD 1212A to a second side of PD 1212A, and from a first side of PD 1212B to a second side of PD 1212B. In some embodiments, electron currents 1219A and 1219B can be of equal magnitude but in opposite directions. In some embodiments, the same electric field can be applied to both PDs 1212A and 1212B, such that electron currents 1219A and 1219B are generated at PDs 1212A and 1212B, respectively. In some embodiments, different electric fields can be applied to each of PDs 1212A and 1212B. Thus, electron current 1219A can generate bidirectional charge transfer 1221A, and electron current 1219B can generate bidirectional charge transfer 1221B. In some embodiments, electron drift currents (e.g., electron current 1219A and / or electron current 1219B) formed by the electric field applied to the first active pixel 1210A and the second active pixel 1210B can increase the conductivity in the PDs 1212A and 1212B. For example, the increased conductivity can induce charge transfer of charged particles (e.g., electrons) from one side of the PD 1212A to the other side of the PD 1212A, and from one side of the PD 1212B to the other side of the PD 1212B. When the operation of the transfer gates 1214A and 1216A adjusts the electric field near the transfer gates 1214A and 1216A, electrons can be transferred from the transfer gates 1214A and 1216A to the floating diffusion node 1224 or the floating diffusion node 1226, respectively. Similarly, when operation of transfer gates 1214B and 1216B modulates the electric field near transfer gates 1214B and 1216B, electrons may be transferred from transfer gates 1214B and 1216B, respectively, to floating diffusion node 1224 or floating diffusion node 1226. In some embodiments, electrons may alternatively be transferred from transfer gates 1214A, 1214B, 1216A, and / or 1216B to the drain.

[0119] A first active pixel 1210A of the non-shared active pixel system 1200 may include a first transfer gate 1214A and a floating diffusion node 1224 for a high conversion gain (HCG) signal and a second transfer gate 1216A and a floating diffusion node 1226 for a low conversion gain (LSG) signal. High dynamic range readout may function by utilizing a first transfer to the floating diffusion node 1224 and a second transfer to the floating diffusion node 1226. Shared active pixel system 1250 may include a first active pixel 1210A for high conversion gain (HCG) signals, including a first transfer gate 1214A and a floating diffusion node 1224, and a second active pixel 1210B for low conversion gain (LSG) signals, including a second transfer gate 1216A and a floating diffusion node 1226, and a second active pixel 1210B for high conversion gain (HCG) signals. The first active pixel 1210A includes a first transfer gate 1214A and a floating diffusion node 1224, while the second active pixel 1210B includes a first transfer gate 1214B and a floating diffusion node 1224 (shared by transfer gates 1214A and 1214B). High dynamic range readout may be achieved by utilizing a first transfer to floating diffusion node 1224 and a second transfer to floating diffusion node 1226.

[0120] In some embodiments, at low brightness levels of incident light, some charge is present in floating diffusion node 1224, and no charge or only a charge less than a threshold amount is present in floating diffusion node 1226. In some embodiments, a single floating diffusion node is used for high-gain readout, however, two floating diffusion nodes may be used for high-gain readout. At high brightness levels of incident light, some charge is present in both floating diffusion node 1224 and floating diffusion node 1226. In some embodiments, in order to use both floating diffusion nodes 1224 and 1226 for low-gain readout, a charge addition processing technique for floating diffusion nodes 1224 and 1226 is required. As described herein, charge addition refers to a digital mixing operation that combines floating diffusion nodes 1224 and 1226 in the digital domain. In this way, a single exposure high dynamic range signal is achieved. For example, floating diffusion node 1226 can be coupled to capacitor 1240 via connection line 1230. Capacitor 1240 may include a metal oxide semiconductor (MOS) capacitor, a metal-insulator-metal (MIM) capacitor, a metal-oxide-metal (MOM) capacitor, or other type of capacitor or other sensor.

[0121] Figure 13is a schematic diagram of an example shared active pixel system 1300 according to one or more embodiments. The shared active pixel system 1300 can be used to implement high dynamic range readout, for high gain / high resolution readout, and for high full well capacity (FWC) and low resolution readout. As used herein, "high dynamic range readout" can include high gain for high resolution readout and high FWC for low resolution readout. In some embodiments, the shared active pixel system 1300 includes a first active pixel 1310A and a second active pixel 1310B. The first active pixel 1310A and the second active pixel 1310B are substantially similar to Figure 4A and 4B active pixels 410, and the previous description can be applied.

[0122] In some embodiments, the shared active pixel system 1300 is configured for high gain / high resolution and high FWC / low resolution readout during overflow operation by using an overflow path, as discussed in further detail below. The first active pixel 1310A may include a photodiode (PD) 1312A, and the second active pixel 1310B may include a photodiode (PD) 1312B. PD 1312A and PD 1312B may share both a floating diffusion node 1324, which is configured to receive transfer electrons from transfer gates 1314A and 1314B, respectively, for high conversion gain (HCG) signals. PD 1312A and PD 1312B may share a floating diffusion node 1326, which is configured to receive transfer electrons from transfer gates 1316A and 1316B, respectively, for low conversion gain (LCG) signals. Applying an electric field may cause an electron drift current to be generated within PD 1312A and PD 1312B, respectively. Figure 13 , an electron flow 1319A corresponding to an electron drift current generated within PD 1312A and an electron flow 1319B corresponding to an electron drift current generated within PD 1312B are depicted. Thus, electron flow 1319A may generate bidirectional charge transfer 1321A and electron flow 1319B may generate bidirectional charge transfer 1321B. In some embodiments, the electron drift current (e.g., electron flows 1319A and 1319B) formed by the electric field applied to the first active pixel 1310A and the second active pixel 1310B may increase the conductivity in the first active pixel 1310A and the second active pixel 1310B. In some embodiments, the first active pixel 1310A and the second active pixel 1310B may be coupled to a capacitor 1340 via a connection line 1330 for charge addition processing. The capacitor 1340 may be coupled to a first active pixel 1310A and a second active pixel 1310B. Figure 12B The capacitor 1240 is the same or similar and the previous description can apply.

[0123] In some embodiments, high-gain / high-resolution operation may include a first transfer of charge from the PD 1312A of the first active pixel 1310A and the PD 1312B of the second active pixel 1310B to the floating diffusion node 1324. During operation in a low-light environment, some charge may be present in the floating diffusion node 1324, and no charge or only a charge less than a threshold amount may be present in the floating diffusion node 1326. During operation in a high-light environment, some charge may be present in the floating diffusion node 1324 and some charge may be present in the floating diffusion node 1326 due to an overflow operation. During the overflow operation, the floating diffusion node 1324 may generate excess electrons from the high-light conditions. An overflow path may be created under the transfer gate (e.g., transfer gate 1316A and / or transfer gate 1316B), and the excess charge may be transferred to the floating diffusion node 1326, thereby providing the overflow operation. In some embodiments, both the floating diffusion nodes 1324 and 1326 may be used for high full-well capacitance (FWC) / low-resolution readout. Charge summing of floating diffusion nodes 1324 and 1326 may be required to achieve high FWC and low resolution readout.

[0124] Figure 14 is a method according to one or more embodiments corresponding to Figures 12A and 12B and Figure 13 In some embodiments, the active pixel system of FIG. Figure 12A and Figure 12B The non-shared active pixel system 1200 and the shared active pixel system 1250, or Figure 13 The shared active pixel system 1300 can be applied to time-of-flight (ToF) readout using an indirect time-of-flight method. In some embodiments, the indirect ToF operation can be implemented using the first active pixel 1210A of the non-shared active pixel system 1200. In some embodiments, the ToF operation can be implemented using the first active pixel 1210A and the second active pixel 1210B of the shared active pixel system 1250 and / or the first active pixel 1310A and the second active pixel 1310B of the shared active pixel system 1300.

[0125] Timing diagram 1400 may describe operation of first active pixel 1210A of non-shared active pixel system 1200, first active pixel 1210A and second active pixel 1210B of shared active pixel system 1250, and / or first active pixel 1310A and second active pixel 1310B of shared active pixel system 1300 for implementing indirect time-of-flight measurement. According to one or more embodiments described herein, a time-of-flight method initiates a first transfer of electron charge from one or more photodiodes to a floating diffusion node (e.g., PD1212A to floating diffusion node 1224, PD1212A and PD1212B to floating diffusion node 1224, PD1312A and PD1312B to floating diffusion node 1324), and a second transfer of electron charge from one or more photodiodes to another floating diffusion node (e.g., PD1212A to floating diffusion node 1226, PD1212A and PD1212B to floating diffusion node 1226, PD1312A and PD1312B to floating diffusion node 1326). For example, at time T1, charge may be detected as being transferred from the photodiode to the first transfer gate, and at time T3, charge may be detected as being transferred from the photodiode to the second transfer gate. Some charge (e.g., electrons) may be transferred to one floating diffusion node (e.g., floating diffusion node 1224, floating diffusion node 1324), while other charge may be transferred to another floating diffusion node (e.g., floating diffusion node 1226, floating diffusion node 1326). The amount of charge transferred to the floating diffusion node corresponds to the reflection time. The reflection time can be used to determine the distance from the LED pulse sensor to the object. For example, the time difference T Delay , as illustrated in timing diagram 1400, may indicate the amount of time between when a signal is emitted from a source (e.g., time T1) and when the signal is received (e.g., detected) by an active pixel (e.g., time T2). Time-of-flight systems have many practical applications, including particle physics measurement systems, signal processing, image processing, and the like.

[0126] As long as the circuit of the DPS image sensing system 100A or 100B is properly modified, Figures 2A-14 Any one or more active pixels described in the embodiments of the present invention can be implemented as one of ordinary skill in the art, respectively. Figure 1A Active pixel 110 or Figure 1B active pixel 110 .

[0127] Figure 15FIG1 is a schematic diagram of an example back-end ADC storage circuit 1500 according to one or more embodiments. Back-end ADC storage circuit 1500 may represent a transistor-level circuit diagram of back-end ADC storage circuit 115 of FIG1 . Multiple ADC schemes are effective for wide dynamic range operations. In some embodiments, back-end ADC storage circuit 1500 provides a write control scheme and circuitry for multiple ADC operations in a DPS device with a small area. Furthermore, back-end ADC storage circuit 1500 can efficiently utilize memory.

[0128] For digital processing systems (e.g. Figure 1A DPS image sensing system 100A or Figure 1B Each pixel in the DPS image sensing system 100B) requires a back-end ADC storage circuit and a digital memory. In some embodiments, the back-end ADC storage circuit 1500 is operably coupled to the active pixel 1510. The back-end ADC storage circuit 1500 includes a comparator 1520 and a write control circuit 1530. In some embodiments, the active pixel 1510, the comparator 1520, and the write control circuit 1530 are substantially similar to Figure 1A The back-end ADC storage circuit 1500 includes active pixels 110, comparator 120, and write control circuit 130, and the previous description may apply. In some embodiments, the back-end ADC storage circuit 1500 may also include a state latch 1540. The state latch 1540 may be effectively used for multiple ADC operations, which will be described in further detail below. The state latch 1540 is the same as or similar to the state latch 140 of Figure 1, and the previous description may apply. In some embodiments, the back-end ADC storage circuit 1500 represents an example of the back-end ADC storage circuit 115 of the DPS image sensing system 100A or a similar component of the DPS image sensing system 100B. The write control circuit 1530 includes a positive feedback circuit 1531 at the output stage of the write control circuit 1530, and an initialization circuit 1532. In some embodiments, the positive feedback circuit 1531 and the initialization circuit 1532 are the same as or similar to the positive feedback circuit 131 and the initialization circuit 132 of Figure 1, respectively, and the previous description may apply.

[0129] In response to the output of comparator 1520 (e.g., "OutA") flipping from a specific logic value (e.g., logic 0) to the opposite logic value (e.g., logic 1), the positive feedback output FB of the positive feedback circuit 1531 changes to FB = 1. FB = 1 is maintained (e.g., the positive feedback circuit 1531 is "locked") regardless of the output of comparator 1520 (e.g., "OutA") until an initialization operation is performed using COMP_SET_n = 0. In some embodiments, COMP_SET_n = 0 is used for an initialization operation, which requires setting OutB = 1 and FB = 0. In some embodiments, the initialization operation of comparator 1520 is used to start ADC conversion. As shown in more detail with reference to FIG. 1 , the initialization operation is performed using a minimum VRAMP voltage, which causes OutA to change to OutA = 0, and a switch of the output of the initialization circuit 1532, which is connected to the node "Init." The initialization operation may also be performed using COMP_SET_n = 0. In the case of State = 0, the output of the positive feedback circuit 1531 in the write control circuit 1530 is FB = 0 and OutB = 1. It should be noted that, unlike FIG1 , the positive feedback circuit 1531 and the initialization circuit 1532 use COMP_SET_n and State instead of COMP_SET and State_n used in FIG1 . COMP_SET_n is obtained by inverting COMP_SET, and State is obtained by inverting State_n.

[0130] Next, comparator 1520 and positive feedback circuit 1531 are initialized using these states (i.e., COMP_SET_n = 0 and State = 0). Once comparator 1520 and positive feedback circuit 1531 are initialized, ADC operation can be started with COMP_SET_n = 1, thereby enabling write operations to ADC memory 1550. In the case of State = 1, even when the lowest VRAMP voltage is used and OutA = 0 at COMP_SET_n = 0, FB = 1 (OutB = 0) is maintained. After toggling COMP_SET_n = 1, the memory is not written because WL = 0. In this way, state latch 1540 can output "State" to control the activation of back-end ADC storage circuit 1500. In some embodiments, when State = 0, data can be written to memory (e.g., ADC memory 1550) using comparator 1520.

[0131] In some embodiments, comparator 1520 may be configured to facilitate the following operations:

[0132] 1) Perform an auto-zero operation by setting COMP_RST_n = 0 with VRAMP equal to the reset level.

[0133] 2) Comparator 1520 is initialized by transitioning positive feedback circuit 1531 from a locked state (e.g., FB=1) to an unlocked state (e.g., FB=0) using COMP_SET=1. In the case of State_n=0, positive feedback circuit 1531 becomes unlocked (e.g., FB=0), whereas in the case of State_n=1, positive feedback circuit 1531 remains locked (e.g., FB=1). In the latter scenario, data is not written to the memory (e.g., ADC memory 1550) because WL=0.

[0134] 3) Use the VRAMP signal to perform a ramp-up operation. ADC data can be stored at comparator 1520 and flipped only when FB = 1. In some embodiments, 'WL_SEL = 0' is used for read operations from ADC memory 1550. WL_SEL = 0 can also be used to initialize State = 0 before the first ADC operation in multiple ADC operation scenarios.

[0135] like Figure 15 As shown, write control circuit 1530 includes a positive feedback circuit 1531 and an initialization circuit 1532 combined with a constant current inverter of comparator stage 2. In some embodiments, for the pMOS gate, COMP_SET_n and State have opposite polarities of COMP_SET and State_n in FIG. 1 , respectively. In FIG. 1 , OutA of comparator 120 is OutA=0 for the COMP_SET switch in FIG. 1 , but this can be removed in some embodiments. In some embodiments, for comparator 1520, an initialization operation can be performed using an appropriate VRAMP voltage after an auto-zero operation without the switch, setting OutA=0 to ground (GND).

[0136] In some embodiments, STATE_DATA is connected to the state latch 1540 circuit via an nMOS transistor pair. When comparator 1520 switches the word line select from WL=1 to WL=0, state latch 1540 can be fixed to state=STATE_DATA at the time of the flip. ADC memory 1550 can also store bit line data. STATE_DATA=1 can be intentionally set for any suitable ADC range for each operation of back-end ADC storage circuit 1500.

[0137] As long as the circuit of the DPS image sensing system 1500 is appropriately modified as understood by those skilled in the art, Figures 2A-14 Any one or more active pixels described in the embodiments can be implemented as Figure 15 active pixel 1510.

[0138] Figure 16 is a schematic diagram of an example back-end ADC storage circuit 1600 according to one or more embodiments. The back-end ADC storage circuit 1600 can be used with Figure 15 The back-end ADC storage circuit 1500 is the same or similar to the back-end ADC storage circuit 1500 and the previous description is applicable. For example, the back-end ADC storage circuit 1600 includes a comparator 1620 and a write control circuit 1630, which is the same as the back-end ADC storage circuit 1500. Figure 15 Comparator 1520 and write control circuit 1530 are identical or similar. Write control circuit 1630 includes a positive feedback circuit 1631 and an initialization circuit 1632. Back-end ADC storage circuit 1600 differs from back-end ADC storage circuit 1500 in that an nMOS transistor pair 1633 is added to positive feedback circuit 1631 to implement a CMOS structure for both COMP_SET_n and the output signal of positive feedback circuit 1631. In this way, nMOS transistor pair 1633 can be used to accelerate the switching speed of positive feedback circuit FB. Furthermore, write control circuit 1630 can advantageously reduce shoot-through current during switching. Furthermore, comparator 1620 of back-end ADC storage circuit 1600 includes an nMOS switch 1621 for COMP_SET to achieve additional device performance, for example, to prevent significant initialization delays when CL is large. In some embodiments, nMOS switch 1621 is implemented as a pair of transistors (e.g., nMOS transistors). This facilitates faster initialization of ADC operations.

[0139] As understood by those skilled in the art, Figures 2A-14 Any one or more active pixels described in the embodiments may be implemented as active pixels of the back-end ADC storage circuit 1600 .

[0140] Figure 17 1700 is a timing diagram illustrating exemplary operation of an example back-end ADC storage circuit according to one or more embodiments. The timing diagram 1700 may be applied to each of the circuits shown in FIG. 1 , 15 , or 16 , with the caveat that for example Figure 15 and 16 In the circuit shown in , COMP_SET_n replaces COMP_SET and State replaces State_n. COMP_SET_n is obtained by inverting COMP_SET, and State is obtained by inverting State_n.

[0141] Timing diagram 1700 may depict an example of overlapping 3Q operation. In some embodiments, WL_SEL may be set to 1 (WL_SEL=1) so that WL has the same value as OutB during ADC operation. In some embodiments, when WL flips from logic 1 to logic 0, a time code (i.e., an ADC code) is written to a memory (e.g., ADC memory 150, 1550, 1650). In some embodiments, the time code written and stored in the memory represents the time when WL flipped (i.e., the time when a comparator such as comparator 120, 1520, 1620 flipped). That is, the time code stored in the memory is a digitized light intensity value. When WL flips from logic 1 to logic 0, STATE_DATA is written to a state latch (e.g., state latch 140, 1540, 1640) based on the time code written to the memory.

[0142] In some embodiments, an auto-zero operation is performed before each ADC operation. To perform the auto-zero operation, COMP_RST may be set to 1 (e.g., COMP_RST=1). In some embodiments, a comparator (e.g., comparator circuit 120) may perform an initialization operation of setting COMP_SET to 1 (e.g., COMP_SET=1), which may release the positive feedback circuit (e.g., positive feedback circuits 131, 1531, 1631) from a locked state after each auto-zero operation. In some embodiments, a comparator (e.g., comparator 120, 1520, 1620) may perform an initialization operation of setting COMP_SET_n to 0 (e.g., COMP_SET_n=0). During the period when STATE_DATA is set to logic 1, when the comparator is toggled, the time code (i.e., ADC code) is written to memory and retained for the remainder of one ADC cycle. The STATE_DATA waveform is designed based on the time range within which it is desired to retain the time code written to memory for the remainder of one ADC cycle. The time period during which STATE_DATA is set to logic 0 is not limited to a specific time period within the cycle of a given ADC operation.

[0143] Timing diagram 1700 shows three cases:

[0144] Case 1 - Output OutB flips once;

[0145] Case 2 – Output OutB toggles twice; and

[0146] Case 3 - Output OutB flips three times.

[0147] As shown in timing diagram 1700, when the output OutB (WL) toggles from logic 1 to logic 0, the state is maintained at the same value as STATE DATA (ie, STATE=STATE_DATA). Figure 17 As shown, in the current ADC operation cycle initiated at time t1, if OutB(WL) switches from logic 1 to logic 0 during the timestamp ADC operation, for example, at time t2, when STATE DATA = 1 as shown in Case 1, the time code at time t2 (i.e., ADC code) is written to the memory (e.g., ADC memory 150, 1550, 1650), and State is set to logic 1 (i.e., State = 1). In some cases, setting State to logic 1 causes the comparator (e.g., comparator 120, 1520, 1620) and the positive feedback circuit (e.g., positive feedback circuit 131, 1531, 1631) to enter a locked state. Since State remains at logic 1 (i.e., State = 1) for the remainder of the current cycle of ADC operation, even when COMP_SET becomes logic 1 before entering the HCG ADC or LCG ADC, the ADC code stored in the memory is retained until the end of the current cycle of ADC operation at time t9.

[0148] If OutB(WL) is inverted from logic 1 to logic 0 when STATE DATA = 0 during the timestamp ADC, for example, at time t4 as shown in Case 2 and Case 3, the time code at time t4 (i.e., ADC code) is written to the memory (e.g., ADC memory 150, 1550, 1650), and since STATE DATA = 0, the state is set to logic 0 (i.e., State = 0). Therefore, in Case 2 or Case 3, when COMP_SET is set to logic 1 (or COMP_SET_n is set to logic 0) at time t5 before the start of HCG ADC, the initialization circuit (e.g., initialization circuit 132, 1532, 1632) changes the comparator (e.g., comparator 120, 1520, 1620) and the positive feedback circuit (e.g., positive feedback circuit 131, 1531, 1631) to the unlocked state, and HCG ADC has started.

[0149] In case 2, during the HCG ADC period, OutB(WL) inverts from logic 1 to logic 0. For example, at time t6, when STATE DATA = 1, the time code at time t6 (i.e., ADC code) can be written to the memory (e.g., ADC memory 150, 1550, 1650), and the state is set to logic 1 (i.e., State = 1), which causes the comparator (e.g., comparator 120, 1520, 1620) and the positive feedback circuit (e.g., positive feedback circuit 131, 1531, 1631) to return to the locked state. In case 2, since State is maintained at logic 1 (i.e., State = 1) for the remainder of the current cycle of ADC operation, even when COMP_SET becomes logic 1 before entering the LCG ADC, the ADC code stored in the memory during the HCG ADC period is maintained until the end of the current cycle of ADC operation at time t9.

[0150] In case 3, OutB (WL) is inverted from logic 1 to logic 0 during the LCG ADC operation. For example, at time t8, when STATE DATA = 1, the time code at time t8 (i.e., ADC code) is written to the memory (e.g., ADC memory 150, 1550, 1650), and State is set to logic 1 (i.e., State = 1), which causes the comparator and the positive feedback circuit to enter the locked state again. In case 3, since State is maintained at logic 1 (i.e., State = 1) for the remainder of the current cycle of ADC operation, the ADC code stored in the memory during the LCG ADC operation is also maintained until the current cycle of ADC operation ends at time t9. Therefore, OutB(WL) toggles from logic 1 to logic 0 during STATE DATE=1, and the time code (i.e., ADC code) at the time of OutB(WL) toggling is written to the memory (e.g., ADC memory 150, 1550, 1650), and the state latch (e.g., state latch 140, 1540, 1640) maintains State=1. This can keep the comparator (e.g., comparator 120, 1520, 1620) and the positive feedback circuit (e.g., positive feedback circuit 131, 1531, 1631) locked for the remainder of the current ADC operation cycle. In some embodiments, STATE_DATA is set to logic 1 only once in each of the timestamp ADC, HCG ADC, and LCG ADC, as shown in FIG. Figure 17 In some embodiments, STATE_DATA can alternate between logic 1 and logic 0 to implement complex ADC operations.

[0151] Figures 18A and 18B1 is a diagram of example data structures 1800 and 1820 according to one or more embodiments. In some embodiments, the data of ADC memory 150 can be used as a state latch (e.g., state latches 140, 1540, 1640). In some embodiments using ADC memory 150 instead of the state latch State (or State_n), as described below, it is stored in ADC memory 150. The data of ADC memory 150 can be configured with flag bits and data bits, as shown in FIG1. ​​The flag bit arrangement described herein is well suited for implementing the above-described embodiments, however, those skilled in the art will recognize that other flag bit arrangements may be used in addition or alternatively.

[0152] like Figure 18A As shown, data structure 1800 may be suitable for ADC operations, such as a three-phase ADC operation including a timestamp ADC operation (ADC1), an HCG ADC operation (ADC2), and an LCG ADC (ADC3) operation. In some embodiments, data structure 1800 may include data strings 1802-1806, each data string including a flag bit and an ADC bit. For example, first data string 1802 is a 6-bit string including a flag bit 1808 and a data bit (ADC bit) 1810. First data string 1802 may correspond to a given time during a first ADC operation (e.g., Figure 19 The time code is written to the memory (e.g., ADC memory 150, 1550, 1650) during the timestamp ADC. As described above, the time code can be provided from the time code generator (not shown) to the read / write data bus 160 and can be written to the memory (e.g., ADC memory 150, 1550, 1650). The flag bit 1808 of the first data string 1802 includes the most significant bit (MSB) of the time code (or ADC code) that can be written to the memory (e.g., ADC memory 150, 1550, 1650) at some point during the timestamp ADC. The MSB of the first data string 1802 is designated as a logic 1 so that the memory maintains the ADC code in response to the output of the comparator (e.g., comparator 120, 1520, 1620) flipping from a particular logic value (e.g., logic 0) to the opposite logic value (e.g., logic 1). As Figure 19 As shown, the first data string 1802 starts from "100000" and increments to "101111" during the timestamp ADC period. Figure 19 In the example, the lower 5 bits of the first data string 1802 are called ADC code <4:0>.

[0153] The second data string 1804 is also a 6-bit data string including a flag bit 1812 and a data bit (ADC bit) 1814. The second data string 1804 may correspond to a 6-bit data string in a second ADC operation (e.g., Figure 19 The flag bit 1812 of the second data string 1804 may include the most significant bit (MSB) of the time code (or ADC code) that may be written to the memory (e.g., ADC memory 150, 1550, 1650) at a given time during the HCG ADC. The MSB of the second data string 1804 may be designated as a logic 1 so that the memory may hold the ADC code in response to the output of the comparator (e.g., comparator 120, 1520, 1620) flipping from a particular logic value (e.g., logic 0) to an opposite logic value (e.g., logic 1). Figure 19 As shown, the second data string 1804 starts from "110000" and increments to "111111" during HCG ADC.

[0154] The third data string 1806 is also a 6-bit data string including a flag bit 1816 and a data bit (ADC bit) 1818. The third data string 1806 may correspond to the ADC bit 1818 in the third ADC operation (e.g., Figure 19 The flag bit 1816 of the third data string 1806 may include the most significant bit (MSB) of the time code (or ADC code) that may be written to the memory (e.g., ADC memory 150, 1550, 1650) at a given time during the LCG ADC. The MSB of the third data string 1806 may be designated as a logic 0. Thus, the MSB of the third data string 1806 does not maintain the ADC code by keeping the positive feedback circuit (e.g., positive feedback circuit 131, 1531, 1631) in a locked state. In some embodiments, the LCG ADC is as follows Figure 19 The final ADC operation in one ADC cycle is shown, and once the ADC code is written to the memory (e.g., ADC memory 150, 1550, 1650), it will not be overwritten. Instead, during a subsequent ADC operation in the cycle, in response to the output of the comparator (e.g., comparator 120, 1520, 1620), the comparator flips from a particular logic value (e.g., logic 0) to an opposite logic value (e.g., logic 1). The third data string 1806 starts at "000000" and increments to "011111" during the LCG ADC period.

[0155] In such Figure 18BIn some embodiments of a cycle including a four-phase ADC operation as shown in , data structure 1820 includes data strings 1822-1828, each of which includes a flag bit and an ADC bit. The most significant bit (MSB) of the last ADC (ADC4) data string 1828 can be designated as a logic 0. The most significant bit (MSB) of each of the earlier ADCs (e.g., ADC1, ADC2, ADC3) corresponding to data strings 1822-1826 can be designated as a logic 1. For example, first data string 1822 includes flag bit 1830 and data bit (ADC bit) 1832. Second data string 1824 includes flag bit 1834 and data bit (ADC bit) 1836. Third data string 1826 includes flag bit 1838 and data bit (ADC bit) 1840. Fourth data string 1828 can include flag bit 1842 and data bit (ADC bit) 1844.

[0156] Figure 18C is a schematic diagram of an example memory array 1850 according to one or more embodiments. Figure 18C As shown, the memory array 1850 can use the MSBs of memory from a data structure to achieve advantages beyond the scope of known memory layout arrangements, discussed in further detail below.

[0157] Memory array 1850 depicts two instances of memory arrangement 1854 and the remaining elements of the back-end ADC memory circuitry (e.g., back-end ADC memory circuitry 115) in a 2-pixel configuration. Figure 18C As shown, memory array 1850 includes, for example, two instances of a comparator and write control circuit 1852 (e.g., comparator 120 and write control circuit 130 include positive feedback circuit 131). In some embodiments, each pixel has an instance of comparator and write control circuit 1852, as well as a 6-bit memory arrangement 1854 with bits D0-D5 communicating with bit lines B0-B5. In some embodiments, the MSB, D5, is configured so that it is directly or indirectly coupled to the corresponding instance of the write control circuit. In this way, in the case of a memory with CMOS level outputs, communication and wiring of the state is relatively efficient without modifying the alignment with memory arrangement 1854. This can achieve the technical effect of having a DPS imaging system with lower power consumption, fast operation, and also allows the use of small pixel sizes in some types of memory devices.

[0158] Figure 1915 or 16. In some embodiments, the circuit to which this timing diagram is applied is the same as any of the circuits shown in FIG1 , 15 or 16, except that such circuit does not need to have a state latch (e.g., state latch 140, 1540, 1640), but uses the most significant bit (MSB) of the ADC code as State (or State_n). In addition, the timing diagram 1900 is applicable to Figure 18A Data structures 1800 and 1820 and Figure 18C Memory array 1850.

[0159] Timing diagram 1900 illustrates an example of overlapping 3Q operations that apply state control to the data structure of memory array 1850. For example, the MSB of the time code (e.g., the MSB of flag bits 1808, 1812, 1816) can be used as the state to control initialization operations. Another flag bit may not be necessary for state control, but can be used to distinguish ADC1, ADC2, and ADC3 from each other. Figure 19 The operations and timing shown in the timing diagram 1900 are similar to Figure 17 The difference of the timing diagram 1700 is that Figure 19 STATE_DATA (or ADC code <5> ) throughout the LCG ADC is set to logic 0, the time code (or ADC code <5> ) is used as STATE_DATA. STATE_DATA=0 remains in the final ADC operation (ie, LCG ADC). Figure 19 In the ADC, the status data in LCGADC is set to logic 0.

[0160] In some embodiments, an auto-zero operation is performed before each ADC operation. To perform the auto-zero operation, COMP_RST may be set to 1 (e.g., COMP_RST=1). In some embodiments, the comparator (e.g., comparator 120, 1520, 1620) performs an initialization operation of setting COMP_SET to 1 (e.g., COMP_SET=1), which releases the positive feedback circuit (e.g., positive feedback circuit 131, 1531, 1631) from the locked state after each auto-zero operation. In some embodiments, the comparator (e.g., comparator 120, 1520, 1620) may perform an initialization operation of setting COMP_SET_n to 0 (e.g., COMP_SET_n=0). During the period when STATE_DATA is set to logic 1, when the comparator is flipped, the time code (i.e., ADC code) is written to the memory and retained for the remainder of one ADC cycle. STATE_DATA (ADC code) <5> ) is set to logic 1, and ADC code <4:0> increases from "100000" to "101111". The comparator initialization operation and ADC operation released from the locked state can be similar to the above Figure 17 1700 as described in the timing diagram.

[0161] Timing diagram 1900 shows three cases:

[0162] Case 1 - Output OutB flips once;

[0163] Case 2 – Output OutB toggles twice; and

[0164] Case 3 - Output OutB flips three times.

[0165] As shown in the timing diagram 1900, for Case 1, at time t2, when the output OutB (WL) switches from logic 1 to logic 0, the state is maintained at the same level as the ADC code <5> Same value (i.e., the MSB of the time code when OutB is inverted). Figure 19As shown, in the current ADC operation cycle started at time t1, if OutB(WL) is reversed from logic 1 to logic 0 during the time stamp ADC, for example, at time t2, when the ADC code is as shown in case 1 <5> =1 (i.e., MSB=1), the time code (i.e., ADC code) at time t2 is written to the memory (e.g., ADC memory 150, 1550, 1650), and the MSB of the time code written to the memory at time t2 is output from the memory as State, with State set to logic 1 (i.e., State=1). In some cases, setting State to logic 1 causes the comparator (e.g., comparator 120, 1520, 1620) and the positive feedback circuit (e.g., positive feedback circuit 131, 1531, 1631) to enter a locked state. Since State remains at logic 1 (i.e., State=1) for the remainder of the current cycle of ADC operation, even when COMP_SET becomes logic 1 before entering the HCG ADC or LCG ADC, the ADC code stored in the memory is retained until the end of the current cycle of ADC operation at time t9.

[0166] For cases 2 and 3, if OutB(WL) switches from logic 1 to logic 0 during the timestamp ADC period and the ADC code <5> = 0, for example, at time t3 as shown in case 2, or at time t4 as shown in case 3, then the time code (i.e., ADC code) at time t3 or time t4 is written into the memory (e.g., ADC memory 150, 1550, 1650), and since the ADC code <5> =0, State is set to logic 0 (i.e., State=0). Thus, in case 2 or case 3, when COMP_SET is set to logic 1 (or COMP_SET_n is set to logic 0) at time t5 before the start of HCG ADC, the initialization circuit (e.g., initialization circuit 132, 1532, 1632) changes the comparator (e.g., comparator 120, 1520, 1620) and the positive feedback circuit (e.g., positive feedback circuit 131, 1531, 1631) to the unlocked state, and HCG ADC has started.

[0167] In case 2, during the HCG ADC period, OutB(WL) switches from logic 1 to logic 0. For example, at time t7, when the ADC code <5> =1, the time code (i.e., ADC code) at time t7 is written to the memory (e.g., ADC memory 150, 1550, 1650), and State is set to logic 1 (i.e., State=1), which causes the comparator (e.g., comparator 120, 1520, 1620) and the positive feedback circuit (e.g., positive feedback circuit 131, 1531, 1631) to become locked again. In case 2, since State is maintained at logic 1 (i.e., State=1) for the remainder of the current cycle of ADC operation, even when COMP_SET becomes logic 1 before entering the LCG ADC, the ADC code stored in the memory during the HCG ADC is maintained until the end of the current cycle of ADC operation at time t9.

[0168] In case 3, OutB (WL) inverts from logic 1 to logic 0 during LCG ADC (e.g., at time t9). At time t9, STATE DATA = 0, so the data is written to the memory (e.g., ADC memory 150, 1550, 1650) and State is set to logic 0 (i.e., State = 0).

[0169] Figure 20 is a schematic diagram of an example DPS image sensing system 2000 according to one or more embodiments. As described above, any active pixel and its components can be incorporated into the DPS image sensing system 2000. In some embodiments, the DPS image sensing system 2000 includes Figure 1A The features and components of the DPS image sensing system 100A are similar to those of the DPS image sensing system 100A, and the previous description is applicable. In some embodiments, the DPS image sensing system 2000 can be modified to include the same Figure 1B The features and components of the DPS image sensing system 100B are similar to those of the DPS image sensing system 100B, and the previous description is applicable. The DPS image sensing system 2000 includes a small area with high-density memory, which can improve efficiency and can be easily arranged. In some embodiments, write control can be performed with a latch circuit even when many ADC iterations are applied. In this way, the DPS image sensing system 2000 can provide a simple and robust arrangement with independently arranged comparators and memory areas, thereby providing efficient use of memory with a small footprint. In addition, as discussed in further detail below, a flexible combination of flag bits and ADC data can efficiently allocate memory.

[0170] In some embodiments, the DPS image sensing system 2000 includes an active pixel 2010, a comparator 2020, a write control circuit 2030 including a state latch 2040, and an ADC memory 2050 operatively coupled to a read / write data bus 2060. In some embodiments, the active pixel 2010 includes an intra-pixel lateral overflow integration capacitor (LOFIC). In some embodiments, the active pixel 2010 can be connected to a Figure 2A and Figure 2B The active pixels 2010 function similarly and the previous description is applicable. As discussed above, the active pixels 2010 can be configured for bidirectional charge transfer and full charge transfer by means of an induced electron drift current. In some embodiments, the active pixels 2010 include a photodiode (PD), a transfer gate (TG), a floating diffusion node (FD), and one or more control transistors (e.g., RST, DCG, Vbn_sf). The active pixels 2010 are interchangeably referred to herein as first-tier on-chip sensor (SOC) pixels, first-tier SOC active pixels, and / or SOC active pixels.

[0171] In some embodiments, comparator 2020, write control circuit 2030, state latch 2040, and ADC memory 2050 may form a second-tier application-specific integrated circuit (ASIC) active pixel. The second-tier ASIC active pixel is interchangeably referred to herein as a second-tier active pixel and / or a second-tier ASIC pixel.

[0172] In some embodiments, write control circuitry 2030 and / or state latch 2040 can facilitate state control of ADC memory 2050. As discussed in further detail below, DPS image sensing system 2000 can implement a novel write control scheme implemented on write control circuitry 2030 for performing multiple ADC operations in a DPS with a small pixel area and efficient memory usage. For example, in some embodiments, state latch 2040 operates independently of n-bit ADC memory 2050 and control comparator 2020. Flag bit 2052 can be implemented as an ADC ID. In some embodiments, flag bit 2052 can be written as part of n-bit ADC memory 2050 in combination with ADC data bits 2054.

[0173] In some embodiments, write control for multiple ADC operations implemented via write control circuit 2030 may be applied according to the following method:

[0174] (1) In the first case, where state=0 is output from the state latch 2040 , a write operation to the write memory (eg, the ADC memory 2050 ) may be activated, and data may be written via the comparator 2020 flip.

[0175] (2) In the second case, where state=1 is output from the status latch 2040, the write operation may be disabled.

[0176] In some embodiments, the status latch 2040 may operate according to the following write scheme:

[0177] (1) Initialize the state to state = 0;

[0178] (2) Provide a control signal COMP_CHECK as a window period for each ADC operation;

[0179] (3) Determine whether state = 0 or state = 1 based on the comparator output during the window period (e.g., comparator 2020);

[0180] (4) Once the state transitions to state = 1, the memory (e.g., ADC memory 2050) cannot be written to and the memory retains the last ADC data; and

[0181] (5) The ADCID flag is combined with the ADC data for each ADC operation.

[0182] As described herein, only one latch circuit (e.g., state latch 2040) is used to control multiple iterations of ADC operation, and the latch circuit is more efficient than multiple iterations of ADC operation. In some embodiments, flag bits 2052 can be flexibly combined with ADC data bits 2054 in ADC memory 2050 to achieve the most efficient memory usage. In addition, control signal COMP_CHECK is also interchangeably referred to herein as "COMP_CHECK" and / or comparator check signal.

[0183] The ADC memory 2050 may include word lines (WL) and N bit lines (BL) (e.g., bit line m to bit line Nm), and the N bit lines may operate as a read / write data bus 2060. The structure of the word lines and bit lines depends on the type of memory implemented by the DPS image sensing system 2000. For example, the ADC memory 2050 may implement an SRAM memory structure such that the bit lines are differential pairs. In some embodiments, the ADC memory 2050 may utilize a flash memory structure, a DRAM memory structure, a non-volatile memory device, a volatile memory, other types of solid-state memory devices, and / or a disk drive memory device.

[0184] In some embodiments, ADC operations can be performed as write operations on ADC memory 2050. Write control circuit 2030 can control word line WL based on the output of comparator 2020 (e.g., output COMP_OUT). Read / write data bus 2060 can provide counter data synchronized with ramp waveform VRAMP. Counter data at the time of a transition of output COMP_OUT is stored in ADC memory 2050. Written memory data can be read and controlled by signal WL_READ.

[0185] In some embodiments, digital pixel sensors require efficient use of physical area (e.g., on-chip space) for small pixel sizes. Multiple ADC operations with different sensitivities for active pixels can be effectively used for high dynamic range. To save memory area, ADC data can be stored in a memory (e.g., ADC memory 2050), where a flag bit 2052 is used as an identifier to distinguish each ADC operation. In some embodiments, a 1-bit state latch (e.g., state latch 2040) can be applied for efficient memory usage. The state latch 2040 is independently arranged in the DPS image sensing system 2000 as part of the write control circuit 2030. Doing so can provide a robust architecture and improve upon known memory write schemes, in which the flag bit memory is separated from the data bit memory and can also be used as part of the write control circuit 2030.

[0186] As long as the circuit of DPS image sensing system 2000 is properly modified, Figures 2A-14 Any one or more active pixels described in the embodiments of can be implemented as active pixels 110 of or active pixels 110 of respectively, as understood by one of ordinary skill in the art.

[0187] Figure 21 FIG. 2 is a schematic diagram of an example DPS image sensing system 2100 including a write control circuit 2130 and a data memory according to one or more embodiments. Figure 202 is an exemplary embodiment of a DPS image sensing system 2000, and the previous description is applicable. In some embodiments, the write control circuit 2130 may include a state latch 2140 and one or more write control transistors 2142. The write control circuit 2130 is initialized to a zero state (e.g., state = 0) by setting STATE_RST = 1 and by connecting the word line (WL) to WL_WRITE, a signal from COMP_OUT. In some embodiments, COMP_CHECK can be set to 1 (e.g., COMP_CHECK = 1) and applied to determine whether COMP_OUT has flipped (e.g., COMP_OUT = 1) or not flipped (e.g., COMP_OUT = 0) at the appropriate time during each ADC operation, which is discussed in further detail below.

[0188] As long as the circuit of the DPS image sensing system 2100 is properly modified, Figures 2A-14 Any one or more active pixels described in the embodiments of the present invention may be implemented as understood by those skilled in the art. Figure 21 Active pixels of the DPS image sensing system 2100.

[0189] Figure 22 2200 is a timing diagram of an exemplary operation of an ADC according to one or more embodiments. The timing diagram 2200 may describe a 2Q ADC operation. For example, a 5-bit memory may be allocated as 1 flag bit and 4 ADC data bits. In some embodiments, the 2Q operation may be combined with a timestamp ADC and a linear ADC. This achieves the technical effect of making the read operation and circuit less complex because no state latch data is required to perform the read. In addition, a memory bank combining flag bits and ADC data bits is read. This facilitates additional technical features for improving small pixels when the pixel size is limited by the number of lines. Memory arrays are typically highly dense, and therefore simplifying the wiring scheme results in smaller pixel sizes even if additional state latches are required.

[0190] In timing diagram 2200, for Case 1, COMP_CHECK = 1 applies, including the moment at which the timestamp ADC portion of the ADC cycle ends. When comparator 2120 flips during the first ADC period of the timestamp ADC, at time t2, the output of comparator 2120 changes to COMP_OUT = 1 at the end of the first ADC, and the State value also changes to State = 1. As shown in Case 1, any time can be used for COMP_CHECK up to and including the end of the first ADC, i.e., COMP_CHECK = 1 at time t3. The State = 1 state indicates that word line WL is connected to WL_READ. This means that the memory is not overwritten after State = 1. At time t4, comparator 2120 flips from a logic 1 state to a logic 0 state, however, State remains at a logic 1 state. At time t5, comparator 2120 flips again to a logic 1 state (e.g., COMP_OUT = 1) during the linear ADC portion of the ADC operation. However, in Case 1, State remains fixed at State = 1 through the linear ADC portion until the ADC operation ends at time t8.

[0191] In timing diagram 2200, for Case 2, when comparator 2120 does not flip during the first ADC period of the timestamp ADC, write control circuit 2130 maintains the state at State = 0, and word line WL can still be connected to WL_WRITE. At time t7, during the linear ADC portion, comparator 2120 flips from logic 0 to logic 1 (e.g., COMP_OUT = 1), and the state also flips to State = 1. In some cases, the memory can then be written during the next (e.g., subsequent) linear ADC period.

[0192] Figures 23A to 23C 2300, 2320, and 2340 according to one or more embodiments. The data structures 2300, 2320, and 2340 may represent ADC data structures having a combination of flag bits and ADC data bits. Some embodiments include a quadratic ADC example, such as Figure 23B and Figure 23C The data structures 2320 and 2340 are shown respectively. In some embodiments, the triple ADC has the advantage of having fewer instances than the quadruple ADC.

[0193] Figure 23A The data structure 2300 corresponds to three ADC examples. Figure 23AIn the data structure 2300, if the flag bits are arranged independently, the data structure 2300 may include 2 flag bits. The ADC data bits of the ADC may become N-2 bits in the data structure 2300. In some embodiments, the digital pixel sensor system may enable the use of 1.5 flag bits, as shown in the data structure 2300. Each flag bit may be designated as "0 0" for ADC1, "0 1" for ADC2, and "1" for ADC3. Therefore, N-1 bits may be designated for ADC3. Therefore, higher resolution may be used for the same storage bit, and one state latch for write control may be effective for a given physical area of ​​the system. Furthermore, write control using one state latch improves the robustness and simplicity of the pixel structure, which in turn provides significant technical advantages when increasing the number of ADC operations.

[0194] Figure 23B and Figure 23C Data structures 2320 and 2340 respectively illustrate examples of use cases including four ADCs. In data structure 2320, two (2) flag bits are equally allocated to each of the four ADC operations, and each resolution is N-2 bits. In data structure 2340, different flag bit and resolution schemes are adopted. For example, for a higher resolution ADC operation (e.g., ADC4), N-1 ADC data bits can be used with 1 flag bit. As ADC4, in the example of data structure 2340, includes N1 ADC data bits and 1 flag bit, the lower resolution ADC operations (e.g., ADC1 and ADC2) can be N3 ADC data bits plus 3 flag bits as a compromise. This enables data structure 2340 to achieve higher resolution even when using one ADC, which is beneficial for multiple ADC operations of a digital pixel sensor (e.g., sensing front-end circuit 112). The flexible flag bit arrangement of data structures 2320 and 2340 can give a technical effect of improving memory usage efficiency.

[0195] Figure 24 2400 is a timing diagram of an exemplary operation of an ADC according to one or more embodiments. In some embodiments, the timing diagram 2400 describes the operation of an ADC using a write control circuit (e.g., Figure 212130). In timing diagram 2400, the ADC state includes a timestamp ADC operation and two linear ADC operations. In some embodiments, one of the two linear ADC operations can be configured for low conversion gain (LCG), and one of the two linear ADC operations can be configured for high conversion gain (HCG). The three ADC operations can be performed during an exposure period (e.g., the period during which the pixels of the DPS image sensing system 2100 are exposed to incident light). In some embodiments, as shown in the ADC code in timing diagram 2400, a 5-bit memory situation is implemented using a flag bit.

[0196] Timing diagram 2400 includes three use cases that illustrate three different behaviors of comparator 2120. In the first case, "Case 1," a large signal level is present. In Case 1, during a first ADC operation (e.g., a timestamp ADC operation), the comparator (e.g., comparator 2120) flips from logic 0 to logic 1 (e.g., COMP_OUT=1) at time t3. Subsequently, the state flips from State=0 to State=1. After the state changes to State=1, the memory is not written to ADC memory 2150, and the first ADC data bit is retained.

[0197] In the second case, "Case 2," there is a medium signal level. In Case 2, during a second ADC operation (e.g., a timestamp ADC operation), the comparator (e.g., comparator 2120) flips from logic 0 to logic 1 (e.g., COMP_OUT = 1) at time t5. Subsequently, the state flips from State = 0 to State = 1. Additionally, during the second ADC operation (e.g., an LCG ADC operation), when COMP_CHECK = 1, a second ADC data bit is stored.

[0198] In the third case, "Case 3," a low signal level is present. In Case 3, during the second ADC operation, the comparator (e.g., comparator 2120) flips from logic 0 to logic 1 (e.g., COMP_OUT=1) at time t7. However, in Case 3, because COMP_CHECK=0 when the comparator flips, the state may remain at State=0. COMP_CHECK=0 may be specified for very small signal terms in LCG ADC operation. The memory (e.g., ADC memory 2150) may be rewritten during the third ADC operation (e.g., HCG ADC operation).

[0199] Figure 252 is a schematic diagram of a DPS image sensing system 2500 including a comparator 2520, a write control circuit 2530, and a state latch 2540 according to one or more embodiments. In some embodiments, one or more components of the DPS image sensing system 2500 may be included in the DPS image sensing system 2000. The write control circuit 2530 includes a positive feedback circuit 2531 that outputs a feedback signal FB. After the positive feedback circuit 2531 flips FB from 0 to 1, FB can remain at 1 regardless of the value of the output 'OutA' of the comparator 2520. Then, COMP_SET is set to 1 (e.g., COMP_SET=1) for initialization operation to set OutB of the write control circuit 2530 to 1 (e.g., OutB=1) and FB to 0 (e.g., FB=0).

[0200] In some embodiments, the initialization operation begins by setting State = 0. When COMP_SET_n is also set to 1 (e.g., COMP_SET_n = 0), initialization is completed as OutB becomes 1 (e.g., OutB = 1). The state latch 2540 can output "State" to control the initialization operation, and the comparator 2520 only operates for the state set to 0 (e.g., State = 0).

[0201] In some embodiments, the operation of the comparator 2520 may be:

[0202] (1) Use reset level VRAMP and COMP_RST = 1 for auto-zero operation;

[0203] (2) After COMP_RST becomes COMP_RST=0, the initialization operation is completed using COMP_SET_n=0 and VRAMP at the starting level. In addition, when State=0, OutB becomes OutB=1 or when State=1, OutB=0;

[0204] (3) In the former case, the ramp-up operation of VRAMP is performed, and the ADC data can be written into the ADC memory when the comparator 2520 flips. In addition, OutB remains at OutB=0, and because the word line WL=0, the data is not written into the memory.

[0205] In some embodiments, the switch between OutA and GND controlled by COMP_SET_n can be removed because OutA=0 (e.g., GND) can be set with the appropriate VRAMP voltage after the auto-zero operation. Since COMP_SET_n=0, OutB becomes OutB=1, and State=0 is added with the appropriate VRAMP voltage. In some embodiments, STATE_DATA can be connected to the state latch 2540 and can be combined with two inverters using a switch through an nMOS transistor pair, such as Figure 25 In this case, when comparator 2520 changes word line WL from 1 to 0 (e.g., from WL=1 to WL=0), the state node is fixed to State=STATE_DATA during the flip of comparator 2520. ADC memory (e.g., ADC memory 2050) can also store bit line data at the same time. STATE_DATA is intentionally controlled to be set to the appropriate state.

[0206] As long as the circuit of the DPS image sensing system 2500 is properly modified, Figures 2A-14 Any one or more active pixels described in the embodiments of the present invention may be implemented as understood by those skilled in the art. Figure 25 Active pixels of the DPS image sensing system 2500.

[0207] Figure 26 is a schematic diagram of an example DPS image sensing system 2600 including a comparator 2620, a write control circuit 2630, and a state latch 2640. In some embodiments, Figure 25 Compared to the write control circuit 2530 of FIG5 , an nMOS transistor 2634 can be added to the write control circuit 2630 to serve as a CMOS structure for both the COMP_SET_n signal and the FB signal. In some embodiments, the nMOS transistor 2634 can be used to accelerate the flipping of the positive feedback circuit of the write control circuit 2630. An nMOS switch can also be added to the write control circuit 2630 between OutA of the comparator 2620 and ground (GND). This can prevent large delays when performing initialization of the DPS image sensing system 2600 for large values ​​of capacitor CL.

[0208] As long as the circuit of the DPS image sensing system 2600 is properly modified, Figures 2A-14 Any one or more active pixels described in the embodiments of the present invention may be implemented as understood by those skilled in the art. Figure 26 DPS Image Sensing System 2600.

[0209] Figure 27is a timing diagram 2700 of an exemplary operation of an ADC according to one or more embodiments. In some embodiments, the timing diagram 2700 depicts the overlap of three quantization operations, which may be performed using Figure 26 In some embodiments, the three quantization operations described in timing diagram 2700 are Figure 24 The three quantization operations described in the timing diagram 2400 are the same or similar, but the order of the HCG ADC operation and the LCG ADC operation is reversed.

[0210] As shown in timing diagram 2700, during HCG ADC operation, it is desirable to store the dark signal for toggling at a high VRAMP voltage as HCG ADC data, and it is desirable to overwrite the light signal level for toggling at a low VRAMP voltage with the LCG ADC data. In timing diagram 2700, three use cases are presented: Case 1, Case 2, and Case 3. In Case 1, output OutB toggles from logic 0 to logic 1 once. In Case 2, output OutB toggles from logic 0 to logic 1 twice. In Case 3, output OutB toggles from logic 0 to logic 1 three times. When OutB toggles from 1 to 0 (e.g., OutB=1 to OutB=0), if STATE_DATA=1, the state can change from 0 to 1 (e.g., state=0 to state=1).

[0211] In some embodiments, multiple applications may be performed. Figures 25 and 26 The combination of the positive feedback circuit and the state latch structure (e.g., state latch 2640) shown in . For example, Figure 21 Comparator 2120 cannot perform the above operation because when COMP_CHECK=1, state latch 2140 changes state to 1 (e.g., state=1) in response to detecting OutA=0. Data stored in the HCG ADC operation can be pre-flipped instead of rewriting the data using the LCG ADC operation, however, the flipping time is reversed. Therefore, DPS image sensing system 2100 adopts a control scheme that may be problematic in this specific use case. On the other hand, DPS image sensing system 2500 may be more suitable for this particular case because the state signal of state latch 2540 is STATE_DATA when comparator 2520 flips, making DPS image sensing system 2500 more flexible than DPS image sensing system 2100 for the above use case.

[0212] Figures 28A to 28Cis a schematic diagram of an exemplary data structure according to one or more embodiments. is a schematic diagram of exemplary data structures 2800, 2820 and 2840 according to one or more embodiments. Also described herein is a method for using data structures 2800, 2820 and / or 2840 to provide efficient memory usage for multiple ADC operations in a digital pixel sensor system. Data structures 2800, 2820 and 2840 are configured for use in a system having a pixel structure that includes: an active pixel having a photodiode, a comparator, an n-bit memory, a state latch for state control, or other components. For example, data structures 2800, 2820 and 2840 can be used with a DPS imaging sensing system (such as DPS image sensing system 2000). In some embodiments, data structures 2800, 2820 and 2840 can be configured for use in a write control circuit, such as write control circuit 130 of FIG. 1, Figure 20 The write control circuit 2030 and other write control circuits described herein. As discussed above, the circuitry of the state latch can operate independently of the memory and control comparator operation. In some embodiments, a flag bit in the memory that can be used as an ADC identifier is written as part of the n-bit memory and combined with the ADC data (e.g., ADC data bits).

[0213] Figure 28A Data structure 2800 can be configured for performing three ADC operations. Data structures 2820 and 2840 are each configured for performing four ADC operations. For many DPS systems, regardless of the type of memory implemented (e.g., SRAM, DRAM, etc.), the majority of the area is consumed by the memory portion. This is particularly likely when performing multiple ADC operations, as each ADC operation requires at least the Nth bit of memory.

[0214] In some embodiments, a write control circuit for multiple ADC operations (e.g., write control circuit 2030) may utilize data structures 2800, 2820, and / or 2840. In some embodiments, data structures 2800, 2820, and 2840 may combine flag bits and ADC data bits. Data structures 2800, 2820, and 2840 provide efficient use of memory by exhibiting flexibility in allocating various resolutions. Using a combination of flag bits and ADC data bits of different lengths, different ADC resolutions are applied to each ADC operation, giving the technical effect of providing flexible communication of flag bits and ADC data bits, which can be allocated to memory in an efficient manner. Regardless of how many ADC operations are performed, a higher resolution is allocated to the N-1 ADC data bits. In addition, using the most significant bit (MSB) for state control can save the number of memory bits used.

[0215] In some embodiments, data structure 2800 enables the use of 1.5 flag bits. For data structure 2800, the flag bit associated with the first ADC operation (e.g., ADC1) can be assigned a value of "0 0", the flag bit associated with the second ADC operation (e.g., ADC2) can be assigned a value of "0 1", and the flag bit associated with the third ADC operation (e.g., ADC3) can be assigned a value of "1". Data structure 2800 enables N-1 bits to be assigned for the last ADC operation (e.g., ADC3), thereby enabling higher resolution to be obtained on the same memory bit. In some embodiments, a state latch can be included for write control, which is also region-effective. Some embodiments may include two flag bits and logic circuitry for one write control signal. In some embodiments, the write control circuitry with one state latch enables a simplified pixel structure with improved efficiency for an increased number of ADC operations.

[0216] In some embodiments, data structure 2820 includes four ADC operations. For data structure 2820, the flag bits associated with the first ADC operation (e.g., ADC1) may be assigned a value of "0 0 0," the flag bits associated with the second ADC operation (e.g., ADC2) may be assigned a value of "0 0 1," the flag bits associated with the third ADC operation (e.g., ADC3) may be assigned a value of "0 1," and the flag bits associated with the fourth ADC operation (e.g., ADC4) may be assigned a value of "1." Data structure 2820 includes 3 flag bits for the first and second ADC operations, 2 flag bits for the third ADC operation, and 1 flag bit for the fourth ADC operation. Additionally, the ADC data bits may be N-3 bits for the first and second ADC operations and N-2 bits for the third and fourth ADC operations.

[0217] In some embodiments, the data structure 2840 includes four ADC operations, and each resolution (e.g., the resolution of each ADC operation) may be N-2 bits. For the data structure 2840, the flag bit associated with the first ADC operation (e.g., ADC1) may be assigned a value of "0 0," the flag bit associated with the second ADC operation (e.g., ADC2) may be assigned a value of "01," the flag bit associated with the third ADC operation (e.g., ADC3) may be assigned a value of "1 0," and the flag bit associated with the fourth ADC operation (e.g., ADC4) may be assigned a value of "1 1."

[0218] If flag bits are specified, as in data structures 2820 and 2840, the most significant bit can be used as a status signal. For example, the most significant bit of the last ADC operation stored in data structure 2820 is "1." The most significant bit of each of the other ADC operations stored in data structure 2820 is "0." Data structures 2820 and 2840 allow for flexible flag bit arrangement, which has the technical effect of improving memory usage efficiency in digital pixel sensing systems.

[0219] In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The words "comprising" or "including" do not exclude the presence of elements or steps other than those listed in the claim. In a device claim enumerating several means, several of these means may be embodied by one and the same item of hardware. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. In any device claim enumerating several means, several of these means may be embodied by one and the same item of hardware. The sole fact that certain elements are recited in mutually different dependent claims does not mean that these elements cannot be used in combination.

[0220] Although the description provided above provides details for the purpose of illustrating what are presently considered to be the most practical and preferred embodiments, it should be understood that such details are for that purpose only and that the present disclosure is not limited to the expressly disclosed embodiments, but on the contrary is intended to cover modifications and equivalent arrangements within the spirit and scope of the appended claims. For example, it should be understood that the present disclosure contemplates that, to the extent possible, one or more features of any embodiment can be combined with one or more features of any other embodiment.

[0221] Additional exemplary embodiments are provided with reference to the following enumerated embodiments:

[0222] A1. A back-end analog-to-digital conversion (ADC) storage circuit, the back-end ADC storage circuit comprising: a comparator operatively coupled to an active pixel and configured to receive an output of the active pixel; a write control circuit; an ADC memory operatively coupled to the write control circuit; and a status latch operatively coupled to the write control circuit, the status latch being configured to control whether writing to the ADC memory is enabled or disabled.

[0223] A2. The back-end ADC storage circuit of embodiment A1, wherein the status latch is used to control ADC operation.

[0224] A3. The back-end ADC storage circuit of embodiment A2, wherein the state latch is configured to output a 1-bit Boolean control signal to control the ADC operation.

[0225] A4. The back-end ADC storage circuit of any one of embodiments A1-A3, wherein the ADC operation comprises at least one of a timestamp ADC operation, a high conversion gain ADC operation, or a low conversion gain ADC operation.

[0226] A5. The back-end ADC memory circuit of any one of embodiments A1-A4, wherein the control signal output from the status latch controls whether writing to the ADC memory is enabled or disabled by toggling a word line operatively coupled to the ADC memory.

[0227] A6. A back-end ADC storage circuit according to any one of embodiments A1-A5, wherein the write control circuit includes: a positive feedback circuit configured to receive the output from the comparator as a first input and receive the output of the positive feedback circuit as a second input.

[0228] A7. The back-end ADC storage circuit according to embodiment A6, wherein the positive feedback circuit includes an inverter.

[0229] A8. The back-end ADC storage circuit according to any one of embodiments A1-A7, wherein the write control circuit comprises: an initialization circuit comprising a pair of transistors configured to function as NAND gates.

[0230] A9. The back-end ADC storage circuit of any one of embodiments A7-A8, wherein when the output of the positive feedback circuit is a first value, the positive feedback circuit is in a locked state.

[0231] A10. The back-end ADC storage circuit of embodiment A9, wherein the first value comprises a logic 0 or a logic 1.

[0232] A11. The back-end ADC storage circuit of embodiments A8-A10, wherein the initialization circuit is configured to release the locked state of the positive feedback circuit using a control signal output from the state latch.

[0233] A12. A back-end ADC storage circuit according to any one of embodiments A1A10, wherein the write control circuit includes: a positive feedback circuit, which includes a first transistor associated with the output of the comparator and a second transistor associated with the output of the positive feedback circuit; and an initialization circuit, which includes a transistor pair formed by a third transistor and a fourth transistor.

[0234] A13. The back-end ADC storage circuit according to embodiment A12, wherein, for a logic state of the gate of the first transistor or a logic state of the gate of the second transistor being high, the output of the write control circuit is a first value; and for a logic state of the gate of the third transistor and a logic state of the gate of the fourth transistor being low, the output of the write control circuit is a second value.

[0235] A14. The back-end ADC storage circuit of any one of embodiments A12-A13, wherein the output of the write control circuit is a first value when the logic state of the gate of the third transistor or the logic state of the gate of the fourth transistor is high; or, the output of the write control circuit is a second value when the logic state of the gate of the third transistor and the logic state of the gate of the fourth transistor are both low. A15. The back-end ADC storage circuit of any one of embodiments A13-A14, wherein the first value comprises a logic 1 and the second value comprises a logic 0; or the first value comprises a logic 0 and the second value comprises a logic 1.

[0236] A16. The back-end ADC storage circuit of any one of embodiments A1-A15, wherein the write control circuit comprises a read / write control circuit configured to perform a read operation. A17. An imaging system comprising: the active pixel; and the back-end ADC storage circuit of any one of embodiments A1-A16.

[0237] A18. The imaging system of embodiment A17, wherein the comparator is operatively coupled to the active pixel.

[0238] B1. An imaging system comprising: an active pixel; a comparator operatively coupled to the active pixel and configured to receive an output of the active pixel; and a back-end analog-to-digital conversion (ADC) storage circuit operatively coupled to the active pixel, the back-end ADC storage circuit comprising: a read / write control circuit; an ADC memory operatively coupled to a read / write data bus and the read / write control circuit; and a state latch operatively coupled to the read / write control circuit and the ADC memory.

[0239] B2. An imaging system according to embodiment B1, wherein the read / write control circuit includes: a NAND gate, which is operably coupled to the state latch; a NOR gate, which is operably coupled to the comparator; and a switch configured to couple the NAND gate and the NOR gate, wherein: the NAND gate receives as input a first signal output from the state latch and a second signal for setting the read / write control circuit, and the NOR gate receives as input a comparator output signal output by the comparator and a NAND output signal output by the NAND gate.

[0240] B3. The imaging system according to embodiment B2 further comprises: an inverting device operatively coupled to the NOR gate and the ADC memory, such that the inverting device inverts the value of the output of the NOR gate.

[0241] B4. The imaging system of embodiment B3, wherein, to initiate an analog-to-digital conversion process, the second signal is set to a first value such that the switch couples the NAND gate to the NOR gate and the comparator outputs a signal output having an output value. B5. The imaging system of any one of embodiments B3-B4, wherein, in response to the first signal being set to a second value: the output of the NAND gate has a value of 0 and the output of the NOR gate has a value of 1, and the comparator (i) is initialized by the node at the output of the inverting device having a value of 0, and (ii) causes the second signal to have a value of 0.

[0242] B6. The imaging system of embodiment B4, wherein the first value is a logic 1 or a logic 0, the second value is a logic 0 or a logic 1, and the output value is 0.

[0243] B7. The imaging system of any one of embodiments B3 to B6, wherein in response to the first signal being set to a value of 0, after the second signal is set to have a value of 0, the node at the output of the inverting device is maintained at a value of 1.

[0244] B8. The imaging system of any one of embodiments B3 to B7, wherein in response to the first signal being set to a value of 1, data is written to an ADC memory by the comparator.

[0245] B9. An imaging system as described in any one of embodiments B3 to B8, wherein an auto-zero operation is performed on the comparator by setting the comparator reset signal to have a value of 1, wherein the comparator takes as input (i) the comparator reset signal or the output of the active pixel, and (ii) a ramp voltage set at a reset level.

[0246] B10. The imaging system of embodiment B9, wherein the auto-zero operation is performed before each ADC operation by setting the comparator quiet signal to have a value of 1.

[0247] B11. An imaging system as described in any of embodiments B9 to B10, wherein an initialization operation is performed on the comparator after the auto-zero operation, wherein the initialization operation includes turning the node at the output end of the inverting device to a value from a value of 1 to a value of 0 in response to the second signal.

[0248] B12. An imaging system as described in embodiment B11, wherein for the first signal output from the state latch is set to a value of 1, the node at the output of the inverting device has a value of 0, and for the first signal output from the state latch is set to a value of 0, the node at the output of the inverting device remains at a value of 1.

[0249] B13. The imaging system of any one of embodiments B3 to B12, further comprising: a pair of nMOS transistors operably coupled to the state latch.

[0250] B14. The imaging system of any one of embodiments B3 to B13, wherein the read / write control circuit further comprises an nMOS transistor, wherein the nMOS transistor increases the speed at which the value of the node at the output of the inverting device switches.

[0251] B15. The imaging system of any one of embodiments B1 to B14, wherein the data structure for storing data in the ADC memory includes a flag bit configured for status control of the back-end ADC storage circuit.

[0252] C1. A back-end analog-to-digital conversion (ADC) circuit, comprising: a read / write control circuit; an ADC memory operatively coupled to a read / write data bus and the read / write control circuit; and a state latch operatively coupled to the read / write control circuit and the ADC memory, wherein the back-end ADC memory circuit is operatively coupled to a comparator configured to receive an output of an active pixel, wherein the read / write control circuit comprises: a NAND gate operatively coupled to the state latch; a NOR gate operatively coupled to the comparator; a switch configured to couple the NAND gate and the NOR gate, wherein: the NAND gate takes as input a first signal output from the state latch and a second signal for setting the read / write control circuit, the NOR gate takes as input a comparator output signal output by the comparator and a NAND output signal output by the NAND gate; and an inverting device operatively coupled to the NOR gate and the ADC memory, such that the inverting device inverts the value of the output of the NOR gate.

[0253] C2. The back-end ADC storage circuit of embodiment C1, wherein, to start the analog-to-digital conversion process, the second signal is set to a value of 1, so that the switch couples the NAND gate with the NOR gate, and the signal output of the comparator has a value of 0.

[0254] C3. A back-end ADC storage circuit as described in any one of embodiments C1 to C2, wherein: in response to the first signal being set to value 1: the output of the NAND gate has a value of 0 and the output of the NOR gate has a value of 1, and the comparator (i) is initialized by the node with a value of 0 at the output end of the inverting device, and (ii) causes the second signal to have a value of 0.

[0255] C4. A back-end ADC storage circuit as described in any one of embodiments C1 to C3, wherein in response to the first signal being set to a value of 0, after the second signal is set to have a value of 0, the node at the output end of the inverting device is maintained at a value of 1.

[0256] C5. A back-end ADC storage circuit as described in any one of embodiments C1 to C4, wherein an automatic zeroing operation is performed on the comparator by setting the comparator reset signal to have a value of 1, wherein the comparator takes (i) the comparator reset signal or the output of the active pixel, and (ii) a ramp voltage set at a reset level as input; and the automatic zeroing operation is performed before each ADC operation by setting the comparator reset signal to have a value of 1.

[0257] C6. A back-end ADC storage circuit as described in any one of embodiments C1 to C5, wherein for the first signal output from the state latch being set to a value of 1, the node at the output of the inverting device has a value of 0, and for the first signal output from the state latch being set to a value of 0, the node at the output of the inverter remains at a value of 1. D1. An active pixel for use in a digital pixel sensor (DPS) imaging system with full intra-pixel charge transfer, the active pixel comprising: a first photodiode; a first transfer gate operatively coupled to the first photodiode; and a second transfer gate operatively coupled to the first photodiode, wherein the first transfer gate and the second transfer gate are located on opposite sides of the first photodiode, and wherein: an electron drift current in the first photodiode causes bidirectional charge transfer of the first photodiode to the first transfer gate and the second transfer gate.

[0258] D2. An active pixel according to embodiment D1, wherein: the electron flow corresponding to the electron drift current is guided from the first side of the first photodiode to the second side of the first photodiode; and the first transfer gate and the second transfer gate are located on the second side of the first photodiode.

[0259] D3. The active pixel of any one of embodiments D1-D2, wherein the first transfer gate and the second transfer gate include an active layer intersecting a polysilicon layer and a charge well layer configured as a floating diffusion layer.

[0260] D4. The active pixel of any one of embodiments D1-D3, further comprising: a first floating diffusion node operatively coupled to the first transfer gate; and a second floating diffusion node operatively coupled to the second transfer gate.

[0261] D5. The active pixel of any one of embodiments D1-D3, further comprising: a floating diffusion node operably coupled to the first transfer gate; and a drain operably coupled to the second transfer gate and configured to receive charge output by the second transfer gate.

[0262] D6. The active pixel of any one of embodiments D1-D5, wherein the electron drift current is generated in response to an electric field applied to the active pixel, the electric field being based on an impurity concentration gradient of the first photodiode.

[0263] D7. The active pixel according to any one of embodiments D1-D3 and D6 further includes: a second photodiode; a third transfer gate operably coupled to the second photodiode; and a fourth transfer gate operably coupled to the second photodiode, wherein the third transfer gate and the fourth transfer gate are located on opposite sides of the second photodiode, and wherein: the electron drift current within the second photodiode causes charge transfer in two directions of the second photodiode to the third transfer gate and the fourth transfer gate.

[0264] D8. An active pixel according to embodiment D7, wherein: the electron drift current is guided from the first side of the second photodiode to the second side of the second photodiode; the direction of the electron drift current in the first photodiode is opposite to the direction of the electron drift current in the second photodiode, and the third transfer gate and the fourth transfer gate are located on the second side of the second photodiode.

[0265] D9. The active pixel of any one of embodiments D7-D8, wherein the third transfer gate and the fourth transfer gate are located on asymmetrically opposite sides of the second photodiode.

[0266] D10. The active pixel of embodiments D8-D9, further comprising: a first floating diffusion node operably coupled to the first transfer gate and the third transfer gate; and a second floating diffusion node operably coupled to the second transfer gate and the fourth transfer gate.

[0267] D11. The active pixel of embodiments D8-D9, further comprising: a first floating diffusion node operably coupled to the first transfer gate and the third transfer gate; and a drain operably coupled to the second transfer gate and the fourth transfer gate.

[0268] D12. The active pixel according to embodiments D7-D8 further includes: a third photodiode; a fourth photodiode; a fifth transfer gate operably coupled to the third photodiode; a sixth transfer gate operably coupled to the third photodiode; a seventh transfer gate operably coupled to the fourth photodiode; and an eighth transfer gate operably coupled to the fourth photodiode, wherein the fifth transfer gate and the sixth transfer gate are arranged on opposite sides of the third photodiode, and the seventh transfer gate and the eighth transfer gate are arranged on opposite sides of the fourth photodiode.

[0269] D13. The active pixel of embodiment D12, wherein the fifth transfer gate and the sixth transfer gate are located on asymmetrically opposite sides of the third photodiode.

[0270] D14. The active pixel of any one of embodiments D12-D13, wherein the seventh transfer gate and the eighth transfer gate are disposed on asymmetrically opposite sides of the fourth photodiode.

[0271] D15. An active pixel according to any one of embodiments D11-D14, wherein the electron flow corresponding to the electron drift current in the third photodiode causes charge transfer in two directions of the third photodiode to the fifth transfer gate and the sixth transfer gate, and the electron drift current in the fourth photodiode causes charge transfer in two directions of the fourth photodiode to the seventh transfer gate and the eighth transfer gate.

[0272] D16. The active pixel according to any one of embodiments D11-D15 further includes: a first drain, which is operably coupled to the first transfer gate of the first photodiode and the third transfer gate of the second photodiode; a second drain, which is operably coupled to the sixth transfer gate of the third photodiode and the eighth transfer gate of the fourth photodiode; and a floating diffusion node, which is operably coupled to the second transfer gate of the first photodiode, the fourth transfer gate of the second photodiode, the fifth transfer gate of the third photodiode, and the seventh transfer gate of the fourth photodiode.

[0273] D17. The active pixel of any one of embodiments D11-D15, further comprising: a first floating diffusion node operatively coupled to the first transfer gate of the first photodiode and the third transfer gate of the second photodiode; a second floating diffusion node operatively coupled to the second transfer gate of the first photodiode, the fourth transfer gate of the second photodiode, the fifth transfer gate of the third photodiode, and the seventh transfer gate of the fourth photodiode; and a third floating diffusion node operatively coupled to the sixth transfer gate of the third photodiode and the eighth transfer gate of the fourth photodiode. D18. The active pixel of any one of embodiments D1-D17, wherein: the electron drift current causes the bidirectional charge transfer of charge from the first photodiode to the first transfer gate and the second transfer gate; and the electron drift current is formed in response to an electric field generated within the first photodiode. D19. An active pixel according to embodiment D15, wherein the first photodiode includes a first layer and a second layer, and the electric field is generated within the first photodiode based on the first photodiode having an impurity concentration gradient caused by the first layer and the second layer each having a different impurity concentration.

[0274] D20. An active pixel according to embodiment D19, wherein: the first photodiode includes at least one additional layer, the additional layer having an impurity concentration different from the first layer and the second layer; and the magnitude and direction of the electric field are adjusted based on the number of layers included in the first photodiode.

[0275] D21. The active pixel of any one of embodiments D1-D20, wherein the first photodiode is a bidirectional charge transfer photodiode.

[0276] D22. The active pixel of any one of embodiments D1-D21, wherein the active pixel implements backside illumination and a pinned photodiode.

[0277] D23. The active pixel of any one of embodiments D1-D20, wherein a time-of-flight (ToF) measurement is determined using the active pixel.

[0278] D24. The active pixel of any one of embodiments D1-D23, wherein the first transfer gate and the second transfer gate are located on asymmetrically opposite sides of the first photodiode.

[0279] D25. A digital pixel sensor (DPS) imaging system for full intra-pixel charge transfer functionality, the DPS imaging system comprising one or more active pixels, wherein each of the one or more active pixels comprises an active pixel as described in any one of embodiments D1-D24.

[0280] D26. The DPS imaging system of embodiment D25, further comprising: a capacitor operably coupled to the second floating diffusion node or the drain.

[0281] E1. An application-specific integrated circuit (ASIC) active pixel, comprising: a comparator configured to receive the output of the photodiode of the SOC active pixel; a read / write control circuit operably coupled to the comparator and a status latch, the read / write control circuit being configured to: receive an output from the comparator and determine whether a read operation or a write operation will be performed based on the output from the comparator and the state of the status latch; and an analog-to-digital conversion (ADC) memory operably coupled to the read / write control circuit and a read / write data bus.

[0282] E2. The ASIC active pixel of embodiment E1, wherein: the ADC memory includes a word line and a plurality of bit lines; and the read / write control circuit is configured to control the word line based on the output from the comparator.

[0283] E3. The ASIC active pixel of any one of embodiments E1-E2, wherein during initialization of the ASIC active pixel: a reset signal is used to initialize a state of a state latch to 0; and a word line is configured to couple the ADC memory to a word line write connection, the word line write connection having a value based on an output from the comparator.

[0284] E4. The ASIC active pixel of any one of embodiments E1-E3, wherein during each analog-to-digital conversion (ADC) operation, a comparator check signal is applied to the output of the comparator to determine whether the comparator flips from a value of 1 to a value of 0 or vice versa.

[0285] E5. The ASIC active pixel of any one of embodiments E1-E4, wherein, for a comparator flip during a first analog-to-digital conversion (ADC) operation: a comparator check signal having a value of 1 is applied to the read / write control circuit at the end of the first ADC operation, and the value of the state of the state latch is 1; and a word line of the ADC memory is connected to a word line read connection so that data in the ADC memory is not overwritten.

[0286] E6. The ASIC active pixel of any one of embodiments E1-E5, wherein the comparator does not flip during a first analog-to-digital conversion (ADC) operation, the state of the state latch remains at a value of 0, and a word line of the ADC memory is connected to a word line write connection so that data is written to the ADC memory during a second ADC operation. E7. The ASIC active pixel of any one of embodiments E1-E6, wherein the ADC memory comprises a five-bit memory having one flag bit and four bits of ADC data. E8. The ASIC active pixel of any one of embodiments E1-E7, wherein the ADC memory comprises 1.5 flag bits for three ADC operations.

[0287] E9. The ASIC active pixel of embodiment E8, wherein a flag bit for a first ADC operation of the three ADC operations is assigned a value of 00; a flag bit for a second ADC operation of the three ADC operations is assigned a value of 01; a flag bit for a third ADC operation of the three ADC operations is assigned a value of 1; the ADC memory includes: N-2 bits of ADC data for the first ADC operation and the second ADC operation; and the ADC memory includes N-1 bits of ADC data for the third ADC operation.

[0288] E10. The ASIC active pixel of any one of embodiments E1-E7, wherein, for four ADC operations, the ADC memory comprises 2 flag bits and N-2 bits of ADC data for each of the four ADC operations.

[0289] E11. The ASIC active pixel of any one of embodiments E1 to E7, wherein, for four ADC operations, the ADC memory comprises: 3 flag bits and N-3 bits of ADC data for a first ADC operation and a second ADC operation; 2 flag bits and N-2 bits of ADC data for a third ADC operation; and 1 flag bit and N-1 bit of ADC data for a fourth ADC operation.

[0290] E12. An ASIC active pixel according to any one of embodiments E1 to E11, wherein the data provided by the read / write data bus is synchronized with the waveform of a ramp function, and the ramp function is provided as an input to the comparator; so as to store the data in the ADC memory based on the output of the comparator flipping.

[0291] E13. The ASIC active pixel of any one of embodiments E1 to E12, wherein ADC data is stored in the ADC memory, the ADC data comprising one or more flag bits configured to serve as identifiers for each ADC operation performed.

[0292] E14. The ASIC active pixel according to any one of embodiments E1 to E13, wherein the ASIC active pixel is operably coupled to a system on chip (SOC) active pixel comprising one or more photodiodes.

[0293] E15. An imaging system comprising the ASIC active pixel according to any one of embodiments E1 to E14.

[0294] E16. An analog-to-digital conversion (ADC) circuit comprising the ASIC active pixel according to any one of embodiments E1 to E14.

[0295] E17. A digital pixel sensing (DPS) imaging system comprising the ASIC active pixel of any one of embodiments E1-E14.

[0296] F1. An imaging system comprising: an active pixel including a photodiode; a comparator operably coupled to the active pixel and configured to receive an output of the photodiode; a read / write control circuit including a state latch and operably coupled to the comparator and configured to receive an output from the comparator; and an analog-to-digital conversion (ADC) memory operably coupled to the read / write control circuit, wherein a data structure is stored in the ADC memory, the data structure being configured to store one or more flag bits and one or more ADC data bits for identifying each ADC operation.

[0297] F2. The imaging system of embodiment F1, wherein the state latch is configured to operate independently of control operations of the ADC memory and the comparator.

[0298] F3. An imaging system according to any one of embodiments F1-F2, wherein: for the state of the state latch having a zero value, a write operation to write data to an ADC memory is activated; and in response to the output of the comparator being flipped, the data is written to the ADC memory.

[0299] F4. The imaging system of any one of embodiments F1-F3, wherein write operations are disabled for a state of the status latch having a value of 1.

[0300] F5. An imaging system according to any one of embodiments F1-F4, wherein: the one or more flag bits and the one or more ADC data bits are flexibly arranged so that different numbers of flag bits and ADC data bits can be stored by the data structure.

[0301] F6. An imaging system according to any one of embodiments F1-F5, wherein: the most significant bit of the one or more flag bits is used as a state signal of the state latch; and for the most significant bit of the last ADC operation has a value of 1, the most significant bit of each other ADC operation has a value of 0.

[0302] F7. An imaging system according to any one of embodiments F1-F6, wherein: the read / write control circuit is configured to: receive an output from the comparator and determine whether to perform a read operation or a write operation based on the output from the comparator and the state of the state latch. F8. An imaging system according to any one of embodiments F1-F7, wherein: the ADC memory includes a five-bit memory, the one or more flag bits include one flag bit, and the one or more ADC data bits include four ADC data bits.

[0303] F9. The imaging system of any one of embodiments F1-F8, wherein the one or more flag bits comprise 1.5 flag bits for three ADC operations.

[0304] F10. An imaging system according to embodiment F9, wherein a flag bit for a first ADC operation of the three ADC operations is designated as a value of 00; a flag bit for a second ADC operation of the three ADC operations is designated as a value of 01; a flag bit for a third ADC operation of the three ADC operations is designated as a value of 1; and the one or more ADC data bits include: N-2 bits of ADC data, which are used for the first ADC operation and the second ADC operation; and N-1 bits of ADC data, which are used for the third ADC operation.

[0305] F11. The imaging system of any one of embodiments F1-F8, wherein, for four ADC operations, the one or more flag bits include two flag bits, and the one or more ADC data bits include N-2 bits of ADC data.

[0306] F12. An imaging system according to any one of embodiments F1-F8, wherein: for a first ADC operation and a second ADC operation among four ADC operations, the one or more flag bits include 3 flag bits, and the one or more ADC data bits include N-3 ADC data bits; for a third ADC operation among the four ADC operations, the one or more flag bits include 2 flag bits, and the one or more ADC data bits include N-2 bits of ADC data; and for a fourth ADC operation among the four ADC operations, the one or more flag bits include 1 flag bit, and the one or more ADC data bits include N-1 bits of ADC data.

[0307] G1. An analog-to-digital conversion (ADC) circuit comprising: a read / write control circuit including a status latch and configured to receive an output from the comparator; and an analog-to-digital conversion (ADC) memory operably coupled to the read / write control circuit, wherein a data structure is stored in the ADC memory, the data structure being configured to store one or more flag bits and one or more ADC data bits for identifying each ADC operation.

[0308] G2. The back-end ADC storage circuit of embodiment G1, further comprising: a comparator configured to receive an output of a photodiode, wherein the output of the comparator is based on the output of the photodiode.

[0309] G3. A back-end ADC storage circuit according to any one of embodiments G1-G2, wherein: the state of the state latch having a zero value activates a write operation to write data to the ADC memory; and in response to the output of the comparator flipping, the data is written to the ADC memory.

[0310] G4. The back-end ADC storage circuit of any one of embodiments G1-G3, wherein: write operations are disabled for a state of the status latch having a value of 1.

[0311] G5. A back-end ADC storage circuit according to any one of embodiments G1-G4, wherein: the most significant bit of the one or more flag bits is used as a state signal of the state latch; and for the most significant bit of the last ADC operation having a value of 1, the most significant bit of each other ADC operation has a value of 0.

[0312] G6. A back-end ADC storage circuit according to any one of embodiments G1-G4, wherein: the ADC memory includes a five-bit memory, the one or more flag bits include one flag bit, and the one or more ADC data bits include four ADC data bits.

[0313] G7. A back-end ADC storage circuit according to any one of embodiments G1-G5, wherein a flag bit for a first ADC operation among the three ADC operations is designated as a value of 00; a flag bit for a second ADC operation among the three ADC operations is designated as a value of 01; a flag bit for a third ADC operation among the three ADC operations is designated as a value of 1; and the one or more ADC data bits include: N-2 bits of ADC data, which are used for the first ADC operation and the second ADC operation; and N-1 bits of ADC data, which are used for the third ADC operation.

[0314] G8. The back-end ADC storage circuit of any one of embodiments G1-G5, wherein, for each of four ADC operations, the one or more flag bits include two flag bits, and the one or more ADC data bits include N-2 bits of ADC data.

[0315] G9. A back-end ADC storage circuit according to any one of embodiments G1-G5, wherein: for a first ADC operation and a second ADC operation among four ADC operations, the one or more flag bits include 3 flag bits, and the one or more ADC data bits include N-3 ADC data bits; for a third ADC operation among the four ADC operations, the one or more flag bits include 2 flag bits, and the one or more ADC data bits include N-2 bits of ADC data; and for a fourth ADC operation among the four ADC operations, the one or more flag bits include 1 flag bit, and the one or more ADC data bits include N-1 bits of ADC data.

Claims

1. An imaging system, characterized in that: include: an active pixel comprising a photodiode and a plurality of transistors; a comparator operatively coupled to the active pixel and configured to receive an output of the active pixel; a write control circuit operatively coupled to the comparator and configured to receive an output from the comparator; as well as an analog-to-digital converter (ADC) memory operatively coupled to the write control circuit, wherein a data structure is stored in the ADC memory, the data structure being configured to store at least a first data string, wherein the first data string includes a set of flag bits and a set of ADC data bits for identifying each ADC operation performed, and the data structure being further configured to store a second data string corresponding to a time code written to the memory during an ADC operation; the second data string includes a set of flag bits and a set of ADC data bits for identifying each ADC operation performed; a flag bit in the set of flag bits of the second data string includes a most significant bit of the time code to be written to the ADC memory; The write control circuit includes a positive feedback circuit, and by keeping the positive feedback circuit in a locked state, the ADC code is not held by the second data string.

2. The imaging system according to claim 1, wherein: Based on the most significant bit of the first data string, a write operation of writing data into the ADC memory is activated; in response to the inverted output of the comparator, the data is written to the ADC memory.

3. The imaging system according to claim 2, wherein: The most significant bit of the first data string is designated as a first value, and the ADC memory is configured to hold an ADC code in response to a toggled output of the comparator.

4. The imaging system according to claim 2, wherein: The data written to the ADC memory includes a time code written to the ADC memory during ADC operation.

5. The imaging system according to claim 1, wherein: The ADC operation includes a final ADC operation of an ADC cycle, and in response to the comparator toggling, the ADC code written to the ADC memory is not overwritten.

6. The imaging system according to claim 1, wherein: The ADC memory includes a memory array including a memory arrangement having a most significant bit coupled to the write control circuit.

7. The imaging system according to claim 1, wherein: The data structure includes a first data string and at least one second data string; The first data string corresponds to a first ADC operation, and the second data string corresponds to a second ADC operation performed after the first ADC operation; The second data string includes an additional set of flag bits and an additional set of ADC data bits; The number of ADC data bits included in the additional group of ADC data bits of the second data string is greater than the number of ADC data bits included in the group of ADC data bits of the first data string.

8. The imaging system according to claim 1, wherein: The set of flag bits and the set of ADC data bits are flexibly arranged such that different numbers of flag bits and ADC data bits can be stored by the data structure.

9. The imaging system according to claim 1, wherein: The most significant bit of the set of flag bits is used as a status signal; with respect to the most significant bit of the final ADC operation having the first value, the most significant bit of each of the other ADC operations has a second value.

10. The imaging system according to claim 9, wherein: The first value comprises a logical one and the second value comprises a logical zero; or the first value comprises a logical zero and the second value comprises a logical one.

11. The imaging system according to claim 1, wherein: The write control circuit is further configured to determine whether writing is enabled or disabled based on a most significant bit of an ADC code written to the memory during a final ADC operation.

12. A back-end analog-to-digital conversion (ADC) storage circuit, comprising: a comparator operatively coupled to the active pixel and configured to receive an output of the active pixel; a write control circuit operatively coupled to the comparator and the status latch and configured to receive an output from the comparator and determine whether writing is enabled or disabled based on a most significant bit of an ADC code written to the memory during a final ADC operation; as well as an analog-to-digital conversion (ADC) memory operably coupled to the write control circuit, wherein a data structure is stored in the ADC memory, the data structure being configured to store at least a first data string, wherein the first data string includes a set of flag bits and a set of ADC data bits for identifying each ADC operation performed.

13. The back-end analog-to-digital conversion (ADC) storage circuit according to claim 12, wherein: activating a write operation of writing data into the ADC memory based on the most significant bit of the first data string; In response to the comparator output being flipped, writing data into an ADC memory; The most significant bit of the first data string is assigned a first value, the ADC memory being configured to hold an ADC code in response to a toggled output of the comparator; The data written to the ADC memory includes a time code written to the ADC memory during ADC operation.

14. The back-end analog-to-digital conversion (ADC) storage circuit according to claim 12, wherein: The write control circuit further includes: Positive feedback circuit, The data structure is further configured to store a second data string corresponding to a time code written to the memory during ADC operation; The second data string includes a set of flag bits and a set of ADC data bits for identifying each ADC operation performed; and The flag bits in the set of flag bits of the second data string include the most significant bits of the time code to be written to the ADC memory; By keeping the positive feedback circuit in a locked state, the ADC code is not retained by the second data string; and The ADC operation includes a final ADC operation of an ADC cycle, and in response to the comparator toggling, the ADC code written to the ADC memory is not overwritten.

15. The back-end analog-to-digital conversion (ADC) storage circuit according to claim 12, wherein: The data structure includes a first data string and at least one second data string; the first data string corresponds to a first ADC operation, and the second data string corresponds to a second ADC operation performed after the first ADC operation; the second data string includes an additional group of flag bits and an additional group of ADC data bits; the number of ADC data bits included in the additional group of ADC data bits of the second data string is greater than the number of ADC data bits included in the group of ADC data bits of the first data string.

16. The back-end analog-to-digital conversion (ADC) storage circuit according to claim 12, wherein: The set of flag bits and the set of ADC data bits are flexibly arranged such that different numbers of flag bits and ADC data bits can be stored by the data structure.

17. The back-end analog-to-digital conversion (ADC) storage circuit according to claim 12, wherein: The most significant bit of the group of flag bits is used as a state signal of the state latch; relative to the most significant bit of the final ADC operation having the first value, the most significant bit of each other ADC operation has a second value; The first value comprises a logical one and the second value comprises a logical zero; or the first value comprises a logical zero and the second value comprises a logical one.

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