A method for optimizing the feeding of batches of silicon carbide wafer substrates for polishing
By constructing a processing quality prediction model and optimizing the wafer batching scheme, the problem of yield fluctuation in the silicon carbide wafer production line was solved, and the yield was improved and production stability was achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NANJING UNIV OF AERONAUTICS & ASTRONAUTICS
- Filing Date
- 2023-03-14
- Publication Date
- 2026-06-12
Smart Images
Figure CN116061013B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to an intelligent manufacturing technology, particularly a silicon carbide wafer substrate processing technology, specifically an optimized batch loading method for silicon carbide wafer substrate grinding and polishing processing. Background Technology
[0002] Silicon carbide (SiC) is an important new semiconductor material with properties such as high hardness, high Young's modulus, corrosion resistance, high temperature resistance, and high pressure resistance. It meets the requirements of miniaturization, lightweighting, and high efficiency, and has a huge demand in aerospace, 5G communications, defense manufacturing, and automotive electronics. In actual production of silicon carbide wafers, due to their difficult processing characteristics and still immature technology, the surface quality parameters of wafers in the buffer zones of key processing steps such as wire cutting, grinding, and polishing are inconsistent, leading to the production of defective wafers. For defective wafers exceeding tolerance, some can be reworked after inspection and sorting. The influx of reworked wafers further disrupts the consistency of surface quality parameters in the buffer zones of batch processing stations. Traditional manual sorting or random batching results in significant fluctuations in the station's yield and output. Therefore, addressing the rework disturbance of defective products and improving the product qualification rate of each batch processing step in the silicon carbide production line has become essential for achieving stable and efficient production.
[0003] Currently, research on methods for dealing with various disturbances in production lines mainly focuses on manufacturing system scheduling, which can be subdivided into two categories: shop floor rescheduling and production line parameter control. This involves scheduling workpieces with different processing times in each process or rationally controlling production line operating parameters to achieve goals such as production line performance optimization. However, most of the research on these methods is based on mature production processes and stable yield rates. Few studies focus on production systems that lack stable and mature processes, aiming to improve the yield rate. Therefore, to address the rework disturbance problem of out-of-tolerance products during silicon carbide production line processing, it is necessary to propose a batch optimization method for the grinding and polishing process. Summary of the Invention
[0004] The purpose of this invention is to address the problem of low yield rates and frequent rework of defective products in production systems lacking stable and mature processes. This invention provides an optimized batching method for silicon carbide wafer polishing. The batching method provided by this invention, using known information about the wafers to be processed as input, establishes a processing quality prediction model for the polishing process to obtain a predicted yield value for the batch of wafers after processing. Based on this prediction, wafers with good consistency are batched and sent to the equipment for processing, thereby improving the yield rate of this process and reducing output losses.
[0005] The technical solution of this invention is:
[0006] An optimized batch loading method for silicon carbide wafer substrate grinding and polishing is characterized by the following steps:
[0007] Step 1: Analyze the historical processing data of silicon carbide wafer polishing process using grey relational analysis, and obtain the consistency index of wafer group surface quality parameters that are strongly correlated with the yield of this process as the input parameter of the processing quality prediction model. The output parameter is the predicted value of the yield of this process.
[0008] Step 2: Based on the historical processing data of the polishing process collected from the silicon carbide wafer production line, and combined with the input and output parameters determined in Step 1, construct a prediction model training and testing dataset; construct a silicon carbide wafer processing quality prediction model based on the GA-SVR algorithm;
[0009] Step 3: Based on the processing quality prediction model constructed in Step 2, and with the constraint that the predicted yield of the selected wafer group after processing meets the requirements, and with the goal of achieving the best consistency of the surface quality parameters of the remaining wafers in the workpiece pool, establish a wafer loading batch optimization problem model for the buffer zone of the multi-wafer polishing process.
[0010] Step 4: Use an optimization algorithm to solve the wafer loading and batching optimization problem in the polishing process buffer zone to obtain an optimized wafer batching production scheme.
[0011] Furthermore, the wafer assembly surface consistency parameters include: wafer thickness (T) consistency, warpage (WARP) consistency, bending (BOW) consistency, surface roughness (Ra) consistency, and total thickness deviation (TTV) consistency.
[0012] Taking wafer thickness consistency as an example, the consistency parameter is calculated as follows:
[0013]
[0014] Furthermore, the correlation analysis between wafer consistency parameters and yield based on grey relational analysis in step 1 includes the following steps:
[0015] (1) Set the consistency of surface quality parameters of each wafer as the comparison sequence X. i If the yield of each data sample is set as the reference sequence Y, it can be expressed as:
[0016] Y = {Y(j)|j = 1, 2, ..., n} Y}
[0017] X i ={Xi (j)|j=1,2,…,n Y}, i = 1, 2, ..., n X
[0018] (2) Perform min-max normalization on the elements in the reference sequence and the comparison sequence to map their data values to the [0,1] interval.
[0019] (3) Calculate the correlation coefficient as shown in the following formula, where ζ i (j) represents the correlation coefficient of the i-th influencing factor, Y′(j) represents the dimensionless reference sequence element value, and X i ′(j) represents the element value of the comparison sequence after dimensionless processing of the i-th influencing factor, and ρ represents the resolution coefficient, which is taken as ρ = 0.5.
[0020]
[0021] (4) Calculate the correlation degree as shown in the following formula. The value indicates the degree of correlation between the sequence of the i-th influencing factor and the reference sequence. Sort all the calculated correlation degrees of the influencing factors in descending order, and then analyze and screen the influencing factors according to the magnitude and order of their correlation degrees.
[0022]
[0023] Furthermore, step 2, which involves constructing a silicon carbide wafer processing quality prediction model based on the GA-SVR algorithm, includes the following steps:
[0024] (1) Based on the dataset constructed in step 2, the optimal SVR kernel function is determined through cross-validation experiments; the GA algorithm is used to optimize the penalty parameters and kernel function parameters of the SVR regression model to obtain the optimal parameter combination.
[0025] The commonly used SVR kernel functions and their expressions are as follows:
[0026] Table 1 Commonly Used Kernel Functions
[0027] Kernel function name expression Radial basis function (RBF) i i 2 Sigmoid kernel function [ K(x, x i ) = tanh(β′x T x i + θ), β′ > 0, θ < 0] Polynomial kernel function K(x, x i ) = (x T x i + 1) d′ ]]> Linear kernel function <![CDATA[K(x,x i )=(x T x i )]]>
[0028] Taking the Simigod kernel function as an example, the GA algorithm is used to optimize the penalty parameter C and kernel function parameter γ of the SVR regression model;
[0029] (2) Substitute the obtained parameters into the SVR model, import the training set samples to train the model, construct the SVR prediction model for the batch processing of silicon carbide wafers, and use the test set to verify the accuracy of the model prediction.
[0030] Furthermore, the wafer batching optimization problem model for the multi-wafer processing buffer in step 3 is as follows:
[0031] The optimization objective is the overall quality consistency index W of the remaining wafers in the buffer zone. rest Minimum (i.e., highest consistency of overall surface quality parameters):
[0032] min{W rest =W×E}
[0033] Where W represents the weight vector of the consistency characteristics of wafer surface quality parameters obtained from expert scoring to the overall quality consistency, and E represents the consistency vector of individual surface shape accuracy.
[0034] The assumptions and constraints are as follows:
[0035] (1) The current station's front buffer capacity is not less than the real-time inventory size within the rush zone, as expressed below, where b now This indicates the real-time inventory size of the current workstation's front buffer zone, b c This indicates the current capacity of the front buffer zone of the workstation.
[0036] b now ≤b c
[0037] (2) The yield rate is greater than 0 and less than 1, and the expression is as follows, where p rc This indicates the predicted yield rate for this batch of processing.
[0038] 0 <p rc <1
[0039] (3) The buffer capacity is not less than the batch size, as shown in the following expression, where b′ represents the buffer capacity of the current workstation.
[0040] k c ≤b′
[0041] (4) At this time, the real-time inventory size in the buffer is not less than the batch processing batch size, and its expression is as follows:
[0042] k c ≤b now
[0043] (5) Predict that the finished product rate of this batch of processing is greater than or equal to the set pass rate requirement. The expression is as follows, where sta represents the preset finished product rate pass line.
[0044] p rc ≥sta
[0045] (6) Each batching is performed according to the maximum processing batch size of the equipment, and its expression is as follows, where s jIndicates whether the chip is selected for batching; if so, then s j =1, otherwise s j =0.
[0046]
[0047] (7) Considering that the secondary processing of reworked wafers requires resetting the equipment's process parameters, reworked wafers can only be batched with other reworked wafers. If the batching conditions are not met, they will wait in the buffer. The expression is as follows, where r j This indicates whether the chip is a reworked chip requiring secondary processing; if so, then r j =1, otherwise r j =0;
[0048]
[0049] (8) The calculation methods for wafer group thickness, total thickness deviation, and warpage consistency index are as follows:
[0050]
[0051]
[0052]
[0053] Compared with the prior art, the present invention has the following advantages:
[0054] The silicon carbide wafer substrate polishing and grinding processing optimization method provided by this invention, with known information about the wafers to be processed as input, obtains the predicted yield of the wafers after processing by establishing a processing quality prediction model for the polishing and grinding process. Based on this, a buffer wafer loading and batching optimization problem model is constructed. The problem model is optimized and solved to obtain the wafer combinations to be processed. These wafer batches with good consistency are sent into the equipment for processing, thereby effectively improving the yield of multi-wafer processing steps in silicon carbide production lines with single-variety and large-volume characteristics, reducing output losses, and has good application value. Attached Figure Description
[0055] Figure 1 This is a schematic diagram illustrating the batching problem involved in this invention.
[0056] Figure 2 This is a flowchart of the batch optimization method involved in the present invention.
[0057] Figure 3 This is a schematic diagram of the double-sided grinding process of silicon carbide wafers in an embodiment of the present invention.
[0058] Figure 4 These are the test results of the training and testing sets of the processing quality prediction model in this embodiment of the invention. Figure 4 (a) Training set test results Figure 4 (b) Test results of the test set.
[0059] Figure 5 These are the test results of the experimental verification set for the processing quality prediction model in this embodiment of the invention.
[0060] Figure 6 This is a schematic diagram of the encoding strategy of the improved differential evolution algorithm involved in this invention.
[0061] Figure 7 This is a schematic diagram of the mutation operation of the improved differential evolution algorithm involved in this invention.
[0062] Figure 8 This is a schematic diagram of the crossover operation of the improved differential evolution algorithm involved in this invention.
[0063] In the diagram: 1-outer ring, 2-substrate, 3-upper grinding disc, 4-sun gear, 5-planet gear, 6-lower grinding disc, 7-motor, 8-reducer. Detailed Implementation
[0064] The technical solutions of the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0065] like Figure 1-8 As shown.
[0066] A batch optimization method for silicon carbide wafer substrate grinding and polishing is shown in the schematic diagram of the batching problem. Figure 1 As shown, in actual production, due to the stringent inspection process for reworked wafers, the probability of reworkable wafers among the scrapped wafers is low, resulting in a small proportion in the buffer workpiece pool and a low frequency of reworked wafers entering the station. To free up space in the buffer and prevent reworked wafers from occupying its effective buffer space, during each batch initialization, after receiving real-time buffer-related information, if the total number of reworked wafers reaches the maximum processing batch size, they are directly batched for processing. If not, the normal process is followed, selecting normal batch wafers for batching. The overall execution flow is as follows: Figure 2 As shown.
[0067] This example uses a 6-inch silicon carbide wafer processing production line as the research object to test the batch optimization method for silicon carbide wafer polishing process based on the processing quality prediction model proposed in this embodiment of the invention. The double-sided polishing process is selected as the implementation object, and the schematic diagram of this process is shown below. Figure 3 As shown.
[0068] Taking the double-sided grinding process of this 6-inch silicon carbide wafer processing production line as the implementation object, the workflow of the above-mentioned silicon carbide wafer grinding and polishing process material loading and batching optimization method based on the silicon carbide wafer processing quality prediction model is as follows:
[0069] Step 1: Analyze the historical processing data of silicon carbide wafer batch processing process using grey relational analysis method, and obtain three types of parameters that are strongly correlated with the yield of the process: thickness consistency, thickness variation consistency, and warpage consistency. These parameters are used as input parameters for the processing quality prediction model, and the output parameter is the predicted value of the yield of the process.
[0070] Table 2 Summary of input and output parameters.
[0071]
[0072] Step 2: Based on historical processing data of batch processing steps collected from the silicon carbide wafer production line, and combined with the input and output parameters determined in Step 1, construct a prediction model training and testing dataset; construct a silicon carbide wafer processing quality prediction model based on the GA-SVR algorithm, and the prediction results of the training set, test set, and experimental validation set are as follows: Figure 4 , Figure 5 As shown in Table 3, the test results of the three datasets are compared. It can be seen that the prediction model has good accuracy in actual production applications and can provide valuable reference for scheduling and decision-making in the production process.
[0073] Table 3. Test results for different test sets.
[0074] Test dataset Sample mean square error Mean Absolute Error Coefficient of determination training set 0.00013 0.007621 0.9309 test set 0.0001589 0.01115 0.9157 Experimental verification set 0.000177 0.01172 0.9188 .
[0075] Step 3: When there is idle equipment in the double-sided grinding process and there are enough wafers to be processed in the buffer zone, based on the processing quality prediction model constructed in Step 2, and with the constraint that the predicted yield of the selected wafer group after processing meets the requirements, and with the objective of maximizing the consistency of the surface quality parameters of the remaining wafers in the workpiece pool, a wafer loading batch optimization problem model for the double-sided grinding process buffer zone is established. Taking the relevant information of the double-sided grinding process buffer zone at a certain moment as an example, the specific information is shown in Table 4. The batch processing quantity of this process is 24 wafers, and the preset pass rate standard is 91.7%.
[0076] Table 4. Information on the buffer zone of the double-sided grinding process at a certain moment:
[0077]
[0078] Step 4: The improved differential evolution algorithm is used to solve the buffer wafer loading batch optimization problem. The improvement of the differential evolution algorithm is as follows:
[0079] (1) A corresponding coding strategy was designed, encoding the wafer according to its group. Each gene locus represents the group number of the wafer. The rework wafer is placed at the end of the chromosome, such as... Figure 6 As shown;
[0080] (2) Corresponding mutation operations were designed, and discretization mutation operations were defined:
[0081]
[0082] In the formula, Represents individuals in a population The d′-th dimension component, where g is the iteration number; V represents the population individual. i g The d′-th element; at this point, the mutation factor F is no longer a fixed value, but changes with the value of the d′-th dimension component of the randomly selected individual. The following operation can restrict the values at the gene loci of the mutated individual to 1 and 2, thus preventing the generation of illegally mutated individuals, such as... Figure 7 As shown.
[0083] (3) A corresponding crossover operation was designed, which uses substring swapping for crossover. For individual population Z... i g and variant individual V i g Two unequal positions are randomly generated, and the substring between these two positions is used as the swap part. After swapping the two substrings, the two offspring are checked for legitimacy. If the number of chips in the first group exceeds the batch size or reworked chips are mixed into the first group, the excess chips are randomly selected and inserted into other groups with insufficient quantities to complete the legitimacy. The fitness values of the two offspring are calculated, and the better individual is returned. Figure 8 As shown.
[0084] The initial population size of the algorithm is set to 400, and the maximum number of iterations is set to 200. After obtaining the optimized wafer batching scheme in each batch solution, production is carried out according to the batching scheme.
[0085] The specific processing parameters are shown in Table 5. After processing 20 sets continuously, the yield information is recorded. Then, random batch processing is adopted to process 20 sets continuously, and the yield information is recorded as shown in Table 6.
[0086] Table 5. Double-sided grinding process parameters:
[0087]
[0088] Table 6 Comparison of the effects of batching methods:
[0089]
[0090] As shown in the table above, the batching method proposed in this paper improves the yield by 1.44% compared to the random batching method. For difficult-to-process products such as silicon carbide wafers, the optimized batching method for silicon carbide wafer substrate grinding and polishing proposed in this invention can effectively improve the yield of the double-sided grinding process. The improved yield can increase the utilization rate of raw materials and reduce production costs, demonstrating effectiveness and feasibility.
[0091] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.
[0092] The parts not covered in this invention are the same as or can be implemented using existing technologies.
Claims
1. A batch optimization method for the grinding and polishing of silicon carbide wafer substrates, characterized in that, Includes the following steps: Step 1: Analyze the historical processing data of silicon carbide wafer polishing process using grey relational analysis method, and obtain the consistency of wafer group surface quality parameters that are strongly correlated with the yield of this process as input parameters for the processing quality prediction model. The output parameter is the predicted value of the yield of this process. Step 2: Based on the historical processing data of the polishing process collected from the silicon carbide wafer production line, and combined with the input and output parameters determined in Step 1, construct a prediction model training and testing dataset; establish a silicon carbide wafer processing quality prediction model based on the GA-SVR algorithm; Step 3: Obtain the surface quality parameters of all wafers to be processed in the buffer zone through surface quality inspection. With the yield obtained by the wafer processing quality prediction model constructed in Step 2 as a constraint after batching the wafers, and with the goal of achieving the best consistency of surface quality of the remaining wafers in the buffer zone, establish a batching optimization problem model for wafer loading in the buffer zone of this batch processing process. Step 4: Use an optimization algorithm to solve the optimization problem of silicon carbide wafer loading and batching in the buffer zone, and obtain the optimized wafer batching production scheme, including the wafer number of the wafer selected after batching in the buffer zone and sent to the equipment for processing, as well as the number of the remaining wafers to be processed in the buffer zone.
2. The method according to claim 1, characterized in that, The surface quality parameters of the wafer group include: wafer thickness (T), warpage (WARP), bending (BOW), surface roughness (Ra), and total thickness deviation (TTV); the consistency of the surface quality parameters is defined as the fluctuation of the wafer surface quality, and the variance of each surface quality parameter of each wafer group is used to characterize its fluctuation.
3. The method according to claim 1, characterized in that, Step 2, establishing a silicon carbide wafer processing quality prediction model based on the GA-SVR algorithm, includes the following steps: (1) Based on the dataset constructed in step 2, the optimal SVR kernel function is determined through cross-validation experiments; the GA algorithm is used to optimize the penalty parameters and kernel function parameters of the SVR regression model to obtain the optimal parameter combination. (2) Substitute the obtained parameters into the SVR model, import the training set samples to train the model, construct the SVR prediction model for the processing quality of silicon carbide wafer polishing process, and use the test set to verify the accuracy of the model prediction.
4. The method according to claim 1, characterized in that, Step 3, which establishes the wafer loading batch optimization problem model for the batch processing buffer zone, includes the following steps: Suppose there is a buffer in front of a parallel batch processing station. Each batch of wafers awaiting processing can be processed by a single machine at this batch polishing station. The number of wafers to be processed may not be the processing batch. The number of wafers to be processed in the current buffer, the number and number of normal batch wafers, the number and number of rework wafers, and the surface quality parameters of each wafer are real-time input information. The pass rate of this batch of wafers after processing is predicted by the processing quality prediction model constructed in step 2. It is assumed that a new idle machine appears in the current workstation. The goal is to satisfy various constraints, among the alternatives From the wafers awaiting processing, select those to be processed in the currently idle batch processing equipment. The number of wafers to be processed should be such that the expected yield of this processing meets the preset requirements. In order to avoid the solution of the problem falling into the optimum of a single batch, if there are still multiple wafers to be processed in the buffer after batching, the surface quality parameters of the remaining wafers in the buffer should meet the consistency requirements. The decision variables in the model are the chip member numbers of the chip group selected after batching and sent to the equipment for processing, as well as the preset yield rate; The constraints in the model are: (1) The current buffer zone capacity of the workstation is not less than the real-time inventory size within the buffer zone; (2) The yield rate is greater than 0 and less than 1; (3) The buffer zone capacity shall not be less than the batch size; (4) The real-time inventory size within the buffer zone shall not be less than the batch processing volume; (5) The predicted yield of the wafer set selected and sent to the equipment for processing is greater than or equal to the preset yield value; (6) Each batch should be batched according to the maximum processing batch size of the equipment; (7) Reworked wafers can only be batched with other reworked wafers. If the batching conditions are not met, they will wait in the buffer zone. The optimization objective of the model is to achieve the best consistency of the surface quality parameters of the remaining wafers in the buffer after batch loading.