IGBT fault self-holding and self-resetting circuit device

Abstract

The application discloses an IGBT fault self-keeping and self-resetting circuit device, wherein a fault signal processing unit, a fault signal self-keeping unit, a fault self-resetting unit and a fault reporting unit are connected with an IGBT driving board; the fault signal processing unit detects the level signals of the IGBT driving board unsaturation and output undervoltage protection pins to judge whether the IGBT is faulty; the fault signal self-keeping unit keeps the fault signal output within a certain time after the IGBT fault occurs; the fault reporting unit converts the IGBT fault signal processed by the fault signal processing unit into a level signal and transmits the level signal to an upper computer, so that the problem can be located in time through the upper computer when the IGBT is faulty, and the maintenance workload is reduced; the fault self-resetting unit resets the driving chip state and clears the upper computer fault signal within a period of time after the IGBT fault occurs and is cleared. The application can realize the IGBT fault detection, fault reporting, fault self-keeping and fault self-resetting without building various circuits, and the circuit is simple and has high reliability.

Description

Technical Field

[0001] This invention relates to the field of IGBT drive technology, specifically to an IGBT fault self-holding and self-reset circuit device. Background Technology

[0002] As one of the core components of converters, IGBT driver boards are widely used in popular industries such as wind power, photovoltaics, energy storage, electric vehicles, and rail transit. Their operational stability and reliability are of paramount importance.

[0003] Because traction converters in rail transit are large and complex, a host computer is needed to quickly locate the problem when a fault occurs. Therefore, the requirements for fault detection and fault protection functions of the IGBT driver board are very high. Most existing IGBT driver board solutions are equipped with short-circuit desaturation and output voltage undervoltage protection, but they lack fault feedback, fault self-holding, and fault self-reset functions. Summary of the Invention

[0004] The purpose of this invention is to provide an IGBT fault self-holding and self-reset circuit device, which has fault signal feedback, fault self-holding and fault self-reset functions, and the circuit is simple and highly stable.

[0005] The technical solution to achieve the purpose of this invention is: an IGBT fault self-holding and self-reset circuit device, comprising a fault signal processing unit, a fault signal self-holding unit, a fault self-reset unit, and a fault reporting unit, wherein:

[0006] The fault signal processing unit, fault signal self-holding unit, fault self-reset unit, and fault reporting unit are connected to the protection pins of the IGBT driver board. The fault signal processing unit determines whether the IGBT has failed by detecting the level signals of the IGBT driver board's desaturation and undervoltage protection pins. The fault signal self-holding unit maintains the fault signal output for a certain period of time after the IGBT failure occurs. The fault reporting unit performs level conversion on the IGBT fault signal processed by the fault signal processing unit and uploads it to the host computer so that the host computer can locate the problem in time when the IGBT fails, reducing maintenance workload. The fault self-reset unit resets the driver chip state and clears the fault signal from the host computer for a certain period of time after the IGBT failure occurs and is cleared.

[0007] Furthermore, the fault signal processing unit includes fast recovery diodes D4 and D5, resistors R5, R6, and R7, capacitor C1, and NPN transistor T1. The anode of fast recovery diode D4 is electrically connected to the desaturation protection detection pin Desat of the IGBT driver board, the anode of fast recovery diode D5 is electrically connected to the output voltage protection detection pin UVLO of the IGBT driver board, the cathodes of fast recovery diodes D4 and D5 are electrically connected to the fault signal output pin FAULT, the base B of the NPN transistor is electrically connected to the fault signal output pin FAULT through resistor R5, the collector E of the NPN transistor is electrically connected to the reference ground through resistor R7, and the error signal output pin ERROR is located between the collector E of the transistor and resistor R7.

[0008] Furthermore, when the IGBT driver board triggers desaturation protection or output undervoltage protection, its desaturation detection pin Desat or output undervoltage detection pin UVLO outputs a high-level signal. At this time, fast recovery diode D4 or fast recovery diode D5 is turned on. Only one of the above two detection pins needs to output a high-level signal, and the fault signal pin FAULT will output a high-level signal. The high-level signal of the fault signal pin FAULT is sent to the base of NPN transistor T1 through resistor R5, so that NPN transistor T1 starts to conduct, and the error signal pin ERROR outputs a high-level signal.

[0009] When the IGBT driver board does not detect a fault, its desaturation detection pin Desat and output undervoltage detection pin UVLO output low-level signals. At this time, fast recovery diodes D4 and D5 are turned off, and the fault signal pin FAULT outputs a low-level signal. The low-level signal of the fault signal pin FAULT is sent to the base of NPN transistor T1 through resistor R5, causing NPN transistor T1 to turn off, and the error signal ERROR outputs a low-level signal.

[0010] Furthermore, the fault self-holding unit includes a dual-input Schmitt inverting trigger U1A, a single-input Schmitt inverting trigger U2A, a fast recovery diode D1, a fast recovery diode D2, and a resistor R1. The voltage signal at the first input terminal of the dual-input Schmitt inverting trigger U1A is between the pull-up resistor R1 and the anode of the fast recovery diode D1, and the voltage signal at the second input terminal is electrically connected to the error signal output pin ERROR. The input terminal of the single-input Schmitt inverting trigger U2A is electrically connected to the output terminal of the dual-input Schmitt inverting trigger U1A. The anode of the fast recovery diode D1 is electrically connected to the voltage signal at the first input terminal of the dual-input Schmitt inverting trigger U1A, and the cathode is electrically connected to the reset signal output pin RST / . The anode of the fast recovery diode D2 is electrically connected to the output terminal of the single-input Schmitt inverting trigger U2A, and the cathode is electrically connected to the error signal pin ERROR.

[0011] Furthermore, the fault self-reset unit includes a dual-input Schmitt inverting trigger U1B, a dual-input Schmitt inverting trigger U1C, a single-input Schmitt inverting trigger U2B, a single-input Schmitt inverting trigger U2C, a voltage comparator U3B, a fast recovery diode D3, resistors R8, R9, R10, and a capacitor C2. The voltage signal at the first input terminal of the dual-input Schmitt inverting trigger U1B is electrically connected to the output terminal of the voltage comparator U3B, and the voltage signal at the second input terminal is electrically connected to the output terminal of the single-input Schmitt inverting trigger U2B. The voltage signal at the first input terminal of the dual-input Schmitt inverting trigger U1C is... The signal is electrically connected to the cathode of the fast recovery diode D2, and the voltage signal at the second input terminal is electrically connected to the output terminal of the single-input Schmitt inverting trigger U2C; the input terminal of the single-input Schmitt inverting trigger U2B is electrically connected to the fault signal output pin FAULT; the input terminal of the single-input Schmitt inverting trigger U2C is electrically connected to the output terminal of the dual-input Schmitt inverting trigger U1B; the first input terminal of the voltage comparator U3B is used to input the fault signal FAULT, and the second input terminal is used to input the given voltage signal; the fault reset signal output pin RST / is electrically connected to the output terminal of the dual-input Schmitt inverting trigger U1C.

[0012] Furthermore, the fault signal reporting unit includes a voltage comparator U3A, resistors R2, R3, and R4. The first input terminal of the voltage comparator U3A is used to input the output level signal of the single-input Schmitt trigger U2A, and the second input terminal is used to input a given voltage signal. The fault signal reporting pin FD / is electrically connected to the output terminal of the voltage comparator U3A and is also electrically connected to the pull-up resistor R4.

[0013] Furthermore, when there is no fault signal: the error signal pin ERROR is low, the first input of the dual-input Schmitt inverting flip-flop U1A is high due to the pull-up resistor R1, and the second input of the dual-input Schmitt inverting flip-flop U1A is low due to the error signal pin ERROR. At this time, the dual-input Schmitt inverting flip-flop U1A outputs a high-level signal; the single-input Schmitt inverting flip-flop U2A outputs a low-level signal, the fast recovery diode D2 is turned off, the voltage signal at the first input of the voltage comparator U3A is low, and the voltage comparator U3A outputs a high-level signal. The fault self-holding state is not established.

[0014] When a fault occurs: the error signal pin ERROR is high, the first input of the dual-input Schmitt inverting flip-flop U1A is high due to the pull-up resistor R1, the second input of the dual-input Schmitt inverting flip-flop U1A is high due to the error signal pin ERROR, and the dual-input Schmitt inverting flip-flop U1A outputs a low-level signal; the single-input Schmitt inverting flip-flop U2A outputs a high-level signal, the fast recovery diode D2 is turned on, the voltage signal at the first input of the voltage comparator U3A is high, the voltage comparator U3A outputs a low-level signal, and the fault self-holding state is established;

[0015] The fault is cleared immediately after it occurs: If the fault disappears at this time, the fault signal pin FAULT quickly jumps to a low level. Due to the voltage hysteresis effect of the Schmitt trigger, the anode of the fast recovery diode D2 remains at a high level for a certain period of time. The error signal pin ERROR is at a high level. The single-input Schmitt inverting trigger U2A outputs a high-level signal until the voltage hysteresis effect disappears. The voltage signal at the first input terminal of the voltage comparator U3A is at a high level. The voltage comparator U3A outputs a low-level signal, and the fault self-holding state is established.

[0016] Furthermore, when there is no fault signal: the fault signal pin FAULT is low, the single-input Schmitt inverting trigger U2B outputs a high level, the voltage signal at the first input terminal of the voltage comparator U3B is less than the voltage signal obtained by the series voltage divider formed by resistors R9 and R10 at the second input terminal, and the voltage comparator U3B outputs a high level. The first input terminal of the dual-input Schmitt inverting trigger U1B is determined to be high by the output terminal of the voltage comparator U3B, and the second input terminal of the dual-input Schmitt inverting trigger U1B is determined to be high by the output terminal of the single-input Schmitt inverting trigger U2B. At this time, the dual-input Schmitt inverting trigger U1B outputs a low-level signal, and the single-input Schmitt inverting trigger U2C outputs a high-level signal; the first input terminal of the dual-input Schmitt inverting trigger U1C is determined to be low by the error signal pin ERROR, and the second input terminal of the dual-input Schmitt inverting trigger U1C is determined to be high by the output terminal of the single-input Schmitt inverting trigger U2C. At this time, the dual-input Schmitt inverting trigger U1B outputs a high-level signal.

[0017] When a fault occurs: the fault signal pin FAULT is high, the single-input Schmitt inverting trigger U2B outputs a low level, and the voltage signal at the first input terminal of the voltage comparator U3B is greater than the voltage signal obtained by the series voltage divider formed by resistors R9 and R10 at the second input terminal, so the voltage comparator U3B outputs a low level. The first input terminal of the dual-input Schmitt inverting trigger U1B is determined to be low by the output terminal of the voltage comparator U3B, and the second input terminal of the dual-input Schmitt inverting trigger U1B is determined to be low by the output terminal of the single-input Schmitt inverting trigger U2B. At this time, the dual-input Schmitt inverting trigger U1B outputs a high-level signal, and the single-input Schmitt inverting trigger U2C outputs a low-level signal. The first input terminal of the dual-input Schmitt inverting trigger U1C is determined to be high by the error signal pin ERROR, and the second input terminal of the dual-input Schmitt inverting trigger U1C is determined to be low by the output terminal of the single-input Schmitt inverting trigger U2C. At this time, the dual-input Schmitt inverting trigger U1B outputs a high-level signal.

[0018] The fault is immediately cleared: the fault signal pin FAULT changes from high to low, the single-input Schmitt inverting trigger U2B outputs a high level, and the voltage signal at the first input terminal of the voltage comparator U3B, which is greater than the voltage signal divided by resistors R9 and R10 in series at the second input terminal after a time Δt, becomes less than the voltage signal divided by resistors R9 and R10 in series at the second input terminal. At this time, the voltage comparator U3B outputs a high level, and the time Δt is determined by the formula:

[0019]

[0020] The first input of the dual-input Schmitt inverting trigger U1B is determined to be high by the output of voltage comparator U3B, and the second input of the dual-input Schmitt inverting trigger U1B is determined to be high by the output of single-input Schmitt inverting trigger U2B. At this time, the dual-input Schmitt inverting trigger U1B outputs a low-level signal, and the single-input Schmitt inverting trigger U2C outputs a high-level signal. Due to the voltage hysteresis effect of the Schmitt trigger, the error signal pin ERROR remains high for a period of time. The first input of the dual-input Schmitt inverting trigger U1C is determined to be high by the error signal pin ERROR, and the second input of the dual-input Schmitt inverting trigger U1C is determined to be high by the output of single-input Schmitt inverting trigger U2C. At this time, the dual-input Schmitt inverting trigger U1B outputs a low-level signal. When the voltage hysteresis effect disappears, the error signal pin ERROR is low, and the dual-input Schmitt inverting trigger U1B outputs a high-level signal.

[0021] Furthermore, when there is no fault signal: the voltage signal at the first input terminal of the voltage comparator U3A is determined to be low by the output terminal of the single-input Schmitt inverting trigger U2A, which is less than the voltage signal of the series voltage divider formed by resistors R9 and R10 at the second input terminal; the voltage comparator U3B outputs a high level and uploads it to the host computer.

[0022] When a fault occurs: the voltage signal at the first input terminal of the voltage comparator U3A is determined to be high by the output terminal of the single-input Schmitt inverting trigger U2A, which is greater than the voltage signal divided by the series voltage divider of resistors R9 and R10 at the second input terminal. The voltage comparator U3B outputs a low level and uploads it to the host computer.

[0023] The fault is cleared immediately after it occurs: When the fault occurs, the voltage comparator U3B outputs a low level. After the fault is cleared, the reset signal pin goes low after a time Δt. At this time, the voltage signal at the first input terminal of the voltage comparator U3A is determined to be low by the output terminal of the single-input Schmitt trigger U2A, which is less than the voltage signal divided by the series resistors R9 and R10 at the second input terminal. The voltage comparator U3B then outputs a high level and uploads it to the host computer.

[0024] An IGBT fault self-holding and self-reset method is provided, which realizes IGBT fault self-holding and self-reset based on the aforementioned IGBT fault self-holding and self-reset circuit.

[0025] Compared with the prior art, the significant advantages of this invention are: by performing hysteresis processing on the voltage through a Schmitt inverting trigger, even after a period of time has passed since the fault occurred, when the fault disappears and the fault signal pin (FAULT) is at a low level, the error signal pin (ERROR) can still maintain a high level signal output for a certain period of time, uploading the fault signal to the host computer; at the same time, the reset time can be changed by configuring the RC parameters to complete the self-reset function. Attached Figure Description

[0026] Figure 1 This is a block diagram illustrating an embodiment of the IGBT fault self-holding and self-reset circuit device provided by the present invention.

[0027] Figure 2 This is a circuit connection diagram of the fault signal processing unit in the IGBT fault self-holding and self-reset circuit device provided by the present invention.

[0028] Figure 3 The circuit connection diagram shows the fault self-holding and self-reset implementation method in the IGBT fault self-holding and self-reset circuit device provided by the present invention.

[0029] Explanation of main component symbols

[0030] Dual-input Schmitt inverting flip-flop U1

[0031] Schmitt inverting trigger U2

[0032] Comparator U3

[0033] Fast recovery diodes D1 to D5

[0034] NPN transistor T1

[0035] Resistors R1 to R11

[0036] Capacitors C1 to C2 Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0038] Please refer to Figure 1 , Figure 1This is an IGBT fault self-holding and self-reset circuit device, comprising a fault signal processing unit 1, a fault self-holding unit 2, a fault self-reset unit 3, and a fault reporting unit 4, all connected to the protection function pins of the IGBT driver board. The IGBT fault self-holding and self-reset circuit device uses a Schmitt trigger to perform hysteresis processing on the voltage. Even after a period of time following a fault, when the fault disappears and the fault signal pin FAULT is low, the error signal pin ERROR can maintain a high-level signal output for a certain period, uploading the fault signal to the host computer. Simultaneously, the reset time can be changed by configuring RC parameters to complete the self-reset function. Thus, only simple analog devices are needed to output IGBT fault signals and achieve self-reset functionality, eliminating the need for host computer reset.

[0039] Please refer to Figure 2 , Figure 2 This invention provides a circuit structure for the fault signal processing unit in the IGBT fault self-holding and self-reset circuit device. The circuit principle provided in this embodiment is described in detail below.

[0040] The fault signal processing unit includes fast recovery diode D4, fast recovery diode D5, resistor R5, resistor R6, resistor R7, capacitor C1, and NPN transistor T1.

[0041] When the IGBT driver board triggers desaturation protection or output undervoltage protection, its desaturation detection pin Desat or output undervoltage detection pin UVLO outputs a high-level signal. At this time, fast recovery diode D4 or fast recovery diode D5 conducts. Only one of these two detection pins needs to output a high-level signal; the fault signal pin FAULT will then output a high-level signal. This high-level signal from FAULT is sent to the base of NPN transistor T1 via resistor R5, causing NPN transistor T1 to conduct, and the error signal ERROR will output a high-level signal.

[0042] When the IGBT driver board does not detect a fault, its desaturation detection pin Desat and output undervoltage detection pin UVLO output low-level signals. At this time, fast recovery diodes D4 and D5 turn off the fault signal pin FAULT, which outputs a low-level signal. The low-level signal from the fault signal pin FAULT is sent to the base of NPN transistor T1 through resistor R5, causing NPN transistor T1 to turn off, and the error signal ERROR outputs a low-level signal.

[0043] Please refer to Figure 3 Compared with Table 1, Figure 3This invention provides the circuit structure of the fault self-holding and self-reset circuit device, which includes the fault self-holding unit, fault self-reset unit, and fault reporting unit. Table 1 is the working logic table of the IGBT fault self-holding and self-reset circuit device provided by this invention. The following will be combined with… Figure 3 The circuit principles provided in this embodiment are explained in detail in conjunction with Table 1.

[0044] Table 1. Working Logic Table of IGBT Fault Self-Holding and Self-Reset Circuit Device

[0045]

[0046] The fault self-holding unit includes a dual-input Schmitt inverting trigger U1A, a single-input Schmitt inverting trigger U2A, a fast recovery diode D1, a fast recovery diode D2, and a resistor R1.

[0047] When there is no fault signal: the error signal pin ERROR is low, the first input of the dual-input Schmitt trigger U1A is high due to the pull-up resistor R1, and the second input of the dual-input Schmitt trigger U1A is low due to the error signal pin ERROR. At this time, the dual-input Schmitt trigger U1A outputs a high-level signal. The single-input Schmitt trigger U2A outputs a low-level signal, the fast recovery diode D2 is turned off, the voltage signal at the first input of the voltage comparator U3A is low, and the voltage comparator U3A outputs a high-level signal. The fault self-holding state is not established.

[0048] When a fault occurs: the error signal pin ERROR is high, the first input of the dual-input Schmitt trigger U1A is high due to the pull-up resistor R1, and the second input of the dual-input Schmitt trigger U1A is also high due to the error signal pin ERROR. At this time, the dual-input Schmitt trigger U1A outputs a low-level signal. The single-input Schmitt trigger U2A outputs a high-level signal, the fast recovery diode D2 is turned on, the voltage signal at the first input of the voltage comparator U3A is high, and the voltage comparator U3A outputs a low-level signal, thus establishing the fault self-holding state.

[0049] The fault is cleared immediately upon occurrence: if the fault disappears at this time, the fault signal pin FAULT quickly jumps to a low level. Due to the voltage hysteresis effect of the Schmitt trigger, the anode of the fast recovery diode D2 remains at a high level for a certain period of time, the error signal pin ERROR is at a high level, the single-input Schmitt inverting trigger U2A outputs a high-level signal until the voltage hysteresis effect disappears, the voltage signal at the first input terminal of the voltage comparator U3A is at a high level, the voltage comparator U3A outputs a low-level signal, and the fault self-holding state is established.

[0050] The fault self-reset unit includes a dual-input Schmitt inverting flip-flop U1B, a dual-input Schmitt inverting flip-flop U1C, a single-input Schmitt inverting flip-flop U2B, a single-input Schmitt inverting flip-flop U2C, a voltage comparator U3B, a fast recovery diode D3, resistors R8, R9, and R10, and a capacitor C2. Generally, most IGBT driver boards require a low-level signal to clear all fault signals; that is, the reset pin RST is active low. After clearing all fault signals, the reset pin needs to be set high.

[0051] When there is no fault signal: the fault signal pin FAULT is low, the single-input Schmitt inverting trigger U2B outputs a high level, and the voltage signal at the first input terminal of the voltage comparator U3B is less than the voltage signal obtained by the series division of resistors R9 and R10 at the second input terminal; therefore, the voltage comparator U3B outputs a high level. The first input terminal of the dual-input Schmitt inverting trigger U1B is determined to be high by the output terminal of the voltage comparator U3B, and the second input terminal of the dual-input Schmitt inverting trigger U1B is determined to be high by the output terminal of the single-input Schmitt inverting trigger U2B. At this time, the dual-input Schmitt inverting trigger U1B outputs a low-level signal, and the single-input Schmitt inverting trigger U2C outputs a high-level signal. The first input terminal of the dual-input Schmitt inverting trigger U1C is determined to be low by the error signal pin ERROR, and the second input terminal of the dual-input Schmitt inverting trigger U1C is determined to be high by the output terminal of the single-input Schmitt inverting trigger U2C. At this time, the dual-input Schmitt inverting trigger U1B outputs a high-level signal.

[0052] When a fault occurs: the fault signal pin FAULT is high, the single-input Schmitt inverting trigger U2B outputs a low level, and the voltage signal at the first input terminal of the voltage comparator U3B is greater than the voltage signal obtained by the series voltage divider formed by resistors R9 and R10 at the second input terminal, so the voltage comparator U3B outputs a low level. The first input terminal of the dual-input Schmitt inverting trigger U1B is determined to be low by the output terminal of the voltage comparator U3B, and the second input terminal of the dual-input Schmitt inverting trigger U1B is determined to be low by the output terminal of the single-input Schmitt inverting trigger U2B. At this time, the dual-input Schmitt inverting trigger U1B outputs a high-level signal, and the single-input Schmitt inverting trigger U2C outputs a low-level signal. The first input terminal of the dual-input Schmitt inverting trigger U1C is determined to be high by the error signal pin ERROR, and the second input terminal of the dual-input Schmitt inverting trigger U1C is determined to be low by the output terminal of the single-input Schmitt inverting trigger U2C. At this time, the dual-input Schmitt inverting trigger U1B outputs a high-level signal.

[0053] The fault is immediately cleared: the fault signal pin FAULT changes from high to low, the single-input Schmitt inverting trigger U2B outputs a high level, and the voltage signal at the first input terminal of the voltage comparator U3B, which is greater than the voltage signal divided by resistors R9 and R10 in series at the second input terminal after a time Δt, becomes less than the voltage signal divided by resistors R9 and R10 in series at the second input terminal. At this time, the voltage comparator U3B outputs a high level, and the time Δt is determined by the formula:

[0054]

[0055] The first input of the dual-input Schmitt inverting trigger U1B is determined to be high by the output of voltage comparator U3B, and the second input of the dual-input Schmitt inverting trigger U1B is determined to be high by the output of single-input Schmitt inverting trigger U2B. At this time, the dual-input Schmitt inverting trigger U1B outputs a low-level signal, and the single-input Schmitt inverting trigger U2C outputs a high-level signal. Due to the Schmitt trigger voltage hysteresis effect, the error signal pin ERROR remains high for a period of time. The first input of the dual-input Schmitt inverting trigger U1C is determined to be high by the error signal pin ERROR, and the second input of the dual-input Schmitt inverting trigger U1C is determined to be high by the output of single-input Schmitt inverting trigger U2C. At this time, the dual-input Schmitt inverting trigger U1B outputs a low-level signal.

[0056] When the voltage hysteresis effect disappears, the error signal pin ERROR goes low, and the dual-input Schmitt inverted trigger U1B outputs a high-level signal.

[0057] It is important to note that when the fault signal pin FAULT is always high, the single-input Schmitt inverted flip-flop U2B will always output a low level, causing the reset pin RST / to always be high, thus the self-reset state is not valid, which matches the actual logic.

[0058] The fault signal reporting unit includes a voltage comparator U3A, resistors R2, R3, and R4. Generally, most host computers detect IGBT faults by using a low-level signal, i.e., the fault reporting pin FD / is active low.

[0059] When there is no fault signal: the voltage signal at the first input terminal of the voltage comparator U3A is determined to be low by the output terminal of the single-input Schmitt inverting trigger U2A, which is less than the voltage signal of the series voltage divider formed by resistors R9 and R10 at the second input terminal. The voltage comparator U3B outputs a high level and uploads it to the host computer.

[0060] When a fault occurs: the voltage signal at the first input terminal of the voltage comparator U3A is determined to be high by the output terminal of the single-input Schmitt inverting trigger U2A, which is greater than the voltage signal divided by the series voltage divider of the second input terminals resistors R9 and R10. The voltage comparator U3B outputs a low level and uploads it to the host computer.

[0061] The fault is cleared immediately after it occurs: When the fault occurs, the voltage comparator U3B outputs a low level. After the fault is cleared, the reset signal pin goes low after a time Δt. At this time, the voltage signal at the first input terminal of the voltage comparator U3A is determined to be low by the output terminal of the single-input Schmitt trigger U2A, which is less than the voltage signal divided by the series resistors R9 and R10 at the second input terminal. The voltage comparator U3B then outputs a high level and uploads it to the host computer.

[0062] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0063] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these modifications and improvements all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. An IGBT fault self-holding and self-resetting circuit arrangement, characterized by The fault signal processing unit, the fault signal self-holding unit, the fault self-resetting unit and the fault reporting unit are connected with the protection pin of the IGBT drive board, the fault signal processing unit judges whether the IGBT is faulty by detecting the level signal of the IGBT drive board desaturation and output undervoltage protection pin; the fault signal self-holding unit keeps the fault signal output within a certain time after the IGBT fault occurs; the fault reporting unit converts the IGBT fault signal processed by the fault signal processing unit to a level and uploads it to the upper computer, so that the problem can be located in time through the upper computer when the IGBT is faulty, and the maintenance workload is reduced; the fault self-resetting unit resets the state of the drive chip and clears the fault signal of the upper computer within a period of time after the IGBT fault occurs and is cleared. The fault signal self-holding unit includes a double-input Schmitt inverter U1A, a single-input Schmitt inverter U2A, a fast recovery diode D1, a fast recovery diode D2 and a resistor R1, the first input end voltage signal of the double-input Schmitt inverter U1A is between the pull-up resistor R1 and the anode of the fast recovery diode D1, and the second input end voltage signal is electrically connected with the error signal output pin ERROR; the input end of the single-input Schmitt inverter U2A is electrically connected with the output end of the double-input Schmitt inverter U1A; the anode of the fast recovery diode D1 is electrically connected with the first input end voltage signal of the double-input Schmitt inverter U1A, and the cathode is electrically connected with the reset signal output pin RST / ; the anode of the fast recovery diode D2 is electrically connected with the output end of the single-input Schmitt inverter U2A, and the cathode is electrically connected with the error signal pin ERROR. The fault signal processing unit includes a fast recovery diode D4, a fast recovery diode D5, a resistor R5, a resistor R6, a resistor R7, a capacitor C1 and an NPN transistor T1, the anode of the fast recovery diode D4 is electrically connected with the desaturation protection detection pin Desat of the IGBT drive board, the anode of the fast recovery diode D5 is electrically connected with the output voltage protection detection pin UVLO of the IGBT drive board, the cathodes of the fast recovery diodes D4 and D5 are electrically connected with the fault signal pin FAULT, the base B of the NPN transistor is electrically connected with the fault signal pin FAULT through the resistor R5, the collector E of the NPN transistor is electrically connected with the reference ground through the resistor R7, and the error signal output pin ERROR is between the collector E of the transistor and the resistor R7.

2. The IGBT fault self-holding and self-resetting circuit device according to claim 1, characterized by ​ 3. The IGBT fault self-holding and self-resetting circuit arrangement according to claim 2, characterized in that When the IGBT drive board triggers the desaturation protection or the output undervoltage protection, the desaturation detection pin Desat or the output undervoltage detection pin UVLO outputs a high-level signal, at this time, the fast recovery diode D4 or the fast recovery diode D5 is turned on; the two detection pins only need to output a high-level signal, the fault signal pin FAULT outputs a high-level signal, and the high-level signal of the fault signal pin FAULT is sent to the base of the NPN transistor T1 through the resistor R5, so that the NPN transistor T1 starts to be turned on, and the error signal pin ERROR outputs a high-level signal; When the IGBT drive board cannot detect the fault, the desaturation detection pin Desat and the output undervoltage detection pin UVLO output a low-level signal, at this time, the fast recovery diode D4 and the fast recovery diode D5 are turned off, the fault signal pin FAULT outputs a low-level signal, and the low-level signal of the fault signal pin FAULT is sent to the base of the NPN transistor T1 through the resistor R5, so that the NPN transistor T1 is turned off, and the error signal pin ERROR outputs a low-level signal.

4. The IGBT fault self-holding and self-resetting circuit device of claim 1, wherein, The fault self-resetting unit comprises a double-input Schmitt inverter U1B, a double-input Schmitt inverter U1C, a single-input Schmitt inverter U2B, a single-input Schmitt inverter U2C, a voltage comparator U3B, a fast recovery diode D3, a resistor R8, a resistor R9, a resistor R10 and a capacitor C2, the first input end of the double-input Schmitt inverter U1B is electrically connected with the output end of the voltage comparator U3B, and the second input end is electrically connected with the output end of the single-input Schmitt inverter U2B; the first input end of the double-input Schmitt inverter U1C is electrically connected with the cathode of the fast recovery diode D2, and the second input end is electrically connected with the output end of the single-input Schmitt inverter U2C; the input end of the single-input Schmitt inverter U2B is electrically connected with the fault signal pin FAULT; the input end of the single-input Schmitt inverter U2C is electrically connected with the output end of the double-input Schmitt inverter U1B; the first input end of the voltage comparator U3B is used for inputting the fault signal FAULT, and the second input end is used for inputting a given voltage signal; and the reset signal output pin RST / is electrically connected with the output end of the double-input Schmitt inverter U1C.

5. The IGBT fault self-holding and self-resetting circuit arrangement according to claim 4, characterized in that The fault reporting unit comprises a voltage comparator U3A, a resistor R2, a resistor R3 and a resistor R4, the first input end of the voltage comparator U3A is used for inputting the output level signal of the single-input Schmitt inverter U2A, the second input end is used for inputting a given voltage signal, the fault signal reporting pin FD / is electrically connected with the output end of the voltage comparator U3A and the pull-up resistor R4.

6. The IGBT fault self-holding and self-resetting circuit arrangement according to claim 5, characterized in that When no fault signal: the error signal pin ERROR is low, the first input of the double input Schmitt inverter U1A is determined as high by the pull-up resistor R1, the second input of the double input Schmitt inverter U1A is determined as low by the error signal pin ERROR, at this time the double input Schmitt inverter U1A outputs a high level signal; the single input Schmitt inverter U2A outputs a low level signal, the fast recovery diode D2 is off, the voltage signal of the first input of the voltage comparator U3A is low, the voltage comparator U3A outputs a high level signal, the fault self-holding state is not established; When fault occurs: the error signal pin ERROR is high, the first input of the double input Schmitt inverter U1A is determined as high by the pull-up resistor R1, the second input of the double input Schmitt inverter U1A is determined as high by the error signal pin ERROR, at this time the double input Schmitt inverter U1A outputs a low level signal; the single input Schmitt inverter U2A outputs a high level signal, the fast recovery diode D2 is on, the voltage signal of the first input of the voltage comparator U3A is high, the voltage comparator U3A outputs a low level signal, the fault self-holding state is established; The fault is cleared immediately after the fault occurs: if the fault disappears at this time, the fault signal pin FAULT jumps to low quickly, due to the voltage hysteresis effect of the Schmitt trigger, the anode of the fast recovery diode D2 is still high for a certain time, the error signal pin ERROR is high, the single input Schmitt inverter U2A outputs a high level signal until the voltage hysteresis effect disappears, the voltage signal of the first input of the voltage comparator U3A is high, the voltage comparator U3A outputs a low level signal, the fault self-holding state is established.

7. The IGBT fault self-holding and self-resetting circuit arrangement according to claim 6, characterized in that When no fault signal: the fault signal pin FAULT is low, the single input Schmitt inverter U2B outputs a high level, the voltage signal of the first input of the voltage comparator U3B is less than the voltage signal of the second input resistor R9, resistor R10 series voltage division, the voltage comparator U3B outputs a high level; the first input of the double input Schmitt inverter U1B is determined as high by the output of the voltage comparator U3B, the second input of the double input Schmitt inverter U1B is determined as high by the output of the single input Schmitt inverter U2B, at this time the double input Schmitt inverter U1B outputs a low level signal, the single input Schmitt inverter U2C outputs a high level signal; the first input of the double input Schmitt inverter U1C is determined as low by the error signal pin ERROR, the second input of the double input Schmitt inverter U1C is determined as high by the output of the single input Schmitt inverter U2C, at this time the double input Schmitt inverter U1B outputs a high level signal; When the fault occurs: the fault signal pin FAULT is high, the single input Schmitt inverter U2B outputs low, the voltage comparator U3B first input voltage signal is greater than the voltage signal of the resistance R9 and the resistance R10 in series, the voltage comparator U3B outputs low; the first input of the double input Schmitt inverter U1B is determined as low by the output of the voltage comparator U3B, the second input of the double input Schmitt inverter U1B is determined as low by the output of the single input Schmitt inverter U2B, at this time the double input Schmitt inverter U1B outputs high signal, the single input Schmitt inverter U2C outputs low signal; the first input of the double input Schmitt inverter U1C is determined as high by the error signal pin ERROR, the second input of the double input Schmitt inverter U1C is determined as low by the output of the single input Schmitt inverter U2C, at this time the double input Schmitt inverter U1B outputs high signal; When the fault is cleared: the fault signal pin FAULT jumps from high to low, the single input Schmitt inverter U2B outputs high, the voltage comparator U3B first input voltage signal is less than the voltage signal of the resistance R9 and the resistance R10 in series after Δt time, at this time the voltage comparator U3B outputs high, Δt time is determined by the formula: the first input of the double input Schmitt inverter U1B is determined as high by the output of the voltage comparator U3B, the second input of the double input Schmitt inverter U1B is determined as high by the output of the single input Schmitt inverter U2B, at this time the double input Schmitt inverter U1B outputs low signal, the single input Schmitt inverter U2C outputs high signal; due to the existence of the voltage hysteresis effect of the Schmitt trigger, the error signal pin ERROR is still high for a period of time, the first input of the double input Schmitt inverter U1C is determined as high by the error signal pin ERROR, the second input of the double input Schmitt inverter U1C is determined as high by the output of the single input Schmitt inverter U2C, at this time the double input Schmitt inverter U1B outputs low signal; when the voltage hysteresis effect disappears, the error signal pin ERROR is low, at this time the double input Schmitt inverter U1B outputs high signal.

8. The IGBT fault self-holding and self-resetting circuit device of claim 5, wherein, When there is no fault signal: the voltage comparator U3A first input voltage signal is determined as low by the output of the single input Schmitt inverter U2A, less than the voltage signal of the resistance R9 and the resistance R10 in series, the voltage comparator U3B outputs high to the upper computer; When the fault occurs: the voltage signal at the first input terminal of the voltage comparator U3A is determined as high level by the output terminal of the single-input Schmitt inverter U2A, which is greater than the voltage signal divided by the series connection of the resistor R9 and the resistor R10 at the second input terminal of the voltage comparator U3A, and the output of the voltage comparator U3B is low level and is transmitted to the upper computer; When the fault is cleared: the output of the voltage comparator U3B is low level when the fault occurs; after the reset signal output pin RST / becomes low level after a time of Δt, the voltage signal at the first input terminal of the voltage comparator U3A is determined as low level by the output terminal of the single-input Schmitt inverter U2A, which is less than the voltage signal divided by the series connection of the resistor R9 and the resistor R10 at the second input terminal of the voltage comparator U3A, and the output of the voltage comparator U3B is high level and is transmitted to the upper computer.

9. A method for IGBT fault self-holding and self-resetting, characterized in that, The IGBT fault self-holding and self-resetting circuit based on any one of claims 1-8, realizes IGBT fault self-holding and self-resetting.

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