Layout of the output power transistor in a power management chip for improving sampling accuracy

Abstract

The layout of the output power transistors in a power management chip for improving sampling accuracy is characterized in that: the chip includes multiple groups of output power transistors, a solder ball pin Vsource connected to the sources of the multiple groups of output power transistors, a solder ball pin Vdrain connected to the drains of the multiple groups of output power transistors, and multiple sampling transistors respectively connected to the multiple solder ball pins; wherein, the multiple groups of output power transistors are arranged in a column at equal intervals; the number of the solder ball pins Vsource and the solder ball pin Vdrain is the same as the number of the multiple groups of output power transistors; the solder ball pins Vsource and the solder ball pin Vdrain are respectively arranged in two columns at equal intervals and are distributed on both sides of each group of output power transistors; the multiple sampling transistors are respectively located between the corresponding solder ball pins Vsource and the solder ball pin Vdrain. The method of the present invention is simple and has a small cost, reduces the chip process requirements, and improves the chip test accuracy.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and more specifically, to an output power tube layout in a power management chip for improving sampling accuracy. Background Art

[0002] At present, with the continuous pursuit of new energy and low-carbon environmental protection by human society, people have put forward more stringent requirements for the power density, working efficiency and other indicators of power management (PM) chips and similar power devices. The stable, efficient and safe operation of equipment is inseparable from the power management system. In the power management system, the power management chip has become a key component to achieve efficient, fast and stable output of the power management system because of its integrated power tube with high power density.

[0003] In a power management chip, whether the output power tube (Power MOS) can perform accurate voltage and current sampling is crucial to the output performance of the power management chip. In the prior art, in order to achieve the accuracy of the output power tube, the power tube is usually set at the center of the chip layout during the chip layout design process, and the sampling information is led out of the chip through the Kelvin connection to achieve system control.

[0004] However, in the prior art, although the internal circuit of the tube-level chip can effectively and significantly reduce the error caused by the parasitic voltage drop, during the chip testing or use process, the slight difference in the distance between the chip's multiple solder ball pins PAD and the output power tube will cause the sampling ratio of different solder ball pins PADs to deviate from the ideal sampling ratio in the early design process during the sampling of the output chip of the chip output power tube. In addition, due to the different chip manufacturing processes, there is also the problem of uneven contact between the solder balls connected to the solder ball pins and the test fixture, which will also cause the accuracy of the current test to be greatly affected.

[0005] Therefore, there is an urgent need for a new output power tube layout in a power management chip with sampling accuracy. Summary of the invention

[0006] In order to solve the deficiencies in the prior art, the purpose of the present invention is to provide an output power tube layout in a power management chip with a new sampling accuracy, which realizes accurate sampling of the chip output performance by dividing the sampling power tubes into multiple groups and connecting them to multiple solder ball pins nearby.

[0007] The present invention adopts the following technical solution.

[0008] The layout of the output power transistors in a power management chip for improving sampling accuracy, where the chip includes multiple groups of output power transistors, a solder ball pin Vsource connected to the sources of the multiple groups of output power transistors, a solder ball pin Vdrain connected to the drains of the multiple groups of output power transistors, and multiple sampling transistors respectively connected to the multiple solder ball pins; among them, the multiple groups of output power transistors are arranged in a row at equal intervals; the number of solder ball pins Vsource and Vdrain is the same as the number of the multiple groups of output power transistors; the solder ball pins Vsource and Vdrain are respectively arranged in two columns at equal intervals on both sides of each group of output power transistors; the multiple sampling transistors are respectively located between the corresponding solder ball pins Vsource and Vdrain.

[0009] Preferably, the output power transistors are evenly grouped based on the number of solder ball pins Vsource and Vdrain; the number of output power transistors in each group of output power transistors is equal.

[0010] Preferably, a metal wire with a size of nR is used to connect each sampling transistor to the sources and drains of each group of output power transistors; where n is the number of groups of output power transistors, and R m is the designed resistance value of the Kelvin connection after n sampling transistors are connected in parallel. m

[0011] Preferably, each sampling transistor is arranged at the same vertical position in the chip corresponding to the middle of each group of output power transistors it corresponds to; a connection position for the solder ball pin Vsource is reserved on the source side of each group of output power transistors, and a connection position for the solder ball pin Vdrain is reserved on the drain side.

[0012] Preferably, the chip sampling transistors are connected to the sources, drains, and solder ball pins of the corresponding groups of output power transistors in the chip by the Kelvin connection method.

[0013] Preferably, the chip realizes high-precision sampling of the output voltage or output current based on the matching of the sampling transistors with the corresponding groups of output power transistors and the solder ball pins.

[0014] Preferably, the chip is tested based on the solder ball pins and the test fixture that matches the solder ball pins.

[0015] The beneficial effect of the present invention is that, compared with the prior art, in the present invention, the layout of the output power transistors in a power management chip with a new sampling accuracy can achieve accurate sampling and testing of the chip output performance by dividing the sampling power transistors into multiple groups and connecting them to multiple solder ball pins in a nearby manner. The method of the present invention is simple and has a small cost. It only needs to connect multiple parallel power transistors to the solder ball pins in sequence nearby, reducing the precision requirements of the chip process, improving the chip yield rate, and at the same time improving the accuracy of chip testing.​

[0016] The beneficial effects of the present invention also include:

[0017] 1. The power management chip in the present invention can make the distances between multiple solder ball pins and the MOS transistors equal, thereby preventing different internal resistances caused by different lengths of metal wires and further preventing errors during the testing process. On this basis, it is easier and more reasonable to arrange the positions of the multiple solder ball pins, enabling each of the solder ball pins to be effectively connected to the corresponding test fixture, reducing the problem of decreased test accuracy caused by uneven contact between the chip solder balls and the test fixture, and effectively ensuring the accuracy of the test.

[0018] 2. The method of the present invention does not change the original circuit structure. It only splits the output power transistors in a set ratio, and the parameters such as the size and dimensions of the multiple MOS transistors obtained after splitting are equal. Moreover, in order to ensure the accuracy of testing the internal parameters of the chip in the Kelvin connection method, the resistance value of the metal wire connecting the multiple MOS transistors after splitting and the solder ball pins only needs to be set as a multiple of the original resistance value to achieve the goal, and the method is simple and accurate. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a sampling layout schematic diagram of a power management chip in the prior art of the present invention;

[0020] Figure 2 is a sampling layout schematic diagram of a power management chip for improving test accuracy in the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0021] The following further describes the present application with reference to the drawings. The following embodiments are only used to more clearly illustrate the technical solutions of the present invention and cannot be used to limit the protection scope of the present application.

[0022] Figure 1 is a sampling layout schematic diagram of a power management chip in the prior art of the present invention. As Figure 1 shown, in the power management chips commonly used in the prior art, in order to ensure layout matching and the output performance of the chip, the sampling transistors are usually arranged at the center of the chip, and multiple conductive pads for connecting to the source or drain of the power transistors in the chip are provided on both sides or around the chip.

[0023] In Figure 1 , the conductive pads marked with Vdrain are respectively connected to the Kelvin connection terminals of the MOS transistor drains through metal wires of different lengths, while the conductive pads marked with Vsource are respectively connected to the Kelvin connection terminals of the MOS transistor sources through metal wires of different lengths.

[0024] In order to accurately measure the relevant parameters of the power transistor through the Kelvin connection method, the resistance value of the resistance in the Kelvin connection part can be set to Rm.

[0025] As Figure 1 shown, since the distances between multiple conductive pins and a single power transistor are different, even if the power transistor is placed obliquely or the Kelvin connection leads are placed obliquely, the problem of different metal wire lengths caused by different distances cannot be completely overcome. That is to say, the different resistance values of the metal wires will affect the accuracy of the circuit test for different solder ball pins.

[0026] On the other hand, if the circuit test accuracy is to be ensured, the distances between multiple solder ball pins and the ends or nearby positions of the Kelvin connection leads need to be minimized as much as possible. Therefore, the distances between multiple solder ball pins should be made as small as possible, which leads to an increase in the manufacturing difficulty of the chip manufacturing process and the manufacturing difficulty of the test fixture adapted to the chip.

[0027] Figure 2 This is a schematic diagram of the sampling layout of a power management chip for improving sampling accuracy in the present invention. As Figure 2 shown, in the output power transistor layout of a power management chip for improving sampling accuracy in the present invention, the chip includes multiple groups of output power transistors, solder ball pins Vsource connected to the sources of the multiple groups of output power transistors, solder ball pins Vdrain connected to the drains of the multiple groups of output power transistors, and multiple sampling transistors respectively connected to the multiple solder ball pins; the multiple groups of output power transistors are arranged in a row at equal intervals; the number of solder ball pins Vsource and solder ball pins Vdrain is the same as the number of the multiple groups of output power transistors; the solder ball pins Vsource and solder ball pins Vdrain are respectively arranged in two columns at equal intervals and are distributed on both sides of each group of output power transistors; the multiple sampling transistors are respectively located between the corresponding solder ball pins Vsource and solder ball pins Vdrain.

[0028] It can be understood that in the present invention, in order to make the distances between multiple solder ball pins and the sampling transistors equal, multiple parallel-connected MOS transistors are used. After multiple MOS transistors are connected in parallel, they should have the same parameters as the output sampling transistors in the initial circuit design. For example, the total threshold turn-on current, voltage-current ratio and other parameters of the multiple parallel-connected MOS transistors are consistent to achieve the original function of the chip.

[0029] On the other hand, the parameters of the multiple parallel-connected MOS transistors in the present invention should be completely consistent, such as the size, etc., so that the parameters measured by multiple different solder ball pins are the same, and the connection method of each MOS transistor to the solder ball pin can also be completely consistent.

[0030] In the present invention, the number of solder ball pins Vsource, the number of solder ball pins Vdrain, and the number of multiple groups of output power transistors are the same, and the interconnection relationship among the three should also be exactly the same.

[0031] Specifically referring to Figure 2 , the solder ball pin Vsource can be located at the middle position on the right side of the queue formed by multiple output power transistors in a group arranged at equal intervals, and is indirectly connected to the source electrode of the nearest MOS transistor, that is, a MOS transistor in parallel, through the Kelvin connection method.

[0032] It should be noted that the Kelvin connection here is the same for each MOS transistor. Through the four-wire connection method, the measurement circuit can measure the voltage and current data at both ends of each MOS transistor, thereby ensuring the accuracy of the test through multi-parameter measurement. The measurement of the present invention can be performed on the voltage of the source and drain electrodes. Therefore, the solder ball pins should also be connected to the voltage pins in the Kelvin connection method.

[0033] On the left side of each MOS transistor in the sampling transistor, it can be respectively connected to a corresponding solder ball pin Vdrain in the vicinity. In this connection method, it is also indirectly connected through the Kelvin connection method.

[0034] Preferably, the output power transistors are evenly grouped based on the number of solder ball pins Vsource and Vdrain; the number of output power transistors in each group of output power transistors is equal.

[0035] It can be understood that in the present invention, the output power transistors are evenly grouped based on the number of solder ball pins. For example, when there are a total of 20 power transistors in the chip, and the number of solder ball pins Vsource and Vdrain is 5 respectively, then every four adjacent output power transistors need to be set as a group, and the source and drain electrodes of the four output power transistors in this group are respectively connected to the corresponding solder ball pins.

[0036] Preferably, a metal wire with a size of nR m is used to connect between each sampling transistor and the source and drain electrodes of each group of output power transistors; where n is the number of groups of output power transistors, and R m is the designed resistance value of the Kelvin connection after n sampling transistors are connected in parallel.

[0037] In order to make the total resistance impedance between the solder ball pins and the sampling transistors meet the test requirements, the method of the present invention makes the resistance impedance between each solder ball pin and the sampling transistor be nR m . After parallel connection, the wiring resistance of the source electrode of the power transistor is R m , and the wiring resistance of the gate electrode is Rm , thus meeting the original design requirements of the circuit.

[0038] Preferably, each sampling tube is correspondingly arranged at the same vertical position in the chip with the middle part of each corresponding group of output power tubes; a solder ball pin Vsource connection position is reserved on the source side of each group of output power tubes, and a solder ball pin Vdrain connection position is reserved on the drain side.

[0039] It can be understood that, in order to make the solder ball pins evenly distributed on one surface of the chip, so that the test fixture can better adapt to the chip and be more reasonably and reliably connected to the solder ball pins, according to the method in the prior art, multiple output power tubes can be arranged in the middle of the chip, while the solder ball pins are arranged at equal intervals on both sides of the output power tubes.

[0040] Preferably, the chip sampling tube uses a Kelvin connection method to realize the connection with the source and drain of each corresponding group of output power tubes in the chip and the solder ball pins.

[0041] As described above, for the accuracy of internal loop sampling and testing, the present invention adopts a Kelvin connection method. Therefore, the connection between the chip solder ball pins and the MOS tube is also realized by the Kelvin connection method.

[0042] Preferably, the chip realizes high-precision sampling of the output voltage or output current based on the matching of the sampling tube with each corresponding group of output power tubes and the solder ball pins.

[0043] Specifically, the chip in the present invention can cancel errors based on the connection method of the sampling tube, so as to realize high-precision sampling of the output voltage or output current.

[0044] Preferably, the chip realizes the test of itself based on the solder ball pins and the test fixture matched with the solder ball pins.

[0045] It can be understood that the chip in the present invention can realize the test of itself based on the interval of the solder ball pins. Therefore, by reasonably setting the solder ball pins and respectively allocating the same number of output power tubes and a corresponding sampling tube to each solder ball pin, the accuracy of the test result can be ensured.

[0046] The beneficial effect of the present invention is that, compared with the prior art, a new power management chip for improving test accuracy in the present invention can realize accurate sampling and testing of the chip output performance by dividing the sampling power tubes into multiple groups and connecting them to multiple solder ball pins in a nearby manner.

[0047] The applicant of the present invention has made a detailed description and illustration of the embodiments of the present invention in conjunction with the accompanying drawings. However, those skilled in the art should understand that the above embodiments are only the preferred implementation schemes of the present invention, and the detailed description is only to help readers better understand the spirit of the present invention, rather than a limitation on the protection scope of the present invention. On the contrary, any improvement or modification made based on the spirit of the present invention should fall within the protection scope of the present invention.

Claims

1. The layout of the output power transistors in a power management chip for improving sampling accuracy, characterized in that: the chip includes multiple groups of output power transistors, a solder ball pin Vsource connected to the sources of the multiple groups of output power transistors, a solder ball pin Vdrain connected to the drains of the multiple groups of output power transistors, and multiple sampling transistors respectively connected to the multiple solder ball pins; wherein, the multiple groups of output power transistors are arranged in a row at equal intervals; the number of the solder ball pins Vsource and the solder ball pins Vdrain is the same as the number of the multiple groups of output power transistors; the solder ball pins Vsource and the solder ball pins Vdrain are respectively arranged in two rows at equal intervals and are distributed on both sides of the respective groups of output power transistors; the multiple sampling transistors are respectively located between the corresponding solder ball pins Vsource and the solder ball pins Vdrain.

2. The layout of the output power transistors in a power management chip for improving sampling accuracy according to claim 1, characterized in that: the output power transistors are evenly grouped based on the number of the solder ball pins Vsource and Vdrain; the number of output power transistors in each group of output power transistors is equal.

3. The layout of the output power transistors in a power management chip for improving sampling accuracy according to claim 2, characterized in that: A metal wire with a size of nR is used to connect each of the sampling tubes to the source and drain of each group of output power tubes; m ​ where n is the number of groups of the output power transistors, and R m is the designed resistance value of the Kelvin connection after n sampling transistors are connected in parallel.

4. The layout of the output power transistors in a power management chip for improving sampling accuracy according to claim 3, characterized in that: each of the sampling transistors is correspondingly arranged at the same vertical position in the chip with the middle part of the corresponding group of output power transistors; a connection position for the solder ball pin Vsource is reserved on the source side of each group of output power transistors, and a connection position for the solder ball pin Vdrain is reserved on the drain side.

5. The layout of the output power transistors in a power management chip for improving sampling accuracy according to claim 4, characterized in that: the chip sampling transistors are connected to the sources and drains of the corresponding groups of output power transistors and the solder ball pins in the chip by means of a Kelvin connection method.

6. The layout of the output power transistors in a power management chip for improving sampling accuracy according to claim 5, characterized in that: the chip realizes high-precision sampling of the output voltage or output current based on the matching of the sampling transistors with the corresponding groups of output power transistors and the solder ball pins.

7. The layout of the output power transistors in a power management chip for improving sampling accuracy according to claim 6, characterized in that: the chip realizes the test of the chip itself based on the solder ball pins and the test fixture matched with the solder ball pins.

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