Verification platform, control method and control device of SOC system and storage medium

Abstract

The application relates to integrated chip testing technology and discloses a verification platform of an SOC system, which comprises an FPGA and a peripheral board, wherein the FPGA comprises a logic control module and a plurality of bidirectional ports, and the peripheral board is connected with the SOC system through the FPGA; a data sending end of the SOC system is connected with an input end of the bidirectional port; a bidirectional transmission end of the bidirectional port is connected with a transceiving multiplexing end of the peripheral board through the FPGA; and the bidirectional transmission end of the bidirectional port is also connected with a data receiving end of the SOC system; and an output end of the logic control module is connected with a control end of the bidirectional port. The application also provides a verification platform control method, a control device and a computer readable storage medium of the SOC system. The application solves the problem of insufficient I / O pin numbers of the FPGA when the SOC system is verified based on the FPGA, and guarantees the stability of the test on the SOC system.

Description

Technical Field

[0001] This application relates to the field of integrated circuit testing technology, and in particular to a verification platform for a System-on-a-Chip (SOC) system, a control method for the verification platform of an SOC system, a control device, and a computer-readable storage medium. Background Technology

[0002] A System on Chip (SOC) is a product, an integrated circuit with a specific purpose, containing a complete system and embedded software. Currently, testing and verification of SOC systems often requires an FPGA (Field Programmable Gate Array) verification platform.

[0003] The general method for FPGA verification is to synthesize and program the SOC to be verified onto the FPGA chip, which is equivalent to turning the FPGA chip into a copy of the SOC system. Then, various peripherals are connected to the FPGA development board (usually through external daughterboards, i.e., connecting to peripheral boards) to verify the logical functions of the SOC system in a real application scenario.

[0004] Because FPGA verification platforms have a limited number of I / O pins, and the testing process consumes a lot of pin resources, I / O multiplexing is generally used to address the insufficient pin count. However, the peripheral boards used in the testing process are often designed by the testers themselves. Factors such as improper routing on these peripheral boards can affect signal quality, and I / O multiplexing introduces time delays. Furthermore, the limited adjustment space for I / O timing in FPGAs can affect data transmission via the high-speed USB 2.0 interface. All of these factors can cause the FPGA verification platform to malfunction, impacting the test results of the SoC system.

[0005] The above content is only used to help understand the technical solution of this application and does not represent an admission that the above content is prior art. Summary of the Invention

[0006] The main objective of this application is to provide a verification platform for a SOC system, a control method for the verification platform of a SOC system, a control device, and a computer-readable storage medium. This solves the problem of insufficient I / O pins of the FPGA when verifying a SOC system based on an FPGA, while ensuring the stability of the SOC system during testing.

[0007] To achieve the above objectives, this application provides a verification platform for a System-on-a-Chip (SOC) system, including an FPGA and a peripheral board. The FPGA includes a logic control module and multiple bidirectional ports. The feedback transmission terminal of the peripheral board is connected to the feedback transmission terminal of the SOC system via the feedback transmission terminal of the FPGA. The notification transmission terminal of the SOC system is connected to the notification transmission terminal of the peripheral board via the notification transmission terminal of the FPGA, and the notification transmission terminal of the SOC system is also connected to the input terminal of the logic control module. The data transmission terminal of the SOC system is connected to the input terminal of the bidirectional ports, and the bidirectional transmission terminal of the bidirectional ports is connected to the transceiver multiplexing terminal of the peripheral board via the transceiver multiplexing terminal of the FPGA. The bidirectional transmission terminal of the bidirectional ports is also connected to the data receiving terminal of the SOC system.

[0008] The output of the logic control module is connected to the control terminal of the bidirectional port, and the logic control module is used to control the bidirectional port to switch to the corresponding transmission mode, which includes a sending mode and a receiving mode.

[0009] Optionally, the logic control module includes at least a logic NOR module, the data receiving end includes a first data receiving end and a second data receiving end, the data sending end includes a first data sending end and a second data sending end, and the bidirectional port is divided into a first bidirectional port and a second bidirectional port.

[0010] The notification transmission terminal of the SOC system is connected to the first input terminal of the logic NOR module, and the output terminal of the logic NOR module is connected to the control terminals of the first bidirectional port and the second bidirectional port, respectively.

[0011] The first data transmitting end is connected to the input end of the first bidirectional port and the second input end of the logic OR module, respectively; the first data receiving end is connected to the bidirectional transmission end of the first bidirectional port.

[0012] The second data sending end is connected to the input end of the second bidirectional port, the second data receiving end is connected to the bidirectional transmission end of the second bidirectional port, and the transceiver multiplexing end of the peripheral board connected to the second bidirectional port via the transceiver multiplexing end of the FPGA is a multi-high-byte data transmission end.

[0013] Optionally, the logic control module further includes a logic NOT module, the notification transmission end includes a first notification transmission end and a second notification transmission end, the data receiving end further includes a third data receiving end, the data sending end further includes a third data sending end, and the bidirectional port further includes a third bidirectional port.

[0014] The first notification transmission terminal of the SOC system is connected to the first notification transmission terminal of the peripheral board via the first notification transmission terminal of the FPGA. The first notification transmission terminal of the SOC system is also connected to the first input terminal of the logic OR module.

[0015] The second notification transmission terminal of the SOC system is connected to the second notification transmission terminal of the peripheral board via the second notification transmission terminal of the FPGA. The second notification transmission terminal of the SOC system is also connected to the input terminal of the logic NOT module, and the output terminal of the logic NOT module is connected to the control terminal of the third bidirectional port.

[0016] The third data transmitting end is connected to the input end of the third bidirectional port, and the third data receiving end is connected to the bidirectional transmission end of the third bidirectional port. The transceiver multiplexing end of the peripheral board connected to the third bidirectional port via the transceiver multiplexing end of the FPGA consists of multiple low-byte data transmission ends.

[0017] Optionally, the logic control module includes a logic NOR module and a logic NOT module, the data receiving end includes a first data receiving end and a third data receiving end, the data sending end includes a first data sending end and a third data sending end, the bidirectional port is divided into a first bidirectional port and a third bidirectional port, and the notification transmission end includes a first notification transmission end and a second notification transmission end.

[0018] The first notification transmission terminal of the SOC system is connected to the first notification transmission terminal of the peripheral board via the first notification transmission terminal of the FPGA. The first notification transmission terminal of the SOC system is also connected to the first input terminal of the logic NOR module. The output terminal of the logic NOR module is connected to the control terminal of the first bidirectional port.

[0019] The first data transmitting end is connected to the input end of the first bidirectional port and the second input end of the logic OR module, respectively; the first data receiving end is connected to the bidirectional transmission end of the first bidirectional port.

[0020] The second notification transmission terminal of the SOC system is connected to the second notification transmission terminal of the peripheral board via the second notification transmission terminal of the FPGA. The second notification transmission terminal of the SOC system is also connected to the input terminal of the logic NOT module, and the output terminal of the logic NOT module is connected to the control terminal of the third bidirectional port.

[0021] The third data transmitting end is connected to the input end of the third bidirectional port, and the third data receiving end is connected to the bidirectional transmission end of the third bidirectional port. The transceiver multiplexing end of the peripheral board connected to the third bidirectional port via the transceiver multiplexing end of the FPGA consists of multiple low-byte data transmission ends.

[0022] To achieve the above objectives, this application also provides a verification platform control method for a SOC system, applied to the verification platform of the SOC system described above, the verification platform control method for the SOC system comprising:

[0023] Based on the control signals output by the SOC system, control the bidirectional port of the FPGA to switch to the corresponding transmission mode;

[0024] Specifically, when the transmission mode is switched to transmit mode, the SOC system sends data to the external board via the FPGA; when the transmission mode is switched to receive mode, the SOC system receives data sent by the external board via the FPGA.

[0025] To achieve the above objectives, this application also provides a control device applied to the verification platform of the SOC system described above;

[0026] The control device is used to control the bidirectional port of the FPGA to switch to the corresponding transmission mode according to the control signal output by the SOC system; wherein, when the transmission mode is switched to the transmit mode, the SOC system sends data to the external board via the FPGA; when the transmission mode is switched to the receive mode, the SOC system receives data sent by the external board via the FPGA.

[0027] To achieve the above objectives, this application also provides a computer-readable storage medium storing a verification platform control program for a SOC system. When executed by a processor, the verification platform control program for the SOC system implements the steps of the verification platform control method for the SOC system described above.

[0028] The SOC system verification platform, SOC system verification platform control method, control device, and computer-readable storage medium provided in this application establish a communication connection between the FPGA and the peripheral board based on the UTMI interface multiplexing optimization method of the USB 2.0 protocol. This allows both the FPGA and the peripheral board to save nearly half of the DATA pin resources, solving the problem of insufficient I / O pins of the FPGA when verifying the SOC system based on the FPGA. At the same time, by setting up corresponding bidirectional ports on the FPGA as data relays between the SOC system and the peripheral board, the latency problem caused by FPGA I / O multiplexing is solved, ensuring the stable operation of the SOC system verification platform and thus improving the accuracy of testing the SOC system using the FPGA verification platform. Attached Figure Description

[0029] Figure 1 This is an example diagram of the verification platform structure of the SOC system in one embodiment of this application;

[0030] Figure 2This is another structural example diagram of the verification platform of the SOC system in one embodiment of this application;

[0031] Figure 3 This is an example diagram of the verification platform structure of the SOC system in another embodiment of this application;

[0032] Figure 4 This is an example diagram of the first bidirectional port and associated devices in the verification platform of the SOC system in another embodiment of this application;

[0033] Figure 5 This is an example diagram of the second bidirectional port and associated devices in the verification platform of the SOC system in another embodiment of this application;

[0034] Figure 6 This is an example diagram of the verification platform structure of the SOC system in another embodiment of this application;

[0035] Figure 7 This is an example diagram of the third bidirectional port and associated devices in the verification platform of the SOC system in another embodiment of this application;

[0036] Figure 8 This is an example diagram of the verification platform structure of the SOC system in another embodiment of this application.

[0037] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0038] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0039] Reference Figure 1 or Figure 2In one embodiment, the verification platform includes an FPGA and a peripheral board. The FPGA includes a logic control module and multiple bidirectional ports. The feedback transmission terminal of the peripheral board is connected to the feedback transmission terminal of the SOC system via the feedback transmission terminal of the FPGA. The notification transmission terminal of the SOC system is connected to the notification transmission terminal of the peripheral board via the notification transmission terminal of the FPGA, and the notification transmission terminal of the SOC system is also connected to the input terminal of the logic control module. The data transmission terminal of the SOC system is connected to the input terminal of the bidirectional port, and the bidirectional transmission terminal of the bidirectional port is connected to the transceiver multiplexing terminal of the peripheral board via the transceiver multiplexing terminal of the FPGA. The bidirectional transmission terminal of the bidirectional port is also connected to the data receiving terminal of the SOC system.

[0040] The output of the logic control module is connected to the control terminal of the bidirectional port, and the logic control module is used to control the bidirectional port to switch to the corresponding transmission mode, which includes a sending mode and a receiving mode.

[0041] In this embodiment, the verification platform of the SOC system includes an FPGA and a peripheral board. The FPGA device is a semi-custom circuit in application-specific integrated circuits (ASICs), which is a programmable logic array that can effectively solve the problem of the limited number of gate circuits in the original devices. The peripheral board is a development board equipped with various peripherals for performing various functional tests on the SOC system. The peripheral board can be a PHY (Port Physical Layer) development board. The PHY development board can be used as a test sub-board and also as a communication bridge between the SOC system, the FPGA, and other test motherboards. That is, in some test scenarios, the verification platform of the SOC system can also be connected to other test motherboards (or test equipment) through the PHY development board for testing the corresponding functions of the SOC system. Of course, the PHY development board itself can also be used to test some serial communication functions of the SOC system.

[0042] It should be noted that in USB (Universal Serial Bus) applications, the PHY chip is generally integrated into the USB controller on the host side or into the embedded system, serving as a bridge that provides interfaces for digital and modular components.

[0043] Optionally, the SOC system, FPGA, and peripheral board communicate based on the USB 2.0 protocol. It should be noted that the USB 2.0 protocol's communication bus is a set of DP / DM differential lines, data transmission is half-duplex, and RX and TX transmissions are time-division multiplexed. Therefore, the RX and TX related signals of the UTMI (USB 2.0 Transceiver Macrocell Interface) can be I / O multiplexed between the FPGA and peripheral board to save a pair of I / O pins, simplifying the peripheral board design and reducing costs.

[0044] Optionally, given the limited I / O pin resources of the FPGA, the RX / TX serial ports can be multiplexed using MUX (Multiplexer) by leveraging the half-duplex transmission characteristics of the USB 2.0 protocol. This involves multiplexing the txvalidh and rxvalidh pins in the UTMI interface on the FPGA and peripheral board into a single validh pin (as a transmit / receive multiplexer, which can be used to receive or send data), and / or multiplexing the txdata and rxdata pins into a set of data pins (as transmit / receive multiplexers). Furthermore, the transmit / receive multiplexers between the FPGA and the peripheral board can be connected to each other. This allows both the FPGA and the peripheral board to save half of their pin resources.

[0045] In the SOC system, the txvalidh and / or txdata pins are used as data transmitters, and the rxvalidh and / or rxdata pins are used as data receivers. The data transmitters are connected to the input of the bidirectional port on the FPGA, and the data receivers are connected to the bidirectional transmission port on the FPGA. The bidirectional transmission port on the FPGA is also connected to the FPGA's transmit / receive multiplexing port.

[0046] Optionally, an IOBUF tri-state gate is instantiated at the top level of the FPGA's RTL (register transfer level), and an application layer PAD_WRAPPER (the entire PAD_WRAPPER contains a bidirectional port PAD) is wrapped around it to obtain the FPGA's bidirectional port. This allows the FPGA's bidirectional port to implement the functions of the PAD pins required by the SOC system. The FPGA's bidirectional port includes an input terminal, a control terminal, and a bidirectional transmission terminal (i.e., the three ports of the tri-state gate can be divided into an input terminal, a control terminal, and a bidirectional transmission terminal).

[0047] Optionally, the control terminal of the FPGA's bidirectional port is connected to the output terminal of the logic control module on the FPGA and is controlled by the logic control module. The input terminal of the logic control module is connected to the notification transmission terminal of the SOC system, and the notification transmission terminal of the SOC system is also connected to the notification transmission terminal of the peripheral board via the FPGA's notification transmission terminal. The notification transmission terminal can be the txready pin and / or txvalid pin of the USB 2.0 protocol. The txready and txvalid pins are generally used for transmission notifications, such as the data sender notifying the receiver that data is ready to be sent (i.e., notifying that data is ready to be sent), or the data receiver notifying the sender that it is ready to receive data.

[0048] In this way, when the SOC system is ready to transmit data with the peripheral board, it can notify the peripheral board to prepare to receive or send data through the notification transmission end. At the same time, the logic control module will also control the bidirectional port of the FPGA to switch to the corresponding transmission mode according to the output of the notification transmission end of the SOC system. The transmission mode includes a sending mode and a receiving mode.

[0049] Optionally, when the SOC system is ready to send data to the peripheral board, it can notify the peripheral board to prepare to receive data through the notification transmission end. At the same time, the logic control module will also control the bidirectional port of the FPGA to switch to the transmit mode according to the output of the notification transmission end of the SOC system. At this time, the data transmission end of the SOC system can send data to the transmit / receive multiplexer of the peripheral board through the bidirectional transmission end of the FPGA's bidirectional port and the transmit / receive multiplexer of the FPGA. When the SOC system is ready to receive data sent by the peripheral board, it can notify the peripheral board to prepare to send data through the notification transmission end. At the same time, the logic control module will also control the bidirectional port of the FPGA to switch to the receive mode according to the output of the notification transmission end of the SOC system. At this time, the data sent by the peripheral board through the transmit / receive multiplexer is received by the transmit / receive multiplexer of the FPGA and can be received by the data receiving end of the SOC system through the bidirectional transmission end of the FPGA's bidirectional port.

[0050] It should be understood that, based on the half-duplex transmission characteristics of the USB 2.0 protocol, both the bidirectional transmission end and the transceiver multiplexing end in the verification platform can realize the multiplexing of receiving and sending data (that is, they can have the functions of receiving and sending data, and can switch between receiving mode and sending mode).

[0051] Optionally, the feedback transmission terminal of the peripheral board is connected to the feedback transmission terminal of the FPGA, and the feedback transmission terminal of the FPGA is connected to the feedback transmission terminal of the SOC system. The feedback transmission terminal can be the txvalidh pin of the USB 2.0 protocol.

[0052] In this way, the peripheral board can send feedback to the SOC system to indicate whether the transmitted data is valid, or to indicate that there is data to be sent to the SOC system.

[0053] It should be noted that, according to the USB 2.0 UTMI interface protocol specification, when the txvalidh pin is high, the txdata pin is active (high byte valid), and vice versa; when rxvalidh is high, the rxdata pin is active (high byte valid), and vice versa. The rxvalidh pin is only active when the rxactive pin is high, while the txvalidh pin is active when the txready pin is high. Due to the half-duplex transmission characteristic, the rxactive and txready pins cannot be active simultaneously. Therefore, the SOC system can connect to the validh pin of the peripheral board by outputting a control signal to the bidirectional port as RX / TX high byte active. Similarly, the transmission of the txdata and rxdata pins follows the same principle: when the txvalidh pin is active, the txdata pin is active (low byte valid); when the rxvalidh pin is active, the rxdata pin is active (low byte valid). Therefore, the SOC system can connect to the data pin of the peripheral board by outputting the corresponding control signal to the bidirectional port. Based on this principle, by controlling the relevant pins of the SOC system to output corresponding high and low level signals, the bidirectional port can be controlled to switch between receive mode and transmit mode.

[0054] Optional, refer to Figure 1 Alternatively, since a System-on-a-Chip (SoC) system typically involves multiple data transmitters and receivers, multiple bidirectional ports can be configured on the FPGA to accommodate the needs of the SoC system's multiple data transmitters and receivers. For example, Figure 1 As shown, multiple bidirectional ports can be controlled by the same logic control module; or as... Figure 2 As shown, multiple bidirectional ports can be controlled by different logic control modules; of course, the SOC system can also configure a corresponding notification transmission end for each logic control module.

[0055] The SOC system verification platform proposed in one embodiment establishes a communication connection between the FPGA and the peripheral board based on the optimized method of UTMI interface multiplexing of the USB 2.0 protocol. This saves nearly half of the DATA pin resources for both the FPGA and the peripheral board, solving the problem of insufficient I / O pins on the FPGA when verifying the SOC system based on the FPGA. At the same time, by setting up corresponding bidirectional ports on the FPGA as data relays between the SOC system and the peripheral board, the latency problem caused by I / O multiplexing in the FPGA is solved, ensuring the stable operation of the SOC system verification platform and thus improving the accuracy of testing the SOC system using the FPGA verification platform.

[0056] In one embodiment, reference is made to Figure 3 Based on the above embodiments, the logic control module includes at least a logic OR-NOT module, the data receiving end includes a first data receiving end and a second data receiving end, the data sending end includes a first data sending end and a second data sending end, and the bidirectional port is divided into a first bidirectional port and a second bidirectional port.

[0057] The notification transmission terminal of the SOC system is connected to the first input terminal of the logic NOR module, and the output terminal of the logic NOR module is connected to the control terminals of the first bidirectional port and the second bidirectional port, respectively.

[0058] The first data transmitting end is connected to the input end of the first bidirectional port and the second input end of the logic OR module, respectively; the first data receiving end is connected to the bidirectional transmission end of the first bidirectional port.

[0059] The second data sending end is connected to the input end of the second bidirectional port, the second data receiving end is connected to the bidirectional transmission end of the second bidirectional port, and the transceiver multiplexing end of the peripheral board connected to the second bidirectional port via the transceiver multiplexing end of the FPGA is a multi-high-byte data transmission end.

[0060] In this embodiment, the FPGA is provided with at least one logic NOR module, which can implement the logic NOR function (it can be composed of a logic OR gate + a logic NOT gate, or directly composed of logic NOR gates; the following description takes the logic NOR function composed of logic NOR gates as an example), and the logic NOR module can be used to control multiple bidirectional ports set on the FPGA.

[0061] Optionally, the multiple data transmitters on the SOC system can be divided into a first data transmitter and a second data transmitter. The pin corresponding to the first data transmitter is the txvalidh pin, and the pin corresponding to the second data transmitter is the txdata pin. The txdata pin can also be multiple high-byte txdata pins (generally the 8th to 15th txdata pins, denoted as txdata[15:8]). That is, multiple high-byte txdata pins can be connected to the input end of the same bidirectional port at the same time. The multiple data receivers on the SOC system can be divided into a first data receiver and a second data receiver. The pin corresponding to the first data receiver is the rxvalidh pin, and the pin corresponding to the second data receiver is the rxdata pin. The rxdata pin can also be multiple high-byte rxdata pins (generally the 8th to 15th rxdata pins, denoted as rxdata[15:8]). That is, multiple high-byte rxdata pins can be connected to the bidirectional transmission end of the same bidirectional port at the same time.

[0062] Among the multiple bidirectional ports set on the FPGA, the bidirectional port connected to the first data transmitter and the first data receiver is marked as the first bidirectional port; the bidirectional port connected to the second data transmitter and the second data receiver is marked as the second bidirectional port.

[0063] Optionally, since the OR / NOT logic has two inputs and one output, the OR / NOT module also has two input terminals, namely a first input terminal and a second input terminal. The notification transmission terminal of the SOC system is connected to the first input terminal of the OR / NOT module in addition to the notification transmission terminal of the FPGA; the first data transmission terminal of the SOC system is connected to the second input terminal of the OR / NOT module in addition to the input terminal of the first bidirectional port on the FPGA.

[0064] Of course, the output of the logic OR module can be connected to the control terminals of the first bidirectional port and the second bidirectional port, respectively.

[0065] Optionally, the bidirectional transmission end of the first bidirectional port, in addition to being connected to the first data receiving end of the SOC system, is also connected to the transceiver multiplexing end of the peripheral board via the transceiver multiplexing end on the FPGA. The transceiver multiplexing end connected to the first bidirectional port is a validh pin multiplexed using txvalidh and rxvalidh pins. The bidirectional transmission end of the second bidirectional port, in addition to being connected to the second data receiving end of the SOC system, is also connected to the transceiver multiplexing end of the peripheral board via the transceiver multiplexing end on the FPGA. The transceiver multiplexing end connected to the second bidirectional port is a data pin multiplexed using txdata and rxdata pins. The transceiver multiplexing end of the peripheral board can also be composed of multiple high-byte data pins (i.e., high-byte data transmission ends) (generally the 8th to 15th data pins, denoted as data[15:8]), to correspond to the high-byte second data sending end and second data receiving end in the SOC system. In this way, by using port multiplexing, multiple pins can be transmitted using a single port, which can greatly save pin resources.

[0066] Optional, refer to Figure 4 The operating principle of the first bidirectional port and related ports is as follows:

[0067] Optionally, an IOBUF tri-state gate is instantiated at the top level of the FPGA's RTL, and an application layer PAD_WRAPPER (the entire PAD_WRAPPER contains a bidirectional port PAD) is wrapped around it. Corresponding pins on the FPGA need to be assigned to obtain the FPGA's first bidirectional port PAD1. Furthermore, using a logic NOR module, the signal outputs of the SOC system's notification transmission end and the first data transmission end are NOR-NOT-operated. The calculation result is then output to the control terminal OEN1 of the first bidirectional port through the output of the logic NOR module. The logic formula is as follows: Where t1 is the output of the notification transmission end, and t2 is the output of the first data transmission end.

[0068] Optionally, the first data transmitter can also output to the input of the first bidirectional port. When the control terminal OEN1 is low, the first bidirectional port switches to the transmit mode. At this time, the data transmitted by the first data transmitter is output to the transceiver multiplexing terminal of the FPGA through the bidirectional transmission terminal of the first bidirectional port, and then sent to the transceiver multiplexing terminal of the peripheral board through the transceiver multiplexing terminal of the FPGA.

[0069] Optionally, the first data receiving end is connected to the bidirectional transmission end of the first bidirectional port. When the air terminal OEN1 is high, the first bidirectional port switches to the receiving mode. At this time, the data sent by the peripheral board to the FPGA can be relayed to the first data receiving end through the first bidirectional port.

[0070] Optional, refer to Figure 5The operating principle of the second bidirectional port and related ports is as follows:

[0071] Optionally, eight single-bit IOBUF tri-state gates are instantiated at the top layer of the FPGA's RTL, and an application layer PAD_WRAPPER (the entire PAD_WRAPPER contains a bidirectional port PAD) is wrapped around them. Corresponding pins on the FPGA need to be assigned to obtain the FPGA's second bidirectional port PAD2. Furthermore, using a logic NOR module, the signal outputs from the SOC system's notification transmission end and the first data transmission end are NOR-NOT-operated. The result is then output to the control terminal OEN1 of the second bidirectional port through the logic NOR module's output. The logic formula is as follows: Where t1 is the output of the notification transmission end, and t2 is the output of the first data transmission end.

[0072] Optionally, multiple high-byte txdata pins of the second data transmitter are also output to the input of the second bidirectional port. When the control terminal OEN1 is low, the second bidirectional port switches to the transmit mode (and outputs high bytes). At this time, the data sent by the second data transmitter is output to the transceiver multiplexing terminal of the FPGA through the bidirectional transmission terminal of the second bidirectional port, and then sent to multiple high-byte data pins of the transceiver multiplexing terminal of the peripheral board through the transceiver multiplexing terminal of the FPGA.

[0073] Optionally, multiple high-byte rxdata pins of the second data receiving end are connected to the bidirectional transmission end of the second bidirectional port. When the control terminal OEN1 is high, the second bidirectional port switches to the receiving mode (and high-byte receiving). At this time, multiple high-byte data pins of the peripheral board can send data to multiple high-byte rxdata pins of the second data receiving end through the second bidirectional port on the FPGA.

[0074] The SOC system verification platform proposed in one embodiment establishes a communication connection between the FPGA and the peripheral board based on the optimized method of UTMI interface multiplexing of the USB 2.0 protocol. This saves nearly half of the DATA pin resources for both the FPGA and the peripheral board, solving the problem of insufficient I / O pins on the FPGA when verifying the SOC system based on the FPGA. At the same time, by setting up corresponding bidirectional ports on the FPGA as data relays between the SOC system and the peripheral board, the latency problem caused by I / O multiplexing in the FPGA is solved, ensuring the stable operation of the SOC system verification platform and thus improving the accuracy of testing the SOC system using the FPGA verification platform.

[0075] In one embodiment, reference is made to Figure 6Based on the above embodiments, the logic control module further includes a logic NOT module, the notification transmission end includes a first notification transmission end and a second notification transmission end, the data receiving end further includes a third data receiving end, the data sending end further includes a third data sending end, and the bidirectional port further includes a third bidirectional port.

[0076] The first notification transmission terminal of the SOC system is connected to the first notification transmission terminal of the peripheral board via the first notification transmission terminal of the FPGA. The first notification transmission terminal of the SOC system is also connected to the first input terminal of the logic OR module.

[0077] The second notification transmission terminal of the SOC system is connected to the second notification transmission terminal of the peripheral board via the second notification transmission terminal of the FPGA. The second notification transmission terminal of the SOC system is also connected to the input terminal of the logic NOT module, and the output terminal of the logic NOT module is connected to the control terminal of the third bidirectional port.

[0078] The third data transmitting end is connected to the input end of the third bidirectional port, and the third data receiving end is connected to the bidirectional transmission end of the third bidirectional port. The transceiver multiplexing end of the peripheral board connected to the third bidirectional port via the transceiver multiplexing end of the FPGA consists of multiple low-byte data transmission ends.

[0079] In this embodiment, the multiple bidirectional ports in the FPGA are divided into a first bidirectional port, a second bidirectional port, and a third bidirectional port; and the logic control module of the FPGA includes a logic NOR module and a logic NOT module; wherein the logic NOR module is used to control the first bidirectional port and the second bidirectional port, and the logic NOT module is used to control the third bidirectional port.

[0080] Optionally, the NOT module can implement the NOT function (which can be constructed from an inverter).

[0081] Optionally, the notification transmission end can be divided into a first notification transmission end and a second notification transmission end. The first notification transmission end can use the txready pin, and the second notification transmission end can use the txvalid pin. Specifically, the first notification transmission end of the SOC system is connected to the first notification transmission end of the peripheral board via the first notification transmission end of the FPGA, and the first notification transmission end of the SOC system is also connected to the first input terminal of the logic NOR module. The second notification transmission end of the SOC system is connected to the second notification transmission end of the peripheral board via the second notification transmission end of the FPGA, and the second notification transmission end of the SOC system is also connected to the input terminal of the logic NOR module, while the output terminal of the logic NOR module is connected to the control terminal of the third bidirectional port.

[0082] Optionally, in addition to being divided into a first data sending end and a second data sending end, the data sending end also includes a third data sending end; in addition to being divided into a first data receiving end and a second data receiving end, the data receiving end also includes a third data receiving end.

[0083] The third data transmitter is connected to the input of the third bidirectional port. The pin corresponding to the third data transmitter is the txdata pin, and the txdata pin can also be multiple low-byte txdata pins (generally the 0th to the 7th txdata pin, denoted as txdata[7:0]). That is, multiple low-byte txdata pins can be connected to the input of the third bidirectional port at the same time. The third data receiver is connected to the bidirectional transmission end of the third bidirectional port. The pin corresponding to the third data receiver is the rxdata pin, and the rxdata pin can also be multiple low-byte rxdata pins (generally the 0th to the 7th rxdata pin, denoted as rxdata[7:0]). That is, multiple low-byte rxdata pins can be connected to the bidirectional transmission end of the third bidirectional port at the same time.

[0084] Optionally, in addition to connecting to the third data receiver of the SOC system, the bidirectional transmission end of the third bidirectional port is also connected to the transceiver multiplexer of the peripheral board via the transceiver multiplexer on the FPGA. The transceiver multiplexer connected to the third bidirectional port is a data pin multiplexed from txdata and rxdata pins. Furthermore, the transceiver multiplexer of the peripheral board can also consist of multiple low-byte data pins (i.e., low-byte data transmission ends) (generally the 0th to 7th data pins, denoted as data[7:0]), corresponding to the low-byte third data transmitter and receiver in the SOC system. In this way, through port multiplexing, multiple pin data transmissions can be achieved using a single port, greatly saving pin resources.

[0085] Optional, refer to Figure 7 The operating principle of the third bidirectional port and related ports is as follows:

[0086] Optionally, eight IOBUF tri-state gates with a single-bit data width are instantiated at the top layer of the FPGA's RTL, and an application layer PAD_WRAPPER (the entire PAD_WRAPPER contains a bidirectional port PAD) is wrapped around it. Corresponding pins need to be assigned on the FPGA to obtain the FPGA's third bidirectional port PAD3. Furthermore, using a logic NOT module, the signal output from the second notification transmission terminal of the SOC system is logically NOTed. The calculation result is then output to the control terminal OEN2 of the third bidirectional port through the output of the logic NOT module. The logic formula is as follows: Where t3 is the output of the second notification transmission end (the aforementioned t1 is equivalent to the output of the first notification transmission end).

[0087] Optionally, multiple byte txdata pins of the third data transmitter are also output to the input of the third bidirectional port. When the control terminal OEN2 is low, the third bidirectional port switches to transmit mode (and outputs low byte data). At this time, the data sent by the third data transmitter is output to the transceiver multiplexing terminal of the FPGA through the bidirectional transmission terminal of the third bidirectional port, and then sent to multiple low byte data pins of the transceiver multiplexing terminal of the peripheral board through the transceiver multiplexing terminal of the FPGA.

[0088] Optionally, multiple low-byte rxdata pins of the third data receiver are connected to the bidirectional transmission end of the third bidirectional port. When the control terminal OEN2 is output at a high level, the third bidirectional port switches to the receive mode (and low-byte reception). At this time, multiple low-byte data pins of the peripheral board can send data to multiple low-byte rxdata pins of the third data receiver through the third bidirectional port on the FPGA.

[0089] The SOC system verification platform proposed in one embodiment establishes a communication connection between the FPGA and the peripheral board based on the optimized method of UTMI interface multiplexing of the USB 2.0 protocol. This saves nearly half of the DATA pin resources for both the FPGA and the peripheral board, solving the problem of insufficient I / O pins on the FPGA when verifying the SOC system based on the FPGA. At the same time, by setting up corresponding bidirectional ports on the FPGA as data relays between the SOC system and the peripheral board, the latency problem caused by I / O multiplexing in the FPGA is solved, ensuring the stable operation of the SOC system verification platform and thus improving the accuracy of testing the SOC system using the FPGA verification platform.

[0090] In one embodiment, reference is made to Figure 8 Based on the above embodiments, the logic control module includes a logic NOR module and a logic NOT module, the data receiving end includes a first data receiving end and a third data receiving end, the data sending end includes a first data sending end and a third data sending end, the bidirectional port is divided into a first bidirectional port and a third bidirectional port, and the notification transmission end includes a first notification transmission end and a second notification transmission end.

[0091] The first notification transmission terminal of the SOC system is connected to the first notification transmission terminal of the peripheral board via the first notification transmission terminal of the FPGA. The first notification transmission terminal of the SOC system is also connected to the first input terminal of the logic NOR module. The output terminal of the logic NOR module is connected to the control terminal of the first bidirectional port.

[0092] The first data transmitting end is connected to the input end of the first bidirectional port and the second input end of the logic OR module, respectively; the first data receiving end is connected to the bidirectional transmission end of the first bidirectional port.

[0093] The second notification transmission terminal of the SOC system is connected to the second notification transmission terminal of the peripheral board via the second notification transmission terminal of the FPGA. The second notification transmission terminal of the SOC system is also connected to the input terminal of the logic NOT module, and the output terminal of the logic NOT module is connected to the control terminal of the third bidirectional port.

[0094] The third data transmitting end is connected to the input end of the third bidirectional port, and the third data receiving end is connected to the bidirectional transmission end of the third bidirectional port. The transceiver multiplexing end of the peripheral board connected to the third bidirectional port via the transceiver multiplexing end of the FPGA consists of multiple low-byte data transmission ends.

[0095] The wiring, operating principle, and corresponding effects of the first and third bidirectional ports can be referred to the above embodiments, and will not be repeated here. The main purpose of this embodiment is to provide a solution similar to the above embodiments (such as a logic OR NOT module + two bidirectional ports). Figure 3 ), or a verification platform structure consisting of a logical OR-NOT module, a logical NOT module, and three bidirectional ports (corresponding to Figure 6 Different verification platform structures (i.e., logical OR-NOT module, logical NOT module + two bidirectional ports verification platform structures, corresponding to...) Figure 8 )) as an optional option for users.

[0096] Furthermore, this application also provides a verification platform control method for a SOC system. This SOC system verification platform control method is applied to the verification platform of the SOC system as described in any of the above embodiments. The SOC system verification platform control method includes:

[0097] Based on the control signals output by the SOC system, control the bidirectional port of the FPGA to switch to the corresponding transmission mode;

[0098] Specifically, when the transmission mode is switched to transmit mode, the SOC system sends data to the external board via the FPGA; when the transmission mode is switched to receive mode, the SOC system receives data sent by the external board via the FPGA.

[0099] In one embodiment, the SOC system verification platform control method is optimized based on the UTMI interface multiplexing of the USB 2.0 protocol to establish a communication connection between the FPGA and the peripheral board. This allows both the FPGA and the peripheral board to save nearly half of their DATA pin resources, solving the problem of insufficient I / O pins on the FPGA when the SOC system is verified based on the FPGA. At the same time, by setting up corresponding bidirectional ports on the FPGA and outputting corresponding control signals to control the bidirectional ports to switch between transmit / receive modes, the bidirectional ports can be used as data relays between the SOC system and the peripheral board. This solves the latency problem caused by FPGA I / O multiplexing, ensures the stable operation of the SOC system verification platform, and improves the accuracy of testing the SOC system using the FPGA verification platform.

[0100] Furthermore, this application embodiment also provides a control device, which is applied to the verification platform of the SOC system as described in any of the above embodiments. The control device is a virtual control device, which can be used to control the bidirectional port of the FPGA to switch to the corresponding transmission mode according to the control signal output by the SOC system. When the transmission mode is switched to the transmit mode, the SOC system sends data to the external board via the FPGA. When the transmission mode is switched to the receive mode, the SOC system receives data sent by the external board via the FPGA.

[0101] Furthermore, this application also proposes a computer-readable storage medium, which includes a verification platform control program for a System-on-a-Chip (SOC) system. When executed by a processor, the verification platform control program implements the steps of the verification platform control method for an SOC system as described in the above embodiments. It is understood that the computer-readable storage medium in this embodiment can be a volatile readable storage medium or a non-volatile readable storage medium.

[0102] In summary, the verification platform, control method, control device, and computer-readable storage medium for the SOC system provided in this application embodiment are optimized based on the UTMI interface multiplexing of the USB 2.0 protocol. This establishes a communication connection between the FPGA and the peripheral board, saving nearly half of the DATA pin resources for both the FPGA and the peripheral board. This solves the problem of insufficient I / O pins on the FPGA when verifying the SOC system based on it. Simultaneously, by setting corresponding bidirectional ports on the FPGA and outputting corresponding control signals to control the switching between transmit / receive modes, the bidirectional ports can act as data relays between the SOC system and the peripheral board. This solves the latency problem caused by FPGA I / O multiplexing, ensuring the stable operation of the SOC system verification platform and improving the accuracy of testing the SOC system using the FPGA verification platform.

[0103] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media provided in this application and in the embodiments may include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual-speed SDRAM (SSRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0104] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, apparatus, article, or method that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, apparatus, article, or method. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, apparatus, article, or method that includes that element.

[0105] The above description is only a preferred embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural changes made based on the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A verification platform for a SOC system, characterized in that, The verification platform includes an FPGA and a peripheral board. The platform establishes a communication connection between the FPGA and the peripheral board based on UTMI interface multiplexing. The FPGA includes a logic control module and multiple bidirectional ports. The feedback transmission terminal of the peripheral board is connected to the feedback transmission terminal of the SOC system via the FPGA. The notification transmission terminal of the SOC system is connected to the notification transmission terminal of the peripheral board via the FPGA, and the notification transmission terminal of the SOC system is also connected to the input terminal of the logic control module. The data transmission terminal of the SOC system is connected to the input terminal of the bidirectional ports. The bidirectional transmission terminal of the bidirectional ports is connected to the transceiver multiplexing terminal of the peripheral board via the transceiver multiplexing terminal of the FPGA, and the bidirectional transmission terminal of the bidirectional ports is also connected to the data receiving terminal of the SOC system. The output of the logic control module is connected to the control terminal of the bidirectional port, and the logic control module is used to control the bidirectional port to switch to the corresponding transmission mode, which includes a sending mode and a receiving mode. The logic control module includes a logic NOR module and a logic NOT module; the notification transmission end includes a first notification transmission end and a second notification transmission end; the data receiving end includes a first data receiving end, a second data receiving end and a third data receiving end; the data sending end includes a first data sending end, a second data sending end and a third data sending end; and the bidirectional port is divided into a first bidirectional port, a second bidirectional port and a third bidirectional port. The first notification transmission terminal of the SOC system is connected to the first notification transmission terminal of the peripheral board via the first notification transmission terminal of the FPGA. The first notification transmission terminal of the SOC system is also connected to the first input terminal of the logic OR module. The second notification transmission terminal of the SOC system is connected to the second notification transmission terminal of the peripheral board via the second notification transmission terminal of the FPGA. The second notification transmission terminal of the SOC system is also connected to the input terminal of the logic NOT module, and the output terminal of the logic NOT module is connected to the control terminal of the third bidirectional port. The first data transmitting end is connected to the input end of the first bidirectional port and the second input end of the logic OR module, respectively; the first data receiving end is connected to the bidirectional transmission end of the first bidirectional port. The second data transmitting end is connected to the input end of the second bidirectional port, the second data receiving end is connected to the bidirectional transmission end of the second bidirectional port, and the transceiver multiplexing end of the peripheral board connected to the second bidirectional port via the transceiver multiplexing end of the FPGA is a multi-high-byte data transmission end; The third data transmitting end is connected to the input end of the third bidirectional port, and the third data receiving end is connected to the bidirectional transmission end of the third bidirectional port. The transceiver multiplexing end of the peripheral board connected to the third bidirectional port via the transceiver multiplexing end of the FPGA consists of multiple low-byte data transmission ends.

2. A verification platform control method for a SOC system, characterized in that, The verification platform for the SOC system as described in claim 1, wherein the control method for the verification platform of the SOC system includes: Based on the control signals output by the SOC system, control the bidirectional port of the FPGA to switch to the corresponding transmission mode; Specifically, when the transmission mode is switched to transmit mode, the SOC system sends data to the external board via the FPGA; when the transmission mode is switched to receive mode, the SOC system receives data sent by the external board via the FPGA.

3. A control device, characterized in that, A verification platform applied to the SOC system as described in claim 1; The control device is used to control the bidirectional port of the FPGA to switch to the corresponding transmission mode according to the control signal output by the SOC system; wherein, when the transmission mode is switched to the transmit mode, the SOC system sends data to the external board through the FPGA; when the transmission mode is switched to the receive mode, the SOC system receives data sent by the external board through the FPGA.

4. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a verification platform control program for the SOC system, which, when executed by a processor, implements the steps of the verification platform control method for the SOC system as described in claim 2.

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