Memory adapter, memory test assembly, and test method

Abstract

The present disclosure relates to a memory adapter plate, a memory test assembly and a memory test method, and belongs to the technical field of integrated circuits. The memory adapter plate comprises a circuit board and a memory chip test seat, a power conversion module and a switch unit arranged on the circuit board. The memory chip test seat is used for mounting a memory chip. The power conversion module is used for providing power for the memory chip. The switch unit is used for connecting the memory chip and a programmable board card. The programmable board card is used for controlling the memory chip to execute test instructions. The present disclosure can test the memory chip according to the test instructions.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and more specifically, to a memory adapter board, a memory test component, and a memory test method. Background Technology

[0002] The memory test mode is a mode that accesses the DFT (Design For Test) registers defined during the design phase after the chip tape-out is completed. It can change some of the power supply voltages, I / O timings, etc. inside the memory chip, thereby improving the efficiency of memory chip debugging.

[0003] In the existing testing mode that accesses DRAM (Dynamic Random Access Memory) chips through the CPU motherboard, the CPU motherboard cannot recognize and control the completion of memory testing for some test instructions, such as those that do not meet the JEDEC (Joint Electron Device Engineering Council) specifications.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this disclosure is to provide a memory adapter board, a memory test component, and a memory test method, thereby overcoming, at least to some extent, the problem of being unable to test DRAM chips according to test instructions.

[0006] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part by practice of the invention.

[0007] According to a first aspect of this disclosure, a memory adapter board is provided, comprising: a circuit board and a memory chip test socket, a power conversion module, and a switching unit disposed on the circuit board; wherein, the memory chip test socket is used to mount a memory chip; the power conversion module is used to provide power to the memory chip; the switching unit is used to connect the memory chip and a programmable board, and the programmable board is used to control the memory chip to execute test instructions.

[0008] In one optional exemplary embodiment, the programmable board is used to control the switching unit to connect the memory chip and the programmable board according to the test instruction after the memory chip is reset.

[0009] In an exemplary embodiment, the programmable board card is configured to convert the test instruction into test information, extract a waveform signal corresponding to the test information from a preset timing diagram, and input the waveform signal to the memory chip at a falling edge of a command clock.

[0010] In an exemplary embodiment, the test instruction and the test information correspond to the falling edge of the command clock.

[0011] In an exemplary embodiment, the test information includes a control signal, an array signal, and an address signal.

[0012] In an exemplary embodiment, the programmable board card includes a programmable chip, a peripheral circuit connected to the programmable chip, an interface unit, a storage unit, and a power supply unit, and the interface unit is connected to the switch unit.

[0013] In an exemplary embodiment, the storage unit includes a random access memory configured to store the preset timing diagram.

[0014] In an exemplary embodiment, the peripheral circuit includes a clock circuit configured to provide a working clock for the programmable board card, and a first reset circuit configured to trigger a logical reset of the programmable chip.

[0015] In an exemplary embodiment, the power conversion module further includes a second reset circuit configured to provide a reset signal for the memory chip.

[0016] In an exemplary embodiment, the second reset circuit includes a resistor and a capacitor connected in series.

[0017] In an exemplary embodiment, the power conversion module is configured to send the reset signal to reset the memory chip after supplying power to the memory chip for a preset time.

[0018] In an exemplary embodiment, the memory chip is connected to the switch unit through a cable.

[0019] In an exemplary embodiment, the switch unit is a high-speed switch with a switching speed greater than or equal to 4 Gbps.

[0020] In an exemplary embodiment, a spacer plate is arranged at the bottom of the circuit board.

[0021] In an alternative exemplary embodiment, the programmable board card is an FPGA board card or a CPLD board card.

[0022] According to a second aspect of the present disclosure, a memory testing assembly is provided, comprising: a system platform mainboard; the memory adapter board as described above, integrated on the system platform mainboard, the switch unit of the memory adapter board being connected with the system platform mainboard; and a programmable board card, connected with the switch unit, for controlling a memory chip to execute a test instruction.

[0023] In an alternative exemplary embodiment, the switch unit is a switchable switch unit, for switching electrical signals between the system platform mainboard and the programmable board card.

[0024] In an alternative exemplary embodiment, the system platform mainboard comprises: a CPU, a CPU interface unit and a CPU storage unit; wherein the CPU storage unit and the CPU are respectively connected with the CPU interface unit, and the CPU interface unit is connected with the switch unit.

[0025] According to a third aspect of the present disclosure, a memory testing method is provided, for the memory testing assembly as described above, comprising: disconnecting a memory chip from a system platform mainboard; powering the memory chip through a power conversion module in a memory adapter board; after a preset time of power supply, sending a reset signal to reset the memory chip; connecting the memory chip with a programmable board card, controlling the memory chip to enter a test mode through the programmable board card, executing a test instruction; after completing the test, powering off the programmable board card, and connecting the memory chip with the system platform mainboard.

[0026] In an alternative exemplary embodiment, controlling the memory chip to enter the test mode through the programmable board card comprises: writing the test instruction into the programmable board card through a program; converting the test instruction into test information through the programmable board card, and extracting a waveform signal corresponding to the test information from a preset timing diagram, inputting the waveform signal into the memory chip at a falling edge of a command clock; and controlling the memory chip to perform a test according to the waveform signal.

[0027] According to the memory adapter board in the example embodiment, on one hand, the detachable connection of the memory chip can be realized by setting the memory chip test seat, and the power conversion module in the memory adapter board can provide power supply for the memory chip, so that the independent power supply in the memory chip test process can be met, and the test process of the memory chip can be completely independent of the terminal device, and is not affected by the power-off of the terminal system platform, so that the application range is wider, and the debugging is more convenient. On the other hand, the memory adapter board can be set on the system platform mainboard of the terminal device, so as to find and analyze the problems of the memory chip as soon as possible according to the actual situation of the system platform mainboard, so as to achieve the test purpose. On the other hand, the memory adapter board can be connected to the programmable board card, and the programmable board card can control the memory chip to execute the test instruction according to the test instruction customized by the user, such as the unconventional test instruction, so that the test range of the memory chip can be expanded, and the user demand can be met to the maximum extent.

[0028] It should be understood that the foregoing general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0029] The drawings incorporated into the specification and forming a part thereof illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the disclosure. It is clear that the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained from these drawings without creative labor for those skilled in the art. In the drawings:

[0030] Figure 1 The structure of a memory adapter board according to an example embodiment of the present disclosure is schematically shown;

[0031] Figure 2 The side view of the memory adapter board according to an example embodiment of the present disclosure is schematically shown;

[0032] Figure 3 The schematic diagram of a programmable board card converting test instructions according to an example embodiment of the present disclosure is schematically shown;

[0033] Figure 4 The correspondence between test information and waveform signals according to an example embodiment of the present disclosure is schematically shown;

[0034] Figure 5 The structure of a memory test assembly according to an example embodiment of the present disclosure is schematically shown;

[0035] Figure 6A flowchart schematically illustrating a memory test method according to an example embodiment of the present disclosure is shown.

[0036] BRIEF DESCRIPTION OF DRAWINGS

[0037] 100 - memory adapter board; 110 - circuit board; 120 - memory chip test socket; 130 - power conversion module; 140 - switch unit; 150 - spacer plate; 310 - programmable board card; 320 - memory chip; 500 - memory test assembly; 510 - system platform mainboard. DETAILED DESCRIPTION

[0038] Example embodiments now will be described more fully hereinafter with reference to the accompanying drawings. Example embodiments, however, can be implemented in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of example embodiments to those skilled in the art. Like reference numerals refer to like elements throughout the several views.

[0039] Moreover, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the

[0040] The block diagrams in the drawings show only the functionality of the embodiments and do not imply any particular physical or architectural arrangement of the devices, systems, or methods. No inference should be drawn regarding the implementational aspects of the embodiments as shown and described herein. Further, having described a few embodiments, modifications, alternatives, and variations of the embodiments can be apparent to others skilled in the art.

[0041] The memory test mode is a super mode that can be accessed only by the original factory, and is usually not open to users. For example, after the DRAM chip tape-out package is completed, the DFT (Design For Test) register inside the DRAM chip can be accessed and modified by entering the DRAM chip test mode, so as to change part of the internal power supply voltage, I / O timing and interface parameters for debugging of the DRAM chip. This is beneficial to improve the efficiency of DRAM chip debugging, accelerate error positioning, and make the entire DRAM chip test process converge quickly.

[0042] For the traditional way of entering the DRAM chip test mode, for example, ATE machine and CPU mainboard and the like, are not suitable for use on the user system platform, and once the user system platform is powered off or reset, the settings completed in the test mode before will be lost. In the process of testing the memory through the CPU mainboard, it is necessary to have complete CPU mainboard bottom code and control code capable of correctly modifying the PHY (Physical, physical layer) of the memory, which is too high in cost. Moreover, part of the test instructions of the memory test mode cannot be directly decoded, for example, the test instructions that do not meet the JEDEC specification, that is, do not belong to the irregular test instructions defined in the JEDEC specification, and the CPU mainboard cannot be implemented for this part of the test instructions. For example, for the DRAM chip, in the test mode, the information output by the DRAM chip to the outside is usually implemented using the DQ pin, without the jump of the DQS signal. This results in that after entering the DRAM chip test mode using the CPU mainboard, the chip ID reading operation cannot be performed.

[0043] Based on this, the exemplary embodiments of the present disclosure provide a memory adapter plate, which is described with reference to Figure 1 and Figure 2 , a structural schematic diagram of a memory adapter plate according to an exemplary embodiment of the present disclosure is shown. As Figure 1 indicated, the memory adapter plate 100 provided by the present exemplary embodiment is used to assist the test of the memory chip, wherein the memory adapter plate 100 comprises a circuit board 110 and a memory chip test seat 120, a power conversion module 130 and a switch unit 140 arranged on the circuit board 110; wherein,

[0044] The memory chip test seat 120 is mainly used for mounting the memory chip; the power conversion module 130 is mainly used for providing power supply for the memory chip. In actual application, the power conversion module 130 can convert the power supply into all the power required by the memory chip to meet the needs of the memory chip. That is, the power conversion module 130 can convert the power supply into power with different voltage VDDx sizes to provide for the memory chip. Taking the LPDDR4X (Low Power Double Data Rate 4) DRAM chip as an example, the power conversion module 130 can convert multiple voltages VDDX such as VDD1 (1.8V), VDD2 (1.1V) and VDDQ (0.6V) to provide power supply for the LPDDR4X chip.

[0045] In the exemplary embodiments of the present disclosure, the switch unit 140 can be used to connect the memory chip and the programmable board card. The programmable board card is an external device relative to the memory adapter 100. When the memory chip needs to be tested, the programmable board card can be connected to the memory adapter 100, and the programmable board card can be used to control the memory chip to execute the test instruction through the switch unit 140.

[0046] In actual applications, the programmable board card can be an FPGA (Field Programmable Gate Array) board card, a CPLD (Complex Programmable logic device) board card, or the like. The programmable board card is a semi-custom circuit in an application-specific integrated circuit, and is a programmable logic array. The programmable chip in the programmable board card can receive the writing of the code and output the corresponding test instruction information to the memory chip.

[0047] The programmable board card provided by the exemplary embodiments of the present disclosure can not only realize the writing of the test instruction, but also can convert the test instruction into a waveform signal that can be recognized by the memory chip, so as to facilitate the memory chip to execute the corresponding test instruction.

[0048] In actual applications, when the memory chip on a terminal such as a mobile phone or a computer needs to be tested, the memory chip can be taken down and installed on the memory chip test seat. Then, the power conversion module 130 can be used to supply power to the memory chip. After a preset time of power supply, the memory chip can be reset by a reset signal. That is, the power conversion module 130 can send a reset signal to reset the memory chip after a preset time of power supply to the memory chip. After the memory chip is reset, the programmable board card can control the switch unit to connect the memory chip and the programmable board card according to the test instruction, for example, the test instruction written by the code.

[0049] In the exemplary embodiments of the present disclosure, the programmable board card can convert the above test instruction into test information. The test information can include a control signal, an array signal, and an address signal. Taking the test instruction "change the 0 signal in the 0010 address in BANK1 to a 1 signal" as an example, after receiving the above instruction, the programmable board card can convert the test instruction into test information such as a control signal "change the 0 signal to a 1 signal", an array signal "BANK1", and an address signal "0010".

[0050] Next, the programmable board can extract the waveform signal corresponding to the above test information from a pre-stored timing diagram, and then input the waveform signal to the memory chip. The memory chip can perform tests based on the waveform signal and execute the above-mentioned modification and other test tasks. (Refer to...) Figure 3 The diagram shows a schematic of the programmable board 310 converting test instructions. After the programmable board 310 converts the test instructions into control signals, array signals and address signals, it extracts the waveform signals corresponding to the control signals, array signals and address signals, and then inputs the waveform signals to the memory chip 320 for testing.

[0051] Reference Figure 4 This diagram illustrates the correspondence between test information and waveform signals in an exemplary embodiment of this disclosure. Taking an address signal as an example... Figure 4 In this configuration, both the test command (Command) and the address signal (Address) correspond to the falling edge of the command clock (CK_t). The programmable board 310 inputs the waveform signal to the memory chip 320 at the falling edge of the command clock. By corresponding the test information such as the address signal and the test command to the falling edge of the command clock, command customization can be achieved. For example, users can set unconventional test commands that are not defined in the JEDEC specification according to their own needs. The programmable board 310 then converts the unconventional test commands into waveform signals that the memory chip can recognize, thereby enabling the memory chip 320 to execute the unconventional test commands. Of course, test commands that meet the JEDEC specification can also be defined using the embodiments of this disclosure and executed. The test here may involve accessing and modifying the DFT register inside the memory chip 310, that is, controlling the memory chip 320 to enter test mode and modifying the value in the DFT register to improve the performance of the memory chip 320.

[0052] Figure 4 In this context, MRS refers to the transfer instruction from the status register to the general-purpose register. The MRS (ModeRegister) instruction controls the DRAM to enter test mode, thereby setting values ​​in the DFT register. In practical applications, the MRS instruction can be a combination of MRW (Mode Register Write) commands from the protocol. By setting specific values ​​for each MRW in the combination, the test mode can be entered based on those specific values ​​to execute the test process. DES represents the intermediate idle state, where no commands are used. CKE is the clock enable signal. Generally, the logic state of the input signal needs to be determined by sampling the rising edge of CK_t. This exemplary embodiment of the present disclosure achieves the execution of unconventional test instructions by mapping test instructions to the falling edge of CK_t.

[0053] In actual application, the preset time can be set according to actual situation, as long as the provided power meets the reset and restart of the memory chip, and the size of the preset time is not specially limited in the example embodiment of the present disclosure. The reset signal can be generated by the power conversion module 130, and specifically, a second reset circuit can be arranged in the power conversion module 130 to provide the reset signal for the memory chip 320.

[0054] In actual application, the second reset circuit can include a resistor and a capacitor connected in series, and the capacitor is charged at the moment of power-on. The capacitor is equivalent to a short circuit, and the resistor connected to the capacitor end is pulled up or pulled down. After charging is completed, the capacitor end is open, and a reset process is completed.

[0055] With reference to Figure 4 In the example embodiment of the present disclosure, the programmable board card 310 can include a programmable chip, a peripheral circuit connected to the programmable chip, an interface unit, a storage unit, and a power supply unit, wherein the interface unit is connected to the switch unit 140. The programmable chip is used for input and output of programming information, and the peripheral circuit can include a clock circuit and a first reset circuit, wherein the clock circuit can be used to provide a working clock for the programmable board card; the first reset circuit can be used to trigger a logic reset of the programmable chip, and the internal structure of the first reset circuit can refer to the second reset circuit, which will not be described here.

[0056] In the example embodiment of the present disclosure, the connection of the programmable board card 310 and the memory adapter board 100 can be realized through the connection of the interface unit and the switch unit 140. The interface unit of the programmable board card 310 is connected to one connection end of the switch unit 140, and the communication or disconnection of the interface unit and the switch unit 140 can be controlled through the programmable board card 310.

[0057] In the example embodiment of the present disclosure, the storage unit in the programmable board card 310 can include a random access memory, which can be used to store a preset timing diagram, so that the programmable chip can call the preset timing diagram through the random access memory. The random access memory can use, for example, a FIFO (First Input First Output) memory.

[0058] In actual application, whether it is an FPGA board card or a CPLD board card, it has the characteristics of rich wiring resources, repeated programming, and high integration, which can meet the needs of the memory adapter board 100 in the example embodiment of the present disclosure, and can also reduce the cost.

[0059] In actual application, the connection between the memory chip 320, the programmable board card 310 and the switch unit 140 can be realized through a cable, and a pluggable socket can be arranged on the cable to realize the detachable connection between the memory chip 320 and the switch unit 140 and the detachable connection between the programmable board card 310 and the switch unit 140. In addition, the connection between the memory chip 320 and the switch unit 140 can also be realized through the connection between the memory chip test seat 120 and the switch unit 140. The memory chip 320 can realize the electrical connection with the memory chip test seat 120 after being installed into the memory chip test seat 120, so as to realize the connection between the memory chip 320 and the switch unit 140. The connection between the memory chip test seat 120 and the switch unit 140 can realize the fixed electrical connection through the circuit on the circuit board 110, so as to reduce the damage caused by repeated disassembly.

[0060] When the memory is a memory device with a high-speed interface such as DRAM, the switch unit 140 can be a high-speed switch to meet the speed matching requirement. In an optional example embodiment, the switching speed of the high-speed switch 140 can be greater than or equal to 4 Gbps. In actual application, the switching speed of the high-speed switch can also be adjusted according to actual needs, and the present disclosure is not limited thereto.

[0061] In actual application, referring to Figure 2 The bottom of the memory adapter board 100 provided by the present disclosure can also be provided with a raised plate 150. Specifically, the raised plate 150 can be arranged at the bottom of the circuit board 110, that is, the side opposite to the memory chip test seat 120. The memory adapter board 100 can be raised by the raised plate 150 to avoid interference with surrounding components when the memory adapter board 100 is installed on the system platform mainboard of the terminal device.

[0062] According to the memory adapter board in the example embodiment, on one hand, the detachable connection of the memory chip 320 can be realized by arranging the memory chip test seat 120, and the power conversion module 130 in the memory adapter board 100 can provide power supply for the memory chip 320, so that the independent power supply in the memory chip 320 testing process can be met, the testing process of the memory chip 320 can be completely independent of the terminal equipment, and is not affected by the power-off of the terminal system platform, the application range is wider, and the debugging is more convenient. On the other hand, the memory adapter board 100 can be arranged on the system platform mainboard of the terminal equipment, so as to find and analyze the problems of the memory chip 320 as soon as possible according to the actual situation of the system platform mainboard, and the testing purpose is achieved. On the other hand, the memory adapter board 100 can be connected with the programmable board card 310, and the memory chip 320 can be controlled to execute the test instruction according to the unconventional test instruction through the programmable board card 310, so that the test range of the memory chip 320 can be expanded, and the user demand can be met to the maximum extent.

[0063] A memory testing assembly is also provided in the example embodiment of the present disclosure. Referring to Figure 5 , a structural schematic diagram of a memory testing assembly according to the example embodiment of the present disclosure is shown. As shown in Figure 5 , the memory testing assembly 500 provided by the example embodiment includes a system platform mainboard 510, a programmable board card 310 and the above-mentioned memory adapter board 100. The system platform mainboard 510 can be the mainboard of an electronic device such as a mobile phone or a computer having a memory. The memory adapter board 100 is integrated on the system platform mainboard 510, and the switch unit 140 of the memory adapter board 100 is connected with the system platform mainboard 510; the programmable board card 310 is connected with the switch unit 140 of the memory adapter board 100, and the programmable board card 310 can be used to control the memory chip 320 to execute the test instruction.

[0064] In the memory testing assembly provided by the example embodiment of the present disclosure, the above-mentioned switch unit 140 needs to be a switchable switch unit, so as to switch the electrical signals between the system platform mainboard 510 and the programmable board card 310. Specifically, when the programmable board card 310 is externally connected, the clock signal, the address signal and the control signal in the memory chip 320 are switched to the programmable board card 310; when the programmable board card 310 is not externally connected, the clock signal, the address signal and the control signal in the memory chip 320 are switched to the system platform mainboard 510.

[0065] In actual application, the switchable switch unit can be a single-pole double-throw switch, and can also be other types of switches, as long as the connection switching can be realized, and the example embodiment of the present disclosure does not specially limit this.

[0066] In an example embodiment of the present disclosure, the switching of the switching unit 140 can also be controlled according to the type of test instruction. When the test instruction is, for example, a regular test instruction that meets the JEDEC specification, the switching unit 140 can be switched to connect the memory chip 320 and the system platform mainboard 510, and the memory chip 320 can be controlled to execute the test instruction through the system platform mainboard 510. When the test instruction is, for example, an irregular test instruction that does not meet the JEDEC specification, the switching unit 140 can be switched to connect the memory chip 320 and the programmable board card 310, and the memory chip 320 can be controlled to execute the irregular test instruction through the programmable board card 310. The specific execution manner can refer to the above-mentioned embodiments, and will not be described here.

[0067] In actual application, the system platform mainboard 510 can include a CPU, a CPU interface unit, and a CPU storage unit, wherein the CPU storage unit and the CPU are connected with the CPU interface unit respectively, and the CPU interface unit is connected with the switching unit 140, so as to realize the connection between the memory adapter board 100 and the system platform mainboard 510.

[0068] In the specific structure connection process between the memory adapter board 100 and the system platform mainboard 510, the elevation plate 150 of the memory adapter board 100 can be fixed on the system platform mainboard 510, specifically, the elevation plate 150 can be fixed on the packaging position of the memory chip 320 on the system platform mainboard 510, so as to facilitate the simulation of the actual situation of the memory chip 320 and be beneficial to the analysis of the problem of the memory chip 320 on the system platform mainboard 510.

[0069] In actual application, the fixing of the elevation plate 150 on the system platform mainboard 510 can be achieved in various ways, for example, by welding or by gluing, and the example embodiment of the present disclosure does not make special limitation thereto.

[0070] Since the position of the elevation plate 150 is the position of the memory chip 320 on the system platform mainboard 510, the size of the elevation plate 510 can be designed with reference to the size of the memory chip 320, for example, the cross-sectional size of the elevation plate 510 is the same as the cross-sectional size of the memory chip 320, and the height of the elevation plate 510 is greater than or equal to the thickness of the memory chip 320, for example, the height of the elevation plate 510 can be 1.5-2.5 mm, and the example embodiment of the present disclosure does not make specific limitation thereto.

[0071] In the example embodiment of the present disclosure, the elevation plate 510 can be one of an epoxy plate, an epoxy resin plate, a brominated epoxy resin plate, a glass fiber plate, a glass cloth plate, a flexible circuit board reinforcing plate, a flame-retardant insulating plate, an epoxy glass cloth plate, an epoxy glass cloth laminated plate, and a circuit board drilling backing plate.

[0072] According to the memory test assembly in the example embodiment, on the one hand, the system platform mainboard 510 and the programmable board card 310 are connected through the memory adapter 100, and the memory chip 320 can be controlled to execute test instructions, such as irregular test instructions, through the programmable board card 310, so that the test range of the memory chip can be expanded to meet the user demand to the maximum. On the other hand, the power conversion module 130 in the memory adapter 100 can provide independent power supply for the memory chip 320, so that the independent power supply during the test process of the memory chip 320 can be met, and the test process of the memory chip 320 can be completely independent of the terminal device, and will not be affected by the power failure of the terminal system platform, so that the application range is wider and the debugging is more convenient. On the other hand, the memory adapter 100 is arranged on the system platform mainboard 510 of the terminal device, so that the problems existing in the memory chip 320 can be found and analyzed as soon as possible according to the actual situation of the system platform mainboard 510, and the test purpose is achieved.

[0073] In the example embodiment of the present disclosure, a memory test method is also provided. Referring to Figure 6 , a flowchart of a memory test method according to an example embodiment of the present disclosure is shown. As Figure 6 indicated, the memory test method is used for the above-mentioned memory test assembly. The memory test method can specifically include the following steps:

[0074] Step S610, disconnecting the memory chip from the system platform mainboard;

[0075] Step S620, supplying power to the memory chip through the power conversion module in the memory adapter;

[0076] Step S630, after supplying power for a preset time, sending a reset signal to reset the memory chip;

[0077] Step S640, connecting the memory chip with the programmable board card, controlling the memory chip to enter the test mode through the programmable board card, and executing the test instructions;

[0078] Step S650, after completing the test, powering off the programmable board card, and connecting the memory chip with the system platform mainboard.

[0079] Before the test starts, if the system platform mainboard is running, the system platform mainboard can be switched to the sleep state or the power-off state. Then, the memory chip is supplied with power through the power conversion module in the memory adapter; after supplying power for a preset time, the memory chip is reset through the power conversion module; then, the programmable board card is powered on, the switch unit is switched through the switch, and the memory chip is connected with the programmable board card.

[0080] In the example embodiment of the present disclosure, the test instruction can be written into the programmable board card by program writing, and then the programmable board card converts the test instruction into test information, extracts the waveform signal corresponding to the test information from the preset timing diagram, and inputs the waveform signal into the memory chip at the falling edge of the command clock. Finally, the memory chip is controlled to test according to the waveform signal to modify the value in the DFT register. The specific test instruction conversion and waveform signal extraction can refer to the foregoing embodiments, which will not be described here.

[0081] After the test is completed, if the system platform mainboard is not powered on, the system platform mainboard is powered on for normal operation; if the system platform mainboard is powered on and in a hibernation state, the hibernation state is exited to resume operation. At this time, the modification in the memory chip test mode will take effect on the system platform mainboard.

[0082] According to the memory test method in the example embodiment, on the one hand, the memory adapter board is used to connect the system platform mainboard and the programmable board card, and the programmable board card can write test instructions and control the memory chip to execute, for example, unconventional test instructions, so as to expand the test range of the memory chip and maximize the user demand. On the other hand, the power conversion module in the memory adapter board can provide independent power supply for the memory chip, so as to meet the independent power supply in the memory chip test process, facilitate the test process of the memory chip to be completely independent of the terminal device, and not be affected by the power failure of the terminal system platform, so as to have a wider application range and be more convenient for debugging. On the other hand, the memory adapter board is arranged on the system platform mainboard of the terminal device, so as to quickly find and analyze the problems of the memory chip according to the actual situation of the system platform mainboard, so as to achieve the test purpose. On the other hand, even if the system platform mainboard is powered off during the test process, the modification during the test process will not be affected, so as to ensure the smooth progress of the test modification process, thereby improving the efficiency of the test instruction execution.

[0083] Other embodiments of the present disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure following, in general, the principles of the present disclosure and including such departures from the present disclosure that come within known or customary practice within the art to which the present disclosure pertains. The specification and examples are to be regarded as illustrative only, and the true scope and spirit of the present disclosure are indicated by the claims.

[0084] It should be understood that the present disclosure is not limited to the precise structures described herein and illustrated in the drawings and that various modifications and changes can be made without departing from the scope thereof. The scope of the present disclosure is indicated by the appended claims rather than by the specification and embodiments.

Claims

1. A memory-adapter board, characterized by, The application relates to a memory adapter plate and a system platform mainboard. The memory adapter plate comprises a circuit board and a memory chip test seat, a power conversion module and a switch unit arranged on the circuit board; wherein, The memory chip test seat is used for mounting a memory chip; The power conversion module is used for providing power supply for the memory chip; The switch unit is used for connecting the memory chip and a programmable board card, the programmable board card is used for controlling the memory chip to execute a test instruction, converting the test instruction into test information, extracting a waveform signal corresponding to the test information from a preset timing diagram, and inputting the waveform signal to the memory chip at a falling edge of a command clock; and the memory chip is used for testing according to the waveform signal.

2. The memory pod according to claim 1, wherein, The programmable board card is used for, after the memory chip is reset, controlling the switch unit to connect the memory chip and the programmable board card according to the test instruction.

3. The memory pod of claim 1, wherein, The test instruction and the test information are both corresponding to the falling edge of the command clock.

4. The memory pod of claim 1, wherein, The test information comprises a control signal, an array signal and an address signal.

5. The memory pod of claim 1, wherein, The programmable board card comprises a programmable chip and peripheral circuits, an interface unit, a storage unit and a power supply unit connected with the programmable chip, and the interface unit is connected with the switch unit.

6. The memory pod of claim 5, wherein, The storage unit comprises a random access memory used for storing the preset timing diagram.

7. The memory-adapter board of claim 5, wherein, The peripheral circuits comprise: A clock circuit used for providing a working clock for the programmable board card; A first reset circuit used for triggering logical reset of the programmable chip.

8. The memory pod of claim 1, wherein, The power conversion module further comprises a second reset circuit used for providing a reset signal for the memory chip.

9. The memory-adapter board of claim 8, wherein, The second reset circuit comprises a resistor and a capacitor connected in series.

10. The memory pod of claim 8, wherein, The power conversion module is used for, after providing power supply for the memory chip for a preset time, sending the reset signal to reset the memory chip.

11. The memory pod of claim 1, wherein, The memory chip is connected with the switch unit through a cable.

12. The memory pod of claim 1, wherein, The switch unit is a high-speed switch, and the switching speed of the high-speed switch is greater than or equal to 4Gbps.

13. The memory pod of claim 1, wherein, Further, a pad plate is arranged at the bottom of the circuit board. The programmable board card is an FPGA board card or a CPLD board card.

14. The memory pod of any one of claims 1-13, wherein, The application relates to a memory adapter plate and a system platform mainboard.

15. A memory test assembly comprising: The memory adapter plate comprises a circuit board and a memory chip test seat, a power conversion module and a switch unit arranged on the circuit board; wherein, The memory chip test seat is used for mounting a memory chip; The power conversion module is used for providing power supply for the memory chip; The switch unit is used for connecting the memory chip and a programmable board card, the programmable board card is used for controlling the memory chip to execute a test instruction, converting the test instruction into test information, extracting a waveform signal corresponding to the test information from a preset timing diagram, and inputting the waveform signal to the memory chip at a falling edge of a command clock; and the memory chip is used for testing according to the waveform signal.

16. The memory test assembly of claim 15, wherein, The programmable board card is used for, after the memory chip is reset, controlling the switch unit to connect the memory chip and the programmable board card according to the test instruction.

17. The memory test assembly of either of claims 15 or 16, wherein, The test instruction and the test information are both corresponding to the falling edge of the command clock. The test information comprises a control signal, an array signal and an address signal. The programmable board card comprises a programmable chip and peripheral circuits, an interface unit, a storage unit and a power supply unit connected with the programmable chip, and the interface unit is connected with the switch unit. The storage unit comprises a random access memory used for storing the preset timing diagram. The peripheral circuits comprise: A clock circuit used for providing a working clock for the programmable board card; A first reset circuit used for triggering logical reset of the programmable chip. The power conversion module further comprises a second reset circuit used for providing a reset signal for the memory chip. The second reset circuit comprises a resistor and a capacitor connected in series. The power conversion module is used for, after providing power supply for the memory chip for a preset time, sending the reset signal to reset the memory chip. The memory chip is connected with the switch unit through a cable. The switch unit is a high-speed switch, and the switching speed of the high-speed switch is greater than or equal to 4Gbps. Further, a pad plate is arranged at the bottom of the circuit board. The programmable board card is an FPGA board card or a CPLD board card. The application relates to a memory adapter plate and a system platform mainboard. The memory adapter plate comprises a circuit board and a memory chip test seat, a power conversion module and a switch unit arranged on the circuit board; wherein, The memory chip test seat is used for mounting a memory chip; The power conversion module is used for providing power supply for the memory chip; The switch unit is used for connecting the memory chip and a programmable board card, the programmable board card is used for controlling the memory chip to execute a test instruction, converting the test instruction into test information, extracting a waveform signal corresponding to the test information from a preset timing diagram, and inputting the waveform signal to the memory chip at a falling edge of a command clock; and the memory chip is used for testing according to the waveform signal. The programmable board card is used for, after the memory chip is reset, controlling the switch unit to connect the memory chip and the programmable board card according to the test instruction. The test instruction and the test information are both corresponding to the falling edge of the command clock. The test information comprises a control signal, an array signal and an address signal. The programmable board card comprises a programmable chip and peripheral circuits, an interface unit, a storage unit and a power supply unit connected with the programmable chip, and the interface unit is connected with the switch unit. The storage unit comprises a random access memory used for storing the preset timing diagram. The peripheral circuits comprise: A clock circuit used for providing a working clock for the programmable board card; A first reset circuit used for triggering logical reset of the programmable chip. The power conversion module further comprises a second reset circuit used for providing a reset signal for the memory chip. The second reset circuit comprises a resistor and a capacitor connected in series. The power conversion module is used for, after providing power supply for the memory chip for a preset time, sending the reset signal to reset the memory chip. The memory chip is connected with the switch unit through a cable. The switch unit is a high-speed switch, and the switching speed of the high-speed switch is greater than or equal to 4Gbps. Further, a pad plate is arranged at the bottom of the circuit board. The programmable board card is an FPGA board card or a CPLD board card. The CPU storage unit and the CPU are connected with the CPU interface unit respectively, and the CPU interface unit is connected with the switch unit.

18. A memory testing method for the memory testing assembly of any one of claims 15-17, wherein, The method comprises: Disconnecting the memory chip from the system platform mainboard; Powering the memory chip through the power conversion module in the memory adapter board; After powering for a preset time, sending a reset signal to reset the memory chip; Communicating the memory chip with a programmable board card, controlling the memory chip to enter a test mode through the programmable board card, and executing a test instruction; After completing the test, powering off the programmable board card, and communicating the memory chip with the system platform mainboard; wherein controlling the memory chip to enter the test mode through the programmable board card comprises: Writing the test instruction into the programmable board card through a program; Converting the test instruction into test information through the programmable board card, extracting a waveform signal corresponding to the test information from a preset timing diagram, and inputting the waveform signal into the memory chip at the falling edge of a command clock; Controlling the memory chip to test according to the waveform signal.

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