Integrated circuit, memory device, and method for single cell memory programming shortening

Abstract

This application relates to shortened single-level cell memory programming. A memory device includes an array of memory cells configured as single-level cell memory and control logic operatively coupled to the array of memory cells. The control logic performs operations including causing hardware initialization of a set of sub-blocks within the array of memory cells to be programmed, causing a first sub-block in the set of sub-blocks to be preconditioned for a program operation, causing a plurality of pages of data to be programmed to respective sets of sub-blocks in the set of sub-blocks, and, after programming the plurality of pages of data, selectively causing a program verify to be performed on memory cells of the set of sub-blocks.

Description

Technical Field

[0001] The embodiments of this disclosure generally relate to memory subsystems, and more specifically, to single-level cell memory programming reduction. Background Technology

[0002] A memory subsystem may include one or more memory devices for storing data. Memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize a memory subsystem to store data at memory devices and retrieve data from memory devices. Summary of the Invention

[0003] In one aspect, this application relates to a memory device comprising: a memory cell array configured as a single-level cell memory; and control logic operatively coupled to the memory cell array, the control logic performing operations including: causing hardware initialization of a plurality of sub-blocks to be programmed within the memory cell array; causing pre-tuning of a first sub-block among the plurality of sub-blocks for programming operations; causing a plurality of data pages to be programmed into corresponding sub-blocks among the plurality of sub-blocks; and, after programming the plurality of data pages, selectively causing programming verification to be performed on the memory cells of the plurality of sub-blocks.

[0004] In another aspect, this application relates to a method comprising: causing hardware initialization of a plurality of programmable sub-blocks within a memory cell array configured as a single-level cell memory via control logic of a memory device; causing a first sub-block among the plurality of sub-blocks to be pre-adjusted for programming operations via the control logic; causing a plurality of data pages to be programmed into corresponding sub-blocks among the plurality of sub-blocks via the control logic; and selectively causing programming verification to be performed on the memory cells of the plurality of sub-blocks via the control logic after programming the plurality of data pages.

[0005] In another aspect, this application relates to an integrated circuit comprising: at least one die including an array of memory cells configured as a single-level cell memory; and control logic operatively coupled to the at least one die, the control logic performing operations including: causing a plurality of data pages to be loaded into a page buffer coupled to the memory cell array; causing hardware initialization of a plurality of sub-blocks to be programmed within the memory cell array; causing pre-tuning of a first sub-block among the plurality of sub-blocks for programming operations; causing the plurality of data pages to be programmed into corresponding sub-blocks among the plurality of sub-blocks; and selectively causing programming verification to be performed on the memory cells of the plurality of sub-blocks after programming the plurality of data pages. Attached Figure Description

[0006] This disclosure will be more fully understood in light of the detailed description provided below and the accompanying drawings of various embodiments thereof.

[0007] Figure 1A This describes an instance computing system including a memory subsystem according to some embodiments.

[0008] Figure 1B It is a block diagram of a memory device communicating with a memory subsystem controller of a memory subsystem according to at least one embodiment.

[0009] Figure 2 This is a reference based on the embodiments. Figure 1B A schematic diagram of a portion of the memory cell array in the described type of memory.

[0010] Figure 3 This is a schematic diagram of two segments of a memory cell array comprising four sub-blocks, according to at least some embodiments.

[0011] Figure 4 This is a block diagram illustrating a memory subsystem with a page buffer according to some embodiments, the page buffer including registers from which a set of sub-blocks of a memory array programmed to be configured as a single-level cell (SLC) memory.

[0012] Figure 5A These are a pair of diagrams illustrating the programming of multiple data pages into a set of sub-blocks in certain memory devices configured as SLC memory.

[0013] Figure 5B It is a flowchart of sequential operations typically performed in some memory devices to program multiple data pages into a set of sub-blocks.

[0014] Figure 6A These are a pair of diagrams illustrating, according to some embodiments, programming multiple data pages into a set of sub-blocks in a current memory device configured as SLC memory.

[0015] Figure 6B This is a flowchart of sequential operations performed in a current memory device, according to some embodiments, to program multiple data pages into a set of sub-blocks.

[0016] Figure 7 It is a graph showing the waveforms of the drain selection line (SGD) and the selected word line of a plurality of SLC-based sub-blocks according to at least one embodiment.

[0017] Figures 8A-8B This is a flowchart of an example method for programming a memory cell configured as an SLC memory according to some embodiments.

[0018] Figure 9This is a block diagram of an example computer system in which embodiments of the present disclosure can be operated. Detailed Implementation

[0019] This disclosure relates to the reduction of programming time for memory devices configured as single-level cell (SLC) memory. In certain memory devices that include non-volatile memory devices (e.g., NAND flash memory devices), system performance requirements are becoming increasingly aggressive, such as the need for shorter programming times to and from NAND cells of the memory device (tProg) and reading times from NAND cells. Therefore, these memory devices tend to include portions of the NAND array that can be used as SLC caches, in which SLC data is programmed (and read from) before being transferred to multi-level cell (MLC) memory (e.g., three-level cell (TLC), four-level cell (QLC), or five-level cell (PLC) memory), referenced. Figure 1A This will be discussed in more detail. SLC memory programming and reading times are faster than TLC and significantly faster than high-order MLC memory such as QLC and PLC memory.

[0020] However, in these memory devices, each programming cycle utilizes the control logic on the memory device to perform a series of operations to program each SLC page into the corresponding sub-block of SLC memory. This causes unwanted execution latency as each page is programmed sequentially. For example, this series of operations for each sub-block includes: starting the programming operation with hardware initialization; performing a seeding operation in which the sub-block cells are pre-adjusted to a specific voltage; causing a pulse to program the sub-block; performing word line / bit line recovery for the sub-block; performing a programming verification (PVFY) operation to check if the sub-block has been programmed to a specific threshold PVFY voltage; performing a final verification operation to determine if programming is complete; and ending the programming operation. All these operations are repeated for each page in each memory cell sub-block configured as SLC memory, thus introducing significant execution latency.

[0021] This disclosure addresses the aforementioned and other drawbacks of programming to SLC memory by shortening the series of operations described above through a local media controller (e.g., control logic) of the memory device to program multiple data pages into a set of sub-blocks before performing programming verification operations (and subsequent operations). In these embodiments, due to the memory cells being configured as SLC memory, a one-to-one correspondence exists between data pages and the sub-blocks in which the data pages are stored.

[0022] In at least some embodiments, after data is programmed into the first sub-block, the control logic can direct a reduced-inoculation operation to each subsequent sub-block in the sub-block set, and then program each of these sub-blocks. The reduced-inoculation operation can be understood as cell pre-conditioning of the sub-block to be programmed, but for example, due to the absence of programming verification between programming operations, there is no need to remove potential negative voltages from the word lines. In some embodiments, this pre-conditioning includes allowing the word lines to discharge to a specific voltage level. Therefore, in these embodiments, programming verification operations are performed in parallel on all sub-blocks of the sub-block set after the sub-block set has been fully programmed. In at least some embodiments, this programming verification includes performing a single programming verification together on all sub-block sets after each sub-block set is in a programmed state. However, if one of the sub-block sets remains in an erased state, then no programming verification operation is performed on any of the sub-blocks. If no programming verification operation is performed, then no additional programming pulse is required, thus further simplifying execution.

[0023] The advantages of this method include, but are not limited to, performance improvements in the memory subsystem. In the manner described herein, performance improvements can increase programming speed to SLC memory by at least one-third, with some programming times reduced by at least forty percent. As programming time decreases, read operations can be completed more quickly. For example, some read operations must wait for the data to be read to be fully programmed into the memory array before the read operation can be completed. These and other advantages, which will be apparent to those skilled in the art of memory programming, will be discussed in detail below.

[0024] Figure 1A This description describes an example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or combinations of such media or memory devices. The memory subsystem 110 may be a storage device, a memory module, or a mixture of storage devices and memory modules.

[0025] Memory device 130 may be a non-volatile memory device. An example of a non-volatile memory device is a NAND memory device. A non-volatile memory device is a package of one or more dies. Each die may contain one or more planes. Planes may be grouped into logic units (LUNs). For some types of non-volatile memory devices (e.g., NAND memory), each plane contains a set of physical blocks. Each block contains a set of pages. Each page contains a set of memory cells (“cells”). A cell is an electronic circuit that stores information. Depending on the cell type, a cell may store one or more bits of binary information and has various logic states associated with the number of bits stored. Logic states may be represented by binary values ​​(e.g., “0” and “1” or combinations of such values).

[0026] Memory device 130 may consist of bits arranged in a two-dimensional or three-dimensional grid, also referred to as a memory array. Memory cells are etched onto a silicon wafer in an array of columns (hereinafter also referred to as bit lines) and rows (hereinafter also referred to as word lines). A word line may refer to one or more rows of memory cells in the memory device, which are used in conjunction with one or more bit lines to generate an address for each of the memory cells. The intersection of bit lines and word lines constitutes the address of the memory cell.

[0027] The memory subsystem 110 may be a storage device, a memory module, or a combination of both. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital storage (SD) drives, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0028] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), Internet of Things (IoT) enabled device, embedded computer (e.g., computer contained in a vehicle, industrial equipment or networked commercially available device), or such computing device that includes memory and processing power.

[0029] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1AThis describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intermediate component), whether wired or wireless, and includes connections such as electrical, optical, and magnetic connections.

[0030] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses, for example, memory subsystem 110 to write data to and read data from memory subsystem 110.

[0031] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Dual Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM sockets supporting Dual Data Rate (DDR)). The physical host interface can be used to transmit data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a physical host interface (e.g., a PCIe bus), host system 120 can additionally utilize an NVM High Speed ​​(NVMe) interface, an Open NAND Flash Interface (ONFI) interface, or some other interface to access components (e.g., memory device 130). The physical host interface provides an interface for transmitting control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1A The memory subsystem 110 is described as an example. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0032] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0033] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory and in-place write memory, such as three-dimensional cross-point ("3D cross-point") memory devices, which are cross-point arrays of non-volatile memory cells. The cross-point array of non-volatile memory can be combined with a stackable cross-grid data access array to perform bit storage based on changes in volume resistance. Furthermore, compared to many flash-based memories, cross-point non-volatile memory can perform in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them. NAND flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0034] Each of the memory devices 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells (e.g., multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC)) may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination of such arrays. In some embodiments, a particular memory device may include an SLC portion, an MLC portion, a TLC portion, a QLC portion, or a PLC portion of memory cells. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical cells of the memory device used for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0035] While non-volatile memory components, such as 3D cross-point non-volatile memory cell arrays and NAND flash memories (e.g., 2D NAND, 3D NAND), are described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0036] The memory subsystem controller 115 (for simplicity, controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, erasing data, and other such operations at the memory device 130. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system with dedicated (i.e., hard-decoded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0037] The memory subsystem controller 115 may be a processing device that includes one or more processors (e.g., processor 117) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logical flows, and routines that control the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120.

[0038] In some embodiments, local memory 119 may include memory registers storing memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although the example memory subsystem 110 in FIG1 is illustrated as including a memory subsystem controller 115, in another embodiment of this disclosure, memory subsystem 110 does not include a memory subsystem controller 115, but may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0039] Typically, the memory subsystem controller 115 receives commands or operations from the host system 120 and translates these commands or operations into instructions or appropriate commands to perform the desired access to the memory device 130. The memory subsystem controller 115 may handle other operations such as wear leveling, garbage collection, error detection and error correction (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into instructions for accessing the memory device 130, and translate responses associated with the memory device 130 into information for the host system 120.

[0040] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include caches or buffers (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0041] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory system controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory subsystem 110 is a managed memory device that includes the original memory device 130 having on-die control logic (e.g., local media controller 135) and a controller (e.g., memory subsystem controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0042] In one embodiment, memory subsystem 110 includes memory interface component 113, which includes cache manager 111. Memory interface component 113 is responsible for handling interactions between memory subsystem controller 115 and memory devices (e.g., memory device 130) of memory subsystem 110. For example, memory interface component 113 may send memory access commands corresponding to requests received from host system 120 to memory device 130, such as programming commands, read commands, or other commands. Additionally, memory interface component 113 may receive data from memory device 130, such as data retrieved in response to a read command or confirmation of successful execution of a programming command. In some embodiments, memory subsystem controller 115 includes at least a portion of cache manager 111. For example, memory subsystem controller 115 may include processor 117 (processing means) configured to execute instructions stored in local memory 119 for performing the operations described herein. In some embodiments, memory interface component 113 is part of host system 120, an application, or an operating system. In one embodiment, memory interface 113 includes cache manager 111 and other subcomponents. The cache manager 111 can direct memory access commands (such as read commands, cache read commands, snapshot read commands, cache read context switch commands, or cache reach context restore commands) to the memory device 130.

[0043] In one embodiment, the local media controller 135 includes an SLC programmer 138, and the memory device 130 includes page buffers 152 among a plurality of page buffers that temporarily store (e.g., buffer) data as it is being programmed into or read from memory cells of the memory device 130. In these embodiments, the SLC programmer 138 may direct programming operations that program data stored in page buffers 152 to a set of sub-blocks of the array of SLC memory of the memory device 130. For example, the SLC programmer 138 may cause hardware initialization of the set of sub-blocks to be programmed within the array. The SLC programmer 138 may additionally cause pre-tuning of a first sub-block in the set of sub-blocks for programming operations. In these embodiments, the SLC programmer 138 may additionally cause programming of a plurality of data pages into a corresponding sub-block set in the set of sub-blocks. The SLC programmer 138 may additionally cause programming verification to be performed on the memory cells of the sub-block set after programming the plurality of data pages. Additional details regarding the operation of the cache manager 111 and the parallel programmer 138 are described below.

[0044] Figure 1B The first device in the form of a presenting memory device 130 and the presenting memory subsystem (e.g., according to the embodiment) are presenting memory devices 130. Figure 1A A simplified block diagram of a second device communicating with a memory subsystem controller 115 in the form of a memory subsystem 110. Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, electrical equipment, vehicles, wireless devices, mobile phones, and the like. The memory subsystem controller 115 (e.g., a controller external to the memory device 130) may be a memory controller or other external host device.

[0045] Memory device 130 includes an array 150 of memory cells logically arranged in rows and columns. Memory cells in a logical row are typically connected to the same access line (e.g., a word line), while memory cells in a logical column are typically selectively connected to the same data line (e.g., a bit line). A single access line may be associated with memory cells in more than one logical row, and a single data line may be associated with more than one logical column. At least a portion of the memory cells in the memory cell array 150 ( Figure 1B (Not shown in the image) can be programmed to one of at least two target data states.

[0046] In some embodiments, the memory cell array 150 includes a portion consisting of memory cells configured as SLC memory, namely the SLC cache 145, which, for example and therefore includes the sub-block set referenced herein. In some embodiments, the SLC cache 145 represents a relatively small percentage of the entire memory cell array 150, for example, a percentage between 5% and 15% in some embodiments. The initial programming is performed more quickly, attributable to the faster execution of programming to SLC memory, when the local media controller 135 can first bootstrap programming into the SLC cache 145. The local media controller 135 can then arrange to compress the SLC data for subsequent programming into the remaining portion of the memory cell array 150, which may contain some other MLC memory type.

[0047] Row decoding circuitry 108 and column decoding circuitry 121 are provided to decode address signals. Address signals are received and decoded to access memory cell array 150. Memory device 130 also includes input / output (I / O) control circuitry 112 for managing inputs of commands, addresses, and data to memory device 130, as well as outputs of data and status information from memory device 130. Address register 114 communicates with I / O control circuitry 112, row decoding circuitry 108, and column decoding circuitry 121 to latch address signals before decoding. Command register 124 communicates with I / O control circuitry 112 and local media controller 135 to latch incoming commands.

[0048] A controller (e.g., a local media controller 135 within memory device 130) controls access to memory cell array 150 in response to commands and generates status information for external memory subsystem controller 115, i.e., the local media controller 135 is configured to perform access operations (e.g., read operations, program operations, and / or erase operations) on memory cell array 150. The local media controller 135 communicates with row decoding circuitry 108 and column decoding circuitry 121 to control them in response to addresses. In one embodiment, the local media controller 135 includes an SLC programmer 138 capable of performing abbreviated SLC programming of the SLC memory of memory device 130, as described herein.

[0049] The local media controller 135 also communicates with cache register 142. While the memory cell array 150 is busy writing or reading other data, cache register 142 latches incoming or outgoing data, such as that guided by the local media controller 135, to temporarily store the data. During programming operations (e.g., write operations), data can be transferred from cache register 142 to data register 144 for transmission to the memory cell array 150; new data can then be latched from I / O control circuitry 112 into cache register 142. During read operations, data can be transferred from cache register 142 to I / O control circuitry 112 for output to the memory subsystem controller 115; new data can then be transferred from data register 144 to cache register 142. Cache register 142 and / or data register 144 may form a page buffer 152 of the memory device 130 (e.g., a portion thereof). Page buffer 152 may additionally include sensing devices ( Figure 1B (Not shown in the diagram), it is used to sense the data status of the memory cells of the memory cell array 150, for example, by sensing the status of the data lines connected to the memory cells. The status register 122 can communicate with the I / O control circuitry system 112 and the local media controller 135 to latch status information for output to the memory subsystem controller 115.

[0050] Memory device 130 receives control signals from local media controller 135 at memory subsystem controller 115 via control link 132. For example, control signals may include chip enable signal CE#, command latch enable signal CLE, address latch enable signal ALE, write enable signal WE#, read enable signal RE#, and write protection signal WP#. Depending on the nature of memory device 130, additional or alternative control signals (not shown) may also be received via control link 132. In one embodiment, memory device 130 receives command signals (representing commands), address signals (representing addresses), and data signals (representing data) from memory subsystem controller 115 via multiplexed input / output (I / O) bus 134, and outputs data to memory subsystem controller 115 via I / O bus 134.

[0051] For example, commands can be received at I / O control circuitry system 112 via I / O pins [7:0] of input / output (I / O) bus 134 and then written to command register 124. Addresses can be received at I / O control circuitry system 112 via I / O pins [7:0] of input / output (I / O) bus 134 and then written to address register 114. Data can be received at I / O control circuitry system 112 via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices and then written to cache register 142. The data can then be written to data register 144 for programming memory cell array 150.

[0052] In this embodiment, cache register 142 may be omitted, and data may be written directly to data register 144. Data may also be output on input / output (I / O) pins [7:0] for 8-bit devices or on input / output (I / O) pins [15:0] for 16-bit devices. While references may be made to I / O pins, they may include any conductive nodes, such as commonly used conductive pads or conductive bumps, that enable electrical connection to memory device 130 via an external device (e.g., memory subsystem controller 115).

[0053] Those skilled in the art should understand that additional circuitry and signals can be provided and have been simplified. Figure 1B The memory device 130. It should be understood that, reference Figure 1B The functionality of the various block components described need not be separated from different components or component portions of the integrated circuit device. For example, a single component or component portion of the integrated circuit device may be adapted to perform... Figure 1B The functionality of more than one block component. Alternatively, one or more components or component portions of an integrated circuit device can be combined to perform... Figure 1B The functionality of a single block component. Furthermore, while specific I / O pins are described according to popular conventions for the reception and output of various signals, it should be noted that other combinations or numbers of I / O pins (or other I / O node structures) may be used in various embodiments.

[0054] Figure 2 This is a reference based on the embodiments. Figure 1B A schematic diagram of a portion of an array 200A of memory cells in a memory of the described type, said portion including, for example, an SLC cache 145. The memory array 200A includes, for example, word lines 2020 to 202. N Access lines and, for example, bit lines 2040 to 204 MThe data cable. Word line 202 can be connected in a many-to-one relationship to... Figure 2 Global access lines (e.g., global word lines) not shown. In some embodiments, the memory array 200A may be formed over a semiconductor, which may be conductively doped to have a conductivity type such as p-type conductivity to form a p-well, or have n-type conductivity to form an n-well, for example.

[0055] The memory array 200A can be arranged in rows (each corresponding to a word line 202) and columns (each corresponding to a bit line 204). Each column can contain a string of memory cells (e.g., non-volatile memory cells) connected in series, such as NAND strings 2060 to 206. M One of them. Each NAND string 206 may be connected (e.g., selectively connected) to a common source (SRC) 216 and may contain memory cells 2080 to 208. N Memory cell 208 may represent a non-volatile memory cell used for storing data. Memory cells 208 in each NAND string 206 may be connected in series with select gate 210 (e.g., a field-effect transistor) (e.g., select gates 2100 to 210). M One of them (e.g., it may be a source-select transistor, often referred to as the selector source) and selector 212 (e.g., a field-effect transistor) (e.g., selector 2120 to 212). M Between one of them (for example, it could be a drain-select transistor, often referred to as the select gate drain)). Select transistors 2100 to 210 M They can be connected together to select line 214, such as the source select line (SGS), and select transistors 2120 to 212. M They can be connected together to select line 215, such as drain select line (SGD). Although depicted as conventional field-effect transistors, select gates 210 and 212 can utilize a structure similar to (e.g., identical to) memory cell 208. Select gates 210 and 212 can represent several select gates connected in series, each selected gate configured in series to receive the same or independent control signals.

[0056] The source of each select gate 210 can be connected to the common source 216 or the SRC. The drain of each select gate 210 can be connected to the memory cell 2080 in the corresponding NAND string 206. For example, the drain of select gate 2100 can be connected to the memory cell 2080 of the corresponding NAND string 2060. Therefore, each select gate 210 can be configured to selectively connect the corresponding NAND string 206 to the common source 216. The control gate of each select gate 210 can be connected to the select line 214.

[0057] The drain of each select gate 212 can be connected to bit line 204 of the corresponding NAND string 206. For example, the drain of select gate 2120 can be connected to bit line 2040 of the corresponding NAND string 2060. The source of each select gate 212 can be connected to memory cell 208 in the corresponding NAND string 206. N For example, the source of select gate 2120 can be connected to the memory cell 208 of the corresponding NAND string 2060. N Therefore, each select gate 212 can be configured to selectively connect the corresponding NAND string 206 to the corresponding bit line 204. The control gate of each select gate 212 can be connected to the select line 215.

[0058] Figure 2 The memory array 200A can be a quasi-two-dimensional memory array and can have a generally planar structure, for example, in which the common source 216, NAND string 206, and bit line 204 extend in a substantially parallel plane. Alternatively, Figure 2 The memory array 200A in the memory array may be a three-dimensional memory array, for example, in which the NAND string 206 may extend substantially perpendicular to the plane containing the common source 216 and substantially perpendicular to the plane containing the bit line 204, which may be substantially parallel to the plane containing the common source 216.

[0059] A typical configuration of memory cell 208 includes a data storage structure 234 (e.g., a floating gate, charge trap, etc.) that determines the data state of the memory cell (e.g., by changing a threshold voltage), and a control gate 236, such as... Figure 2 As shown. The data storage structure 234 may include both conductive and dielectric structures, while the control gate 236 is typically formed of one or more conductive materials. In some cases, the memory cell 208 may additionally have defined source / drain (e.g., source) 230 and defined source / drain (e.g., drain) 232. The memory cell 208 connects its control gate 236 to (and in some cases, forms) a word line 202.

[0060] A column of memory cells 208 may be a NAND string 206 or several NAND strings 206 selectively connected to a given word line 204. A row of memory cells 208 may be memory cells 208 commonly connected to a given word line 202. A row of memory cells 208 may (but may not) contain all memory cells 208 commonly connected to a given word line 202. A row of memory cells 208 may typically be divided into one or more groups of physical pages of memory cells 208, and a physical page of memory cells 208 typically contains every other memory cell 208 commonly connected to a given word line 202. For example, commonly connected to word line 202... NFurthermore, memory cells 208 selectively connected to even-numbered bit lines 204 (e.g., bit lines 2040, 2042, 2044, etc.) can be a physical page of memory cell 208 (e.g., an even-numbered memory cell), while those commonly connected to word line 202 N Furthermore, the memory cell 208 selectively connected to the odd bit line 204 (e.g., bit line 2041, 2043, 2045, etc.) can be another physical page of the memory cell 208 (e.g., the odd memory cell).

[0061] Although Figure 2 Bit lines 2043-2045 are not explicitly depicted in the figure, but it is evident from the figure that bit line 204 of the memory cell array 200A can be connected from bit line 2040 to bit line 204. M Sequential numbering. Other groups of memory cells 208 commonly connected to a given word line 202 may also define physical pages of memory cells 208. For some memory devices, all memory cells commonly connected to a given word line may be considered physical pages of the memory cells. A portion of a physical page of a memory cell (in some embodiments, it may still be an entire row) that is read during a single read operation or programmed during a single programmable operation (e.g., the upper or lower page of the memory cell) may be considered a logical page of the memory cell. A block of memory cells may contain those memory cells configured to be erased together, such as those connected to word lines 2020-202. N All memory cells (e.g., all NAND strings 206 sharing a common word line 202). Unless explicitly distinguished, a reference to a page of a memory cell herein refers to the memory cell of the logical page of the memory cell. This is in conjunction with the discussion of NAND flash memory. Figure 2 Examples are provided, but the embodiments and concepts described herein are not limited to a particular array architecture or structure and may include other structures (e.g., SONOS, phase-change, ferroelectric, etc.) and other architectures (e.g., AND arrays, NOR arrays, etc.).

[0062] Figure 3 This is a schematic diagram of two segments of a memory cell array 300A comprising four sub-blocks, according to at least some embodiments. In some embodiments, the memory cell array 300A is included in an SLC cache 145 of the memory device 130. For example, in a segmented SGS (or SSGS) architecture, strings of memory cells may be divided into sub-blocks, wherein in some embodiments, each SGS segment contains two sub-blocks. A first (e.g., selected) SGS segment may include a first sub-block 3050 and a second sub-block 3051. A second (e.g., unselected) SGS segment may include a third sub-block 3052 and a fourth sub-block 3053. In other embodiments, other numbers of sub-blocks may be included in the segment.

[0063] Specifically, in at least some embodiments, Figure 3 The memory cell array 300A includes bit lines 304, with each sub-block coupled to bit lines 304. A first sub-block 3050 (assumed to be a selected sub-block for ease of explanation) may include a first drain-select (SGD) transistor 3120, a first source-select (SGS) transistor 3100, and a first memory cell string 3060 coupled therebetween. A second sub-block 3051 may include a second SGD transistor 3121, a second SGS transistor 3101, and a second memory cell string 3061 coupled therebetween. A third sub-block 3052 may include a third SGD transistor 3122, a third SGS transistor 3102, and a third memory cell string 3062 coupled therebetween. A fourth sub-block 3053 may include a fourth SGD transistor 3123, a fourth SGS transistor 3103, and a fourth memory cell string 3063 coupled therebetween. For example, a third memory cell string 3062 contained in an unselected SGS segment may contain multiple memory cells 3080…308… N Each SGS transistor can be connected to a common source (SRC), such as a source voltage line, to supply power to multiple memory cells 3080…308. N The source provides a voltage. In some embodiments, the source voltage line includes a source plate that provides the source voltage. In at least some embodiments, a plurality of word lines (WL) are coupled to the gate of the memory cell of each memory cell string 3060…3063. Each memory cell string may include a channel (not shown) coupled between the SGS transistor and SGD transistor of the sub-block.

[0064] In these embodiments, a first drain select gate line (SGD0) can be connected to the gate of a first SGD transistor 3120, a second drain select gate line (SGD1) can be connected to the gate of a second SGD transistor 3121, a third drain select gate line (SGD2) can be connected to the gate of a third SGD transistor 3122, and a fourth drain select gate line (SGD3) can be connected to the gate of a fourth SGD transistor 3123. Additionally, a first source select gate line (SGS0) can be connected to the gates of a first SGS transistor 3100 and a second SGS transistor 3101. Furthermore, a second source select gate line (SGS1) can be connected to the gates of a third SGS transistor 3102 and a fourth SGS transistor 3103. Therefore, the source voltage of each memory cell string can be jointly controlled by the source select gate line (SGS0 or SGS1) of a separate segment, wherein the first segment is a combination of a first sub-block 3050 and a second sub-block 3051, and the second segment is a combination of a third sub-block 3052 and a fourth sub-block 3053.

[0065] Figure 4This is a block diagram illustrating a memory subsystem 430 with a page buffer according to some embodiments of the present disclosure. The page buffer includes registers from which a subset of blocks of a memory array configured as a single-level cell (SLC) memory is programmed. In one embodiment, a memory interface 113 is operatively coupled to a memory device 130. In one embodiment, the memory device 130 includes a page buffer 152 and a memory array 150. The memory array 150 may include word lines formed, for example, on word line 452 and, for example, on... Figure 2 and Figure 3 The 204 mentioned in the document M Or an array of memory cells at the intersection of 304 bit lines. As discussed, these memory cells can be configured as SLC memory and are therefore contained within SLC cache 145.

[0066] In one embodiment, memory cells are grouped into blocks, which can be further divided into sub-blocks, where a given word line, for example, word line 452, is shared across multiple sub-blocks 4050, 4051, 4052, 4053. In one embodiment, each sub-block corresponds to a separate plane in memory array 150. A group of memory cells associated with a word line within a sub-block is called a physical page. Each physical page in one of the sub-blocks can be one of several page types. For example, a physical page formed by a single-level cell (SLC) has a single page type called a lower logical page (LP). A multi-level cell (MLC) physical page type may include LP and upper logical page (UP), a TLC physical page type is LP, UP, and additional logical page (XP), and a QLC physical page type is LP, UP, XP, and top logical page (TP). In some embodiments, a physical page formed by memory cells of the QLC memory type may have a total of four logical pages, where each logical page may store data different from the data stored in other logical pages associated with that physical page.

[0067] Depending on the programming scheme used, each logical page of the memory cell can be programmed in a separate programming pass, or multiple logical pages can be programmed together. For example, in a QLC physical page, LP can be programmed in one pass, and UP, XP, and TP can be programmed in a second pass. Other programming schemes are also possible. Page buffer 152 is used to temporarily store data being read from or written to the memory array 150 of memory device 130, and may include cache register 442 and one or more data registers 4440-444. N For read operations, data is read from memory array 150 into data registers 4440-444. NThe data is then read into cache register 442. Memory interface 113 can then read data from cache register 442. For programming operations, memory interface 113 writes data into cache register 442, which is then transferred to data registers 4440-444. N One of them is ultimately programmed into memory array 250. In at least some embodiments, cache register 442 and one or more data registers 4440-444 are included. N Configured as SLC memory, and therefore, the disclosed embodiments are equally applicable to these registers in the programming page buffer 152. If the programming operation involves multiple pages (e.g., UP, XP, and TP), each page may have a dedicated data register to hold the data for that page. (Refer to...) Figure 6A-8B The functionality of the parallel programmer 138 shown in Figure 1 will be discussed in more detail.

[0068] Figure 5A These are a pair of diagrams illustrating the programming of multiple data pages into a set of sub-blocks within certain memory devices configured as SLC memory. For example, a sub-block set can be understood as, for instance, as shown in the reference... Figure 1B-4 The sub-block sets described and discussed. At the top, the Ready-to-Buy (RB#) signal is described. When the Ready-to-Buy signal is pulsed high, the LUN (e.g., die) containing the sub-block is busy, and data is being loaded from controller 115 into page buffer 152 (e.g., cache register 442). When the Ready-to-Buy signal is pulsed low, the LUN transitions to a ready state and can proceed with the programming operation of programming buffered data into memory cell array 150. As previously discussed, in some embodiments, the programming operation may include a sub-block of programming data into SLC cache 145.

[0069] As can be observed, in some memory devices, programming performed by the memory device (e.g., by the control logic of the local media controller) causes a regular transition between operations that load page data and operations that program the page data into sub-blocks. For example, for a set of sub-blocks such as SB0, SB1, SB2, SB3, the first page is loaded, the first page is programmed into the first sub-block (SB0), the second page is loaded, the second page is programmed into the second sub-block (SB1), and so on. During each programming operation to different sub-blocks, as illustrated in the diagram at the bottom, a programming pulse is generated to program the sub-block, followed by a separate programming verification operation to verify the threshold voltage of the programmed cell of that sub-block. As discussed, performing these programming and programming verification operations sequentially twice in this way can cause execution delays.

[0070] Figure 5B This is a flowchart of sequential operation 502, typically performed in some memory devices to program multiple data pages into a sub-block set. As a result... Figure 5A An extension of the explanation, Figure 5B The flowchart illustrates a series of operations constituting each programming operation for programming data into the SLC memory and verifying the programmed data. For example, for the operation of programming data pages into each sub-block, this series of operations includes, but is not limited to, at operation 510, performing a programming start (or other initialization); at operation 520, seeding or pre-adjusting the voltage level of the memory cells in the sub-block for programming; at operation 530, sending a programming pulse to perform the actual programming of the data page; at operation 540, performing a programming verification of the threshold voltage of the memory cells in the sub-block; at operation 550, performing a check verification operation to determine the result of the programming verification and to determine that the data has been fully programmed; and at operation 560, ending the programming operation.

[0071] More specifically, inoculation operation 520 includes skewing the word line of a sub-block during preparation for programming. Additionally, the programming verification performed at operation 540 involves potentially accumulating negative potential on the word line, which must be reset before another programming can be performed on another sub-block of the word line, such as... Figure 5A As explained in the "Programming Verification" section. This slant and reset of the word line causes additional execution delays.

[0072] These operations are high-level operations because many additional operations or sub-operations related to programming and verification are also performed. For example, some of these additional operations include, in some cases, restoring word lines and bit lines to perform programming verification, and then, in other cases, after programming verification or at the end of programming, such as at operation 560, restoring word lines and bit lines as part of the restoration. As discussed, performing these programming and programming verification operations sequentially twice (to program, for example, all four sub-blocks SB0, SB1, SB2, and SB3) can cause execution delays.

[0073] Figure 6A These are a pair of diagrams illustrating, according to some embodiments, the programming of multiple data pages into a set of sub-blocks in a current memory device configured as SLC memory. These diagrams can be compared... Figure 5A The diagram illustrates the operations that can be performed or guided by the SLC programmer 138 of the local media controller 135 (also referred to herein as control logic). As a first point of comparison, according to at least some embodiments, the loading of all data pages (e.g., by way of example, the first, second, third, and fourth pages) is performed in advance before actual programming occurs. This allows for binding a ready busy signal (RB#) (to load data pages) during a short intermediate period, followed by a longer period during which the memory device 130 programs the loaded data pages into the corresponding sub-blocks (SB0, SB1, SB2, SB3) in the sub-block set, as illustrated in the bottom diagram.

[0074] In at least some embodiments, the “pre-processing” operations performed before the first sub-block (SB0) in the programming sub-block set may include the initialization of the charge pump and other analog hardware to be used when programming the sub-block set. The charge pump will enable the bit lines, word lines, and source voltage lines to be ramped to the target voltage that can be used for programming. However, as illustrated, complete pre-conditioning of subsequent programmed sub-blocks is avoided when programming verification is not required.

[0075] Also refer to the chart at the bottom, and further from... Figure 5A The efficiency improvements in the operation have eliminated the intermediate "programming verification" operation, allowing for the execution of four sequential programming operations to a sub-block set solely through a reduced-inoculation operation. The reduced-inoculation operation can be understood as a pre-conditioning of the cells of the next sub-block to be programmed, but because programming verification is not performed, there is no need to remove potential negative potentials from the word line. Because negative potentials do not accumulate on the word line, there is no need to reset the word line potential between programming operations to the corresponding sub-blocks, thus providing significant execution simplification.

[0076] For further reference Figure 6B Alternatively, after programming multiple data pages into sub-block sets (e.g., SB0, SB1, SB2, SB3), programming verification is selectively performed on the sub-block sets. More specifically, this programming verification is a special version of the programming verification because, while each sub-block set is in a programmed state, the programming verification is actually performed only on the memory cells of the sub-block set. For example, the programming verification is performed on the sub-block sets in parallel only if a programmed state (e.g., depending on the implementation, it could be a "0" value or a "1" value) is stored in each sub-block set. Therefore, if any sub-block in the sub-block set remains in an erased state, then no programming verification is performed on the sub-block set. This behavior of the control logic skipping the programming verification is at least because performing programming verification on memory cells in an erased state can cause the memory cells to discharge through connected bit lines (or common source lines), potentially resulting in a false failure of the programming verification.

[0077] In other words, in these embodiments, no intermediate programming verification is performed between completing the programming of one sub-block and initiating the programming of the next sub-block. In another instance, no additional programming verification is performed after initiating the programming of a sub-block and before performing a single programming verification.

[0078] In at least some embodiments, as a final operation, the control logic causes a check and verification operation to be performed on the subset after a selective programming verification that determines whether the programming operation was successfully completed. The check and verification operation may determine the result of the programming verification and determine that multiple data pages have been fully programmed. The control logic may also cause the programming operation on the subset to exit in response to passing the check and verification operation, or cause a scan of the subset to be performed in response to failing the check and verification operation.

[0079] Figure 6B This is a flowchart of sequential operation 600 performed in a current memory device to program multiple data pages into a sub-block set, according to some embodiments. Sequential operation 600 may be performed by processing logic that may include hardware (e.g., processing means, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions running or executed on a processing means), or a combination thereof. In some embodiments, by Figure 1A-1B The SLC programmer 138 performs sequential operation 600.

[0080] As a response Figure 6A An extension of the explanation, Figure 6B Flowchart Explanation Reference Figure 5A Some of the operations discussed may be performed only once for a set of sub-blocks, and simplified programming of multiple pages into multiple sub-blocks may be performed between the execution of these other operations. More specifically, according to at least some embodiments, operations that do not need to be executed multiple times include operations 610, 620, 640, 650 and 660 discussed below.

[0081] At operation 610, the processing logic performs initialization of the subset of blocks used for programming. For example, this initialization can be referenced... Figure 6A The discussion includes, for example, the initialization of charge pumps and other programming hardware for the subset.

[0082] At operation 620, the processing logic guides the execution of a seeding operation on the sub-block set to pre-adjust the voltage levels of the memory cells (e.g., word lines and bit lines) of the sub-block set in preparation for programming.

[0083] At operation 630A, the processing logic triggers a programming pulse that programs the first page of a plurality of pages into the first sub-block (e.g., SB0) of the sub-block set. Operation 630A may also include processing logic that causes a recovery operation to be performed at the first sub-block.

[0084] At operation 630B, the processing logic causes a reduced inoculation operation to be performed at the second sub-block (e.g., SB1) of the sub-block set for programming. In these embodiments, the reduced inoculation operation takes a shorter time than the time required to pre-adjust the first sub-block. The processing logic further causes a programming pulse to be sent to the second sub-block to program the second page of a plurality of data pages into the third sub-block. The processing logic further causes a recovery operation to be performed at the second sub-block.

[0085] At operation 630C, the processing logic causes a reduced inoculation operation to be performed at the third sub-block (e.g., SB2) in the sub-block set for programming. In these embodiments, the reduced inoculation operation takes a shorter time than the time spent pre-adjusting the first sub-block. The processing logic further causes a programming pulse to be sent to the third sub-block to program the third page of a plurality of data pages into the third sub-block. The processing logic further causes a recovery operation to be performed at the third sub-block.

[0086] At operation 630D, the processing logic causes a reduced inoculation operation to be performed at the fourth sub-block (e.g., SB3) in the sub-block set for programming. In these embodiments, the reduced inoculation operation takes a shorter time than the time spent pre-adjusting the first sub-block. The processing logic further causes a programming pulse to be sent to the fourth sub-block to program the fourth page of a plurality of data pages. The processing logic further causes a recovery operation to be performed at the fourth sub-block.

[0087] At operation 640, after multiple data pages are programmed, for example, after all multiple data pages are programmed into all sub-blocks of multiple sub-blocks, the processing logic selectively causes a programming check to be performed on the memory cells of the sub-block set. As previously discussed, selectively causing the programming check to be performed may include performing a single programming check on all sub-block sets together after each sub-block set is in a programmed state.

[0088] In other words, in these embodiments, no intermediate programming verification is performed between completing the programming of one sub-block and initiating the programming of the next sub-block. In another instance, no additional programming verification is performed after initiating the programming of a sub-block and before performing a single programming verification.

[0089] At operation 650, the processing logic causes a check and verification operation to be performed at the sub-block set to determine the result of the programming verification (performed at operation 640) and to determine that the data page has been fully programmed.

[0090] At operation 660, the processing logic terminates the programming operation to include any final recovery operation of the word lines and / or bit lines of the sub-block set. The processing logic also exits the programming operation of the sub-block set in response to a verification operation that passes, or causes a scan of the sub-block set to be performed in response to a verification operation that fails.

[0091] As explained and discussed previously, incorporating programming into sequential programming operations, avoiding repetitive operations 610, 620, 640, 650, and 660, and avoiding additional word line voltage resets involved in programming verification operations, all of these can significantly improve the performance of memory device 130 by eliminating or shortening operations that would otherwise cause execution delays.

[0092] Figure 7 It is a graph showing the waveforms of the drain select line (SGD) and selected word line (SEL WL) of a plurality of SLC-based sub-blocks according to at least one embodiment, including a reference. Figures 6A-6B The embodiments described and discussed herein. As can be observed, the sequential programming of the four sub-blocks (SB0, SB1, SB2, and SB3) occurs rapidly and sequentially within minimal recovery and without programming verification. Finally, programming verification (PVFY) is performed in parallel for all four sub-blocks, for example, where the selected word line voltage becomes negative and the global drain selection line of the corresponding sub-block (e.g., SGD0, SGD1, SGD2, SGD3, etc.) is asserted. Figure 3 Each of the items described herein.

[0093] Figures 8A-8B This is a flowchart of an example method 800 for programming a memory cell configured as an SLC memory according to some embodiments. Method 800 can be executed by processing logic, which may include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, by Figure 1A-1B The SLC programmer 138 performs sequential operations 800. Although shown in a specific order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0094] At operation 810, data pages are loaded. More specifically, the processing logic causes multiple data pages to be loaded into the page buffer of the memory device. This page buffer may be referenced. Figure 1A-4 Page buffer 152 is discussed. In various implementations, operation 810 is optional (and is therefore illustrated with dashed lines) because data pages can be loaded into other caches or streamed directly from different data sources.

[0095] At operation 820, the programming hardware is initialized. More specifically, the processing logic causes the hardware initialization of multiple programmable sub-blocks within a memory cell array configured as a single-level cell memory. In some embodiments, operation 820 is the earlier mentioned ( Figures 6A-6B The "prelude" to ).

[0096] At operation 830, the first subblock is pre-tuned. More specifically, the processing logic causes the first subblock in the pre-tuned subblock set to be used for programming operations. This can be understood as the voltage level of the memory cells of the seeded or pre-tuned subblock being used for programming, such as the voltage levels of the seeded or pre-tuned word lines and / or bit lines.

[0097] At operation 840, multiple data pages are programmed. More specifically, the processing logic causes these multiple data pages to be programmed into corresponding sub-sets within a sub-block set. This can be executed repeatedly. Figure 8B The operation is to program each sub-block in the sub-block set sequentially before performing programming verification.

[0098] At operation 850, programming verification is performed on all sub-blocks. More specifically, after programming multiple data pages into the sub-block set, the processing logic selectively causes programming verification to be performed on the memory cells of the sub-block set. In some embodiments, selectively causing programming verification includes performing programming verification on all sub-block sets together after each sub-block set is in a programmed state.

[0099] Executable Figure 8B The methods 800 described herein, operations 855 to 890, are for programming multiple pages into corresponding sub-blocks in a set of sub-blocks, and are therefore an extension of operation 840. At operation 855, the first sub-block is programmed. More specifically, the processing logic causes a programming pulse to be sent to the first sub-block to program the first page of the multiple data pages into the first sub-block.

[0100] At operation 860, the first sub-block is restored. More specifically, the processing logic causes a restore operation to be performed at the first sub-block, such as discharging the word line.

[0101] At operation 870, a reduced vaccination operation is performed. More specifically, the processing logic causes a pre-tuning of the second sub-block for the programmed reduced vaccination operation to be performed at the second sub-block in the sub-block set. In some embodiments, the reduced vaccination operation takes a shorter time than the time spent pre-tuning the first sub-block.

[0102] At operation 875, a programming pulse is sent. More specifically, the processing logic causes a programming pulse to be sent to the second sub-block to program the second page of the data page set into the second sub-block.

[0103] At operation 880, the second subblock is restored. More specifically, the processing logic causes a restore operation to be performed at the second subblock, such as discharging the word line.

[0104] At operation 885, another page is programmed. More specifically, the processing logic determines whether there is another subsequent data page to be programmed (e.g., the third page, the fourth page, and so on). If another page exists, then at operation 890, the processing logic repeats operations 870, 875, 880, and 885 to program the next data page into a subset, for example, programming the remainder of multiple data pages into a subset. Otherwise, if at operation 885, there are no more pages to be programmed related to the programming operations of multiple data pages, then method 800 reverts to... Figure 8A Operation 850 in the middle is used to complete the programming verification.

[0105] Although not referenced Figures 8A-8B Specific explanations or discussions will be provided, but references can still be used. Figure 6B Operations 650 and 660 are discussed. Additionally, operations discussed in this article but not referenced can still be performed. Figures 8A-8B Other operations discussed in detail can be performed simply by performing programming verification after each sub-block in the data page programming sub-block set according to operations 840 and 850. Furthermore, the embodiments illustrated and described throughout the figures are compatible with cache programming and therefore still utilize the efficiency of cache programming.

[0106] Figure 9 An example machine is described as a computer system 900, within which a set of instructions is executable for causing the machine to perform any or more of the methods discussed herein. In some embodiments, the computer system 900 may correspond to a host system (e.g., Figure 1A The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1A The memory subsystem 110) or can be used to perform controller operations (e.g., to execute an operating system to perform operations corresponding to...). Figure 1A (Operation of the cache manager 111 and / or SLC programmer 138). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, operating at the capacity of a server or client machine in a client-server network environment.

[0107] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network appliance, server, network router, switch, or bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions specifying actions to be taken by the machine. Furthermore, although a single machine is described, the term "machine" should also be understood to include any set of machines that individually or collectively execute one or more sets of instructions to perform any one or more of the methods discussed herein.

[0108] The example computer system 900 includes a processing device 902, a main memory 904 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 906 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 918, which communicate with each other via a bus 930.

[0109] Processing device 902 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a combination of instruction sets. Processing device 902 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, or the like. Processing device 902 is configured to execute instructions 926 for performing the operations and steps discussed herein. Computer system 900 may additionally include a network interface device 908 for communication on network 920.

[0110] Data storage system 918 may include machine-readable storage medium 924 (also referred to as computer-readable medium, such as non-transitory computer-readable medium) storing one or more instruction sets 926 or software embodying any or more of the methods or functions described herein. Instructions 926 may also reside wholly or at least partially in main memory 904 and / or processing device 902 during execution by computer system 900, which also constitute machine-readable storage medium. Machine-readable storage medium 924, data storage device 918, and / or main memory 904 may correspond to... Figure 1A The memory subsystem 110.

[0111] In one embodiment, instruction 926 includes implementing the corresponding Figure 1AThe cache manager 111 and / or SLC programmer 138 provide functional instructions. Although the machine-readable storage medium 924 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more of the methods of this disclosure. The term "machine-readable storage medium" should therefore be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0112] Some parts of the previously described algorithms and symbolic representations of operations on data bits within computer memory have been presented. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. In this document, and generally in general, an algorithm is conceived as a self-consistent sequence of operations that produce a desired result. An operation is an operation that requires physical manipulation of a physical quantity. Typically (but not always), these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has been shown that it is sometimes convenient to refer to these signals as bits, values, elements, symbols, characters, items, numbers, etc., primarily for common use.

[0113] However, it should be remembered that all these and similar terms will be associated with appropriate physical quantities and are merely convenient notations for application to those quantities. This disclosure can refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities in the registers and memories of a computer system into other data similarly represented as physical quantities in the computer system's memory or registers or other such information storage systems.

[0114] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for the desired purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such computer programs may be stored in computer-readable storage media (e.g., non-transitory computer-readable storage media), such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0115] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may prove convenient to construct more specialized devices to perform the methods described herein. The structures of various such systems will be presented as illustrated in the description below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0116] This disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon for programming a computer system (or other electronic device) to perform processes according to this disclosure. Machine-readable media includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, machine-readable (e.g., computer-readable) media includes machine-readable (e.g., computer-readable) storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0117] In the foregoing description, embodiments of this disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to this disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. A memory device comprising: A memory cell array configured as a single-level cell memory; and Control logic, which is operatively coupled to the memory cell array, performs operations including the following: This causes the hardware initialization of multiple programmable sub-blocks within the memory cell array; This causes the first sub-block of the plurality of sub-blocks to be pre-adjusted for programming operations; This causes multiple data pages to be programmed into corresponding sub-blocks within the multiple sub-blocks, including: (i) Causes a programming pulse that programs the first of the plurality of data pages into the first sub-block to be sent to the first sub-block; (ii) causing a recovery operation to be performed at the first sub-block; and (iii) Causing the pre-adjustment of the second sub-block for a programmed reduced inoculation operation to be performed at the second sub-block of the plurality of sub-blocks; and After programming the plurality of data pages, programming verification is selectively performed on the memory cells of the plurality of sub-blocks.

2. The memory device of claim 1, wherein selectively causing the execution of the programming verification comprises performing a single programming verification on all of the plurality of sub-blocks together after each of the plurality of sub-blocks is in a programmed state.

3. The memory device of claim 1, wherein the operation further includes causing the plurality of data pages to be loaded into a page buffer prior to performing the hardware initialization.

4. The memory device of claim 1, wherein the time period for the reduced inoculation operation is shorter than the time period for pre-adjusting the first sub-block.

5. The memory device of claim 1, wherein causing the programming of the plurality of data pages further comprises: (iv) Cause a programming pulse that programs the second page of the plurality of data pages into the second sub-block to be sent to the second sub-block; (v) Causes a recovery operation to be performed at the second sub-block; and Repeat (iii) to (v) to program the remaining portions of the plurality of data pages into the plurality of sub-blocks.

6. The memory device of claim 1, wherein the operation further comprises: This causes a check and verification operation to be performed at the multiple sub-blocks to determine the result of the programming verification and to determine that the data page has been fully programmed. The programming operation that exits the plurality of sub-blocks in response to the verification operation; and In response to failure of the verification operation, the scanning of the plurality of sub-blocks is performed.

7. A method for a memory device, comprising: The control logic of the memory device causes the hardware initialization of multiple programmable sub-blocks within the memory cell array configured as a single-level cell memory. The control logic causes the first sub-block of the plurality of sub-blocks to be pre-adjusted for programming operations; The control logic causes multiple data pages to be programmed into corresponding sub-blocks within the multiple sub-blocks, including... (i) Causes a programming pulse that programs the first of the plurality of data pages into the first sub-block to be sent to the first sub-block; (ii) Causes a recovery operation to be performed at the first sub-block; and (iii) Cause the pre-adjustment of the second sub-block for programming of the reduced inoculation operation to be performed at the second sub-block of the plurality of sub-blocks; and After programming the plurality of data pages, the control logic selectively causes programming verification to be performed on the memory cells of the plurality of sub-blocks.

8. The method of claim 7, wherein selectively causing the execution of the programming verification comprises performing a single programming verification on all of the plurality of sub-blocks together after each of the plurality of sub-blocks is in a programmed state.

9. The method of claim 7, further comprising causing the plurality of data pages to be loaded into a page buffer prior to performing the hardware initialization.

10. The method of claim 7, wherein the time period for the reduced vaccination operation is shorter than the time period for pre-adjusting the first sub-block.

11. The method of claim 7, wherein causing the programming of the plurality of data pages further comprises: (iv) Cause a programming pulse that programs the second page of the plurality of data pages into the second sub-block to be sent to the second sub-block; (v) Causes a recovery operation to be performed at the second sub-block; and Repeat (iii) to (v) to program the remaining portions of the plurality of data pages into the plurality of sub-blocks.

12. The method of claim 7, further comprising: This causes a check and verification operation to be performed at the multiple sub-blocks to determine the result of the programming verification and to determine that the data page has been fully programmed. The programming operation that exits the plurality of sub-blocks in response to the verification operation; and In response to failure of the verification operation, the scanning of the plurality of sub-blocks is performed.

13. An integrated circuit, comprising: At least one die includes an array of memory cells configured as a single-level cell memory; and Control logic, operatively coupled to the at least one die, performs operations including: This causes multiple data pages to be loaded into the page buffer coupled to the memory cell array; This causes the hardware initialization of multiple programmable sub-blocks within the memory cell array; This causes the first sub-block of the plurality of sub-blocks to be pre-adjusted for programming operations; Cause the plurality of data pages to be programmed into corresponding sub-blocks within the plurality of sub-blocks, which includes: (i) Causes a programming pulse that programs the first of the plurality of data pages into the first sub-block to be sent to the first sub-block; (ii) causing a recovery operation to be performed at the first sub-block; and (iii) Causing the pre-adjustment of the second sub-block for a programmed reduced inoculation operation to be performed at the second sub-block of the plurality of sub-blocks; and After programming the plurality of data pages, programming verification is selectively performed on the memory cells of the plurality of sub-blocks.

14. The integrated circuit of claim 13, wherein selectively causing the execution of the programming verification comprises performing a single programming verification on all of the plurality of sub-blocks together after each of the plurality of sub-blocks is in a programmed state.

15. The integrated circuit of claim 13, wherein the time period for the reduced inoculation operation is shorter than the time period for pre-adjusting the first sub-block.

16. The integrated circuit of claim 13, wherein causing the programming of the plurality of data pages further comprises: (iv) Cause a programming pulse that programs the second page of the plurality of data pages into the second sub-block to be sent to the second sub-block; (v) Causes a recovery operation to be performed at the second sub-block; and Repeat (iii) to (v) to program the remaining portions of the plurality of data pages into the plurality of sub-blocks.

17. The integrated circuit of claim 13, wherein the operation further comprises: This causes a check and verification operation to be performed at the multiple sub-blocks to determine the result of the programming verification and to determine that the data page has been fully programmed. The programming operation that exits the plurality of sub-blocks in response to the verification operation; and In response to failure of the verification operation, the scanning of the plurality of sub-blocks is performed.

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