Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, wherein the structure comprises: a substrate, the substrate including a first region and a second region; a first dielectric structure located on the substrate; a second etch-stop layer located on the first dielectric structure, the second etch-stop layer having a first opening therein; a second dielectric layer located within the first opening and on the second etch-stop layer; a second opening located within the first dielectric structure and the second dielectric layer; a third opening located within the second dielectric layer; a second conductive plug located within the second opening; and a third conductive plug located within the third opening. Because the metal used in the selective metal growth process is not easily diffused, a barrier layer need not be formed before forming the second and third conductive plugs. Furthermore, the second opening is an integral structure, thereby improving connectivity between the second conductive plug located within the first dielectric structure and the second conductive plug located within the second dielectric layer, thereby reducing contact resistance within the second conductive plug itself.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] During the integrated circuit (IC) manufacturing process, after the semiconductor device structure is formed, the individual semiconductor devices need to be connected together to form a circuit. With the continuous advancement of IC manufacturing technology, the requirements for IC integration and performance are becoming increasingly higher. To increase integration and reduce costs, the critical dimensions of components are continuously reduced, and the circuit density within the IC is increasing. This development has resulted in insufficient surface area on the wafer to produce the interconnects required for conventional circuits.

[0003] To meet interconnect requirements after critical dimensions have been reduced, current interconnect structures are used to connect different metal layers, or between a metal layer and a semiconductor device structure. These structures include interconnect lines and conductive plugs located within contact holes. The conductive plugs are used to connect semiconductor devices, and the interconnect lines connect the conductive plugs on different semiconductor devices, thereby forming a circuit.

[0004] However, the conductive plug in the prior art still has the problem of relatively large contact resistance during electrical connection. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, which can effectively improve the performance of the finally formed semiconductor structure.

[0006] To solve the above problems, the present invention provides a semiconductor structure, comprising: a substrate, the substrate including a first region and a second region, the substrate having a conductive layer therein, the substrate exposing a top surface of the conductive layer; a first dielectric structure located on the substrate, the first dielectric structure having a first conductive plug therein, the first dielectric structure exposing a top surface of the first conductive plug, the first conductive plug being electrically connected to a portion of the conductive layer located in the first region; a second etch-stop layer located on the first dielectric structure and the first conductive plug, the second etch-stop layer having a first opening therein, the first opening exposing a portion of the top surface of the first dielectric structure located in the second region; a second dielectric layer located in the first opening and on the second etch-stop layer; a second opening located in the first dielectric structure and the second dielectric layer located in the second region, the second opening exposing a portion of the top surface of the conductive layer located in the second region; a third opening located in the second dielectric layer located in the second etch-stop layer and the first region; a second conductive plug located in the second opening; and a third conductive plug located in the third opening.

[0007] Optionally, the method further includes: the first conductive plug includes a first portion and a second portion located on the first portion, and a width of the second portion is greater than a width of the first portion.

[0008] Optionally, the first dielectric structure includes: a first etch stop layer located on the substrate, and a first dielectric layer located on the first etch stop layer.

[0009] Optionally, a material of the first etch stop layer is different from a material of the second etch stop layer.

[0010] Optionally, the material of the first etch stop layer includes one or more of Al2O3, AlN, HfO2, Ta2O5, SiO2, SiN, SiOC, SiON, SiC and SiCN; the material of the second etch stop layer includes one or more of Al2O3, AlN, HfO2, Ta2O5, SiO2, SiN, SiOC, SiON, SiC and SiCN.

[0011] Optionally, the material of the second conductive plug includes: cobalt, ruthenium, tungsten, rhodium, iridium or tungsten-cobalt alloy.

[0012] Optionally, the material of the third conductive plug includes: cobalt, ruthenium, tungsten, rhodium, iridium or tungsten-cobalt alloy.

[0013] Optionally, the substrate includes a base and a device layer located on the base, wherein the device layer has a device structure; the conductive layer is located in the device layer, the device layer exposes the top surface of the conductive layer, and the conductive layer is electrically connected to the device structure.

[0014] Optionally, the device structure includes one or more of a transistor structure, a capacitor structure, a resistor structure and an inductor structure.

[0015] Accordingly, the technical solution of the present invention further provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a first region and a second region, the substrate having a conductive layer therein, and the substrate exposing a top surface of the conductive layer; forming a first dielectric structure on the substrate, the first dielectric structure having a first conductive plug therein, the first dielectric structure exposing a top surface of the first conductive plug, the first conductive plug being electrically connected to a portion of the conductive layer located in the first region; forming a second etch-stop layer on the first dielectric structure and the first conductive plug, the second etch-stop layer having a first opening therein, the first opening exposing a portion of the top surface of the first dielectric structure located on the second region; forming a second dielectric layer in the first opening and on the second etch-stop layer; forming a second opening in the first dielectric structure and the second dielectric layer located on the second region, and forming a second opening in the first dielectric structure and the second dielectric layer located on the first region. An initial third opening is formed in the second dielectric layer, the second opening exposes a portion of the surface of the conductive layer located in the second region, and the initial third opening exposes the surface of the second etch stop layer; a first selective metal growth process is used to form a first conductive plug material layer in the second opening, and the first conductive plug material layer does not fill the second opening; after the first conductive plug material layer is formed, the initial third opening is removed to expose the second etch stop layer to form a third opening; a second selective metal growth process is used to form a second conductive plug material layer in the second opening and in the third opening, and the second conductive plug material layer fills the second opening and the third opening respectively, a second conductive plug is formed by the first conductive plug material layer and the second conductive plug material layer located in the second opening, and a third conductive plug is formed by the second conductive plug material layer located in the third opening.

[0016] Optionally, the first conductive plug includes: a first portion, and a second portion located on the first portion, and a width of the second portion is greater than a width of the first portion.

[0017] Optionally, the first dielectric structure includes: a first etch stop layer located on the substrate, and a first dielectric layer located on the first etch stop layer.

[0018] Optionally, a material of the first etch stop layer is different from a material of the second etch stop layer.

[0019] Optionally, the material of the first etch stop layer includes one or more of Al2O3, AlN, HfO2, Ta2O5, SiO2, SiN, SiOC, SiON, SiC and SiCN; the material of the second etch stop layer includes one or more of Al2O3, AlN, HfO2, Ta2O5, SiO2, SiN, SiOC, SiON, SiC and SiCN.

[0020] Optionally, the method for forming a second opening in the first dielectric structure and the second dielectric layer located on the second area, and forming an initial third opening in the second dielectric layer located on the first area includes: using a first etching process to remove part of the first dielectric layer and the second dielectric layer until the second etch-stop layer and the first etch-stop layer are exposed, thereby forming an initial second opening in the first dielectric structure and the second dielectric layer located on the second area, and forming the initial third opening in the second dielectric layer located on the first area; using a second etching process to remove the initial second opening to expose the first etch-stop layer until the conductive layer located in the second area is exposed, thereby forming the second opening.

[0021] Optionally, the metal material in the first selective metal growth process includes: cobalt, ruthenium, tungsten, rhodium, iridium or tungsten-cobalt alloy.

[0022] Optionally, the metal material in the second selective metal growth process includes: cobalt, ruthenium, tungsten, rhodium, iridium or tungsten-cobalt alloy.

[0023] Optionally, the substrate includes a base and a device layer located on the base, wherein the device layer has a device structure; the conductive layer is located in the device layer, the device layer exposes the top surface of the conductive layer, and the conductive layer is electrically connected to the device structure.

[0024] Optionally, the device structure includes one or more of a transistor structure, a capacitor structure, a resistor structure and an inductor structure.

[0025] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0026] In the semiconductor structure of the technical solution of the present invention, since the metal used in the selective metal growth process is not easy to diffuse, it is not necessary to form a barrier layer before forming the second conductive plug and the third conductive plug, thereby reducing the contact resistance of the second conductive plug and the third conductive plug.

[0027] In addition, the second opening is formed simultaneously in the first dielectric structure and the second dielectric layer using a single etching process, which can ensure better connectivity between the second opening in the first dielectric structure and the second opening in the second dielectric layer. This further improves connectivity between the second conductive plug in the first dielectric structure and the second conductive plug in the second dielectric layer, thereby reducing the contact resistance within the second conductive plug itself.

[0028] In the method for forming a semiconductor structure according to the technical solution of the present invention, the second conductive plug and the third conductive plug are formed using the first selective metal growth process and the second selective metal growth process. Because the metal used in the selective metal growth process is not easily diffused, a barrier layer is not required before forming the second conductive plug and the third conductive plug, thereby reducing the contact resistance of the second conductive plug and the third conductive plug.

[0029] In addition, after forming the first dielectric structure and the second dielectric layer, a single etching process is used to simultaneously form the second opening in the first dielectric structure and the second dielectric layer. This can ensure better connectivity between the second opening in the first dielectric structure and the second opening in the second dielectric layer, thereby improving connectivity between the second conductive plug in the first dielectric structure and the second conductive plug in the second dielectric layer, thereby reducing the contact resistance within the second conductive plug itself.

[0030] In addition, a first selective metal growth process is used to form a first conductive plug material layer within the second opening, with the first conductive plug material layer not completely filling the second opening. The initial third opening is removed to expose the second etch stop layer, forming a third opening. A second selective metal growth process is used to form a second conductive plug material layer within the second opening and the third opening, with the second conductive plug material layer completely filling the second opening and the third opening, respectively. The first conductive plug material layer and the second conductive plug material layer within the second opening form a second conductive plug, and the second conductive plug material layer within the third opening forms a third conductive plug. Forming the second and third conductive plugs through two selective metal growth processes avoids the problem of using a single selective metal growth process, where the third opening is first filled and then grows outward, blocking the top of the second opening and preventing the second conductive plug material layer from continuing to grow. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figures 1 to 2 It is a structural diagram of a semiconductor structure;

[0032] Figures 3 to 11 It is a schematic structural diagram of each step of an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0033] As described in the background art, the prior art conductive plug still has the problem of high contact resistance during electrical connection, which will be described in detail below with reference to the accompanying drawings.

[0034] Please refer to Figure 1 A substrate is provided, the substrate comprising a base 100 and a device layer 101 located on the base 100, the device layer 101 comprising a device structure (not shown) and an electrical interconnection layer 102 electrically connected to the device structure, and the device layer 101 exposing the surface of the electrical interconnection layer 102; a first dielectric structure 103 is formed on the substrate, the first dielectric structure 103 comprising a first contact hole (not shown), the first contact hole exposing a portion of the surface of the electrical interconnection layer 102; a first plug structure 104 is formed in the first contact hole, the first plug structure 104 comprising a first barrier layer 104a and a first metal layer 104b located on the first barrier layer 104a.

[0035] Please refer to Figure 2 A second dielectric structure 105 is formed on the first dielectric structure 103 and the first plug structure 104. The second dielectric structure 105 has a second contact hole (not shown) therein, which exposes a portion of the surface of the first plug structure 104. A second plug structure 106 is formed in the second contact hole. The second plug structure 106 includes a second barrier layer 106a and a second metal layer 106b located on the second barrier layer 106a.

[0036] In this embodiment, the first metal layer 104b and the second metal layer 106b are made of easily diffusible metal materials. Therefore, to prevent diffusion of the metal materials of the first metal layer 104b and the second metal layer 106b, the first barrier layer 104a is formed within the first contact hole, and the second barrier layer 106a is formed within the second contact hole. However, the materials used for the first barrier layer 104a and the second barrier layer 106b have high electrical resistance, resulting in high contact resistance between the first plug structure 106 and the electrical interconnect layer 102, and between the first plug structure 104 and the second plug structure 106, thereby affecting the performance of the resulting semiconductor structure.

[0037] Based on this, the present invention provides a semiconductor structure and a method for forming the same. Because the metal used in the selective metal growth process is not easily diffused, a barrier layer is not required, thereby reducing the contact resistance between the second conductive plug and the second conductive plug. Furthermore, a single etching process is used to simultaneously form a first contact hole within the first dielectric structure and the second dielectric layer, thereby improving connectivity between the second conductive plug within the first dielectric structure and the second conductive plug within the second dielectric layer, thereby reducing the contact resistance within the second conductive plug itself. Furthermore, forming the second and third conductive plugs through two selective metal growth processes effectively avoids the problem of the third opening being filled first and then overflowing with growth, thereby blocking the top of the second opening and preventing further growth of the second conductive plug material layer.

[0038] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0039] Figures 3 to 11 It is a structural schematic diagram of a formation process of a semiconductor structure according to an embodiment of the present invention.

[0040] Please refer to Figure 3 and Figure 4 , Figure 3 It is a three-dimensional diagram of the semiconductor structure. Figure 4 yes Figure 3 In the schematic cross-sectional view along line AA, a substrate is provided. The substrate includes a first region I and a second region II. A conductive layer (not labeled) is provided in the substrate, and the top surface of the conductive layer is exposed on the substrate.

[0041] In this embodiment, the substrate includes a base 200 and a device layer 201 located on the base 200, and the device layer 201 has a device structure (not shown); the conductive layer is located in the device layer 201, and the device layer 201 exposes the top surface of the conductive layer, and the conductive layer is electrically connected to the device structure.

[0042] In this embodiment, the substrate 200 is made of silicon. In other embodiments, the substrate may be made of germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium.

[0043] In this embodiment, the device structure includes one or more of a transistor structure, a capacitor structure, a resistor structure, and an inductor structure.

[0044] Please refer to Figure 5 , Figure 5 The viewing direction and Figure 4In accordance with the viewing direction, a first dielectric structure is formed on the substrate, wherein the first dielectric structure has a first conductive plug 202, and the first dielectric structure exposes the top surface of the first conductive plug 202, and the first conductive plug 202 is electrically connected to a portion of the conductive layer located in the first region I.

[0045] In this embodiment, the first dielectric structure includes: a first etch stop layer 203 located on the substrate, and a first dielectric layer 204 located on the first etch stop layer 203 .

[0046] The material of the first dielectric layer 204 is one or more of SiOCH, SiOC, SiO2, SiN and SiON. In this embodiment, the material of the first dielectric layer 204 is SiO2.

[0047] The material of the first etch stop layer 203 includes one or more of Al2O3, AlN, HfO2, Ta2O5, SiO2, SiN, SiOC, SiON, SiC and SiCN. In this embodiment, the material of the first etch stop layer 203 is Al2O3.

[0048] In this embodiment, the method further includes: forming a first mask layer (not shown) on the first dielectric structure.

[0049] The material of the first mask layer is one or more of SiO 2 , SiN, SiOC, SiON, TiN, AlN and Al 2 O 3 . In this embodiment, the first mask layer is made of SiN.

[0050] In this embodiment, the first mask layer serves as a mask layer when patterning the first dielectric structure, and protects the first dielectric layer 204 .

[0051] In this embodiment, the first conductive plug 202 includes a first portion 202a and a second portion 202b located on the first portion 202a, and a width of the second portion 202b is greater than a width of the first portion 202a.

[0052] In this embodiment, the method for forming the first conductive plug 202 includes: removing a portion of the first mask layer, the first dielectric layer 204, and the first etch stop layer 203 to form an initial conductive opening (not shown); performing a transverse etching process on a portion of the initial conductive opening to form a conductive opening (not shown); and forming the first conductive plug 202 in the conductive opening.

[0053] In this embodiment, the first conductive plug 202 includes a barrier layer, an adhesive layer on the barrier layer, and a conductive layer (not shown) on the adhesive layer.

[0054] In this embodiment, after the first conductive plug 202 is formed, the first mask layer is removed.

[0055] Please refer to Figure 6 A second etch stop layer 205 is formed on the first dielectric structure and the first conductive plug 202. The second etch stop layer 205 has a first opening 206 therein. The first opening 206 exposes a portion of the top surface of the first dielectric structure located on the second region II.

[0056] In this embodiment, the method for forming the second etch stop layer 205 includes: forming an initial second etch stop layer (not shown) on the first dielectric structure and the first conductive plug 202; and patterning the initial second etch stop layer to remove a portion of the initial second etch stop layer to form the second etch stop layer 205.

[0057] In this embodiment, the material of the first etch-stop layer 203 is different from the material of the second etch-stop layer 205. Because the second etch-stop layer 205 needs to be retained on the first conductive plug 202 before the subsequent second selective metal growth process, different materials are selected for the first etch-stop layer 201 and the second etch-stop layer 205 to reduce damage to the second etch-stop layer 205 during etching of the first etch-stop layer 203.

[0058] The material of the second etch stop layer 205 includes one or more of Al2O3, AlN, HfO2, Ta2O5, SiO2, SiN, SiOC, SiON, SiC and SiCN. In this embodiment, the material of the second etch stop layer 205 is SiN.

[0059] In this embodiment, the process of removing part of the initial second etch stop layer adopts a dry etching process; in other embodiments, the process of removing part of the initial second etch stop layer may also adopt a wet etching process.

[0060] Please refer to Figure 7 After forming the second etch stop layer 205 , a second dielectric layer 207 is formed in the first opening 206 and on the second etch stop layer 205 .

[0061] In this embodiment, the material of the second dielectric layer 207 is one or more of SiOCH, SiOC, SiO2, SiN and SiON. In this embodiment, the material of the second dielectric layer 207 is SiO2.

[0062] In this embodiment, the method further includes forming a second mask layer 208 on the second dielectric layer 207 .

[0063] The material of the second mask layer 208 is one or more of SiO 2 , SiN, SiOC, SiON, TiN, AlN, and Al 2 O 3 . In this embodiment, the second mask layer 208 is made of SiN.

[0064] In this embodiment, the second mask layer 208 serves as a mask layer when patterning the second dielectric layer 207 , thereby protecting the second dielectric layer 207 .

[0065] Please refer to Figure 8 A second opening 209 is formed in the first dielectric structure and the second dielectric layer 207 located on the second region II, and an initial third opening 210 is formed in the second dielectric layer 207 located on the first region I. The second opening 207 exposes a portion of the surface of the conductive layer located in the second region II, and the initial third opening 210 exposes the surface of the second etch stop layer 205.

[0066] In this embodiment, after the first dielectric structure and the second dielectric layer 207 are formed, a single etching process is used to simultaneously form the second opening 209 in the first dielectric structure and the second dielectric layer 207. This ensures better connectivity between the second opening 209 in the first dielectric structure and the second opening 209 in the second dielectric layer 207. This further improves connectivity between a subsequent second conductive plug in the first dielectric structure and a second conductive plug in the second dielectric layer 207, thereby reducing contact resistance within the second conductive plug itself.

[0067] In this embodiment, the method for forming the second opening 209 in the first dielectric structure and the second dielectric layer 207 located in the second region II, and forming the initial third opening 210 in the second dielectric layer 207 located in the first region I includes: using a first etching process to remove a portion of the first dielectric layer 204 and the second dielectric layer 207 until the second etch-stop layer 205 and the first etch-stop layer 203 are exposed, thereby forming an initial second opening (not shown) in the first dielectric structure and the second dielectric layer 207 located in the second region II, and forming the initial third opening 210 in the second dielectric layer 207 located in the first region I; and using a second etching process to remove the initial second opening to expose the first etch-stop layer 203 until the conductive layer located in the second region II is exposed, thereby forming the second opening 209.

[0068] In this embodiment, the first etching process adopts a dry etching process; in other embodiments, the first etching process may also adopt a wet etching process.

[0069] In this embodiment, the second etching process adopts a dry etching process; in other embodiments, the second etching process may also adopt a wet etching process.

[0070] Please refer to Figure 9 A first selective metal growth process is used to form a first conductive plug material layer 211 in the second opening 209 , and the first conductive plug material layer 211 does not completely fill the second opening 209 .

[0071] The metal material in the first selective metal growth process includes: cobalt, ruthenium, tungsten, rhodium, iridium or tungsten-cobalt alloy. In this embodiment, the metal material in the first selective metal growth process is tungsten.

[0072] Please refer to Figure 10 After forming the first conductive plug material layer 211 , the initial third opening 210 is removed to expose the second etch stop layer 205 , thereby forming a third opening 212 .

[0073] In this embodiment, the etching process for removing the initial third opening 210 to expose the second etch stop layer 207 is a dry etching process; in other embodiments, the etching process for removing the initial third opening to expose the second etch stop layer may also be a wet etching process.

[0074] Please refer to Figure 11, a second selective metal growth process is used to form a second conductive plug material layer 213 in the second opening 209 and in the third opening 212, and the second conductive plug material layer 213 fills the second opening 209 and the third opening 212 respectively. A second conductive plug is formed by the first conductive plug material layer 211 and the second conductive plug material layer 213 in the second opening 209, and a third conductive plug is formed by the second conductive plug material layer 213 in the third opening 212.

[0075] In this embodiment, the second conductive plug and the third conductive plug are formed using the first selective metal growth process and the second selective metal growth process. Because the metal used in the selective metal growth process is not easily diffused, a barrier layer is not required before forming the second conductive plug and the third conductive plug, thereby reducing the contact resistance of the second conductive plug and the third conductive plug.

[0076] In addition, the second conductive plug and the third conductive plug are formed by two selective metal growth processes, thereby avoiding the problem that when a single selective metal growth process is used, the third opening 212 is first filled and then overflows and grows to the surrounding area, and the top of the second opening 209 is blocked, making it impossible for the second conductive plug material layer 213 to continue to grow.

[0077] The metal material in the second selective metal growth process includes: cobalt, ruthenium, tungsten, rhodium, iridium or tungsten-cobalt alloy. In this embodiment, the metal material in the second selective metal growth process is tungsten.

[0078] In this embodiment, the second conductive plug material layer 213 formed by the second selective metal growth process is also located on the surface of the second mask layer 208; after the second selective metal growth process, the second conductive plug material layer 213 is planarized until the top surface of the second dielectric layer 207 is exposed.

[0079] Therefore, during the planarization process of the second conductive plug material layer 213 , the second mask layer 208 is also removed, which effectively simplifies the process and improves production efficiency.

[0080] In this embodiment, the planarization process adopts a chemical mechanical polishing process.

[0081] Accordingly, an embodiment of the present invention further provides a semiconductor structure, please continue to refer to Figure 11, comprising: a substrate, the substrate comprising a first region I and a second region II, the substrate having a conductive layer therein, and the substrate exposing a top surface of the conductive layer; a first dielectric structure located on the substrate, the first dielectric structure having a first conductive plug 202 therein, the first dielectric structure exposing a top surface of the first conductive plug 202, the first conductive plug 202 being electrically connected to a portion of the conductive layer located in the first region I; a second etch stop layer 205 located on the first dielectric structure and the first conductive plug 202, the second etch stop layer 205 having a first opening 206 therein, the first opening 206 exposing The top surface of the conductive layer in the second region II is exposed by the etching process, and the top surface of the conductive layer in the second region II is exposed by the etching process. The conductive layer in the second region II is exposed by the etching process, and the top surface of the conductive layer in the second region II is exposed by the etching process. The conductive layer in the second region I is exposed by the etching process, and the top surface of the conductive layer in the second region II is exposed by the etching process.

[0082] In this embodiment, the first conductive plug 202 further includes a first portion 202a and a second portion 202b located on the first portion 202a, and a width of the second portion 202b is greater than a width of the first portion 202a.

[0083] In this embodiment, the first dielectric structure includes: a first etch stop layer 203 located on the substrate, and a first dielectric layer 204 located on the first etch stop layer 203 .

[0084] In this embodiment, the material of the first etch stop layer 203 is different from the material of the second etch stop layer 205 .

[0085] The material of the first etch stop layer 203 includes: one or more of Al2O3, AlN, HfO2, Ta2O5, SiO2, SiN, SiOC, SiON, SiC and SiCN; in this embodiment, the material of the first etch stop layer 203 is Al2O3.

[0086] The material of the second etch stop layer 205 includes one or more of Al2O3, AlN, HfO2, Ta2O5, SiO2, SiN, SiOC, SiON, SiC and SiCN. In this embodiment, the material of the first etch stop layer 205 is SiN.

[0087] The material of the second conductive plug includes: cobalt, ruthenium, tungsten, rhodium, iridium or tungsten-cobalt alloy. In this embodiment, the material of the second conductive plug is tungsten.

[0088] The material of the third conductive plug includes: cobalt, ruthenium, tungsten, rhodium, iridium or tungsten-cobalt alloy. In this embodiment, the material of the third conductive plug is tungsten.

[0089] In this embodiment, the substrate includes a base 200 and a device layer 201 located on the base 200, and the device layer 201 has a device structure; the conductive layer is located in the device layer 201, and the device layer 201 exposes the top surface of the conductive layer, and the conductive layer is electrically connected to the device structure.

[0090] In this embodiment, the device structure includes one or more of a transistor structure, a capacitor structure, a resistor structure, and an inductor structure.

[0091] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that include: a substrate, the substrate comprising a first region and a second region, the substrate having a conductive layer therein, and the substrate exposing a top surface of the conductive layer; a first dielectric structure located on the substrate, wherein the first dielectric structure has a first conductive plug therein, and the first dielectric structure exposes a top surface of the first conductive plug, and the first conductive plug is electrically connected to a portion of the conductive layer located in the first region; a second etch-stop layer located on the first dielectric structure and the first conductive plug, wherein the second etch-stop layer has a first opening therein, and the first opening exposes a portion of a top surface of the first dielectric structure located on the second region; a second dielectric layer located in the first opening and on the second etch stop layer; a second opening in the first dielectric structure and the second dielectric layer located on the second region, the second opening exposing a portion of the top surface of the conductive layer located in the second region; a third opening in the second dielectric layer located above the second etch stop layer and the first region; a second conductive plug located in the second opening; A third conductive plug is located in the third opening.

2. The semiconductor structure according to claim 1, wherein: Also includes: The first conductive plug includes a first portion and a second portion located on the first portion, and a width of the second portion is greater than a width of the first portion.

3. The semiconductor structure according to claim 1, wherein: The first dielectric structure includes: a first etch stop layer located on the substrate, and a first dielectric layer located on the first etch stop layer.

4. The semiconductor structure according to claim 3, wherein: A material of the first etch stop layer is different from a material of the second etch stop layer.

5. The semiconductor structure according to claim 4, wherein: The material of the first etch stop layer includes: one or more of Al2O3, AlN, HfO2, Ta2O5, SiO2, SiN, SiOC, SiON, SiC and SiCN; the material of the second etch stop layer includes: one or more of Al2O3, AlN, HfO2, Ta2O5, SiO2, SiN, SiOC, SiON, SiC and SiCN.

6. The semiconductor structure according to claim 1, wherein: The material of the second conductive plug includes: cobalt, ruthenium, tungsten, rhodium, iridium or tungsten-cobalt alloy.

7. The semiconductor structure according to claim 1, wherein: The material of the third conductive plug includes: cobalt, ruthenium, tungsten, rhodium, iridium or tungsten-cobalt alloy.

8. The semiconductor structure according to claim 1, wherein: The substrate includes a base and a device layer located on the base, wherein the device layer has a device structure; the conductive layer is located in the device layer, wherein the device layer exposes the top surface of the conductive layer, and the conductive layer is electrically connected to the device structure.

9. The semiconductor structure according to claim 8, wherein: The device structure includes one or more of a transistor structure, a capacitor structure, a resistor structure and an inductor structure.

10. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a first region and a second region, the substrate having a conductive layer therein, and the substrate exposing a top surface of the conductive layer; forming a first dielectric structure on the substrate, wherein the first dielectric structure has a first conductive plug therein, the first dielectric structure exposing a top surface of the first conductive plug, and the first conductive plug is electrically connected to a portion of the conductive layer located in the first region; forming a second etch stop layer on the first dielectric structure and the first conductive plug, wherein the second etch stop layer has a first opening therein, and the first opening exposes a portion of the top surface of the first dielectric structure located on the second region; forming a second dielectric layer in the first opening and on the second etch stop layer; forming a second opening in the first dielectric structure and the second dielectric layer located on the second region, and forming an initial third opening in the second dielectric layer located on the first region, wherein the second opening exposes a portion of the conductive layer surface located in the second region, and the initial third opening exposes a surface of the second etch stop layer; forming a first conductive plug material layer in the second opening by using a first selective metal growth process, wherein the first conductive plug material layer does not completely fill the second opening; After forming the first conductive plug material layer, removing the initial third opening to expose the second etch stop layer to form a third opening; A second selective metal growth process is used to form a second conductive plug material layer in the second opening and in the third opening, and the second conductive plug material layer fills the second opening and the third opening respectively. A second conductive plug is formed by the first conductive plug material layer and the second conductive plug material layer in the second opening, and a third conductive plug is formed by the second conductive plug material layer in the third opening.

11. The method for forming a semiconductor structure according to claim 10, wherein: The first conductive plug includes a first portion and a second portion located on the first portion, and a width of the second portion is greater than a width of the first portion.

12. The method for forming a semiconductor structure according to claim 10, wherein: The first dielectric structure includes: a first etch stop layer located on the substrate, and a first dielectric layer located on the first etch stop layer.

13. The method for forming a semiconductor structure according to claim 12, wherein: A material of the first etch stop layer is different from a material of the second etch stop layer.

14. The method for forming a semiconductor structure according to claim 13, wherein: The material of the first etch stop layer includes: one or more of Al2O3, AlN, HfO2, Ta2O5, SiO2, SiN, SiOC, SiON, SiC and SiCN; the material of the second etch stop layer includes: one or more of Al2O3, AlN, HfO2, Ta2O5, SiO2, SiN, SiOC, SiON, SiC and SiCN.

15. The method for forming a semiconductor structure according to claim 10, wherein: The method for forming a second opening in the first dielectric structure and the second dielectric layer located on the second area, and forming an initial third opening in the second dielectric layer located on the first area includes: using a first etching process to remove a portion of the first dielectric layer and the second dielectric layer until the second etch-stop layer and the first etch-stop layer are exposed, thereby forming an initial second opening in the first dielectric structure and the second dielectric layer located on the second area, and forming the initial third opening in the second dielectric layer located on the first area; using a second etching process to remove the initial second opening to expose the first etch-stop layer until the conductive layer located in the second area is exposed, thereby forming the second opening.

16. The method for forming a semiconductor structure according to claim 10, wherein: The metal material in the first selective metal growth process includes: cobalt, ruthenium, tungsten, rhodium, iridium or tungsten-cobalt alloy.

17. The method for forming a semiconductor structure according to claim 10, wherein: The metal material in the second selective metal growth process includes: cobalt, ruthenium, tungsten, rhodium, iridium or tungsten-cobalt alloy.

18. The method for forming a semiconductor structure according to claim 10, wherein: The substrate includes a base and a device layer located on the base, wherein the device layer has a device structure; the conductive layer is located in the device layer, wherein the device layer exposes the top surface of the conductive layer, and the conductive layer is electrically connected to the device structure.

19. The method for forming a semiconductor structure according to claim 18, wherein: The device structure includes one or more of a transistor structure, a capacitor structure, a resistor structure and an inductor structure.

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