A preparation method of a bidirectional thyristor device and a bidirectional thyristor device

Abstract

The present invention relates to a method for preparing a bidirectional thyristor (TRIAC) device and the TRIAC device, and relates to the field of semiconductor technology. The device comprises: a semiconductor material of a first conductivity type, a field oxide layer, a first well region, a second well region, a third well region, and a fourth well region of a second conductivity type, sidewall structures formed on both sides of each field oxide layer, first to third heavily doped implant regions of the first conductivity type, a dielectric layer, contact holes, photolithography of a fourth heavily doped region and a fifth heavily doped region of the second conductivity type, and metal wiring. The present invention utilizes a self-aligned process (or semi-self-aligned process) to improve the precision tolerance of the TRIAC device for FAB silicon wafer equipment, reduce equipment capacity requirements, and reduce certain layers, thereby achieving a lower trigger voltage and the same device parameters, while simultaneously optimizing the difficulty and cost of the production process.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a preparation method of a bidirectional thyristor device and the bidirectional thyristor device. Background Art

[0002] Electrostatic discharge (ESD) is typically generated by friction, collision, or electrical induction, and enters electrical equipment through human contact, contact with metal mechanical equipment, and electromagnetic fields. It is characterized by rapid discharge and high transient voltage. ESD poses a significant threat to the normal operation of integrated circuits (ICs) in electrical equipment, and in severe cases, can even burn out and render them inoperable. As integrated circuits (ICs) develop toward ultra-miniaturization, ultra-high integration, and multifunctionality, they are becoming increasingly sensitive to ESD. The economic losses caused by ESD in my country's electronics industry alone amount to hundreds of billions of yuan annually. Improving the ESD protection capabilities of integrated circuits is crucial and urgent.

[0003] A bidirectional thyristor (SCR) is a device commonly used in ESD protection. Due to its inherent positive feedback mechanism, it has the advantages of strong current discharge capability, high discharge efficiency per unit area, low on-resistance, strong robustness, and a high protection level. It can achieve a high level of electrostatic protection with a smaller chip area in semiconductor planar technology.

[0004] At present, the general bidirectional SCR structure is implemented using a lateral NPNPN structure (or PNPNP structure), such as Figure 1 As shown, lateral devices have high requirements on the size and equipment accuracy in the production process, especially the alignment accuracy between different lithography layers has a great impact on it, and it is very easy to have poor uniformity within / between silicon wafers, especially for silicon wafers below 8 inches and when the equipment capacity is insufficient. Therefore, in response to the above problems, it is necessary to design a preparation method of a bidirectional thyristor device and a bidirectional thyristor device to meet the needs of specific application scenarios. Summary of the Invention

[0005] In order to solve the above technical problems, the present invention provides a method for preparing a bidirectional thyristor device and a bidirectional thyristor device.

[0006] The technical problem solved by the present invention can be achieved by adopting the following technical solutions:

[0007] A method for preparing a bidirectional thyristor device, comprising:

[0008] Step S1, providing a semiconductor material of a first conductivity type, growing a field oxide layer on the upper surface of the semiconductor material, and photolithographically defining a display area in the field oxide layer;

[0009] Step S2, using the field oxide layer as a barrier, forming a first well region and a second well region of the second conductivity type in the semiconductor material corresponding to the display area, and performing a high-temperature drive; then forming a third well region of the second conductivity type in the first well region, forming a fourth well region of the second conductivity type in the second well region, and performing a high-temperature drive again;

[0010] Step S3, forming a sidewall structure on both sides of each of the field oxide layers after photolithography, and using the sidewall structure as a self-alignment to form first to third heavily doped implant regions of the first conductivity type, wherein the first heavily doped implant region is formed in the third well region, the second heavily doped implant region is formed in the fourth well region, and the third heavily doped implant region is formed in the semiconductor material and located between the first well region and the second well region;

[0011] Step S4, depositing a dielectric layer, and performing photolithography on contact holes and fourth to fifth heavily doped regions of the second conductivity type in the dielectric layer, wherein the contact holes penetrate the first heavily doped injection region and the second heavily doped injection region from top to bottom, respectively. Then, a fourth heavily doped region is formed in the third well region, and a fifth heavily doped region is formed in the fourth well region. The process then enters a furnace tube for annealing.

[0012] Step S5, depositing metal on the upper surface of the dielectric layer and in the contact hole, and forming metal wiring, so that the first heavily doped injection region and the fourth heavily doped region are connected and led out as the first port of the device, and the second heavily doped injection region and the fifth heavily doped region are connected and led out as the second port of the device.

[0013] The method for preparing a bidirectional thyristor device according to the present invention, before step S4, further comprises:

[0014] forming a deep trench isolation structure on both sides of the semiconductor material to isolate the device; and

[0015] A fifth well region of the first conductivity type is formed between the first well region and the second well region in the semiconductor material to replace the floating third heavily doped implant region.

[0016] In the method for preparing the bidirectional thyristor device of the present invention, the junction depth of the deep trench isolation structure is 10um to 30um.

[0017] The method for preparing a bidirectional thyristor device according to the present invention, before step S4, further comprises:

[0018] A sixth well region of the first conductivity type is formed at both side edges of the semiconductor material.

[0019] In the method for preparing a bidirectional thyristor device according to the present invention, in step S1, the semiconductor material includes:

[0020] substrate; or

[0021] A substrate and an epitaxial layer grown on the surface of the substrate.

[0022] In the method for preparing a bidirectional thyristor device of the present invention, in step S1, the thickness of the field oxide layer is 4000 Å to 8000 Å;

[0023] The field oxide layer is grown at a temperature of 1050° C. to 1150° C., and for a time of 30 to 120 minutes.

[0024] In the method for preparing a bidirectional thyristor device according to the present invention, in step S2, the junction depth of the first well region is greater than the junction depth of the third well region;

[0025] The junction depth of the second well region is greater than the junction depth of the fourth well region;

[0026] The junction depth between the first well region and the second well region is 2 μm to 5 μm;

[0027] The junction depth between the third well region and the fourth well region is 1 um to 4 um.

[0028] In the method for preparing a bidirectional thyristor device according to the present invention, in step S2, the ion implantation element in the first well region and the second well region is phosphorus, the implantation dose is 1E12 to 5E13 per square centimeter, the implantation energy is 60 to 100 KeV, the high-temperature implantation temperature is 1050° C. to 1150° C., and the implantation time is 30 to 120 minutes;

[0029] The ion implantation element of the third well region and the fourth well region is phosphorus, the implantation dose is 5E13-8E14 per square centimeter, the implantation energy is 40-80 KeV, the high temperature advancement temperature is 1000° C.-1100° C., and the advancement time is 30-120 minutes.

[0030] In the method for preparing a bidirectional thyristor device according to the present invention, in step S3, the junction depths of the first to third heavily doped implanted regions are 0.4 μm to 2 μm;

[0031] The ion implantation elements of the first to third heavily doped implantation regions are boron or boron difluoride, with an implantation dose of 5E13-5E14 per square centimeter and an implantation energy of 20-80 KeV;

[0032] After the ion implantation, a high temperature driving process is performed, with a driving temperature of 900° C. to 1050° C. and a driving time of 20 to 100 minutes.

[0033] In the method for preparing a bidirectional thyristor device according to the present invention, in step S4, the implanted element in the fourth heavily doped region and the fifth heavily doped region is phosphorus or arsenic, the implantation dose is 1E15 to 1E16 per square centimeter, the implantation angle is 0 degrees, and the implantation energy is 40 to 100 KeV;

[0034] After the ion implantation, an annealing process is performed, with an annealing temperature of 850° C. to 950° C. and an annealing time of 20 to 60 minutes.

[0035] The present invention further provides a bidirectional thyristor device, which is prepared using the above-mentioned method for preparing a bidirectional thyristor device, comprising:

[0036] a semiconductor material of a first conductivity type;

[0037] a field oxide layer formed on the upper surface of the semiconductor material, wherein a display area is photolithographically defined in the field oxide layer;

[0038] A first well region and a second well region of a second conductivity type are formed in the semiconductor material corresponding to the display area;

[0039] a third well region and a fourth well region of the second conductivity type, wherein the third well region is formed in the first well region, and the fourth well region is formed in the second well region;

[0040] Sidewall structures are located on both sides of each field oxide layer;

[0041] first to third heavily doped implant regions of the first conductivity type, the first heavily doped implant region being formed in the third well region, the second heavily doped implant region being formed in the fourth well region, and the third heavily doped implant region being formed in the semiconductor material and located between the first well region and the second well region;

[0042] The fourth heavily doped region and the fifth heavily doped region of the second conductivity type are formed in the third well region, and the fifth heavily doped region is formed in the fourth well region;

[0043] a dielectric layer covering the semiconductor material, wherein corresponding contact holes are formed in the dielectric layer above the fourth heavily doped region and the fifth heavily doped region, respectively, and the contact holes penetrate the first heavily doped injection region and the second heavily doped injection region from top to bottom;

[0044] A metal layer covers the dielectric layer and fills the contact hole, including a first metal layer, connected to the first heavily doped injection region and the fourth heavily doped region and led out as the first port of the device; and a second metal layer, connected to the second heavily doped injection region and the fifth heavily doped region and led out as the second port of the device.

[0045] The bidirectional thyristor device of the present invention further includes:

[0046] Deep trench isolation structures are formed on both sides of the semiconductor material to isolate the devices;

[0047] The fifth well region of the first conductivity type is formed between the first well region and the second well region in the semiconductor material, and replaces the floating third heavily doped implant region.

[0048] The bidirectional thyristor device of the present invention further includes:

[0049] The sixth well region of the first conductivity type is formed at both side edges of the semiconductor material.

[0050] The beneficial effects of the technical solution of the present invention are:

[0051] The present invention improves the precision tolerance of bidirectional thyristor devices to FAB silicon wafer equipment by adopting a self-alignment process (or semi-self-alignment process), reduces the capacity requirements of the equipment, and reduces a certain level so that it has a lower trigger voltage and the same device parameters, while optimizing the difficulty and cost of the production process. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 This is a schematic diagram of a bidirectional thyristor device implemented using a lateral NPNPN structure (or PNPNP structure) in the prior art;

[0053] Figure 2 1 is a flow chart of a method for preparing a bidirectional thyristor device in a preferred embodiment of the present invention;

[0054] Figure 3-Figure 7 Schematic diagram of each step of a method for preparing a bidirectional thyristor device in a preferred embodiment of the present invention;

[0055] Figure 8 1 is a schematic structural diagram of a bidirectional thyristor device in a second preferred embodiment of the present invention;

[0056] Figure 9 1 is a schematic structural diagram of a bidirectional thyristor device in a third preferred embodiment of the present invention;

[0057] Figure 10It is an equivalent circuit diagram of a bidirectional thyristor device in a preferred embodiment of the present invention.

[0058] Reference numerals:

[0059] 1. Substrate; 2. Epitaxial layer; 3. Field oxide layer; 41. First well region;

[0060] 42, second well region; 51, third well region; 52, fourth well region; 6, sidewall structure;

[0061] 71. First heavily doped implantation region; 72. Second heavily doped implantation region;

[0062] 731. Third heavily doped implantation region; 732. Fifth well region; 8. Dielectric layer;

[0063] 9. Contact hole; 101. Fourth heavily doped region; 102. Fifth heavily doped region;

[0064] 111. First metal layer; 112. Second metal layer; 12. Deep trench isolation structure;

[0065] 13. Sixth well region. DETAILED DESCRIPTION

[0066] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0067] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0068] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but they are not intended to limit the present invention.

[0069] In the embodiment of the present invention, the conductive type includes a first conductive type and a second conductive type, and the first conductive type and the second conductive type are opposite, for example:

[0070] If the first conductivity type is N-type, the second conductivity type is P-type;

[0071] If the first conductivity type is P-type, the second conductivity type is N-type (this is taken as an example in the following embodiment 1).

[0072] Among them, the different situations of the average doping concentrations of N+ type, N type, N- type, P+ type, P type and P- type mentioned below, specifically, the doping concentration of N- type is less than that of N type, the doping concentration of N type is less than that of N+ type, the doping concentration of P- type is less than that of P type, and the doping concentration of P type is less than that of P+ type.

[0073] The present invention provides a method for preparing a bidirectional thyristor device. Figure 1 ,include:

[0074] Step S1, such as Figure 3 and Figure 4 As shown, a semiconductor material of a first conductivity type is provided, and a field oxide layer 3 is grown on the upper surface of the semiconductor material, and a display area is defined in the field oxide layer 3 by photolithography;

[0075] Specifically, first, a P-type silicon wafer is selected as the substrate 1, a P-type epitaxial layer 2 is grown on its surface by a high-temperature epitaxial process, a field oxide layer 3 is grown on the surface of the epitaxial layer 2 at high temperature, and an active area is defined in the field oxide layer 3 by AA lithography.

[0076] Preferably, the P-type substrate 1 should be made of high-resistance material. In this embodiment, the resistivity of the substrate 1 is 1 to 100 Ω*cm.

[0077] Preferably, the thickness of the P-type epitaxial layer 2 is 10 to 15 μm, and the resistivity of the epitaxial layer 2 is greater than the resistivity of the substrate 1, preferably 10 to 200 Ω*cm. The use of an epitaxial layer 2 with a high resistivity is beneficial to reducing the capacitance of the device and can be applied to high-speed signal ports.

[0078] Furthermore, the operation is performed on the epitaxial layer 2 because the defects of the epitaxial layer 2 are better than those of the substrate 1. Therefore, the substrate 1 can also be selected to directly perform the operation.

[0079] In the method for preparing a bidirectional thyristor device of the present invention, in step S1, the thickness of the field oxide layer 3 is 4000 Å to 8000 Å;

[0080] The field oxide layer 3 is grown at a temperature of 1050° C. to 1150° C. for a time of 30 to 120 minutes.

[0081] Step S2, such as Figure 4 As shown, with the field oxide layer 3 as a barrier, a first well region 41 and a second well region 42 of the second conductivity type are formed in the semiconductor material corresponding to the display area, and a high-temperature drive is performed; then a third well region 51 of the second conductivity type is formed in the first well region 41, and a fourth well region 52 of the second conductivity type is formed in the second well region 42, and a high-temperature drive is performed again;

[0082] Specifically, self-alignment is performed using the field oxide layer 3 after photolithography, and the first well region 41 and the second well region 42 are photolithographically defined and ion implanted, followed by high-temperature advancement. Then, the third well region 51 and the fourth well region 52 are photolithographically defined and ion implanted, followed by high-temperature advancement, so that diffusion to a certain depth is achieved between the first well region 41 and the third well region 51 and between the second well region 42 and the fourth well region 52.

[0083] Preferably, the junction depth of the first well region 41 is greater than the junction depth of the third well region 51 ; and the junction depth of the second well region 42 is greater than the junction depth of the fourth well region 52 ;

[0084] The junction depth between the first well region 41 and the second well region 42 is 2 μm to 5 μm;

[0085] The junction depth between the third well region 51 and the fourth well region 52 is 1 μm to 4 μm.

[0086] Preferably, in step S2, the ion implantation element of the first well region 41 and the second well region 42 is phosphorus, the implantation dose is 1E12-5E13 per square centimeter, the implantation energy is 60-100 KeV, the high-temperature advancement temperature is 1050° C.-1150° C., and the advancement time is 30-120 minutes;

[0087] The ion implantation element of the third well region 51 and the fourth well region 52 is phosphorus, the implantation dose is 5E13-8E14 per square centimeter, the implantation energy is 40-80 KeV, the high temperature driving temperature is 1000° C.-1100° C., and the driving time is 30-120 minutes.

[0088] Furthermore, the type of implanted elements can be adjusted according to product requirements, such as changing the implanted phosphorus element to the implanted arsenic element; the high-temperature push can also be combined as needed, such as performing a high-temperature push after all the first to fourth well regions are implanted.

[0089] In the embodiment of the present invention, the addition of the third well region 51 and the fourth well region 52 can effectively suppress the voltage breakdown and leakage anomalies caused by voltage punch-through. Preferably, under different conditions of the first well region 41 and the first well region 41, the injection of the third well region 51 and the fourth well region 52 can be adaptively canceled.

[0090] Since the display area is defined in the field oxide layer 3 composed of silicon dioxide through AA lithography and etching processes before the well region is injected, the first to fourth well regions are subsequently fixed in the predetermined area with the field oxide layer 3 as a barrier, and the lateral well region is obtained by injection and diffusion, which is not affected by other processes. Since lithography operations in the well region are still required, it is defined here as a semi-self-aligned process.

[0091] Step S3, such as Figure 5As shown, a sidewall structure 6 is formed on both sides of each field oxide layer 3 after photolithography. The sidewall structure 6 is used as a self-alignment to form first to third heavily doped implant regions of the first conductivity type. The first heavily doped implant region 71 is formed in the third well region 51, the second heavily doped implant region 72 is formed in the fourth well region 52, and the third heavily doped implant region 731 is formed in the semiconductor material and is located between the first well region 41 and the second well region 42.

[0092] Specifically, a spacer process is used to form sidewall structures 6 on both sides of the field oxide layer 3 after the above-mentioned photolithography, and the first to third heavily doped implantation regions are defined by TEOS spacer deposition and spacer etching, and then ion implantation is performed, followed by high-temperature driving;

[0093] Furthermore, in the embodiment of the present invention, a window can be defined separately by photolithography for the floating third heavily doped implantation region 731 .

[0094] Preferably, in step S3, the junction depths of the first to third heavily doped implanted regions are 0.4 um to 2 um;

[0095] The ion implantation elements of the first to third heavily doped implantation regions are boron or boron difluoride, with an implantation dose of 5E13 to 5E14 per square centimeter and an implantation energy of 20 to 80 KeV;

[0096] After the ion implantation, a high temperature driving process is performed, with a driving temperature of 900° C. to 1050° C. and a driving time of 20 to 100 minutes.

[0097] Furthermore, the first to third heavily doped injection regions adopt an automatic alignment process, using the field oxide layer 3 as a silicon dioxide masking layer and the sidewall structure 6 to define the areas of the first to third heavily doped injection regions. After ion implantation, lateral diffusion is performed and is not affected by other lithography and corrosion processes.

[0098] Step S4, as Figure 6 As shown, a dielectric layer 8 is deposited, and contact holes 9 are photolithographically formed in the dielectric layer 8 to form the fourth to fifth heavily doped regions of the second conductivity type. The contact holes 9 penetrate the first heavily doped injection region 71 and the second heavily doped injection region 72 from top to bottom, respectively. Then, a fourth heavily doped region 101 is formed in the third well region 51, and a fifth heavily doped region 102 is formed in the fourth well region 52. The substrate then enters the furnace for annealing.

[0099] Specifically, the hole area and the fourth to fifth heavily doped regions are defined by hole lithography, and holes are formed by lithography, etching the dielectric layer 8, and etching the epitaxial layer 2 until the SP region is penetrated. The contact hole 9 on the left penetrates the first heavily doped injection region 71, and the contact hole 9 on the right penetrates the second heavily doped injection region 72. Then, ion implantation is performed to form the fourth heavily doped region 101 and the fifth heavily doped region 102, and then enter the furnace tube for annealing to repair the implantation damage.

[0100] Preferably, the dielectric layer 8 may be an oxide layer, borophosphorus glass, or a multi-layer insulating film composite layer.

[0101] Preferably, in step S4 , the implanted element in the fourth heavily doped region 101 and the fifth heavily doped region 102 is phosphorus or arsenic, the implantation dose is 1E15-1E16 per square centimeter, the implantation angle is 0 degrees, and the implantation energy is 40-100 KeV;

[0102] After the ion implantation, an annealing process is performed at a temperature of 850° C. to 950° C. for 20 to 60 minutes. Alternatively, a rapid thermal annealing process is used, with the annealing temperature and time adjusted accordingly.

[0103] Specifically, in the embodiment of the present invention, the contact hole 9 is to penetrate the first heavily doped injection region 71 and the second heavily doped injection region 72, and then inject to form the fourth heavily doped region 101 and the fifth heavily doped region 102. The fourth heavily doped region 101 and the fifth heavily doped region 102 are connected to the bottom of the contact hole 9, and the first heavily doped injection region 71 and the second heavily doped injection region 72 are connected to the side of the contact hole 9, and are jointly connected to the metal layer.

[0104] Step S5, as Figure 7 As shown, metal deposition is performed on the upper surface of the dielectric layer 8 and the contact hole 9, and metal wiring is formed so that the first heavily doped injection region 71 and the fourth heavily doped region 101 are connected and led out as the first port of the device, and the second heavily doped injection region 72 and the fifth heavily doped region 102 are connected and led out as the second port of the device.

[0105] Specifically, the metal layer can be prepared by using the TI process or the TIN+ALSICU process or directly using the ALSICU process; it can be prepared by using AL-CU, pure AL or other metals.

[0106] In the method for preparing a bidirectional thyristor device of the present invention, in step S1, the semiconductor material includes:

[0107] Substrate 1; or

[0108] A substrate 1 and an epitaxial layer 2 grown on the surface of the substrate 1 .

[0109] The preparation method of the bidirectional thyristor device of the present invention, before step S4, as Figure 8 As shown, it also includes:

[0110] forming a deep trench isolation structure 12 on both sides of the semiconductor material to isolate the device; and

[0111] A fifth well region 732 of the first conductivity type is formed between the first well region 41 and the second well region 42 in the semiconductor material to replace the floating third heavily doped implant region 731 .

[0112] Specifically, in the second preferred embodiment of the present invention, a deep trench isolation structure 12 is added to isolate the device using the deep trench isolation structure 12 , and at the same time, the floating third heavily doped injection region 731 is implemented separately using the fifth well region 732 .

[0113] Preferably, the junction depth of the deep trench isolation structure 12 is 10 um to 30 um.

[0114] The preparation method of the bidirectional thyristor device of the present invention, before step S4, as Figure 9 As shown, it also includes:

[0115] A sixth well region 13 of the first conductivity type is formed at both side edges of the semiconductor material.

[0116] Specifically, in the third preferred embodiment of the present invention, sixth well regions 13 are added to both sides of the device to prevent surface leakage, while the floating third heavily doped implant region 731 is implemented solely by the fifth well region 732. Preferably, this embodiment can also be combined with the aforementioned deep trench isolation structure 12 to provide isolation.

[0117] The present invention further provides a bidirectional thyristor device, which is prepared using the above-mentioned method for preparing a bidirectional thyristor device, comprising:

[0118] a semiconductor material of a first conductivity type;

[0119] A field oxide layer 3 is formed on the upper surface of the semiconductor material, and a display area is photolithographically defined in the field oxide layer 3;

[0120] A first well region 41 and a second well region 42 of a second conductivity type are formed in the semiconductor material corresponding to the display area;

[0121] A third well region 51 and a fourth well region 52 of the second conductivity type, wherein the third well region 51 is formed in the first well region 41 , and the fourth well region 52 is formed in the second well region 42 ;

[0122] Sidewall structures 6 are located on both sides of each field oxide layer 3;

[0123] First to third heavily doped implant regions of the first conductivity type, wherein the first heavily doped implant region 71 is formed in the third well region 51 , the second heavily doped implant region 72 is formed in the fourth well region 52 , and the third heavily doped implant region 731 is formed in the semiconductor material and is located between the first well region 41 and the second well region 42 ;

[0124] A fourth heavily doped region 101 and a fifth heavily doped region 102 of the second conductivity type are formed in the third well region 51 , and the fifth heavily doped region 102 is formed in the fourth well region 52 ;

[0125] a dielectric layer 8 covering the semiconductor material, wherein corresponding contact holes 9 are formed in the dielectric layer 8 above the fourth heavily doped region 101 and the fifth heavily doped region 102, respectively, and the contact holes 9 penetrate the first heavily doped implant region 71 and the second heavily doped implant region 72 from top to bottom, respectively;

[0126] The metal layer covers the dielectric layer 8 and fills the contact hole 9, including a first metal layer 111, which is connected to the first heavily doped injection region 71 and the fourth heavily doped region 101 and is led out as the first port of the device; the second metal layer 112, which is connected to the second heavily doped injection region 72 and the fifth heavily doped region 102 and is led out as the second port of the device.

[0127] The bidirectional thyristor device of the present invention further includes:

[0128] Deep trench isolation structures 12 are formed on both sides of the semiconductor material to isolate the devices;

[0129] The fifth well region 732 of the first conductivity type is formed between the first well region 41 and the second well region 42 in the semiconductor material, and replaces the floating third heavily doped implant region 731 .

[0130] The bidirectional thyristor device of the present invention further includes:

[0131] The sixth well regions 13 of the first conductivity type are formed at both side edges of the semiconductor material.

[0132] The technical features and advantages of the embodiments of the present invention are described in detail below:

[0133] (1) The present invention mainly optimizes the production process. First, the first well region 41 and the second well region 42, as well as the third well region 51 and the fourth well region 52, are defined by the display (AA) area, and the field oxide layer is used as a silicon dioxide masking layer to ensure that there is sufficient lithography alignment window and no abnormality caused by lithography offset.

[0134] (2) The first heavily doped implant region 71 and the second heavily doped implant region 72 are subjected to a photoresist removal operation, and a self-aligned process is fully adopted. The windows are defined by a spacer process, thereby increasing alignment accuracy and reducing manufacturing costs.

[0135] (3) The fourth heavily doped region 101 and the fifth heavily doped region 102 are formed using a silicon hole process. A silicon etching process is added to the formation of the contact hole 9. The fourth heavily doped region 101 and the fifth heavily doped region 102 are formed by implantation at a 0-degree angle, thereby ensuring process accuracy and reducing manufacturing costs.

[0136] (4) Figure 10 As shown, an equivalent circuit diagram of a bidirectional thyristor device according to a preferred embodiment of the present invention includes three transistors. The first transistor Q1 and the third transistor Q3 are PNP transistors, which are completely symmetrical. The first transistor Q1 is composed of the first heavily doped implant region 71, the first well region 41, the third well region 51, the epitaxial layer 2, and the third heavily doped implant region 731. The third transistor Q3 is composed of the second heavily doped implant region 72, the second well region 42, the fourth well region 52, the epitaxial layer 2, and the third heavily doped implant region 731. The second transistor Q2 is an NPN transistor, whose base region is a suspended common NPN transistor, composed of the first well region 41, the third well region 51, the fourth heavily doped region 101, the epitaxial layer 2, the fifth well region 732, the second well region 42, the fourth well region 52, and the fifth heavily doped region 102. The first resistor R1 is the parasitic resistance of the first well region 41 and the third well region 51, and the second resistor R2 is the parasitic resistance of the second well region 42 and the fourth well region 52.

[0137] (5) When an electrostatic discharge (ESD) event occurs at the first port IO1 of the device, the voltage rises at the moment, and the first transistor Q1 and the third transistor Q3 are triggered to turn on first. The electrostatic current flows from the first port IO1 to the junction of the second well region 42, the epitaxial layer 2, and the fifth well region 732 of the second port IO2, that is, the access point of the injection current. The electrostatic current flows through the second well region 42, the fourth well region 52, and the fifth heavily doped region 102 to the second port IO2. The ESD voltage continues to increase, and the electrostatic current passes through the first resistor R1. Because the resistance value of the first resistor R1 is relatively large, as long as a small current passes through the first resistor R1, the voltage difference between its two ends can reach more than 0.7V, that is, the emitter junction of the first transistor Q1 (that is, the second heavily doped injection region 72 and the fourth well region 52) is forward biased, so the first transistor Q1 is turned on. After turning on, the first transistor Q1 generates a base current, and then the second transistor Q2 will also be turned on. The thyristor device of the embodiment of the present invention enters positive feedback and is in a large negative resistance conduction state, thereby effectively protecting the subsequent circuit.

[0138] (6) When an electrostatic discharge (ESD) event occurs at the second port IO2 of the device, since it is a bidirectional symmetrical structure, it is consistent with the forward mechanism and will not be described in detail here.

[0139] (7) The trigger voltage of the device of the present invention is determined by the second transistor Q2 with a floating base and low avalanche breakdown or punch-through breakdown formed by the lateral PNP transistor. Since the PNP transistor adopts a self-aligned process, the breakdown voltage Vbr can be accurately controlled and the trigger voltage can be controlled to 4V~12V. Therefore, the embodiment of the present invention has an extremely wide adjustable trigger voltage, especially in the low trigger voltage range, and can protect more circuits with lower operating voltages.

[0140] (8) The device of the present invention adopts a repeating unit structure and connects multiple conduction paths in parallel, which can release current simultaneously, which is conducive to evenly diverting ESD events. Therefore, it has strong ESD discharge capability, excellent stability and high reliability.

[0141] The above technical solution has the following advantages or beneficial effects: the present invention improves the precision tolerance of bidirectional thyristor devices to FAB silicon wafer equipment by adopting a self-alignment process (or semi-self-alignment process), reduces the capacity requirements of the equipment, and reduces a certain level, so that it has a lower trigger voltage and the same device parameters, while optimizing the difficulty and cost of the production process.

[0142] Through the description and drawings, typical embodiments of the specific structure of the specific implementation are given. Based on the spirit of the present invention, other transformations can be made. Although the above invention has proposed the existing preferred embodiments, however, these contents are not intended to be limiting.

[0143] Various changes and modifications will undoubtedly become apparent to those skilled in the art upon reading the foregoing description. Therefore, the appended claims should be construed to encompass all changes and modifications within the true intent and scope of the present invention. Any and all equivalents within the scope of the claims should be considered to be within the intent and scope of the present invention.

Claims

1. A method for preparing a bidirectional thyristor device, characterized in that: include: Step S1, providing a semiconductor material of a first conductivity type, growing a field oxide layer on the upper surface of the semiconductor material, and photolithographically defining a display area in the field oxide layer; Step S2, using the field oxide layer as a barrier, forming a first well region and a second well region of the second conductivity type in the semiconductor material corresponding to the display area, and performing a high-temperature drive; then forming a third well region of the second conductivity type in the first well region, forming a fourth well region of the second conductivity type in the second well region, and performing a high-temperature drive again; Step S3, forming a sidewall structure on both sides of each of the field oxide layers after photolithography, and using the sidewall structure as a self-alignment to form first to third heavily doped implant regions of the first conductivity type, wherein the first heavily doped implant region is formed in the third well region, the second heavily doped implant region is formed in the fourth well region, and the third heavily doped implant region is formed in the semiconductor material and located between the first well region and the second well region; Step S4, depositing a dielectric layer, and performing photolithography on contact holes and fourth to fifth heavily doped regions of the second conductivity type in the dielectric layer, wherein the contact holes penetrate the first heavily doped injection region and the second heavily doped injection region from top to bottom, respectively. Then, a fourth heavily doped region is formed in the third well region, and a fifth heavily doped region is formed in the fourth well region. The process then enters a furnace tube for annealing. Step S5, depositing metal on the upper surface of the dielectric layer and in the contact hole, and forming metal wiring, so that the first heavily doped injection region and the fourth heavily doped region are connected and led out as the first port of the device, and the second heavily doped injection region and the fifth heavily doped region are connected and led out as the second port of the device.

2. The method for preparing a bidirectional thyristor device according to claim 1, wherein: Before step S4, the method further includes: forming a deep trench isolation structure on both sides of the semiconductor material to isolate the device; and A fifth well region of the first conductivity type is formed between the first well region and the second well region in the semiconductor material to replace the floating third heavily doped implant region.

3. The method for preparing a bidirectional thyristor device according to claim 2, wherein: The junction depth of the deep trench isolation structure is 10um to 30um.

4. The method for preparing a bidirectional thyristor device according to claim 1 or 2, wherein: Before step S4, the method further includes: A sixth well region of the first conductivity type is formed at both side edges of the semiconductor material.

5. The method for preparing a bidirectional thyristor device according to claim 1, wherein: In step S1, the semiconductor material includes: substrate; or A substrate and an epitaxial layer grown on the surface of the substrate.

6. The method for preparing a bidirectional thyristor device according to claim 1, wherein: In the step S1, the thickness of the field oxide layer is 4000 Å to 8000 Å; The field oxide layer is grown at a temperature of 1050° C. to 1150° C., and for a time of 30 to 120 minutes.

7. The method for preparing a bidirectional thyristor device according to claim 1, wherein: In step S2, the junction depth of the first well region is greater than the junction depth of the third well region; The junction depth of the second well region is greater than the junction depth of the fourth well region; The junction depth between the first well region and the second well region is 2 μm to 5 μm; The junction depth between the third well region and the fourth well region is 1 um to 4 um.

8. The method for preparing a bidirectional thyristor device according to claim 1, wherein: In step S2, the ion implantation element of the first well region and the second well region is phosphorus, the implantation dose is 1E12-5E13 per square centimeter, the implantation energy is 60-100 KeV, the high temperature driving temperature is 1050° C.-1150° C., and the driving time is 30-120 minutes; The ion implantation element of the third well region and the fourth well region is phosphorus, the implantation dose is 5E13-8E14 per square centimeter, the implantation energy is 40-80 KeV, the high temperature advancement temperature is 1000° C.-1100° C., and the advancement time is 30-120 minutes.

9. The method for preparing a bidirectional thyristor device according to claim 1, wherein: In step S3, the junction depths of the first to third heavily doped implanted regions are 0.4um to 2um; The ion implantation elements of the first to third heavily doped implantation regions are boron or boron difluoride, with an implantation dose of 5E13-5E14 per square centimeter and an implantation energy of 20-80 KeV; After the ion implantation, a high temperature driving process is performed, with a driving temperature of 900° C. to 1050° C. and a driving time of 20 to 100 minutes.

10. The method for preparing a bidirectional thyristor device according to claim 1, wherein: In step S4, the implantation element of the fourth heavily doped region and the fifth heavily doped region is phosphorus or arsenic, the implantation dose is 1E15-1E16 per square centimeter, the implantation angle is 0 degrees, and the implantation energy is 40-100 KeV; After the ion implantation, an annealing process is performed, with an annealing temperature of 850° C. to 950° C. and an annealing time of 20 to 60 minutes.

11. A bidirectional thyristor device, characterized in that: The bidirectional thyristor device is prepared by the method for preparing the bidirectional thyristor device according to any one of claims 1 to 10, comprising: a semiconductor material of a first conductivity type; a field oxide layer formed on the upper surface of the semiconductor material, wherein a display area is photolithographically defined in the field oxide layer; A first well region and a second well region of a second conductivity type are formed in the semiconductor material corresponding to the display area; a third well region and a fourth well region of the second conductivity type, wherein the third well region is formed in the first well region, and the fourth well region is formed in the second well region; Sidewall structures are located on both sides of each field oxide layer; first to third heavily doped implant regions of the first conductivity type, the first heavily doped implant region being formed in the third well region, the second heavily doped implant region being formed in the fourth well region, and the third heavily doped implant region being formed in the semiconductor material and located between the first well region and the second well region; The fourth heavily doped region and the fifth heavily doped region of the second conductivity type are formed in the third well region, and the fifth heavily doped region is formed in the fourth well region; a dielectric layer covering the semiconductor material, wherein corresponding contact holes are formed in the dielectric layer above the fourth heavily doped region and the fifth heavily doped region, respectively, and the contact holes penetrate the first heavily doped injection region and the second heavily doped injection region from top to bottom; A metal layer covers the dielectric layer and fills the contact hole, including a first metal layer, connected to the first heavily doped injection region and the fourth heavily doped region and led out as the first port of the device; and a second metal layer, connected to the second heavily doped injection region and the fifth heavily doped region and led out as the second port of the device.

12. The bidirectional thyristor device according to claim 11, characterized in that: Also includes: Deep trench isolation structures are formed on both sides of the semiconductor material to isolate the devices; The fifth well region of the first conductivity type is formed between the first well region and the second well region in the semiconductor material, and replaces the floating third heavily doped implant region.

13. The bidirectional thyristor device according to claim 11 or 12, characterized in that: Also includes: The sixth well region of the first conductivity type is formed at both side edges of the semiconductor material.

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