GaN HEMT device structure with high threshold voltage stability and low gate leakage and method of fabrication

Abstract

The application relates to a GaN HEMT device structure with high threshold voltage stability and low gate leakage and a preparation method thereof. The GaN HEMT device structure comprises a substrate, a buffer layer, a channel layer, a barrier layer, a source, a drain, a passivation layer, a pure p-type SnO layer, an atom-doped SnO-based thin film layer and a gate, wherein the substrate, the buffer layer and the channel layer are sequentially stacked; the source is located at one end of the barrier layer, and the drain is located at the other end of the barrier layer; the pure p-type SnO layer is located on part of the barrier layer between the source and the drain; the atom-doped SnO-based thin film layer covers the upper surface of the pure p-type SnO layer; the gate is located on part of the surface of the atom-doped SnO-based thin film layer; and the passivation layer covers the surface of the barrier layer between the pure p-type SnO layer and the source, the surface of the barrier layer between the pure p-type SnO layer and the drain, and part of the surface of the atom-doped SnO-based thin film layer. The embodiment of the application generally improves the gate withstand voltage and the gate leakage of the pure p-type SnO GaN HEMT.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductor gallium nitride electronic devices, and particularly relates to a GaN HEMT device structure with high threshold voltage stability and low gate leakage and a preparation method thereof. BACKGROUND

[0002] GaN wide bandgap semiconductor material has a series of material advantages such as large band gap, high breakdown field strength, high polarization coefficient, high electron mobility and high electron saturation drift speed, and a high-concentration high-mobility two-dimensional electron gas is generated after forming a heterojunction with AlGaN. These advantages make GaN an optimal material for preparing a new generation of high-performance high-frequency power switching devices. At present, HEMT power devices prepared on the basis of GaN can be divided into two categories: depletion mode devices and enhancement mode devices. However, the depletion mode GaN HEMT device has limited applications due to the high power loss problem caused by its inherent negative gate voltage turn-off. In practical applications, the enhancement mode GaN HEMT device with zero gate voltage turn-off and failure protection function is more widely used than the depletion mode GaN HEMT device and is more popular in the market. Its good performance makes it have a very broad application prospect in many aspects such as consumer electronics, rail transit, industrial equipment, communication base stations and the like.

[0003] The technologies for realizing the enhancement mode GaN HEMT device mainly include p-type GaN cap layer technology, thin barrier structure, recessed gate structure and F ion implantation under the gate, among which the enhancement mode device realized by the p-type GaN cap layer technology has been successfully used in the market. However, there are still some problems in the current p-type GaN cap layer that are difficult to overcome, such as a relatively low threshold voltage, poor etching uniformity of the p-type GaN non-gate area and introduction of high-density surface defects on the AlGaN surface during the etching process. Therefore, relevant researchers propose that a p-type metal oxide (stannous oxide, nickel oxide, etc.) material can be used to replace the p-type GaN cap layer to realize the enhancement mode GaN HEMT device through only a stripping operation, so as to solve the above problems and reduce the process cost.

[0004] However, so far, the GaN HEMT devices prepared by using the p-type metal oxide cap layer (mainly nickel oxide and cuprous oxide) that have been disclosed have either a negative threshold voltage and an insignificant positive shift effect, and are still depletion mode devices, or have a relatively low threshold voltage (less than 1V) and no obvious application potential. Among the p-type metal oxides, the p-type concentration of p-type stannous oxide (p-type SnO) without doping can be as high as 10 19 cm -3The band gap can reach 3.9eV, and the low-temperature deposition can be realized by using various thin film processes. Based on this, it is found that, by using pure p-type SnO as a gate cap layer to prepare an enhanced GaN HEMT device, a threshold voltage greater than 1V and a gate breakdown voltage greater than 4V are successfully realized without optimization, and theoretical simulation shows that the threshold voltage of the device can exceed 4V, and the gate breakdown voltage can exceed 7V, which shows great application potential.

[0005] However, the pure p-type SnO GaN HEMT device still has the following problems: (1) The pure p-type SnO material itself is in a metastable state, and the metastable characteristics mainly manifest as being easy to react with hydrogen ions in external water molecules to generate a complex, and n-type tin oxide (SnO2) is generated when high-temperature processes are involved, so that the material characteristics of the p-type SnO are lost, so that the GaN HEMT device using the p-type SnO as the gate cap layer faces the problem of unstable threshold voltage. (2) The peak electric field at the metallurgical junction formed when the pure p-type SnO contacts the gate metal is too large and the peak electric field is uneven, so that the device is broken down in advance, resulting in low gate voltage and large gate leakage of the device. SUMMARY

[0006] In order to solve the above problems in the prior art, the present application provides a GaN HEMT device structure with high threshold voltage stability and low gate leakage and a preparation method thereof. The technical problem to be solved by the present application is solved by the following technical scheme:

[0007] The GaN HEMT device structure with high threshold voltage stability and low gate leakage provided by the embodiment of the present application comprises a substrate, a buffer layer, a channel layer, a barrier layer, a source electrode, a drain electrode, a passivation layer, a pure p-type SnO layer, an atom-doped SnO-based thin film layer and a gate electrode, wherein,

[0008] The substrate, the buffer layer, the channel layer and the barrier layer are sequentially stacked;

[0009] The source electrode is located at one end of the barrier layer, and the drain electrode is located at the other end of the barrier layer;

[0010] The pure p-type SnO layer is located on part of the barrier layer between the source electrode and the drain electrode;

[0011] The atom-doped SnO-based thin film layer covers the upper surface of the pure p-type SnO layer;

[0012] The gate electrode is located on part of the surface of the atom-doped SnO-based thin film layer;

[0013] The passivation layer covers the surface of the barrier layer between the pure p-type SnO layer and the source electrode, the surface of the barrier layer between the pure p-type SnO layer and the drain electrode, and part of the surface of the atomically doped SnO-based thin film layer.

[0014] In one embodiment of the present application, the material of the substrate comprises one or more of sapphire, silicon carbide, silicon, gallium nitride;

[0015] The material of the buffer layer and the channel layer both comprises gallium nitride;

[0016] The material of the barrier layer comprises Al x Ga 1-x N, and x is 0.1-0.25;

[0017] The material of the passivation layer comprises one or more of silicon nitride, silicon dioxide.

[0018] In one embodiment of the present application, the thickness of the buffer layer is 1-5 μm;

[0019] The thickness of the channel layer is 50-500 nm;

[0020] The thickness of the barrier layer is 10-40 nm;

[0021] The thickness of the passivation layer is 50-400 nm;

[0022] The thickness of the pure p-type SnO layer is 70-150 nm.

[0023] In one embodiment of the present application, the material of the atomically doped SnO-based thin film layer comprises one or more of Ca x Sn 1-x O, Mg x Sn 1-x O, In x Sn 1-x O, and x is 0.1-0.3;

[0024] The concentration of the atomic doping in the atomically doped SnO-based thin film layer is 7x10 17 -9x10 19 cm -3 .

[0025] In one embodiment of the present application, the thickness of the atomically doped SnO-based thin film layer is 10-40 nm.

[0026] In one embodiment of the present application, the atomically doped SnO-based thin film layer also covers the side surface of the pure p-type SnO layer.

[0027] Another embodiment of the present application provides a method for preparing a GaN HEMT device structure with high threshold voltage stability and low gate-drain current, comprising the steps of:

[0028] S1, sequentially preparing a buffer layer, a channel layer and a barrier layer on a substrate;

[0029] S2, preparing a source electrode at one end of the barrier layer and a drain electrode at the other end;

[0030] S3, using a low-temperature synthesis technique to prepare a pure p-type SnO layer on part of the barrier layer between the source electrode and the drain electrode;

[0031] S4, using a low-temperature synthesis technique to prepare an atomically doped SnO-based thin film layer on the upper surface of the pure p-type SnO layer, or using a low-temperature synthesis technique to prepare an atomically doped SnO-based thin film layer on the upper surface and the side surface of the pure p-type SnO layer;

[0032] S5, using a low-temperature deposition process to prepare a passivation layer on the surface of the barrier layer between the pure p-type SnO layer and the source electrode, on the surface of the barrier layer between the pure p-type SnO layer and the drain electrode, and on part of the surface of the atomically doped SnO-based thin film layer;

[0033] S6, preparing a gate electrode on part of the surface of the atomically doped SnO-based thin film layer.

[0034] In one embodiment of the present application, step S4 comprises:

[0035] S41, making a mask on the barrier layer, and then performing a glueing pretreatment on the wafer by using nitrogen or argon;

[0036] S42, using a radio frequency magnetron sputtering method to prepare an atomically doped SnO-based thin film layer on the upper surface of the pure p-type SnO layer.

[0037] In one embodiment of the present application, the low-temperature synthesis technique comprises a radio frequency magnetron sputtering method, a direct current sputtering method, an atomic force deposition method and a sol-gel method;

[0038] The low-temperature deposition process comprises an inductively coupled plasma chemical vapor deposition process, and the reaction chamber temperature in the inductively coupled plasma chemical vapor deposition process is 120-150°C.

[0039] In one embodiment of the present application, the atomically doped SnO-based thin film layer comprises Ca x Sn 1-x O, Mg x Sn 1-x O, In x Sn 1-xone or more of O, and x is 0.1-0.3;

[0040] The concentration of the atomic doping in the atomic-doped SnO-based thin film layer is 7*10 17 -9*10 19 cm -3 .

[0041] Compared with the prior art, the present application has the following beneficial effects:

[0042] 1. The present application deposits a layer of atomic-doped SnO-based thin film layer on the pure p-type SnO layer as an insulating layer between the pure p-type SnO layer and the external water molecules, thereby preventing the external water molecules from directly contacting the p-type SnO layer, alleviating the reaction between the p-type SnO and the hydrogen ions in the external water molecules, and improving the stability of the threshold voltage of the device; at the same time, the p-type concentration of the deposited atomic-doped SnO-based thin film layer is lower than that of the p-type SnO layer, and the depletion region formed by the direct contact between the thin film layer with low p-type concentration and the gate metal is further widened, thereby reducing the peak electric field at the metallurgical junction in the p-type SnO GaN HEMT device, and achieving the purposes of improving the gate withstand voltage and reducing the gate leakage current of the device; therefore, the gate withstand voltage and the gate leakage current of the pure p-type SnO GaN HEMT are improved as a whole.

[0043] 2. In the passivation process, the present application uses a low-temperature deposition process to grow the passivation layer, thereby avoiding the oxidation of the p-type SnO layer due to high temperature in the passivation process, and further improving the stability of the threshold voltage of the device.

[0044] 3. In the present application, argon is used for the pretreatment instead of oxygen, before the preparation of the atomic-doped SnO-based thin film layer, thereby avoiding the oxidation of the p-type SnO layer by oxygen in the pretreatment process, and further improving the stability of the threshold voltage of the device. BRIEF DESCRIPTION OF DRAWINGS

[0045] Figure 1 A structure diagram of a GaN HEMT device structure with high threshold voltage stability and low gate leakage current provided for the embodiments of the present application;

[0046] Figure 2 A structure diagram of another GaN HEMT device structure with high threshold voltage stability and low gate leakage current provided for the embodiments of the present application;

[0047] Figure 3 A simulation band diagram of a p-type SnO GaN HEMT and a Ca x Sn 1-x O layer / p-type SnO GaN HEMT at a gate voltage of 0 V based on a device simulation model calibrated by Silvaco software;

[0048] Figure 4 For the pure p-type SnO GaN HEMT and Ca x Sn 1-x The electric field simulation diagram of the O layer / p-type SnO GaN HEMT gate cap layer at a gate voltage of 1V;

[0049] Figures 5a-5f A preparation method process schematic diagram of a GaN HEMT device structure with high threshold voltage stability and low gate leakage is provided for the embodiment of the present application. DETAILED DESCRIPTION

[0050] The present application will be further described in detail below with specific embodiments, but the embodiments of the present application are not limited thereto.

[0051] Embodiment one

[0052] Please refer to Figure 1 and Figure 2 , Figure 1 A structure schematic diagram of a GaN HEMT device structure with high threshold voltage stability and low gate leakage is provided for the embodiment of the present application, Figure 2 A structure schematic diagram of another GaN HEMT device structure with high threshold voltage stability and low gate leakage is provided for the embodiment of the present application.

[0053] The purpose of the present embodiment is to provide a device structure for improving the threshold voltage stability of a pure p-type SnO GaN HEMT and improving the gate reliability of the device, which comprises a substrate 1, a buffer layer 2, a channel layer 3, a barrier layer 4, a source electrode 5, a drain electrode 6, a passivation layer 7, a pure p-type SnO layer 8, an atom-doped SnO-based thin film layer 9 and a gate electrode 10. Among them, the substrate 1, the buffer layer 2, the channel layer 3 and the barrier layer 4 are stacked in sequence; the source electrode 5 is located at one end of the barrier layer 4, and the drain electrode 6 is located at the other end of the barrier layer 4; the pure p-type SnO layer 8 is located on part of the barrier layer 4 between the source electrode 5 and the drain electrode 6; the atom-doped SnO-based thin film layer 9 covers the upper surface of the pure p-type SnO layer 8; the gate electrode 10 is located on part of the surface of the atom-doped SnO-based thin film layer 9; the passivation layer 7 covers the surface of the barrier layer 4 between the pure p-type SnO layer 8 and the source electrode 5, the surface of the barrier layer 4 between the pure p-type SnO layer 8 and the drain electrode 6, and part of the surface of the atom-doped SnO-based thin film layer 9.

[0054] Specifically, the atom-doped SnO-based thin film layer 9 completely covers the upper surface of the pure p-type SnO layer 8; the atom-doped SnO-based thin film layer 9 can not cover the side surface of the pure p-type SnO layer 8, at which time the side surface of the pure p-type SnO layer 8 is in contact with the passivation layer 7, such as Figure 1As shown; the atom-doped SnO-based thin film layer 9 can also cover the two sides of the pure p-type SnO layer 8, at this time, the atom-doped SnO-based thin film layer 9 covering the two sides is in contact with the passivation layer 7, as shown. Figure 2 Due to the limitation of actual process, the atom-doped SnO-based thin film layer 9 usually covers the upper surface of the pure p-type SnO layer 8 and the two sides of the pure p-type SnO layer 8.

[0055] In one specific embodiment, the material of the substrate 1 includes one or more of sapphire, silicon carbide, silicon, gallium nitride; the material of the buffer layer 2 and the channel layer 3 both includes gallium nitride; the material of the barrier layer 4 includes Al x Ga 1-x N, x is 0.1-0.25; the material of the passivation layer 7 includes one or more of silicon nitride, silicon dioxide. The thickness of the buffer layer 2 is 1-5 μm; the thickness of the channel layer 3 is 50-500 nm; the thickness of the barrier layer 6 is 10-40 nm; the thickness of the passivation layer 7 is 50-400 nm; the thickness of the pure p-type SnO layer 8 is 70-150 nm.

[0056] In one specific embodiment, the atom-doped SnO-based thin film layer 9 is a thin film with low p-type concentration, and the p-type concentration is less than that of the pure p-type SnO layer 8. The material of the atom-doped SnO-based thin film layer 9 includes one or more of Ca x Sn 1-x O, Mg x Sn 1-x O, In x Sn 1-x O, x is 0.1-0.3; wherein, Ca x Sn 1-x O is Ca x Sn 1-x O doped with Ca atoms, Mg x Sn 1-x O is Mg x Sn 1-x O doped with Mg atoms, In x Sn 1-x O is In x Sn 1-x O doped with In atoms. The concentration of atom-doping in the atom-doped SnO-based thin film layer 9 is 7×10 17 -9×10 19 cm -3 -2 cm-3. The thickness of the atom-doped SnO-based thin film layer 9 is 10-40 nm.

[0057] It is found by research that the α-SnO atomic layer is generally a tetragonal layered structure, and the Sn-O bond length and interlayer spacing of the p-type SnO layer are and While by doping different proportion of atoms, such as Ca atoms, the Ca x Sn 1-x The Sn-O bond length and interlayer distance of the component layer doped with Ca atoms are both less than that of the pure SnO layer to varying degrees, which indicates that the Ca-doped SnO oxide layer structure is more compact and stable, and is also less susceptible to temperature and hydrogen ions in external water molecules. At the same time, compared with the pure p-type SnO thin film, the Ca x Sn 1-x The hole concentration of the p-type SnO layer is reduced by an order of magnitude. Therefore, in order to alleviate the problems faced by the p-type SnO GaN HEMT device, the embodiment regrows an atomically doped SnO-based thin film layer on the pure p-type SnO layer as an insulating layer of the SnO layer from external water molecules, and as a contact layer with the gate metal.

[0058] Further, by depositing an atomically doped SnO-based thin film layer on the pure p-type SnO layer as an insulating layer of the pure p-type SnO layer from external water molecules, the direct contact between the external water molecules and the p-type SnO layer is blocked, the reaction between the p-type SnO and the hydrogen ions in the external water molecules is alleviated, and the stability of the threshold voltage of the device is improved; at the same time, the deposited atomically doped low-p-type-concentration SnO-based thin film layer as a contact layer with the gate metal forms a depletion region that is further widened, thereby reducing the peak electric field at the metallurgical junction in the p-type SnO GaN HEMT device, so as to achieve the purposes of improving the gate withstand voltage of the device and reducing the gate leakage current.

[0059] See Figure 3 , Figure 3 for the p-type SnO GaN HEMT and the Ca x Sn 1-x The simulated band diagram of the Ca Figure 3 It can be seen that the depletion region of the Ca x Sn 1-x O layer / p-type SnO GaN HEMT is obviously widened compared with the former, and the depletion region expansion further reduces the gate leakage current, and the further widening of the depletion region is due to the relatively low hole concentration of the Ca x Sn 1-x O layer.

[0060] See Figure 4 , Figure 4 for the pure p-type SnO GaN HEMT and the Ca x Sn 1-xThe electric field simulation diagram of the O layer / p-type SnO GaN HEMT gate cap layer at a gate voltage of 10V. Figure 4 It can be seen that Ca x Sn 1-x The peak electric field of the O layer / p-type SnO GaN HEMT is significantly reduced compared with the former, which significantly improves the gate withstand voltage level of the device.

[0061] In summary, by regrowing an atomically doped SnO-based thin film layer on the original pure p-SnO cap layer, the problem of unstable threshold voltage caused by the instability of the pure p-type SnO layer is successfully alleviated, and the gate withstand voltage level of the device is improved, and the gate leakage of the device is reduced, and overall, the gate withstand voltage and gate leakage of the pure p-type SnO GaN HEMT are improved.

[0062] Further, in practical applications, the enhanced GaN HEMT with zero gate voltage off and failure protection function has greater application potential in the field of high-energy efficient high-power electronic devices than the depletion mode GaN HEMT device, and is bound to be more popular in the market. The enhanced device realized by the p-type cap layer technology has been successfully used in the market. For the embodiment, the improvement of the gate withstand voltage and the gate leakage makes it have greater application potential in the field of power electronics requiring high power and high reliability. In general, the device of the embodiment has a very broad application prospect in consumer electronics mobile phone chargers, aerospace, industrial equipment and communication base stations and the like.

[0063] Embodiment two

[0064] On the basis of embodiment one, please refer to Figures 5a-5f , Figures 5a-5f A process diagram of a preparation method of a GaN HEMT device structure with high threshold voltage stability and low gate leakage provided by the embodiment of the application, the method comprising the steps of:

[0065] S1, sequentially prepare a buffer layer 2, a channel layer 3 and a barrier layer 4 on a substrate 1, please refer to Figure 5a .

[0066] First, the substrate is pretreated. Specifically, the operation steps of the pretreatment are: the substrate 1 is ultrasonically cleaned with acetone, anhydrous ethanol solution and deionized water, respectively, and then dried with nitrogen repeatedly, and the substrate 1 is heat treated at 1050℃ in a hydrogen atmosphere for 10 minutes.

[0067] Then, the buffer layer 2 and the channel layer 3 are sequentially prepared on the substrate 1. Specifically, the buffer layer 2 and the channel layer 3 are grown on the substrate 1 by a metal organic chemical vapor deposition (MOCVD) process, the reaction chamber pressure in the MOCVD is 10-100 Torr, the Ga source flow rate is 50-100 μmol / min, the ammonia flow rate is 3000-6000 sccm, the hydrogen flow rate is 1000-2000 sccm, and the temperature is 900°C.

[0068] Finally, the barrier layer 4 is grown on the channel layer 3. Specifically, the barrier layer 4 is grown on the channel layer 3 by MOCVD, the reaction chamber pressure in the MOCVD process is 10-100 Torr, the temperature is 900°C, the Al source flow rate is 10-30 μmol / min, the Ga source flow rate is 30-90 μmol / min, the ammonia flow rate is 3000-6000 sccm, the hydrogen flow rate is 1000-2000 sccm, and an epitaxial wafer is obtained.

[0069] S2, the source electrode 5 is prepared at one end of the barrier layer 4, and the drain electrode 6 is prepared at the other end, please refer to Figure 5b .

[0070] Specifically, a mask is made on the barrier layer 4, the source electrode 6 and the drain electrode 6 are deposited by an electron beam evaporation process, and annealing is performed at a temperature of 860°C under a nitrogen atmosphere for 30 s; the source electrode 5 and the drain electrode 6 are made of a Ti / Al / Ni / Au combination, wherein the thickness of Ti is 20-100 nm, the thickness of Al is 100-300 nm, the thickness of Ni is 20-200 nm, and the thickness of Au is 20-200 nm.

[0071] S3, a pure p-type SnO layer 8 is prepared on part of the barrier layer 4 between the source electrode 6 and the drain electrode 7 by a low-temperature synthesis technique, please refer to Figure 5c .

[0072] Specifically, the low-temperature synthesis technique includes a radio frequency magnetron sputtering method, a direct current sputtering method, an atomic force deposition method, and a sol-gel method, wherein the low temperature is room temperature-100°C.

[0073] Taking the radio frequency magnetron sputtering method as an example, the preparation of the pure p-type SnO layer 8 includes: making a mask on the barrier layer 4, and then placing the epitaxial wafer into a growth chamber to grow a 70-150 nm thick p-type SnO layer 8 by a radio frequency magnetron sputtering method, a pure Sn target is selected, the radio frequency magnetron sputtering process conditions are as follows: in a mixed atmosphere of oxygen and argon, the distance between the target and the substrate is 66 mm, the radio frequency power is set to 50 W, and the growth pressure is 5.7 mTorr. First, pre-sputtering is performed, that is, the vacuum degree in the growth chamber is pumped to 8×10 -4After pre-sputtering for 5 minutes, impurities on the surface of the target are removed. After pre-sputtering, pure p-type SnO is grown by sputtering. The sputtered pure p-type SnO film is sequentially subjected to ultrasonic stripping using acetone and ethanol to obtain the required pure p-type SnO pattern. Finally, the p-type SnO film pattern is obtained by annealing at 225°C in an air environment.

[0074] S4, using a low-temperature synthesis technique, an atomically doped SnO-based film layer 9 is prepared on the upper surface and the two side surfaces of the pure p-type SnO layer 8, as shown in FIG. 4. Figure 5d Specifically, the steps include:

[0075] S41, a mask is made on the barrier layer 4, and then the wafer is pretreated by nitrogen or argon.

[0076] Specifically, a mask of the atomically doped SnO-based film layer 9 is made on the barrier layer 4, and then the wafer is pretreated by nitrogen or argon to achieve better stripping effect.

[0077] In this embodiment, argon is used for pretreatment instead of oxygen before the atomically doped SnO-based film layer is prepared, which avoids the oxidation of the p-type SnO layer by oxygen during the pretreatment process, and further improves the stability of the threshold voltage of the device.

[0078] S42, using a radio frequency magnetron sputtering method, an atomically doped SnO-based film layer 9 is prepared on the upper surface and the two side surfaces of the pure p-type SnO layer 8.

[0079] Specifically, the atomically doped SnO-based film layer 9 is a low-concentration p-type film, and the material includes one or more of Ca x Sn 1-x O, Mg x Sn 1-x O, In x Sn 1-x O, and x is 0.1-0.3; wherein, Ca x Sn 1-x O is Ca x Sn 1- x O doped with Ca atoms, Mg x Sn 1-x O is Mg x Sn 1-x O doped with Mg atoms, In x Sn 1-x O is In x Sn 1-x O doped with In atoms. The concentration of the atomically doped SnO-based film layer 9 is 7×10 17 -9×10 19 cm-3 The thickness of the atom-doped SnO-based thin film layer 9 is 10-40 nm.

[0080] The atom-doped SnO-based thin film layer 9 is doped with Ca atoms Ca x Sn 1-x O layer, the step specifically comprises: placing the epitaxial wafer into a growth chamber to grow a 10-30 nm thick Ca atom-doped Ca x Sn 1-x O layer 9 by radio frequency magnetron sputtering, using a ceramic target composed of CaO and SnO, and the radio frequency magnetron sputtering process conditions are as follows: in a mixed atmosphere of oxygen and argon, the distance between the target and the substrate is 66 mm, the radio frequency power is set to 100 W, and the argon partial pressure is 0.75 Pa. First, pre-sputtering is performed, i.e., the vacuum degree in the growth chamber is pumped to 8×10 -4 Pa below by a vacuum pump, and then pre-sputtering is performed for 5 min to remove impurities on the surface of the target; after the pre-sputtering is completed, the Ca atom-doped Ca x Sn 1-x O layer 9 is grown by formal sputtering. x Sn 1-x O layer 9 is ultrasonically peeled off in sequence using acetone and ethanol to obtain a required Ca atom-doped Ca x Sn 1-x O layer thin film pattern.

[0081] S5, a passivation layer 7 is prepared on the surface of the potential barrier layer 4 between the pure p-type SnO layer 8 and the source electrode 5, on the surface of the potential barrier layer 4 between the pure p-type SnO layer 8 and the drain electrode 6, and on part of the surface of the atom-doped SnO-based thin film layer 9 by using a low-temperature deposition process, please refer to Figure 5e .

[0082] In this embodiment, the low-temperature deposition process includes an inductively coupled plasma chemical vapor deposition process.

[0083] Specifically, the epitaxial wafer is placed in an inductively coupled plasma chemical vapor deposition (ICPCVD) process chamber, the reaction chamber pressure in the ICPCVD process is 5-10 mTorr, the reaction chamber temperature is 120-150°C, and silane and nitrogen gas or silane and ammonia gas are simultaneously introduced into the reaction chamber to obtain a silicon nitride passivation layer 7.

[0084] In this embodiment, the passivation layer is grown by using a low-temperature deposition process during the passivation process, which avoids the oxidation of the p-type SnO layer due to high temperature during the passivation process, and further improves the stability of the threshold voltage of the device.

[0085] S6, a gate electrode 10 is prepared on part of the surface of the atom-doped SnO-based thin film layer 9, please refer to Figure 5f .

[0086] Specifically, the Ca x Sn 1-x A mask is made on the Ca

[0087] In another embodiment, the atomic-doped SnO-based film layer 9 can also be prepared on the upper surface of the pure p-type SnO layer 8 by using a radio frequency magnetron sputtering method in step S4, and the passivation layer 7 and the gate 10 are sequentially prepared on the surface of the device, and the structure prepared is as shown in Figure 1 The embodiment is not described here.

[0088] The embodiment successfully alleviates the problem of unstable threshold voltage caused by the instability of the pure p-type SnO layer by regrowing a Ca x Sn 1-x O thin layer on the original pure p-SnO cap layer, and also improves the gate withstand voltage level of the device and reduces the gate leakage of the device.

[0089] The above is a further detailed description of the present application in combination with the specific preferred embodiments, and the specific implementation of the present application should not be limited to these descriptions. For ordinary skilled persons in the technical field to which the present application belongs, a number of simple deductions or substitutions can be made without departing from the concept of the present application, and all of them should be considered as falling within the protection scope of the present application.

Claims

1. A GaN HEMT device structure with high threshold voltage stability and low gate leakage current, characterized in that, include: Substrate (1), buffer layer (2), channel layer (3), barrier layer (4), source (5), drain (6), passivation layer (7), pure p-type SnO layer (8), atomically doped SnO-based thin film layer (9), and gate (10), wherein, The substrate (1), the buffer layer (2), the channel layer (3), and the barrier layer (4) are stacked sequentially; The source electrode (5) is located at one end of the barrier layer (4), and the drain electrode (6) is located at the other end of the barrier layer (4); The pure p-type SnO layer (8) is located on a portion of the barrier layer (4) between the source (5) and the drain (6); The atomically doped SnO-based thin film layer (9) covers the upper surface of the pure p-type SnO layer (8); the atomically doped SnO-based thin film layer (9) is a low p-type concentration film, with a p-type concentration lower than that of the pure p-type SnO layer (8); the material of the atomically doped SnO-based thin film layer (9) includes Ca. x Sn 1-x O, Mg x Sn 1-x O、In x Sn 1-x One or more of O, x is 0.1-0.3; the concentration of atomic doping in the atomically doped SnO-based thin film layer (9) is 7×10⁻⁶. 17 -9×10 19 cm -3 ; The gate (10) is located on a portion of the surface of the atomically doped SnO-based thin film layer (9); The passivation layer (7) covers the surface of the barrier layer (4) between the pure p-type SnO layer (8) and the source (5), the surface of the barrier layer (4) between the pure p-type SnO layer (8) and the drain (6), and a portion of the surface of the atomically doped SnO-based thin film layer (9).

2. The GaN HEMT device structure with high threshold voltage stability and low gate leakage current according to claim 1, characterized in that, The substrate (1) is made of one or more of sapphire, silicon carbide, silicon, and gallium nitride. The materials of both the buffer layer (2) and the channel layer (3) include gallium nitride; The material of the barrier layer (4) includes Al x Ga 1-x N, x is 0.1-0.25; The material of the passivation layer (7) includes one or more of silicon nitride and silicon dioxide.

3. The GaN HEMT device structure with high threshold voltage stability and low gate leakage current according to claim 1, characterized in that, The thickness of the buffer layer (2) is 1-5 μm; The thickness of the channel layer (3) is 50-500 nm; The thickness of the barrier layer (4) is 10-40 nm; The passivation layer (7) has a thickness of 50-400 nm; The thickness of the pure p-type SnO layer (8) is 70-150 nm.

4. The GaN HEMT device structure with high threshold voltage stability and low gate leakage current according to claim 1, characterized in that, The thickness of the atomically doped SnO-based thin film layer (9) is 10-40 nm.

5. The GaN HEMT device structure with high threshold voltage stability and low gate leakage current according to claim 1, characterized in that, The atomically doped SnO-based thin film layer (9) also covers the sides of the pure p-type SnO layer (8).

6. A method for fabricating a GaN HEMT device structure with high threshold voltage stability and low gate leakage current, characterized in that, Including the following steps: S1. A buffer layer (2), a channel layer (3), and a barrier layer (4) are sequentially prepared on a substrate (1); S2. A source electrode (5) is prepared at one end of the barrier layer (4), and a drain electrode (6) is prepared at the other end. S3. Using low-temperature synthesis technology, a pure p-type SnO layer (8) is prepared on the partial barrier layer (4) between the source (5) and the drain (6); S4. Using a low-temperature synthesis technique, an atomically doped SnO-based thin film layer (9) is prepared on the upper surface of the pure p-type SnO layer (8), or, using a low-temperature synthesis technique, atomically doped SnO-based thin film layers (9) are prepared on the upper surface and side surface of the pure p-type SnO layer (8); the atomically doped SnO-based thin film layer (9) is a thin film with a low p-type concentration, and its p-type concentration is less than that of the pure p-type SnO layer (8); the atomically doped SnO-based thin film layer (9) includes Ca x Sn 1-x O, Mg x Sn 1-x O、In x Sn 1-x One or more of O, x is 0.1-0.3; the concentration of atomic doping in the atomically doped SnO-based thin film layer (9) is 7×10⁻⁶. 17 -9×10 19 cm -3 ; S5. Using a low-temperature deposition process, a passivation layer (7) is prepared on the surface of the barrier layer (4) between the pure p-type SnO layer (8) and the source electrode (5), the surface of the barrier layer (4) between the pure p-type SnO layer (8) and the drain electrode (6), and part of the surface of the atom-doped SnO-based thin film layer (9). S6. A gate (10) is formed on a portion of the surface of the atomically doped SnO-based thin film layer (9).

7. The method for fabricating a GaN HEMT device structure with high threshold voltage stability and low gate leakage current according to claim 6, characterized in that, Step S4 includes: S41. A mask is made on the barrier layer (4), and then nitrogen or argon is used to pre-treat the epitaxial wafer by applying adhesive. S42. Using radio frequency magnetron sputtering, an atomically doped SnO-based thin film layer (9) is prepared on the upper surface of the pure p-type SnO layer (8).

8. The method for fabricating a GaN HEMT device structure with high threshold voltage stability and low gate leakage current according to claim 6, characterized in that, The low-temperature synthesis techniques include radio frequency magnetron sputtering, DC sputtering, atomic force deposition, and sol-gel methods. The low-temperature deposition process includes inductively coupled plasma chemical vapor deposition (ICP-CCVD), in which the reaction chamber temperature is 120-150°C.

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