Trench gate semiconductor device and method of manufacturing the same

Abstract

The application discloses a trench gate semiconductor device and a manufacturing method thereof, and is used for improving the reliability of the trench gate semiconductor. The trench gate semiconductor comprises a substrate with a first conductive type; an epitaxial layer with the first conductive type, which is grown on the substrate; a well region with a second conductive type, which is formed on a surface layer of the epitaxial layer; a source region with the first conductive type, which is formed on a surface layer of the well region; a first trench, which extends from a surface of the source region to the epitaxial layer through the well region; a gate, which is formed in the first trench through a gate insulating film; and an amorphous semiconductor layer, which is formed in the first trench and wraps an outer bottom wall of the gate and corner portions on both sides of the outer bottom wall through the gate insulating film, and the amorphous semiconductor layer is composed of a low dielectric constant material.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of semiconductor technology, and particularly relate to a trench gate semiconductor device and a manufacturing method of the trench gate semiconductor device. BACKGROUND

[0002] The trench gate metal-oxide-semiconductor field-effect transistor (MOSFET) device structure has a higher electron mobility and a smaller JFET resistance effect due to the vertical channel, so that the on-resistance of the trench gate device is much smaller than that of the planar gate device under the same size.

[0003] However, after reverse blocking, the device bears a high voltage, so that the oxide layer at the bottom of the trench gate bears a high electric field, which aggravates the breakdown risk of the oxide layer of the trench gate. SUMMARY

[0004] Embodiments of the present application provide a trench gate semiconductor device and a manufacturing method of the trench gate semiconductor device to improve the reliability of the trench gate semiconductor device.

[0005] The first aspect of the embodiments of the present application provides a trench gate semiconductor device. The trench gate semiconductor device includes a substrate, an epitaxial layer, a well region, a source region, a first trench, a gate, a gate insulating film and an amorphous semiconductor layer. The substrate is of a first conductivity type. The epitaxial layer is of the first conductivity type and is grown on the substrate. The well region is of a second conductivity type and is formed on a surface layer of the epitaxial layer. The source region is of the first conductivity type and is formed on a surface layer of the well region. The first trench extends from the surface of the source region through the well region to the epitaxial layer, and the gate is formed in the first trench through the gate insulating film. The first conductivity type is P-type, and the second conductivity type is N-type. Alternatively, the first conductivity type is N-type, and the second conductivity type is P-type. The P-type conductivity type is formed by doping aluminum ions, boron ions or gallium ions, etc. The N-type conductivity type is formed by doping nitrogen ions or phosphorus ions, etc. The amorphous semiconductor layer is formed in the first trench and wraps the outer bottom wall of the gate and the corner on both sides of the outer bottom wall through the gate insulating film. The amorphous semiconductor layer is composed of a low dielectric constant material. The gate outer wall further wraps the amorphous semiconductor layer of low dielectric constant at the bottom of the gate in addition to the oxide layer, thereby improving the breakdown field strength at the bottom of the trench gate and improving the reliability of the gate oxide layer.

[0006] In some possible implementations, the thickness of the amorphous semiconductor layer is 0.1 um or more.

[0007] In some possible implementation manners, the trench gate semiconductor device further comprises a shielding layer with the second conductivity type, formed on the epitaxial layer at the bottom of the first trench, the shielding layer wraps the amorphous semiconductor layer and extends in a circular arc chamfer to stop on the gate insulating film of the corner or sidewall of the gate. The shielding layer can form a PN junction with the substrate, thereby reducing the voltage borne by the gate insulating film at the corner of the gate and improving the reliability of the trench gate semiconductor device.

[0008] In some possible implementation manners, the junction depth of the shielding layer is greater than or equal to 0.4 um.

[0009] In some possible implementation manners, the corner of the gate is in a circular arc shape in a longitudinal section of the trench gate semiconductor device. In this way, the compression of the electric field lines between the gate and the drain can be reduced, thereby reducing the voltage borne by the gate insulating film at the corner of the gate.

[0010] In some possible implementation manners, the epitaxial layer comprises a first sub-epitaxial layer and a second sub-epitaxial layer, the first sub-epitaxial layer is between the substrate and the second sub-epitaxial layer, the well region, the source region and the amorphous semiconductor layer are formed on the second sub-epitaxial layer, the doping concentration of the first sub-epitaxial layer is less than the doping concentration of the substrate and greater than the doping concentration of the second sub-epitaxial layer. In this way, the on-resistance of the epitaxial layer can be reduced.

[0011] In some possible implementation manners, the trench gate semiconductor device further comprises: a contact region with the second conductivity type, connected to the well region, the doping concentration of the contact region is greater than the doping concentration of the well region; a source electrode connected to the source region and the contact region; and a drain electrode connected to the substrate away from the epitaxial layer. The surface doping concentration of the contact region is greater than the surface doping concentration of the well region, and the contact region is used to be connected to the source electrode. In this way, the resistivity of the well region can be reduced.

[0012] In some possible implementation manners, the semiconductor material constituting the substrate and the epitaxial layer is silicon carbide, and / or the amorphous semiconductor is amorphous silicon carbide. Silicon carbide has superior physical properties such as wide band gap, high critical breakdown field strength and large thermal conductivity, so that the silicon carbide semiconductor device has advantages such as high voltage resistance, high temperature resistance, fast switching speed and small switching loss.

[0013] The second aspect of the embodiment of the present application provides a manufacturing method of a trench gate semiconductor device, which comprises the following steps: depositing an epitaxial layer with a first conductive type on a substrate with the first conductive type; implanting ions with a second conductive type on a surface layer of the epitaxial layer to form a well region; implanting ions with the first conductive type on a surface layer of the well region to form a source region; performing photoetching on a surface of the source region to form a first trench extending through the well region to the epitaxial layer; implanting ions with the second conductive type on a bottom wall and a corner of the first trench to form an amorphous semiconductor layer; and growing a gate insulating film in the first trench and depositing and doping to form a gate of a polysilicon gate structure. The ion implantation is performed on the bottom of the trench after the trench is formed, so that the junction depth of the amorphous semiconductor layer is not high, the process is simple, the performance parameters of the process equipment are low, and the manufacturing cost is low.

[0014] In some possible implementation manners, before the ions are implanted on the bottom wall and the corner of the first trench to form the amorphous semiconductor layer, the method further comprises the following steps: depositing a mask film on the side wall of the first trench; and implanting ions with the second conductive type on the bottom wall and the corner of the first trench to form a shielding layer, wherein the implantation depth of the shielding layer is greater than the implantation depth of the amorphous semiconductor layer, and the doping concentration of the shielding layer is less than the doping concentration of the amorphous semiconductor layer.

[0015] In some possible implementation manners, the implantation junction depth of the shielding layer is greater than or equal to 0.4 um.

[0016] In some possible implementation manners, the thickness of the amorphous semiconductor layer is greater than or equal to 0.1 um.

[0017] In some possible implementation manners, the corner of the gate is in the form of a circular arc in the longitudinal section of the trench gate semiconductor device. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 FIG. 1 is a structural schematic diagram of an embodiment of a trench gate semiconductor device provided by the present application;

[0019] Figure 2 FIG. 1 is a structural schematic diagram of an embodiment of a trench gate semiconductor device provided by the present application;

[0020] Figure 3 FIG. 1 is a structural schematic diagram of an embodiment of a trench gate semiconductor device provided by the present application;

[0021] Figure 4 FIG. 1 is a structural schematic diagram of an embodiment of a trench gate semiconductor device provided by the present application; DETAILED DESCRIPTION

[0022] The embodiment of the present application provides a trench gate semiconductor device and a manufacturing method of the trench gate semiconductor device, so as to improve the reliability of the trench gate semiconductor device.

[0023] Please see Figure 1 , Figure 1 This is a schematic diagram of an embodiment of the trench gate semiconductor device provided in this application. It can be understood that... Figure 1 The thickness and width of each region are merely examples and are not intended to limit the structure of the trench gate semiconductor in this application. Figure 1 The trench gate semiconductor device shown comprises multiple semiconductor devices with the same structure arranged in a strip, square, hexagonal, or atomic lattice arrangement to form a multi-cell semiconductor device. The trench gate semiconductor 100 of this embodiment includes a substrate 11, an epitaxial layer 12, a well region 13, a source region 14, a first trench 15, a gate 16, a gate insulating film 17, an amorphous semiconductor layer 18, a contact region 19, a source 20, and a drain 21.

[0024] In this design, substrate 11 is of the first conductivity type. Epitaxial layer 12 is grown on substrate 11 and is also of the first conductivity type. Well region 13 is formed on the surface of epitaxial layer 12 and is of the second conductivity type. Source region 14 is formed on the surface of well region 13 and is of the first conductivity type. First trench 15 extends from the surface of source region 14 through well region 13 to epitaxial layer 12. Gate 16 is formed in first trench 15 with a gate insulating film 17 in between. Amorphous semiconductor layer 18 is formed in first trench 15 and surrounds the outer bottom wall and corners on both sides of gate 16 with the gate insulating film 17 in between. Source region 14 and well region 13 are located on both sides of gate 16, and contact region 19 is located on the side of source region 14 and / or well region 13 away from gate 16. Contact region 19 is connected to well region 13, source 20 is connected to source region 14 and contact region 19, and drain 21 is connected to the side of substrate 11 away from epitaxial layer 12.

[0025] In this embodiment, the first conductivity type can be N-type, the second conductivity type can be P-type, and the trench gate semiconductor device 100 is an inversion trench gate metal-oxide-semiconductor field-effect transistor (MOSFET) device with an N-channel. Alternatively, the first conductivity type can be P-type, the second conductivity type can be N-type, and the trench gate semiconductor device 100 can be a MOSFET device with a P-channel. This application uses an example where the first conductivity type is N-type and the second conductivity type is P-type for illustration.

[0026] The substrate 11 is doped with N-type impurities such as nitrogen ions or phosphorus ions to achieve a resistivity of 0.01-0.025 Ω·cm. The thickness of the substrate 11 is approximately 150 micrometers (µm), specifically, for example, 145µm, 150µm, or 155µm.

[0027] The doping concentration of N-type ions of the epitaxial layer 12 is lower than the doping concentration of N-type ions of the substrate 11. The thickness of the epitaxial layer 12 is about 11 um, for example, 10.5 um, 11 um, 11.5 um or 12 um.

[0028] Optionally, the epitaxial layer 12 can include a first sub-epitaxial layer 121 and a second sub-epitaxial layer 122. The first sub-epitaxial layer 121 is located between the substrate 11 and the second sub-epitaxial layer 122. The well region 13, the source region 14 and the amorphous semiconductor layer 18 are formed on the second sub-epitaxial layer 122. The doping concentration of the first sub-epitaxial layer 121 is lower than the doping concentration of the substrate 11 and higher than the doping concentration of the second sub-epitaxial layer 122. The thickness of the first sub-epitaxial layer 121 is about 0.5 um, for example, 0.4 um, 0.5 um or 0.6 um. The thickness of the second sub-epitaxial layer 122 is about 11 um, for example, 10 um, 10.6 um, 11 um or 11.4 um. The doping concentration of the first sub-epitaxial layer 121 can be a single concentration, a step concentration or a gradual concentration. When the doping concentration of the first sub-epitaxial layer 121 is a step concentration or a gradual concentration, the doping concentration near the substrate 11 is higher than the doping concentration away from the substrate 11. In this way, the on-resistance of the epitaxial layer 12 can be reduced.

[0029] The well region 13 is formed by ion implantation on the surface layer of the epitaxial layer 12. The implanted ions can be P-type impurities such as aluminum ions, boron ions or gallium ions. The implanted concentration of P-type impurities of the well region 13 is uniformly distributed, the implanted junction depth is greater than or equal to 0.5 um, and the implanted junction depth is less than the thickness of the second sub-epitaxial layer 122.

[0030] The source region 14 is formed by ion implantation on the surface layer of the well region 13. The implanted ions can be N-type impurities such as nitrogen ions or boron ions. The surface implanted concentration of N-type impurities of the source region 14 is greater than 1.0×10 19 / cm 3 , and the implanted junction depth is about 0.2 um. The thickness of the source region 14 can be, for example, 0.18 um, 0.19 um, 2 um or 2.1 um.

[0031] The contact region 19 and the well region 13 are both P-type and have a connection relationship. The contact region 19 is used to connect with the source electrode 20. The surface doping concentration of the contact region 19 is greater than 1.0×10 19 / cm 3 , which is greater than the doping concentration of the well region 13. In this way, the resistivity of the well region 13 can be reduced, and the avalanche energy and the reliability of the semiconductor device can be improved.

[0032] In some embodiments, the contact region 19 can be formed by selectively implanting P-type impurities, such as aluminum ions, boron ions or gallium ions, into the surface layer of the epitaxial layer 12, and the implantation junction depth is greater than that of the source region 14, so that the contact region 19 is connected to the well region 13. In this case, the surface layer of the contact region 19 is flush with the surface layer of the source region 14, and the manufacturing process is relatively simple.

[0033] In other embodiments, the contact region 19 can also be formed by implanting P-type impurities into the vicinity of the well region 13 after etching the epitaxial layer 12 to form a second trench (not shown). The source electrode 20 extends into the second trench to connect to the contact region 19, thereby realizing a trench-type contact, which can reduce the distance between the source and the drain, thereby reducing the on-resistance of the trench gate semiconductor device 100.

[0034] Optionally, the source region 14, the well region 13 and the contact region 19 are symmetrically distributed on both sides of the first trench 15.

[0035] The first trench 15 is formed by selectively performing photolithography and etching on the surface of the source region 14, and the etching depth is greater than the sum of the depths of the source region 14 and the well region 13, so that the first trench 15 penetrates the source region 14 and the well region 13 from the surface of the source region 14 to the epitaxial layer 12. The depth of the first trench 15 is greater than 0.7 um and less than the sum of the thicknesses of the second epitaxial layer 122, the well region 13 and the source region 14. The sidewall of the first trench 15 is perpendicular or substantially perpendicular to the surface of the source region 14, and the bottom wall of the first trench 15 is parallel or substantially parallel to the surface of the source region 14. The corner of the first trench 15 is in a circular arc shape, that is, the circular arc transitions at the junction of the sidewall and the bottom wall of the first trench 15, so as to reduce the compression of the electric field between the gate 16 and the drain 21 by the corner of the first trench 15, reduce the electric field of the corner of the first trench 15, and improve the reliability of the trench gate.

[0036] The amorphous semiconductor layer 18 is formed by low-temperature implantation of boron ions into the epitaxial layer 12 exposed on the bottom wall and at least part of the corner of the first trench 15, so that the amorphous semiconductor layer 18 covers the bottom wall and at least part of the corner of the first trench 15. The boron ion implantation concentration of the amorphous semiconductor layer 18 is 1.0×10 14 / cm 3 , and the thickness of the amorphous semiconductor is greater than or equal to 0.1 um. The amorphous semiconductor layer 18 has a low dielectric constant and exhibits insulating or semi-insulating properties. The amorphous semiconductor layer 18 can be composed of a material with a dielectric constant of about 8.9, which can be amorphous silicon carbide, and can also be other amorphous semiconductor materials that meet the dielectric constant requirement, which is not limited in the present application. Amorphous silicon carbide has the characteristics of high electron mobility, fast saturated electron drift speed and high breakdown field strength, thereby improving the reliability of the trench gate semiconductor device 100.

[0037] The substrate 11 and the epitaxial layer 12 can also be made of silicon carbide material. Silicon carbide has a wide band gap, high critical breakdown field strength, high thermal conductivity, and other superior physical properties, so that the silicon carbide semiconductor device has the advantages of high voltage resistance, high temperature resistance, fast switching speed, and small switching loss. Of course, the substrate and the epitaxial layer can also be made of other wide band gap materials such as gallium nitride, and the present application does not limit this.

[0038] The gate insulating film 17 is grown to cover the side wall, bottom wall and corner of the first trench 15, for isolating the gate 16 from the epitaxial layer 12, the well region 13 and the source region 14. The thickness of the gate insulating film 17 is greater than 50 nanometers (nm) and less than one half of the width of the first trench 15, that is, the gate insulating film 17 cannot completely fill the first trench 15. The thickness of the gate insulating film 17 is specifically, for example, 50 nm, 55 nm or 60 nm, etc. The gate insulating film 17 can specifically be a silicon dioxide film, a silicon nitride film or a low dielectric constant film, etc.

[0039] The gate 16 is formed by depositing polysilicon on the surface of the gate insulating film 17 in the first trench 15, and the gate 16 completely fills the first trench 15. Since the corner of the first trench 15 is in the shape of a circular arc, the gate 16 and the gate insulating film 17 are also in the shape of a circular arc, thereby reducing the field strength of the gate insulating film 17 at the corner of the gate 16 and improving the reliability of the gate insulating film 17. Moreover, the amorphous semiconductor layer 18 wraps the gate insulating film 17 at the corner and the bottom wall of the gate 16, which can improve the breakdown field strength of the gate insulating film 17.

[0040] The source 20 is specifically made by depositing metal on the source region 14 and the contact region 19, and the drain 21 is made by depositing metal on the side away from the epitaxial layer 12. The conduction or turn-off of the gate semiconductor device of the first trench 15 is realized by applying voltage to the source 20, the drain 21 and the gate 16.

[0041] In some other embodiments, in order to further improve the reliability of the trench gate semiconductor device 100, the trench gate semiconductor device further includes a shielding layer 22. The shielding layer 22 is formed by implanting P-type impurities on the epitaxial layer 12 corresponding to the bottom wall and the corner of the first trench 15, and the implantation junction depth is greater than the ion implantation junction depth of the amorphous semiconductor and less than the distance from the bottom wall of the first trench 15 to the first sub-epitaxial layer 121. The implantation junction depth of the shielding layer 22 is, for example, 0.4 um, 0.5 um, 0.6 um or 0.7 um, etc. The doping concentration of the shielding layer is 4.0 x 10 13 / cm 3The doping concentration of the shielding layer 22 is greater than that of the second sub-epitaxial layer 122, so that the shielding layer 22 is N-type ion-containing, and the conductive type of the shielding layer 22 is P-type. Since the conductive type of the shielding layer 22 is P-type and the conductive type of the epitaxial layer 12 is N-type, the shielding layer 22 and the epitaxial layer 12 can form a PN junction, thereby avoiding the electric field from concentrating on the gate insulating film 17 at the corner of the gate 16 and reducing the field strength borne by the gate insulating film 17.

[0042] The implantation range of the shielding layer 22 is greater than the implantation range of the amorphous semiconductor layer 18, so that the shielding layer 22 can wrap the amorphous semiconductor layer 18 and extend in a circular arc chamfer to stop on the gate insulating film 17 at the corner or sidewall of the gate 16. In this way, the gate insulating film 17 at the corner of the gate 16 is wrapped in multiple layers, which can improve the breakdown field strength of the gate insulating film 17 and thereby improve the reliability of the trench gate semiconductor device 100.

[0043] Please refer to Figure 2 , Figure 2 is a flowchart of an embodiment of a manufacturing method of a trench gate semiconductor device provided by the present application. The manufacturing method of the present embodiment is used to manufacture the trench gate semiconductor device described above. When a single-trench trench gate semiconductor device is manufactured, the present embodiment includes the following steps:

[0044] 201: Depositing an epitaxial layer having a first conductive type on a substrate having the first conductive type.

[0045] In the present application, the first conductive type can be N-type and the second conductive type can be P-type. Of course, the first conductive type can also be P-type and the second conductive type can be N-type. The present embodiment is described by taking the first conductive type as N-type and the second conductive type as P-type as an example.

[0046] In the present embodiment, the substrate and the epitaxial layer can both be composed of silicon carbide material. Silicon carbide has high critical avalanche breakdown field strength and carrier saturation drift speed, high thermal conductivity and carrier mobility, which can enable the trench gate semiconductor device to have the ability to withstand high voltage, low on-state resistance, good heat dissipation performance and thermal stability, and strong ability to withstand high temperature and radiation. Of course, the substrate and the epitaxial layer can also be composed of other wide-bandgap materials such as gallium nitride, which is not limited by the present application.

[0047] A first sub-epitaxial layer with a thickness of about 0.5 um is grown on a N+ (heavily doped with N-type impurities) substrate with a resistivity of 0.01-0.025 Ω.cm, and N-type impurities (such as nitrogen ions or phosphorus ions, etc.) with a lower concentration than the substrate are implanted into the first sub-epitaxial layer so that the first sub-epitaxial layer has an N-type conductivity. Then a second sub-epitaxial layer with a thickness of about 11 um is grown on the first sub-epitaxial layer, and N-type impurities with a lower concentration than the first sub-epitaxial layer are implanted into the first sub-epitaxial layer so that the second sub-epitaxial layer also has an N-type conductivity.

[0048] 202: Ions of the second conductivity type are implanted into the surface layer of the epitaxial layer to form a well region.

[0049] Specifically, a silicon dioxide medium layer with a thickness of about 1.5 um is deposited on the second sub-epitaxial layer for masking, and then the silicon dioxide medium layer on the surface of the second sub-epitaxial layer is selectively removed by using photolithography and etching processes to form a well region implantation window, and the silicon dioxide medium layer that is not etched is used as a masking layer for ion implantation. Dry etching can be used so that the etching is performed in a direction perpendicular to the surface of the second sub-epitaxial layer.

[0050] P-type ions are implanted into the second sub-epitaxial layer through the well region implantation window by using an ion implantation method to form a well region with a uniform distribution of concentration and a junction depth greater than 0.5 um. Ion implantation is to make ionized elements collide with the epitaxial layer under high acceleration voltage so that the ions physically invade the crystal lattice of the epitaxial layer.

[0051] 203: Ions of the first conductivity type are implanted into the surface layer of the well region to form a source region.

[0052] Specifically, the remaining silicon dioxide medium layer on the surface of the wafer (i.e., the trench gate semiconductor device in a processing state) is removed, a silicon dioxide medium layer with a thickness of about 1.5 um is deposited again, and the silicon dioxide medium layer on the surface of the second sub-epitaxial layer is selectively removed by using photolithography and etching processes to form a source region implantation window on the surface of the well region.

[0053] N-type impurities such as nitrogen ions are implanted into the second sub-epitaxial layer through the source region implantation window by using an ion implantation method to form an N-type source region with a surface implantation concentration greater than 1.0 x 10 19 / cm 3 and a junction depth of 0.2 um.

[0054] 204: A contact region is formed on the surface of the epitaxial layer.

[0055] The remaining silicon dioxide medium layer on the surface of the wafer is removed, a silicon dioxide medium layer with a thickness of about 1.5 um is deposited again, and the silicon dioxide medium layer on the surface of the second sub-epitaxial layer is selectively removed by using photolithography and etching processes to form a contact region implantation window, and the implantation window of the contact region does not coincide with the surface of the source region.

[0056] The P-type impurities such as boron ions or aluminum ions are implanted into the second sub-epitaxial layer through the contact region by ion implantation to form a contact region with a surface implantation concentration greater than 1.0 x 10 19 / cm 3 and a junction depth greater than that of the source region. The P-type ion implantation concentration of the contact region is greater than that of the well region.

[0057] Since high-energy ions can damage the crystal lattice of the wafer during ion implantation, after the contact region is formed, the silicon dioxide medium layer on the wafer surface is removed, a 20 nm carbon film medium is deposited, and the wafer is subjected to high-temperature annealing treatment to recover the crystal lattice and activate the ions implanted into the epitaxial layer, the well region, the source region, and the contact region. The annealing treatment is specifically, for example, rapid thermal anneal (RTA), which can reduce the wafer heating and cooling time, improve the activation efficiency, and also inhibit the change in impurity distribution and avoid impurity diffusion to other regions. The annealing temperature is greater than or equal to 1600 degrees and less than the melting point of the substrate and the epitaxial layer. The annealing temperature is specifically, for example, 1600 degrees, 1700 degrees, 1750 degrees, etc.

[0058] The carbon film is used to suppress the roughening of the wafer surface during high-temperature annealing, and the carbon film is removed after annealing by plasma etching.

[0059] 205: A first trench extending through the well region to the epitaxial layer is formed on the surface of the source region by lithography.

[0060] A 1.5 um or so silicon dioxide medium layer is deposited on the wafer surface, and part of the silicon dioxide medium layer on the wafer surface is selectively removed by lithography, etching, and other processes to form a trench gate etching window.

[0061] The source region exposed by the trench gate etching window is etched by inductively coupled plasma (ICP) technology to form a first trench extending through the source region, the well region, and to the second sub-epitaxial layer.

[0062] ICP can provide high-speed, high-selectivity, and low-damage etching, and the plasma can remain stable at low pressure, so that the etching morphology can be better controlled to form a straight sidewall and bottom wall without micro-trench morphology.

[0063] 206: The ions of the second conductivity type are implanted into the bottom wall and bottom corner of the first trench to form an amorphous semiconductor layer.

[0064] Specifically, a 1.2um or so silicon dioxide dielectric layer is deposited on the wafer surface, a trench gate process window is etched by using photolithography and etching process, a 100nm or so silicon dioxide dielectric layer is deposited on the wafer, boron ions are injected to the bottom wall and corner of the first trench by ion implantation, the boron ion implantation concentration is 1.0x10 14 / cm 3 , the implantation junction depth is greater than or equal to 0.1um, and the implantation temperature is less than 50 degrees, thereby forming an amorphous semiconductor layer.

[0065] 207: growing a gate insulation film in the first trench and depositing and doping to form a gate of a polysilicon gate structure.

[0066] Before growing the gate insulation film, a greater than 20nm sacrificial oxide layer is formed on the wafer surface (including the first trench) by high temperature oxidation. Then the sacrificial oxide layer is removed by using a wet process, thereby reducing the roughness of the wafer surface and making the wafer surface smooth.

[0067] A 300nm or so silicon dioxide dielectric layer is deposited on the wafer surface, and the active area of the gate (i.e. the area corresponding to the first trench on the wafer surface) is etched by using photolithography, etching and other processes. A 50nm gate insulation film is grown on the wafer surface by high temperature oxidation, a 500nm polysilicon is deposited in the first trench by using low pressure chemical vapor phase method, the polysilicon is in-situ doped, the thin film sheet resistance is less than 30Ω / □, and a polysilicon gate structure is formed by using photolithography and etching process.

[0068] 208: performing ohmic contact embedding and wiring processing on the wafer.

[0069] Specifically, a silicon dioxide dielectric layer of approximately 100 nm and an 800 nm boro-phospho-silicate glass (BPSG) layer are sequentially deposited on the wafer surface, followed by high-temperature reflow at 980 °C. The BPSG layer exhibits fluidity at high temperatures, enabling wafer surface planarization. Next, another silicon dioxide dielectric layer of approximately 100 nm is deposited, and ohmic contact hole process windows are formed using photolithography and etching processes. A nickel (Ni) layer is deposited on the wafer surface, and the Ni layer is annealed using a rapid thermal process (RTP). A nickel-silicon alloy (NiSi) is formed on the wafer surface exposed by the ohmic contact hole process windows, and then the unalloyed Ni layer is removed by self-alignment using acid pickling. A layer of aluminum-copper (AlCu) alloy of approximately 5 μm is sputtered, and metal electrodes are formed using photolithography and etching processes. Finally, a silicon dioxide or silicon nitride dielectric layer and a polyimide thin film layer are deposited on the wafer surface, and the front source and gate electrodes are formed using photolithography and etching processes. The back side of the wafer (i.e., the side of the substrate away from the epitaxial layer) is thinned to about 150um using processes such as etching or grinding and polishing. A layer of Ni metal is evaporated from the back side of the wafer and then annealed at high speed using a laser to form a NiSi alloy. A multilayer metal of titanium / nickel / silver (Ti / Ni / Ag) is evaporated from the back side of the wafer to form the back electrode (i.e., the drain electrode).

[0070] In other implementations, such as Figure 3 As shown, Figure 3 This is a schematic flowchart of another embodiment of the manufacturing method for the trench gate semiconductor device provided in this application. If the trench gate semiconductor device further includes a shielding layer, the manufacturing process is as follows:

[0071] 301: Deposit an epitaxial layer having a first conductivity type on a substrate having a first conductivity type.

[0072] 302: Ionizing ions of a second conductivity type on the surface of the epitaxial layer to form a trap region.

[0073] 303: Ionization of the first conductivity type is performed on the surface of the well region to form a source region.

[0074] Steps 301-303 are the same as steps 201-203, so they will not be repeated here.

[0075] 304: A contact area is formed on the surface of the epitaxial layer.

[0076] Unlike 204, this step does not involve high-temperature annealing of the wafer after the contact area is formed.

[0077] 305: A first trench extending through the well region and into the epitaxial layer is formed by photolithography on the surface of the source region.

[0078] 306: Ions of a second conductivity type are injected into the bottom wall and corners of the first trench to form a shielding layer.

[0079] A masking film was deposited on the sidewalls of the first trench. A 100 nm thick silicon dioxide dielectric layer was deposited on the wafer surface using plasma-enhanced chemical vapor deposition (PECVD). Ion implantation was then used to implant 4.0 × 10⁻⁶ ions into the bottom and corners of the first trench. 13 / cm 3 P-type ions with a junction depth greater than 0.4 μm.

[0080] After forming the shielding layer, all surface dielectric is removed, and a 20nm carbon film is deposited. The wafer is then subjected to high-temperature annealing to activate ions implanted into the epitaxial layer, well region, source region, contact region, and shielding layer. Specific annealing processes, such as RTA or RTP, can reduce wafer heating and cooling times, improve activation efficiency, and the short time also suppresses impurity distribution changes, preventing impurities from diffusing to other areas. The annealing temperature is greater than or equal to 1600 degrees Celsius and less than the melting points of the substrate and epitaxial layer. Specific annealing temperatures can be, for example, 1600 degrees Celsius, 1700 degrees Celsius, or 1750 degrees Celsius. The carbon film is used to suppress surface roughening during high-temperature annealing. After annealing, the carbon film is removed using plasma etching.

[0081] 307: Ion of a second conductivity type is injected into the bottom wall and bottom corner of the first trench to form an amorphous semiconductor layer.

[0082] 308: A gate insulating film is grown in the first trench and deposited and doped to form a polysilicon gate structure.

[0083] 309: Ohmic contact embedding and wiring treatment for wafers.

[0084] Steps 307-309 are similar to steps 206-208, so they will not be repeated here.

[0085] For dual-trench trench gate semiconductor devices, such as Figure 4 As shown, Figure 4 This is a schematic flowchart of another embodiment of the manufacturing method of the trench gate semiconductor device provided in this application. The manufacturing process of this embodiment is as follows:

[0086] 401: Deposit an epitaxial layer having a first conductivity type on a substrate having a first conductivity type.

[0087] 402: Ionizing ions of a second conductivity type on the surface of the epitaxial layer to form a trap region.

[0088] 403: Forming a source region by implanting ions of the first conductivity type on the surface layer of the well region.

[0089] Steps 401-403 are the same as steps 301-303, and thus are not described again here.

[0090] 404: Forming double trenches on the surface of the source region by lithography.

[0091] The first trench is used for forming a gate therein, and the second trench is used for forming a contact region at the bottom thereof and generating a partial source in the second trench.

[0092] The first trench and the second trench can be etched simultaneously or separately. The depth of the first trench is greater than the sum of the thicknesses of the source region and the well region. The depth of the second trench is greater than the depth of the source region and less than the sum of the thicknesses of the source region and the well region, so that the contact region formed at the bottom wall of the second trench is connected with the well region.

[0093] 405: Forming a contact region at the bottom of the second trench.

[0094] A 1.5-um-thick silicon dioxide dielectric layer is deposited on the surface of the wafer, and part of the silicon dioxide dielectric layer on the surface of the wafer is selectively removed by lithography and etching to form a contact region implantation window, i.e., the bottom wall of the second trench.

[0095] A P-type impurity such as boron ions or aluminum ions is implanted into the bottom wall of the second trench through the contact region implantation window by ion implantation to form a contact region with a surface implantation concentration greater than 1.0×10 19 / cm 3 The P-type impurity implantation concentration of the contact region is greater than the ion implantation concentration of the well region.

[0096] 406: Forming a shielding layer by implanting ions of the second conductivity type on the bottom wall and the corner of the trench.

[0097] 407: Forming an amorphous semiconductor layer by implanting ions of the second conductivity type on the bottom wall and the bottom corner of the trench.

[0098] 408: Growing a gate insulating film in the trench and depositing and doping to form a gate of a polysilicon gate structure.

[0099] 409: Performing ohmic contact embedding and wiring processing on the wafer.

[0100] Steps 406-409 are similar to steps 306-309, and thus are not described again here.

[0101] The trench gate semiconductor device provided by the application adopts a vertical trench gate structure, improves the channel mobility by changing the channel direction, and can reduce the specific on-resistance. Meanwhile, the trench gate structure can reduce the cell size, improve the current density, and reduce the specific on-resistance. The P+ shielding layer and amorphous semiconductor layer at the bottom of the trench bear the reverse voltage, reduce the electric field of the gate oxide film, and improve the long-term use reliability of the gate oxide film. The device manufacturing method provided by the application has simple manufacturing process, can perform ion implantation on the bottom of the trench after the trench is formed, the junction depth of the P+ shielding layer and amorphous semiconductor layer is not high, the process equipment performance parameters are low, and the manufacturing cost is low.

[0102] In the above-described embodiments, an example of a case where the application is applied is described, but design changes and the like can be appropriately made. For example, in the above-described embodiments, the oxide film formed by thermal oxidation is given as an example of the gate insulating film, but a film including an oxide film or a nitride film that is not formed by thermal oxidation or the like can also be used. Furthermore, the etching of the first trench can also be performed before the formation of the well region or the source region or the contact region, and the like.

[0103] The application has been described based on the embodiments, but it should be understood that the application is not limited to the embodiments and the configurations. The application also includes various modifications and modifications within the equivalent range. Furthermore, various combinations and modes, and other combinations and modes in which elements are added or deleted, are also included in the scope and the idea range of the application.

Claims

1. A trench gate semiconductor device, characterized by, The trench gate semiconductor device comprises: a substrate with a first conductivity type; an epitaxial layer with the first conductivity type grown on the substrate; a well region with a second conductivity type formed on a surface layer of the epitaxial layer; a source region with the first conductivity type formed on a surface layer of the well region; a first trench extending from a surface of the source region through the well region to the epitaxial layer; a gate formed in the first trench through a gate insulating film; an amorphous semiconductor layer formed in the first trench and wrapping an outer bottom wall of the gate and corners on both sides of the outer bottom wall through the gate insulating film, the amorphous semiconductor layer is composed of a low dielectric constant material, the outer bottom wall of the gate is used to wrap an oxide layer and the amorphous semiconductor layer, and the amorphous semiconductor layer is composed of an amorphous semiconductor material meeting a dielectric constant requirement.

2. The trench gate semiconductor device according to claim 1, wherein The thickness of the amorphous semiconductor layer is greater than or equal to 0.1 um.

3. The trench-gate semiconductor device according to claim 1 or 2, characterized by, The trench gate semiconductor device further comprises: a shielding layer with the second conductivity type formed on the epitaxial layer at the bottom of the first trench, the shielding layer wraps the amorphous semiconductor layer and extends in a circular arc chamfer to stop on the gate insulating film at the corner or sidewall of the gate.

4. The trench gate semiconductor device according to Claim 3, wherein The junction depth of the shielding layer is greater than or equal to 0.4 um.

5. The trench gate semiconductor device according to any one of claims 1 to 2, characterized by, The corner of the gate is in a circular arc shape in a longitudinal section of the first trench gate semiconductor device.

6. The trench gate semiconductor device according to any one of claims 1 to 2, characterized by, The epitaxial layer comprises a first sub-epitaxial layer and a second sub-epitaxial layer, the first sub-epitaxial layer is between the substrate and the second sub-epitaxial layer, the well region, the source region and the amorphous semiconductor layer are formed on the second sub-epitaxial layer, the doping concentration of the first sub-epitaxial layer is less than the doping concentration of the substrate and greater than the doping concentration of the second sub-epitaxial layer.

7. The trench gate semiconductor device according to any one of claims 1 to 2, characterized by, The trench gate semiconductor device further comprises: a contact region with the second conductivity type connected with the well region, the doping concentration of the contact region is greater than the doping concentration of the well region; a source electrode connected with the source region and the contact region; a drain electrode connected with the substrate away from the epitaxial layer.

8. The trench gate semiconductor device according to any one of claims 1 to 2, characterized by, The first conductivity type is N type and the second conductivity type is P type; or The first conductivity type is P type and the second conductivity type is N type.

9. The trench gate semiconductor device according to any one of claims 1 to 2, characterized by, The semiconductor material constituting the substrate and the epitaxial layer is silicon carbide, and / or the amorphous semiconductor is amorphous silicon carbide.

10. A method of manufacturing a trench gate semiconductor device, characterized by, The manufacturing method comprises: depositing an epitaxial layer with a first conductivity type on a substrate with the first conductivity type; implanting ions of a second conductivity type on a surface layer of the epitaxial layer to form a well region; implanting ions of the first conductivity type on a surface layer of the well region to form a source region; lithographically forming a first trench extending through the well region to the epitaxial layer on the surface of the source region; implanting ions of the second conductivity type on a bottom wall and a bottom corner of the first trench to form an amorphous semiconductor layer, the bottom wall of the first trench is used to wrap an oxide layer and the amorphous semiconductor layer, and the amorphous semiconductor layer is composed of an amorphous semiconductor material meeting a dielectric constant requirement; growing a gate insulating film in the first trench and depositing and doping to form a gate of a polysilicon gate structure.

11. The manufacturing method according to claim 10, wherein The thickness of the amorphous semiconductor layer is greater than or equal to 0.1 um.

12. The manufacturing method according to claim 10 or 11, characterized by, Before the amorphous semiconductor layer is formed by implanting ions into the bottom wall and part of the sidewall of the first trench, the method comprises: depositing a mask film on the sidewall of the first trench; forming a shielding layer by implanting ions of the second conductive type into the bottom wall and the corner of the first trench, the implantation depth of the shielding layer being greater than the implantation depth of the amorphous semiconductor layer, and the doping concentration of the shielding layer being less than the doping concentration of the amorphous semiconductor layer.

13. The manufacturing method according to claim 12, wherein The implantation junction depth of the shielding layer is greater than or equal to 0.4 um.

14. The production method according to any one of claims 10 to 11, characterized by, The corner of the gate is in the shape of a circular arc in the longitudinal section of the trench gate semiconductor device.

Images