Board transfer equipment and test method, system, device, equipment and storage medium

Abstract

Embodiments of the present disclosure provide a board card adapter device, a testing method, a system, a device, equipment, and a storage medium. Among them, the board card adapter device includes: a first adapter structure, a second adapter structure, and a signal transmission structure; the first adapter structure has a gold finger matching the board card of the target storage module; the second adapter structure has a connector matching the gold finger; the signal transmission structure includes: a first transmission module for correspondingly connecting the data signal line, clock signal line, address signal line, and control signal line of the gold finger to the corresponding connection lines in the connector; a second transmission module for converting the power input signal into a power output signal matching the power supply of the target storage module and transmitting the power output signal to the power signal line of the connector when the power input signal is accessed. In the embodiments of the present disclosure, the flexibility and accuracy of storage module testing can be improved, and it is convenient to test the storage module on various system platforms.

Description

Technical Field

[0001] The present disclosure relates to, but is not limited to, the field of semiconductor testing, and in particular, to a board card transfer device, a testing method, a system, a device, an equipment, and a storage medium. Background Art

[0002] In related technologies, there are few means to test a storage module. Usually, an Automatic Test Equipment (ATE) or a Central Processing Unit (CPU) motherboard is used for testing. However, the method of using an ATE or a CPU motherboard to test a storage module has a high cost and cannot accurately analyze the problems existing in the storage module during actual application. Summary of the Invention

[0003] In view of this, embodiments of the present disclosure provide a board card transfer device, a testing method, a system, a device, an equipment, and a storage medium.

[0004] The technical solution of the embodiments of the present disclosure is implemented as follows:

[0005] Embodiments of the present disclosure provide a board card transfer device, including: a first transfer structure, a second transfer structure, and a signal transmission structure; wherein,

[0006] The first transfer structure has a gold finger matching the board card of the target storage module;

[0007] The second transfer structure has a connector matching the gold finger;

[0008] The signal transmission structure includes a first transmission module and a second transmission module; the first transmission module is used to correspondingly connect the data signal line, the clock signal line, the address signal line, and the control signal line of the gold finger with the corresponding connection lines in the connector; the second transmission module is used to convert the power input signal into a power output signal matching the power supply of the target storage module and transmit the power output signal to the power signal line of the connector when a power input signal is accessed.

[0009] In some embodiments, the power signal line of the gold finger is floating and / or the reset signal line of the gold finger is floating.

[0010] In some embodiments, the second transmission module includes a power interface and a power conversion unit; wherein, the power interface is configured to connect to an external power supply and transmit the power input signal of the external power supply to the power conversion unit; the power conversion unit is connected to the power interface and the power signal line of the connector, and is configured to convert the power input signal into a power output signal matching the power supply of the target storage module and transmit the power output signal to the power signal line of the connector.

[0011] In some embodiments, the power output signal includes a power supply voltage signal, a programming voltage signal, and a termination voltage signal, and the second transmission module is configured to transmit the power supply voltage signal, the programming voltage signal, and the termination voltage signal to the power supply voltage signal line, the programming voltage signal line, and the termination voltage signal line of the connector, respectively.

[0012] In some embodiments, the signal transmission structure further includes: a third transmission unit connected to the reset signal line of the connector, configured to generate a power-on reset signal and transmit the power-on reset signal to the reset signal line.

[0013] In some embodiments, the third transmission unit includes a reset circuit, and the reset circuit is configured to generate a power-on reset signal.

[0014] In some embodiments, the reset circuit includes at least one of the following: a resistor-capacitor reset circuit, a reset chip.

[0015] In some embodiments, the storage module is a dual in-line memory module.

[0016] An embodiment of the present disclosure provides a testing method, and the method includes:

[0017] In the case that the gold fingers of the board adapter device in any of the above embodiments are connected to the storage module connector of the data configuration board and the board adapter device accesses a power input signal, controlling the data configuration board to power on; the connector of the board adapter device is connected to the storage module to be tested;

[0018] Using the data configuration board, controlling the dynamic random access memory chip on the storage module to enter a test mode through the board adapter device;

[0019] In the case that the dynamic random access memory chip on the storage module enters a test mode and the board adapter device connected to the storage module is switched from being electrically connected to the storage module connector of the data configuration board to being electrically connected to the storage module connector of the target test platform, using the target test platform to test the storage module.

[0020] In some embodiments, the method further includes: when the connector of the board adapter device is connected to the storage module and the gold fingers of the board adapter device are connected to the storage module connector of the data configuration board, inputting a power input signal to the board adapter device.

[0021] In some embodiments, inputting the power input signal to the board adapter device includes: connecting the second transmission structure of the board adapter device to a DC power supply providing a preset voltage value.

[0022] In some embodiments, the method further includes: connecting the connector of the board adapter device to the storage module and connecting the gold fingers of the board adapter device to the storage module connector of the data configuration board.

[0023] In some embodiments, the method further includes: when the dynamic random access memory chips on the storage module enter the test mode, hot-plugging the board adapter device connected to the storage module from the storage module connector connected to the data configuration board to the storage module connector connected to the target test platform.

[0024] An embodiment of the present disclosure provides a test system, including: a storage module to be tested; the board adapter device in any of the above embodiments; a data configuration board; a target test platform;

[0025] wherein, the storage module to be tested is connected to the connector of the board adapter device;

[0026] The data configuration board is configured to: when the gold fingers of the board adapter device are connected to the storage module connector of the data configuration board, and the board adapter device is connected to a power input signal and the data configuration board is powered on, control the dynamic random access memory chips on the storage module to enter the test mode through the board adapter device;

[0027] The target test platform is configured to: when the dynamic random access memory chips on the storage module enter the test mode, and the board adapter device connected to the storage module is hot-plugged from the storage module connector connected to the data configuration board to the storage module connector connected to the target test platform, test the storage module.

[0028] An embodiment of the present disclosure provides a test device, the device includes:

[0029] The power-on module is used to control the power-on of the data configuration board when the gold fingers of the board card adapter device in any of the above embodiments are connected to the storage module connector of the data configuration board and the board card adapter device accesses the power input signal; the connector of the board card adapter device is connected to the storage module to be tested;

[0030] The control module is used to use the data configuration board to control the dynamic random access memory chips on the storage module to enter the test mode through the board card adapter device;

[0031] The test module is used to, when the dynamic random access memory chips on the storage module enter the test mode and the board card adapter device connected to the storage module is switched from being electrically connected to the storage module connector of the data configuration board to being connected to the storage module connector of the target test platform, use the target test platform to test the storage module.

[0032] An embodiment of the present disclosure provides a test device, including a memory and a processor, where the memory stores a computer program that can run on the processor, and when the processor executes the program, some or all of the steps in the above method are implemented.

[0033] An embodiment of the present disclosure provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, some or all of the steps in the above method are implemented.

[0034] In an embodiment of the present disclosure, the board card adapter device includes a first adapter structure, a second adapter structure, and a signal transmission structure; the first adapter structure has gold fingers that match the board card of the target storage module; the second adapter structure has a connector that matches the gold fingers; the data signal lines, clock signal lines, address signal lines, and control signal lines of the gold fingers are correspondingly connected to the corresponding connection lines in the connector, and the power signal line of the connector is connected to the accessed power input signal through the second transmission module in the signal transmission structure. In this way, the power signal of the storage module can be independently controlled without affecting the communication between the board card of the storage module and the existing slots. Thus, using this board card adapter device can support the storage module to remain powered on when switching connections between different board cards or hardware platforms, so that the configuration of the storage module will not be lost when switching connections, and further improve the flexibility and accuracy of storage module testing, facilitating the testing of storage modules on various types of system platforms.

[0035] Details of one or more embodiments of the present disclosure are set forth in the following drawings and description. Other features and advantages of the present disclosure will become apparent from the specification and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0037] Figure 1A A schematic diagram of the structure of a board-to-card adapter provided in an embodiment of the present disclosure;

[0038] Figure 1B A schematic diagram of the hardware structure of a DIMM provided in an embodiment of the present disclosure;

[0039] Figure 1C A schematic diagram of the structure of a board-to-card adapter provided in an embodiment of the present disclosure;

[0040] Figure 2 A schematic diagram of an implementation flow of a testing method provided in an embodiment of the present disclosure;

[0041] Figure 3 A schematic diagram of an implementation flow of a testing method provided in an embodiment of the present disclosure;

[0042] Figure 4 A schematic diagram of an implementation flow of a testing method provided in an embodiment of the present disclosure;

[0043] Figure 5 A schematic diagram of an implementation flow of a testing method provided in an embodiment of the present disclosure;

[0044] Figure 6 A schematic diagram of an implementation flow of a testing method provided in an embodiment of the present disclosure;

[0045] Figure 7A A schematic diagram of the distribution of the number and area of ​​a hole pattern provided in an embodiment of the present disclosure;

[0046] Figure 7B A schematic diagram of implementing defect detection on a line-block type scanned image provided by an embodiment of the present disclosure;

[0047] Figure 8 A schematic diagram of the composition architecture of a test system provided in an embodiment of the present disclosure;

[0048] Figure 9 A schematic diagram of the structure of a test device provided in an embodiment of the present disclosure;

[0049] Figure 10 A hardware entity schematic diagram of a test device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0050] The technical solutions of the present disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be construed as limiting the present disclosure. All other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of the present disclosure.

[0051] In the following description, reference is made to "some embodiments", which describe a subset of all possible embodiments. However, it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict.

[0052] In the following description, the terms "first / second / third" are merely used to distinguish similar objects and do not represent a specific order for the objects. It can be understood that "first / second / third" can be interchanged with a specific order or sequence when permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0053] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present disclosure belongs. The terms used herein are only for the purpose of describing the present disclosure and are not intended to limit the present disclosure.

[0054] In the related art, a memory module generally includes at least one dynamic random access memory (DRAM) chip. The DRAM chip can introduce test logic during the chip design process through design for test (DFT), and use this part of the test logic to complete the automatic generation of test vectors, so as to achieve the purpose of fast and effective chip testing. After the DRAM chip is taped out, engineers can access the DFT signals defined in the test mode access design stage of the DRAM chip. The DFT signals are stored in the DFT registers of the DRAM chip. By modifying the values of the DFT signals in the DFT training set, some power supply voltages inside the DRAM chip, input / output (I / O) timings, etc. can be changed to achieve efficient debugging, speed up error location, and make the entire DRAM chip testing process converge quickly.

[0055] The ways to enter the test mode of the DRAM chip can include entering through an ATE machine and entering through a CPU motherboard. However, these two ways have at least the following problems:

[0056] 1) Enter the test mode of the DRAM chip through an ATE machine or a specific CPU motherboard. The DRAM chip can only be tested in an independent experimental environment, rather than in the system platform where the storage module containing the DRAM chip is actually installed and used. It is impossible to simulate the real signal characteristics in the system platform, which affects the accuracy of the test and results in the inability to accurately analyze the problems existing in the storage module during actual application.

[0057] 2) After entering the test mode of the DRAM chip, once the power is off or reset, the changes made to the power supply voltage, I / O timing, etc. in the test mode before will be lost.

[0058] 3) Entering the test mode of the DRAM chip through the CPU motherboard requires clear and complete underlying code of the CPU motherboard and needs to correctly modify the control code of the DRAM physical layer. The cost is relatively high and it is not universal.

[0059] In view of this, the embodiments of the present disclosure provide a board card adapter device, which can improve the flexibility and accuracy of the storage module test and facilitate the testing of the storage module on various types of customer system platforms. Figure 1A It is a schematic diagram of the composition structure of a board card adapter device provided by the embodiments of the present disclosure. As Figure 1A shown, the board card adapter device 100 includes: a first adapter structure 110, a second adapter structure 120, and a signal transmission structure 130; wherein,

[0060] The first adapter structure 110 has a gold finger 111 that matches the board card of the target storage module;

[0061] The second adapter structure 120 has a connector 121 that matches the gold finger 111;

[0062] The signal transmission structure 130 includes a first transmission module 131 and a second transmission module 132; the first transmission module 131 is used to correspondingly connect the data signal line SL1, clock signal line SL2, address signal line SL3, and control signal line SL4 of the gold finger 111 with the corresponding connection lines in the connector 121; the second transmission module 132 is used to convert the power input signal V1 into a power output signal V2 that matches the power supply of the target storage module and transmit the power output signal V2 to the power signal line of the connector 121 when the power input signal V1 is accessed.

[0063] Here, the target storage module may be any suitable storage module, including but not limited to one or more of a dual inline memory module (DIMM), a single in-line memory module (SIMM), etc. DIMM may be a small-size DIMM (SODIMM), an unbuffered DIMM (UDIMM), a registered DIMM (RDIMM), etc., which is not limited here. Figure 1B A schematic diagram of the hardware structure of a DIMM provided in an embodiment of the present disclosure is shown in FIG. Figure 1B As shown, the DIMM 10 includes a board 11 , a plurality of DRAM chips 12 soldered on the board 11 , and a gold finger 13 located at one end of the board 11 .

[0064] The gold finger 111 in the first adapter structure 110 matches the board of the target storage module, which means that the signal line of the gold finger 111 corresponds to the signal line of the gold finger end on the board of the target storage module one by one and the number is the same. Through the gold finger 111, the board adapter device 100 can be connected to any suitable connector of the board adapted to the target storage module in a plug-in or direct connection manner, and the connector of the board adapted to the target storage module may include, for example, a DIMM slot, a SIMM slot, etc. In implementation, the first adapter structure 110 can be any suitable circuit structure with gold fingers, and the embodiments of the present disclosure are not limited to this.

[0065] The connector 121 in the second adapter structure 120 matches the gold finger 111, which means that the signal lines of the connector 121 correspond one-to-one with the signal lines of the gold finger 111 and are the same in number. Through the connector 121, the board-to-card adapter device 100 can be connected to the board-to-card of the target storage module by plug-in or direct connection. During implementation, the connector 111 can be a slot-type connector or a magnetic-type connector, which is not limited here. The second adapter structure 120 can be any suitable circuit structure with a connector, which is not limited in the embodiments of the present disclosure.

[0066] The signal transmission structure 130 may include a first transmission module 131 and a second transmission module 132. The first transmission module 131 may connect the data signal line, clock signal line, address signal line, and control signal line of the gold finger 111 to the data signal line, clock signal line, address signal line, and control signal line in the connector 121 in a one-to-one correspondence. In implementation, the corresponding signal lines between the gold finger 111 and the connector 121 may be connected via a cable or via a circuit board, which is not limited here.

[0067] The second transmission module 132 may have an input port for accessing a power input signal V1. The second transmission module 132 converts the input power input signal V1 into a power output signal V2 that matches the power supply of the target storage module, and transmits the power output signal V2 to the power signal line of the connector 121. The power supply of the target storage module can be determined according to the specifications of the storage module actually adopted. For example, for a DIMM, the power supply may include a power supply voltage signal VDD, a programming voltage signal VPP, and a termination voltage signal VTT. The voltage of the power supply voltage signal VDD may be 1.2V ± 10%, the voltage of the programming voltage signal VPP may be 2.5 ± 10%, and the voltage of the termination voltage signal VTT may be 0.6V ± 10%. Another example is that for a SIMM, the power supply may include a power supply voltage signal VCC, and the voltage of the power supply voltage signal VCC may be 5V ± 10%. The power input signal V1 may be a DC power signal or an AC power signal. In implementation, those skilled in the art can adopt a suitable power conversion method according to the actual situation to convert the input power input signal V1 into a power output signal V2 that matches the power supply of the target storage module, which is not limited here.

[0068] In the embodiments of the present disclosure, the board card adapter device includes a first adapter structure, a second adapter structure, and a signal transmission structure; the first adapter structure has a gold finger that matches the board card of the target storage module; the second adapter structure has a connector that matches the gold finger; the data signal line, clock signal line, address signal line, and control signal line of the gold finger are correspondingly connected to the corresponding connection lines in the connector, and the power signal line of the connector is connected to the accessed power input signal through the second transmission module in the signal transmission structure. In this way, the power signal of the storage module can be independently controlled without affecting the communication between the board card of the storage module and the existing slot. Thus, using this board card adapter device can support the storage module to remain powered on when switching connections on different board cards or hardware platforms, so that the configuration of the storage module will not be lost when switching connections, and further improve the flexibility and accuracy of the storage module test, facilitating the testing of the storage module on various types of system platforms.

[0069] In some embodiments, the power signal line of the gold finger 111 is floating and / or the reset signal line of the gold finger is floating. Here, the power signal line and the reset signal line of the gold finger 111 are respectively the power signal line and the reset signal line at the gold finger end on the board card of the target storage module. In implementation, at least one of the power signal line and the reset signal line of the gold finger 111 can be floating according to the actual situation. In this way, the influence of the power signal and / or reset signal of the gold finger on the power signal and / or reset signal in the connector can be reduced.

[0070] In some embodiments, Figure 1C As shown, the second transmission module 132 includes a power interface 1321 and a power conversion unit 1322; wherein the power interface 1321 is used to connect an external power source and transmit the power input signal V1 of the external power source to the power conversion unit 1322; the power conversion unit 1322 is connected to the power interface 1321 and the power signal line of the connector 121, and is used to convert the power input signal V1 into a power output signal V2 that matches the power supply of the target storage module, and transmit the power output signal V2 to the power signal line of the connector 121. During implementation, the power conversion unit can be a power conversion chip, such as a current conversion chip, a voltage conversion chip, etc.; the voltage conversion unit can also be a power conversion circuit, such as a current conversion circuit, a voltage conversion circuit, etc. In this way, the power input signal of the external power source can be simply and quickly converted into a power output signal that matches the power supply of the target storage module through the power conversion unit.

[0071] In some embodiments, the power output signal includes a power supply voltage signal, a programming voltage signal, and a termination voltage signal, and the second transmission module 132 is used to transmit the power supply voltage signal, the programming voltage signal, and the termination voltage signal to the power supply voltage signal line, the programming voltage signal line, and the termination voltage signal line of the connector 121. In this way, a variety of voltage signals matching the power supply of the target storage module can be obtained simply and quickly.

[0072] In some embodiments, the signal transmission structure further includes: a third transmission unit connected to the reset signal line of the connector, used to generate a power-on reset signal, and transmit the power-on reset signal to the reset signal line. In this way, the reset signal line of the connector can be independently controlled, so that when the target storage module switches between different system platforms based on the board adapter device, the influence of the power-on reset signal received by the gold finger in the first switching structure on the power-on reset signal of the connector in the second conversion structure can be reduced.

[0073] In some embodiments, the third transmission unit includes a reset circuit, and the reset circuit is used to generate a power-on reset signal. In this way, the power-on reset signal can be generated simply and quickly through the reset circuit.

[0074] In some embodiments, the reset circuit includes at least one of the following: a resistor-capacitor reset circuit and a reset chip. In this way, the complexity of the reset circuit can be further simplified and the stability of the reset signal can be improved.

[0075] In some embodiments, the memory module is a dual in-line memory module. In this way, it is possible to support power-off-free switching of the DIMM when connecting to different boards or system platforms, so that the configuration of the DIMM will not be lost when switching connections, thereby improving the flexibility and accuracy of DIMM testing and facilitating the testing of DIMM on various types of system platforms.

[0076] Based on the board adapter device described in the above embodiments, an embodiment of the present disclosure provides a testing method, which can be executed by a processor of a testing device. Here, the testing device may refer to any suitable device with data processing capabilities such as a server, a laptop, a tablet computer, a desktop computer, an intelligent control device, a testing machine, etc. Figure 2 It is a schematic flowchart of the implementation of a testing method provided by an embodiment of the present disclosure, as Figure 2 shown, the method includes the following steps S201 to step S203:

[0077] Step S201, when the gold fingers of the board adapter device described in any of the above embodiments are connected to the memory module connector of the data configuration board and the board adapter device is connected to a power input signal, control the data configuration board to power on; the connector of the board adapter device is connected to the memory module to be tested.

[0078] Here, the memory module to be tested may be a DIMM or a SIMM, which is not limited here.

[0079] The data configuration board may be any suitable board that can modify the control code of the physical layer of the memory module through the memory module connector. The memory module connector of the data configuration board may be any suitable connector that matches the gold fingers of the memory module to be tested, which is not limited here. The data configuration board can control the DRAM chips on the memory module to enter the test mode by modifying the control code of the physical layer of the memory module. For example, when the memory module to be tested is a DIMM, the memory module connector may be a DIMM slot, and the data configuration board may be a field programmable gate array (FPGA) board or a complex programmable logic device (CPLD) board with a DIMM slot. A control program for modifying the control code of the physical layer of the memory module, such as register-transfer level (RTL) code, can be written in the FPGA chip on the FPGA board or the CPLD chip on the CPLD board.

[0080] The connection between the gold fingers of the board transfer device and the storage module connector of the data configuration board can be manually connected by the user or engineer, or can be automatically connected through a testing machine, an intelligent control device, etc., and there is no limitation here.

[0081] Step S202: Use the data configuration board to control the dynamic random access memory chip on the storage module to enter the test mode through the board transfer device.

[0082] Here, in some embodiments, a pre-written control program for controlling the DRAM chip to enter the test mode can be imported into the data configuration board, and based on this control program, the control code of the physical layer of the storage module can be modified to control the DRAM chip on the storage module to enter the test mode.

[0083] In some embodiments, a control program for controlling the DRAM chip to enter the test mode can be written in the data configuration board, and the data configuration board can modify the control code of the physical layer of the storage module based on the written control program to control the DRAM chip on the storage module to enter the test mode.

[0084] In implementation, the control program for controlling the DRAM chip to enter the test mode can be determined by those skilled in the art based on the actual specifications of the DRAM chip on the storage module to be tested, and the embodiments of the present disclosure do not limit this.

[0085] Step S203: When the dynamic random access memory chip on the storage module enters the test mode, and the board transfer device connecting the storage module is hot-switched from the storage module connector connecting the data configuration board to the storage module connector connecting the target test platform, use the target test platform to test the storage module.

[0086] Here, the target test platform can be a system platform for product debugging of the storage module, or a system platform for actual installation and use of the storage module.

[0087] When the DRAM chips on the memory module enter the test mode, the connected memory module and the board transfer device can be removed from the data configuration board while being powered on, and then connected to the memory module connector of the target test platform. In implementation, the board transfer device connecting the memory module can be manually switched by the user or engineer from the memory module connector connecting the data configuration board to the memory module connector connecting the target test platform while being powered on, or can be automatically switched by the test machine, intelligent control device, etc. from the memory module connector connecting the data configuration board to the memory module connector connecting the target test platform, which is not limited here. For example, when the memory module is a DIMM, the data configuration board is an FPGA / CPLD board with a DIMM slot, and the target test platform is a system platform with a DIMM slot, the board transfer device with the DIMM inserted can be pulled out from the DIMM slot of the FPGA / CPLD board while being powered on and then inserted into the DIMM slot of the target test platform, and the DIMM can be tested using the target test platform.

[0088] In some embodiments, the memory module is a dual in-line memory module.

[0089] In some embodiments, the data configuration board includes one of the following: an FPGA board, a CPLD board. In this way, by controlling the DRAM chips on the memory module to enter the test mode through the FPGA / CPLD board, it is convenient for the user to operate, and the implementation cost is relatively low, which can improve the universality of the application of the test method.

[0090] In the embodiments of the present disclosure, after using the data configuration board to control the dynamic random access memory chips on the memory module to be tested to enter the test mode through the board transfer device, the memory module and the board transfer device are switched while being powered on to the memory module connector connecting the target test platform, and the memory module is tested using the target test platform. In this way, since the memory module remains powered on during the process of being switched from the data configuration board to the target test platform, the modification of the control code of the physical layer of the memory module by the data configuration board will not be lost during the switching connection, and it can continue to be in the test mode after being connected to the target test platform. Thus, the memory module can be tested on the target test platform through the test mode of the DRAM chips of the memory module, which can improve the flexibility and accuracy of the memory module test and is also convenient for testing the memory module on various types of system platforms.

[0091] The embodiments of the present disclosure provide a test method, which can be executed by the processor of the test device. Figure 3 It is a schematic diagram of the implementation process of a test method provided by the embodiments of the present disclosure, as Figure 3As shown, the method includes the following steps S301 to S304:

[0092] Step S301, when the connector of the board adapter device in any of the above embodiments is connected to the storage module, and the gold fingers of the board adapter device are connected to the storage module connector of the data configuration board, input a power input signal to the board adapter device.

[0093] Here, the power input signal input to the board adapter device can be a current signal or a voltage signal, and can be a DC signal or an AC signal. In implementation, those skilled in the art can input an appropriate power input signal to the board adapter device according to the actual situation, which is not limited here.

[0094] Step S302, when the gold fingers of the board adapter device are connected to the storage module connector of the data configuration board, and the board adapter device is connected to the power input signal, control the data configuration board to power on; the connector of the board adapter device is connected to the storage module to be tested.

[0095] Step S303, use the data configuration board to control the dynamic random access memory chips on the storage module to enter the test mode through the board adapter device.

[0096] Step S304, when the dynamic random access memory chips on the storage module enter the test mode, and the board adapter device connected to the storage module is switched from being electrically connected to the storage module connector of the data configuration board to being connected to the storage module connector of the target test platform, use the target test platform to test the storage module.

[0097] Here, the above steps S302 to S304 respectively correspond to steps S201 to S203 in the foregoing embodiments, and the specific implementation manners of steps S201 to S203 can be referred to in implementation.

[0098] In some embodiments, the inputting of the power input signal to the board adapter device in step S301 may include: step S311, connect the second transmission structure of the board adapter device to a DC power supply providing a preset voltage value. Here, the second transmission structure can be connected to the DC power supply by any suitable means such as interface connection or cable direct connection. The preset voltage value can be determined according to the actual situation. For example, the preset voltage value can be a DC voltage of 5 volts (V).

[0099] In an embodiment of the present disclosure, when the connector of the board card adapter device is connected to the storage module and the gold fingers of the board card adapter device are connected to the storage module connector of the data configuration board, a power input signal can be automatically input to the board card adapter device, thereby improving the automation during the testing process.

[0100] An embodiment of the present disclosure provides a testing method, which can be executed by a processor of a testing device. Figure 4 As shown in Figure 4 the schematic flowchart of the implementation of a testing method provided by an embodiment of the present disclosure, the method includes the following steps S401 to S404:

[0101] Step S401: Connect the connector of the board card adapter device described in any of the above embodiments to the storage module, and connect the gold fingers of the board card adapter device to the storage module connector of the data configuration board.

[0102] Here, the connector of the board card adapter device can be automatically connected to the storage module and the gold fingers of the board card adapter device can be automatically connected to the storage module connector of the data configuration board through a testing machine, an intelligent control device, etc.

[0103] Step S402: When the gold fingers of the board card adapter device are connected to the storage module connector of the data configuration board and the board card adapter device is connected to a power input signal, control the data configuration board to power on; the connector of the board card adapter device is connected to the storage module to be tested.

[0104] Step S403: Use the data configuration board to control the dynamic random access memory chips on the storage module to enter the test mode through the board card adapter device.

[0105] Step S404: When the dynamic random access memory chips on the storage module enter the test mode and the board card adapter device connected to the storage module is switched from being connected to the storage module connector of the data configuration board with power to being connected to the storage module connector of the target test platform, use the target test platform to test the storage module.

[0106] Here, the above steps S402 to S404 respectively correspond to steps S201 to S203 in the foregoing embodiments, and the specific implementation manners of steps S201 to S203 can be referred to during implementation.

[0107] In an embodiment of the present disclosure, the storage module, the board card adapter device, and the data configuration board can be automatically connected, thereby improving the automation during the testing process.

[0108] An embodiment of the present disclosure provides a testing method, which can be executed by a processor of a testing device.Figure 5 The following is a schematic implementation flowchart of a testing method provided by an embodiment of the present disclosure. As Figure 5 shown, the method includes the following steps S501 to S504:

[0109] Step S501: When the gold fingers of the board adapter device in any of the above embodiments are connected to the storage module connector of the data configuration board, and the board adapter device is connected to a power input signal, power on the data configuration board; the connector of the board adapter device is connected to the storage module to be tested.

[0110] Step S502: Use the data configuration board to control the dynamic random access memory chips on the storage module to enter the test mode through the board adapter device.

[0111] Here, the above steps S501 to S502 respectively correspond to steps S201 to S202 in the foregoing embodiments, and the specific implementation manners of steps S201 to S202 can be referred to during implementation.

[0112] Step S503: When the dynamic random access memory chips on the storage module enter the test mode, hot-swap the board adapter device connected to the storage module from the storage module connector connected to the data configuration board to the storage module connector connected to the target test platform.

[0113] Here, the board adapter device connected to the storage module can be automatically hot-swapped from the storage module connector connected to the data configuration board to the storage module connector connected to the target test platform through a test machine, an intelligent control device, etc., and the storage module remains powered during the switching process. For example, the robotic arm of the test machine can be controlled to hot-plug the board adapter device connected to the DIMM from the DIMM slot of the data configuration board, and then hot-plug the removed board adapter device connected to the DIMM into the DIMM slot of the target test platform.

[0114] Step S504: When the dynamic random access memory chips on the storage module enter the test mode, and the board adapter device connected to the storage module is hot-swapped from the storage module connector connected to the data configuration board to the storage module connector connected to the target test platform, use the target test platform to test the storage module.

[0115] Here, the above step S504 corresponds to step S203 in the foregoing embodiments, and the specific implementation manner of step S203 can be referred to during implementation.

[0116] In an embodiment of the present disclosure, when the dynamic random access memory chip on the storage module enters the test mode, the board transfer device connected to the storage module can be automatically switched from the storage module connector connected to the data configuration board while being powered on to the storage module connector connected to the target test platform, thereby improving the automation during the test process.

[0117] An embodiment of the present disclosure provides a test method, which can be executed by a processor of a test device. Figure 6 As shown in the schematic implementation flowchart of a test method provided by an embodiment of the present disclosure, Figure 6 as shown, the method includes the following steps S601 to S604:

[0118] Step S601, when the gold fingers of the board transfer device in any of the above embodiments are connected to the storage module connector of the data configuration board and the board transfer device accesses a power input signal, control the data configuration board to power on; the connector of the board transfer device is connected to the storage module to be tested.

[0119] Step S602, use the data configuration board to control the dynamic random access memory chip on the storage module to enter the test mode through the board transfer device.

[0120] Here, steps S601 to S602 respectively correspond to steps S201 to S202 in the foregoing embodiments, and the specific implementation manners of steps S201 to S202 can be referred to during implementation.

[0121] Step S603, use the data configuration board to configure the test logic and test signals of the dynamic random access memory chip on the storage module through the board transfer device.

[0122] Here, the data configuration board can modify the values in the DFT registers in the DRAM chip of the storage module through the board transfer device to affect the behavior of the DRAM circuit, thereby implementing the configuration of the test logic and test signals of the DRAM chip. The configured test logic and test signals can be determined according to actual test requirements, and the embodiments of the present disclosure do not limit this. For example, the value in DFT register 1 can be modified from 0x2A to 0x3B.

[0123] In some embodiments, a pre-written configuration program for configuring the test logic and test signals of the DRAM chip can be imported into the data configuration board in advance, and based on this configuration program, the values in the DFT registers in the DRAM chip of the storage module are modified to implement the configuration of the test logic and test signals of the DRAM chip.

[0124] In some embodiments, a configuration program for configuring the test logic and test signals of the DRAM chip can be written in the data configuration board. The data configuration board can modify the values in the DFT registers in the DRAM chip of the memory module based on the written configuration program to implement the configuration of the test logic and test signals of the DRAM chip.

[0125] In implementation, the configuration program for configuring the test logic and test signals of the DRAM chip can be determined by those skilled in the art based on the actual specifications of the DRAM chip on the memory module to be tested and the actual test requirements, and the embodiments of the present disclosure do not limit this.

[0126] Step S604, when the dynamic random access memory chip on the memory module enters the test mode and the board transfer device connecting the memory module is switched from the memory module connector connected to the data configuration board to the memory module connector connected to the target test platform while being powered on, use the target test platform to test the memory module based on the test logic and test signals of the dynamic random access memory chip.

[0127] In the embodiments of the present disclosure, the test logic and test signals of the dynamic random access memory chip on the memory module are configured by using the data configuration board, and the memory module is tested by using the target test platform based on the test logic and test signals of the dynamic random access memory chip. In this way, the flexibility of memory module testing can be further improved to meet various test requirements.

[0128] Next, the exemplary application of the embodiments of the present disclosure in an actual application scenario will be described, taking the test scenario of DIMM as an example.

[0129] The embodiments of the present disclosure provide a DIMM adapter board, as Figure 7A shown. The DIMM adapter board 700 includes a DIMM connector 710, DIMM gold fingers 720, and a circuit board 730 connecting the DIMM connector 710 and the DIMM gold fingers 720; wherein,

[0130] The circuit board 730 directly connects all the data signal S1, clock signal S2, address signal S3, and control signal S4 on the DIMM gold fingers 720 to the corresponding signal lines on the DIMM connector 710;

[0131] The circuit board 730 includes a power interface 731 and a power conversion unit 732. The DIMM adapter board 700 externally connects to a 5V DC power supply Vin through the power interface 731, and converts the 5V DC power supply Vin into three groups of power supplies, namely VDD, VPP, and VTT, that match the DIMM through the power conversion unit 732, and connects the three groups of power supplies, VDD, VPP, and VTT, to the corresponding power signal lines on the DIMM connector 710 respectively; the power signal lines corresponding to the three groups of power supplies, VDD, VPP, and VTT, on the DIMM gold fingers 720 are left floating.

[0132] The circuit board 730 further includes: a reset circuit 733, which is used to generate a power-on reset signal R and connect the generated power-on reset signal R to the reset signal line on the DIMM connector 710; the reset signal line on the DIMM gold fingers 720 is left floating.

[0133] It should be noted that in implementation, the above DIMM adapter board can be implemented as the board card adapter device in the foregoing embodiment, the DIMM connector can correspond to the second adapter structure in the foregoing embodiment, the DIMM gold fingers can correspond to the first adapter structure in the foregoing embodiment, and the circuit board connecting the DIMM connector and the DIMM gold fingers can correspond to the signal transmission structure in the foregoing embodiment.

[0134] Based on the DIMM adapter board provided in the foregoing embodiments of the present disclosure, the embodiments of the present disclosure provide a test method. This method introduces the test mode of the DRAM chip into the test scheme of the DIMM, uses an external FPGA / CPLD board card to write RTL code to control the DRAM on the DIMM to enter the test mode, and when the DRAM enters the test mode, installs the DIMM on the target test platform and uses the target test platform to test the DIMM.

[0135] Figure 7B It is a schematic diagram of the implementation process of a test method provided by the embodiments of the present disclosure, as Figure 7B shown. This method includes the following steps S701 to step S705:

[0136] Step S701, insert the DIMM adapter board into the DIMM slot of the FPGA / CPLD board card, insert the DIMM to be tested into the DIMM connector of the DIMM adapter board, and connect a 5V power supply to the DIMM adapter board.

[0137] Step S702, power on the FPGA / CPLD board card, and use the written control program to control the DRAM chip on the DIMM module to enter the test mode and change the values in the DFT registers of the DRAM chip to configure the test logic and test signals in the DRAM chip.

[0138] Step S703: Power off the FPGA / CPLD board.

[0139] Step S704: Plug and unplug the DIMM adapter board and the entire DIMM into the DIMM slot of the target test platform while it is powered on. The target test platform can be, for example, an x86 motherboard, etc.

[0140] Step S705: Power on the target test platform. After the target test platform is powered on, since the power supply and reset signals of the DIMM are not provided by the target test platform, the configuration of the DIMM test mode in Step S702 will not disappear.

[0141] In the embodiments of the present disclosure, the DIMM can be made to enter the test mode of the DRAM chip on the target test platform to test the DIMM, which helps to improve the flexibility and accuracy of DIMM testing, facilitates testing the DIMM on various types of system platforms, and thus can quickly and accurately analyze the problems of the DIMM.

[0142] The embodiments of the present disclosure provide a test system. Figure 8 As shown in the schematic diagram of the composition architecture of a test system provided by the embodiments of the present disclosure, Figure 8 as shown, the test system 800 includes: a storage module 810 to be tested, a board card transfer device 820, a data configuration board card 830, and a target test platform 840. Among them,

[0143] The storage module 810 to be tested is connected to the connector 821 of the board card transfer device 820.

[0144] The data configuration board card 830 is configured to: when the gold finger 822 of the board card transfer device 820 is connected to the storage module connector 831 of the data configuration board card 830, and the board card transfer device 820 accesses the power input signal V1 and the data configuration board card 830 is powered on, control the dynamic random access memory chip 811 on the storage module 810 to enter the test mode through the board card transfer device 820.

[0145] The target test platform 840 is configured to: when the dynamic random access memory chip 811 on the storage module 810 enters the test mode, and the board card transfer device 820 connected to the storage module 810 is switched from being connected to the storage module connector 831 of the data configuration board card 830 to being connected to the storage module connector 841 of the target test platform 840 while being powered on, test the storage module 810.

[0146] Here, the board card transfer device 820 can be the board card transfer device described in any of the above embodiments.

[0147] In some embodiments, the board adapter device is further configured to be connected to a DC power supply providing a preset voltage value through a second transmission structure.

[0148] In some embodiments, the data configuration board is further configured to configure the test logic and test signals of the dynamic random access memory chips on the storage module through the board adapter device; the target test platform is further configured to test the storage module based on the test logic and test signals of the dynamic random access memory chips.

[0149] It should be noted that the description of the above system embodiments is similar to the description of the above method embodiments and has similar beneficial effects to the method embodiments. For the technical details not disclosed in the system embodiments of the present disclosure, please refer to the description of the method embodiments of the present disclosure for understanding.

[0150] Figure 9 FIG. is a schematic structural diagram of a test device provided by an embodiment of the present disclosure. As Figure 9 shown, the test device 900 includes: a power-on module 910, a control module 920, and a test module 930, where:

[0151] The power-on module 910 is configured to control the data configuration board to power on when the gold fingers of the board adapter device in any of the above embodiments are connected to the storage module connector of the data configuration board and the board adapter device accesses a power input signal; the connector of the board adapter device is connected to the storage module to be tested.

[0152] The control module 920 is configured to use the data configuration board to control the dynamic random access memory chips on the storage module to enter a test mode through the board adapter device.

[0153] The test module 930 is configured to, when the dynamic random access memory chips on the storage module enter the test mode and the board adapter device connected to the storage module is switched from being electrically connected to the storage module connector of the data configuration board to being electrically connected to the storage module connector of the target test platform, use the target test platform to test the storage module.

[0154] In some embodiments, the test device further includes: a power input module configured to input a power input signal to the board adapter device when the connector of the board adapter device is connected to the storage module and the gold fingers of the board adapter device are connected to the storage module connector of the data configuration board.

[0155] In some embodiments, the power input module is further configured to: connect the second transmission structure of the board adapter device to a DC power supply providing a preset voltage value.

[0156] In some embodiments, the test device further includes: a connection module, configured to connect the connector of the board adapter device to the storage module, and connect the gold fingers of the board adapter device to the storage module connector of the data configuration board.

[0157] In some embodiments, the test device further includes: a switching module, configured to, when the dynamic random access memory chips on the storage module enter the test mode, electrically switch the board adapter device connected to the storage module from being connected to the storage module connector of the data configuration board to being connected to the storage module connector of the target test platform.

[0158] In some embodiments, the test device further includes: a configuration module, configured to use the data configuration board to configure the test logic and test signals of the dynamic random access memory chips on the storage module through the board adapter device; the test module is further configured to: use the target test platform to test the storage module based on the test logic and test signals of the dynamic random access memory chips.

[0159] In some embodiments, the storage module is a dual in-line memory module.

[0160] In some embodiments, the data configuration board includes one of the following: a field programmable gate array board, a complex programmable logic device board.

[0161] The description of the above device embodiments is similar to that of the above method embodiments, and has similar beneficial effects to those of the method embodiments. For the technical details not disclosed in the device embodiments of the present disclosure, please refer to the description of the method embodiments of the present disclosure for understanding.

[0162] It should be noted that in the embodiments of the present disclosure, if the above test method is implemented in the form of software function modules and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the embodiments of the present disclosure, in essence, or the part that contributes to the related art, can be embodied in the form of a software product. The software product is stored in a storage medium and includes several instructions for causing a test device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the methods described in the various embodiments of the present disclosure. The aforementioned storage medium includes: various media such as a USB flash drive, a mobile hard disk, a read only memory (ROM), a magnetic disk, or an optical disc that can store program codes. In this way, the embodiments of the present disclosure are not limited to any specific combination of hardware and software.

[0163] Correspondingly, an embodiment of the present disclosure provides a testing device, including a memory and a processor. The memory stores a computer program that can run on the processor, and when the processor executes the program, the steps in the above method are implemented.

[0164] Correspondingly, an embodiment of the present disclosure provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps in the above method are implemented. The computer-readable storage medium can be a volatile or non-volatile storage medium.

[0165] Correspondingly, an embodiment of the present disclosure provides a computer program product. The computer program product includes a non-transitory computer-readable storage medium storing a computer program. When the computer program is read and executed by a computer, some or all of the steps in the above method are implemented. The computer program product can be specifically implemented in a manner of hardware, software, or a combination thereof. In an alternative embodiment, the computer program product is specifically embodied as a computer storage medium. In another alternative embodiment, the computer program product is specifically embodied as a software product, such as a Software Development Kit (SDK), etc.

[0166] It should be noted here that the descriptions of the above storage medium, computer program product, and device embodiments are similar to the descriptions of the above method embodiments and have beneficial effects similar to those of the method embodiments. For the technical details not disclosed in the embodiments of the present disclosure's storage medium, computer program product, and device, please refer to the descriptions of the method embodiments of the present disclosure for understanding.

[0167] It should be noted that Figure 10 is a schematic diagram of a hardware entity of the testing device in the embodiment of the present disclosure. As Figure 10 shown, the hardware entity of the testing device 1000 includes: a processor 1001, a communication interface 1002, and a memory 1003, where:

[0168] The processor 1001 generally controls the overall operation of the testing device 1000.

[0169] The communication interface 1002 can enable the testing device to communicate with other terminals or servers through a network.

[0170] The memory 1003 is configured to store instructions and applications executable by the processor 1001, and can also cache data to be processed or already processed by the processor 1001 and each module in the testing device 1000 (for example, image data, audio data, voice communication data, and video communication data), and can be implemented by flash memory (FLASH) or random access memory (Random Access Memory, RAM).

[0171] It should be understood that the "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, the appearances of "in one embodiment" or "in an embodiment" throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics may be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present disclosure, the magnitudes of the sequence numbers of the above processes do not mean the order of execution, and the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present disclosure. The sequence numbers of the embodiments of the present disclosure above are only for description and do not represent the advantages or disadvantages of the embodiments.

[0172] It should be noted that in this article, the terms "comprising", "including" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the phrase "including a..." does not exclude the existence of additional identical elements in the process, method, article or device including the element.

[0173] In several embodiments provided by the present disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are only illustrative. For example, the division of the units is only a logical function division, and there may be other division methods in actual implementation. For example, multiple units or components can be combined, or can be integrated into another system, or some features can be ignored, or not executed. In addition, the couplings, direct couplings, or communication connections between the components shown or discussed with each other can be through some interfaces, and the indirect couplings or communication connections of devices or units can be electrical, mechanical or other forms.

[0174] The units described above as separate components may or may not be physically separated, and the components shown as units may or may not be physical units; they can be located in one place or distributed to multiple network units; some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0175] In addition, each functional unit in the embodiments of the present disclosure can be all integrated in one processing unit, or each unit can be separately used as a unit, or two or more units can be integrated in one unit; the above integrated units can be implemented in the form of hardware, or in the form of a combination of hardware and software functional units.

[0176] Those of ordinary skill in the art can understand that all or part of the steps of implementing the above method embodiments can be completed by hardware related to program instructions. The foregoing program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps including those of the above method embodiments; and the foregoing storage medium includes: removable storage devices, read-only memory (ROM), magnetic disks, or optical discs and other various media that can store program codes.

[0177] Alternatively, if the above-mentioned integrated unit is implemented in the form of a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present disclosure, in essence or the part that contributes to the related art, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for causing a test device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the methods described in the various embodiments of the present disclosure. And the foregoing storage medium includes: removable storage devices, ROM, magnetic disks, or optical discs and other various media that can store program codes.

[0178] As described above, the above are only the implementation manners of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should all be covered by the protection scope of the present disclosure.

Claims

1. A board card adapter device, characterized in that, include: A first switching structure, a second switching structure and a signal transmission structure; wherein, The first adapter structure has a gold finger that matches the board of the target storage module; The second adapter structure has a connector matching the gold finger; The signal transmission structure includes a first transmission module and a second transmission module; the first transmission module is used to connect the data signal line, clock signal line, address signal line and control signal line of the gold finger to the corresponding connecting lines in the connector; the second transmission module is used to convert the power input signal into a power output signal that matches the power supply of the target storage module when a power input signal is connected, and transmit the power output signal to the power signal line of the connector.

2. The device according to claim 1, characterized in that, The power signal line of the gold finger is suspended and / or the reset signal line of the gold finger is suspended.

3. The device according to claim 1, characterized in that, The second transmission module includes a power interface and a power conversion unit; wherein, The power interface is used to connect to an external power source and transmit the power input signal of the external power source to the power conversion unit; The power conversion unit is connected to the power interface and the power signal line of the connector, and is used to convert the power input signal into a power output signal that matches the power supply of the target storage module, and transmit the power output signal to the power signal line of the connector.

4. The device according to claim 1, characterized in that, The power output signal includes a power supply voltage signal, a programming voltage signal and a termination voltage signal, and the second transmission module is used to transmit the power supply voltage signal, the programming voltage signal and the termination voltage signal to the power supply voltage signal line, the programming voltage signal line and the termination voltage signal line of the connector respectively.

5. The device according to any one of claims 1 to 4, characterized in that, The signal transmission structure also includes: The third transmission unit is connected to the reset signal line of the connector, and is used to generate a power-on reset signal and transmit the power-on reset signal to the reset signal line.

6. The device according to claim 5, characterized in that, The third transmission unit includes a reset circuit, and the reset circuit is used to generate a power-on reset signal.

7. The device according to claim 6, characterized in that, The reset circuit includes at least one of the following: a resistor-capacitor reset circuit and a reset chip.

8. The device according to any one of claims 1 to 4, characterized in that The storage module is a dual in-line storage module.

9. A testing method, characterized in that, include: When the gold finger of the board-to-card adapter device according to any one of claims 1 to 8 is connected to the storage module connector of the data configuration board and the board-to-card adapter device is connected to a power input signal, the data configuration board is controlled to be powered on; The connector of the board-to-card adapter is connected to the storage module to be tested; Using the data to configure the board, and controlling the dynamic random access memory chip on the storage module to enter a test mode through the board adapter; When the dynamic random access memory chip on the storage module enters the test mode and the board adapter connected to the storage module switches from the storage module connector connected to the data configuration board to the storage module connector connected to the target test platform, the storage module is tested using the target test platform.

10. The method according to claim 9, characterized in that, The method further comprises: When the connector of the board card transfer device is connected to the storage module and the gold fingers of the board card transfer device are connected to the storage module connector of the data configuration board card, a power input signal is input to the board card transfer device.

11. The method according to claim 10, wherein The inputting of the power input signal to the board card transfer device includes: Connecting the second transmission structure of the board card transfer device to a DC power supply providing a preset voltage value.

12. The method according to claim 9, characterized in that, The method further includes: Connecting the connector of the board card transfer device to the storage module and connecting the gold fingers of the board card transfer device to the storage module connector of the data configuration board card.

13. The method according to claim 9, wherein The method further includes: When the dynamic random access memory chips on the storage module enter the test mode, the board card transfer device connected to the storage module is hot-switched from being connected to the storage module connector of the data configuration board card to being connected to the storage module connector of the target test platform.

14. The method according to any one of claims 9 to 13, characterized in that, The method further includes: Using the data configuration board card to configure the test logic and test signals of the dynamic random access memory chips on the storage module through the board card transfer device; The testing of the storage module using the target test platform includes: Using the target test platform to test the storage module based on the test logic and test signals of the dynamic random access memory chips.

15. The method according to any one of claims 9 to 13, characterized in that, The storage module is a dual in-line memory module.

16. The method according to any one of claims 9 to 13, characterized in that The data configuration board card includes one of the following: a field programmable gate array board card, a complex programmable logic device board card.

17. A test system, characterized in that, Includes: A storage module to be tested; The board card transfer device according to any one of claims 1 to 8; A data configuration board card; A target test platform; Wherein, the storage module to be tested is connected to the connector of the board card transfer device; The data configuration board card is configured to: when the gold fingers of the board card transfer device are connected to the storage module connector of the data configuration board card, and the board card transfer device accesses a power input signal and the data configuration board card is powered on, control the dynamic random access memory chips on the storage module to enter the test mode through the board card transfer device; The target test platform is configured to: when the dynamic random access memory chips on the storage module enter the test mode and the board card transfer device connected to the storage module is hot-switched from being connected to the storage module connector of the data configuration board card to being connected to the storage module connector of the target test platform, test the storage module.

18. A test device, characterized in that, Includes: A power-on module configured to control the power-on of the data configuration board card when the gold fingers of the board card transfer device according to any one of claims 1 to 8 are connected to the storage module connector of the data configuration board card and the board card transfer device accesses a power input signal; The connector of the board card transfer device is connected to the storage module to be tested; A control module configured to use the data configuration board card to control the dynamic random access memory chips on the storage module to enter the test mode through the board card transfer device; A test module is used to enter a test mode for a dynamic random access memory chip on the storage module, and when a board transfer device connected to the storage module is hot-switched from a storage module connector connected to the data configuration board to a storage module connector connected to a target test platform, the test module uses the target test platform to test the storage module.

19. A testing device, characterized in that, It includes a memory and a processor. The memory stores a computer program that can run on the processor. When the processor executes the program, it implements the steps in the method according to any one of claims 9 to 16.

20. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps in the method according to any one of claims 9 to 16.

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