Clock signal generation circuit

Abstract

A clock signal generation circuit includes a global phase-locked loop and a plurality of local phase-locked loops. In operation of the clock signal generation circuit, the global phase-locked loop receives a reference clock signal to generate a synchronized clock signal, and the plurality of local phase-locked loops each receive the synchronized clock signal to generate a plurality of clock signals, respectively, which are used to generate a plurality of output clock signals, respectively.

Description

TECHNICAL FIELD

[0001] The present application relates to a clock signal generating circuit, and more particularly to a clock signal generating circuit capable of generating multiple output clock signals. BACKGROUND

[0002] In the current physical layer circuit of Double Data Rate (DDR) Dynamic Random Access Memory (DRAM), a Phase-Locked Loop (PLL) is used to generate an output clock signal, and the output clock signal is then passed through multiple phase interpolators or multiple Delay Locked Loops (DLLs) to generate multiple clock signals required by data signals (DQ), data strobe signals (DQS), command signals (CMD), address signals (ADD), Double Data Rate clock signals (DDRCK), receive clock signals (CK_RX), etc. The above architecture allows the multiple clock signals to be independently phase-adjusted, and also makes it easier to synchronize the multiple clock signals.

[0003] However, the above architecture has the following disadvantages: (1) when the number of data signal (DQ) bits is large, such as 32 bits, the clock tree will have a long length in the circuit layout, thus introducing additional clock jitter, which cannot be filtered out; (2) the current DRAM usually has a Dynamic Frequency Scaling (DFS) mechanism to save power consumption in operation, however, the settling time required by dynamic frequency scaling is very short, and in addition, the PLL is usually not designed to have too high a bandwidth to ensure its stability, so it is difficult to achieve fast and arbitrary frequency dynamic frequency scaling in practice. SUMMARY

[0004] Therefore, one of the purposes of the present application is to provide a clock signal generating circuit that can generate multiple clock signals that can be independently adjusted in phase, and solve the problems of excessively long clock trees and difficulty in achieving fast and arbitrary frequency dynamic frequency scaling in the prior art.

[0005] In one embodiment of the present invention, a clock signal generation circuit is disclosed, comprising a global phase-locked loop (PLL) and a plurality of local phase-locked loops (PLLs). In operation of the clock signal generation circuit, the global PLL receives a reference clock signal to generate a synchronous clock signal, and the plurality of local PLLs each receive the synchronous clock signal to generate a plurality of clock signals, wherein the plurality of clock signals are used to generate a plurality of output clock signals. Attached Figure Description

[0006] Figure 1 This is a schematic diagram of a clock signal generation circuit according to an embodiment of the present invention.

[0007] Figure 2 This is a schematic diagram of using a multiplexer within a clock signal generation circuit to generate multiple output clock signals.

[0008] Figure 3 This is a schematic diagram of a local phase-locked loop according to an embodiment of the present invention.

[0009] Figure 4 This is a schematic diagram of an output enable signal generation circuit according to an embodiment of the present invention. Detailed Implementation

[0010] Figure 1 This is a schematic diagram of a clock signal generation circuit 100 according to an embodiment of the present invention. Figure 1 As shown, the clock signal generation circuit 100 includes a global phase-locked loop (Global PLL) 110, multiple local phase-locked loops (Local PLLs), and multiple phase adjustment circuits. In this embodiment, circuits 130_1 to 130_9, 140_1 to 140_8, 150_1 to 150_8, 160_1 to 160_8, 170_1, and 170_2 are used as examples for explanation. In this embodiment, the clock signal generation circuit 100 is applied to the physical layer circuit of a DRAM controller that generates 32-bit data signals, and the clock signal generation circuit 100 is used to generate multiple clock signals required such as data signal (DQ), data strobe signal (DQS), instruction signal (CMD), address signal (ADD), double data rate clock signal (DDRCK), and receiver clock signal (CK_RX). Furthermore, in this embodiment, the phase adjustment circuits 130_1 to 130_9, 140_1 to 140_8, 150_1 to 150_8, 160_1 to 160_8, 170_1, and 170_2 can be implemented using phase interpolators. Taking five local phase-locked loops 120_1 to 120_5 as an example, the above implementation is only an example and is not a limitation of the present invention.

[0011] In operation of the clock signal generation circuit 100, the global phase-locked loop 110 receives a reference clock signal CKREF to generate a synchronous clock signal CKSYNC having a high frequency, for example, 200-400 MHz. Then, the local phase-locked loop 120_1 receives the synchronous clock signal CKSYNC, takes the synchronous clock signal CKSYNC as a reference clock signal to generate a first clock signal CK_DQ_S0, and the phase adjustment circuits 130_1-130_9 phase-adjust the first clock signal CK_DQ_S0 to generate a first set of output clock signals CK_DQ0-CK_DQ7 and CK_DQS, respectively, wherein the output clock signals CK_DQ0-CK_DQ7 are used for transmission of the 1st-8th bits of the data signal, respectively, and the output clock signal CK_DQS is used for generating a data strobe signal. Similarly, the local phase-locked loop 120_2 receives the synchronous clock signal CKSYNC, takes the synchronous clock signal CKSYNC as a reference clock signal to generate a second clock signal CK_DQ_S1, and the phase adjustment circuits 140_1-140_8 phase-adjust the second clock signal CK_DQ_S1 to generate a second set of output clock signals CK_DQ8-CK_DQ15, respectively, wherein the output clock signals CK_DQ8-CK_DQ15 are used for transmission of the 9th-16th bits of the data signal, respectively. The local phase-locked loop 120_3 receives the synchronous clock signal CKSYNC, takes the synchronous clock signal CKSYNC as a reference clock signal to generate a third clock signal CK_DQ_S2, and the phase adjustment circuits 150_1-150_8 phase-adjust the third clock signal CK_DQ_S2 to generate a third set of output clock signals CK_DQ16-CK_DQ23, respectively, wherein the output clock signals CK_DQ16-CK_DQ23 are used for transmission of the 17th-24th bits of the data signal, respectively. The local phase-locked loop 120_4 receives the synchronous clock signal CKSYNC, takes the synchronous clock signal CKSYNC as a reference clock signal to generate a fourth clock signal CK_DQ_S3, and the phase adjustment circuits 160_1-160_8 phase-adjust the fourth clock signal CK_DQ_S3 to generate a fourth set of output clock signals CK_DQ24-CK_DQ31, respectively, wherein the output clock signals CK_DQ24-CK_DQ31 are used for transmission of the 25th-32th bits of the data signal, respectively.The local phase-locked loop 120_5 receives the synchronization clock signal CKSYNC and uses the synchronization clock signal CKSYNC as a reference clock signal to generate a fifth clock signal CK_CMD. The phase adjustment circuits 170_1, 170_2 phase-adjust the fifth clock signal CK_CMD to generate a fifth set of output clock signals CK_DDR, CK_ADD, respectively, which are used to generate double data rate clock signals and address signals, respectively. In addition, the fifth set of clock signals can further include clock signals CK_CMD, CK_RX, CK_MC, which are used to generate command signals and internal required clock signals.

[0012] In Figure 1 the architecture of the clock signal generation circuit 100, the local phase-locked loops 120_1-120_5 can have a larger bandwidth and a shorter locking time by using the high-frequency synchronization clock signal CKSYNC generated by the global phase-locked loop 110 as a reference clock signal. Therefore, the local phase-locked loops 120_1-120_5 can quickly switch to different frequencies by changing the divisors of the frequency dividers in the local phase-locked loops 120_1-120_5. In addition, since the local phase-locked loops 120_1-120_5 generate the first to fifth sets of clock signals for different signals, respectively, the local phase-locked loops 120_1-120_5 can be disposed near the corresponding contacts / pins, for example, the local phase-locked loop 120_1 can be disposed near the contacts for transmitting the first to eighth bits (i.e., DQ0-DQ7) of the data signal, and the local phase-locked loop 120_2 can be disposed near the contacts for transmitting the ninth to sixteenth bits (i.e., DQ8-DQ15) of the data signal. This can greatly reduce the length of the clock tree in the circuit layout and reduce the clock jitter introduced due to the excessively long clock tree.

[0013] It should be noted that in Figure 1 the embodiment, it is assumed that the data signal transmitted by the DRAM controller is 32 bits, and a clock signal output by each of the four local phase-locked loops 120_1-120_4 is used to generate a clock signal for transmitting 8-bit data signals. However, this is not a limitation of the present application. In other embodiments, the data signal transmitted by the DRAM controller is not limited to 32 bits, and the number of local phase-locked loops 120_1-120_4 used to generate clock signals is not limited to four, and the number of output clock signals generated by the phase adjustment circuits can also vary according to the number of bits of the data signal, and the number of phase adjustment circuits corresponding to each local phase-locked loop is also not limited to that shown in Figure 1 .

[0014] In Figure 1 the illustrated embodiment, the required clock signals are generated by the phase adjustment circuits 130_1-130_9, 140_1-140_8, 150_1-150_8, 160_1-160_8, 170_1, 170_2, however, the present application is not limited thereto. In other embodiments, each local phase-locked loop 120_1-120_5 can generate a plurality of clock signals having different phases, and Figure 1 the phase adjustment circuits of the local phase-locked loop 120_1 can be replaced by a multiplexer to select the required clock signal. Specifically, referring to Figure 2 the local phase-locked loop 120_1 generates 16 clock signals having different phases, and the multiplexer 210_1 receives the 16 clock signals having different phases and selects one of them as the output clock signal CK_DQ0, the multiplexer 210_2 receives the 16 clock signals having different phases and selects one of them as the output clock signal CK_DQ1, the multiplexer 210_8 receives the 16 clock signals having different phases and selects one of them as the output clock signal CK_DQ7, and the multiplexer 210_9 receives the 16 clock signals having different phases and selects one of them as the output clock signal CK_DQS.

[0015] Figure 3 is a schematic diagram of the local phase-locked loop 120_1 according to an embodiment of the present application. As Figure 3 shown, the local phase-locked loop 120_1 includes a phase frequency detector 310, a charge pump 320, a low pass filter 330, an oscillator 340, a loop divider 350, a back-end divider 360, a multi-phase clock generation unit 370, and a sampling circuit (in this embodiment, a flip-flop 380 is taken as an example). In this embodiment, the phase frequency detector 310 generates a detection result according to a synchronization clock signal CKSYNC and a feedback clock signal CKBK, the charge pump 320 generates a control signal Vc according to the detection result, and the low pass filter 330 performs a filtering operation on the control signal Vc to generate a filtered control signal Vc' to control the oscillator 340 to generate a plurality of oscillator output clock signals (hereinafter referred to as clock signals CK0, CKVCO<7:0>). The above-mentioned contents about the phase frequency detector 310, the charge pump 320, the low pass filter 330, and the oscillator 340 are well known to those skilled in the art, and thus details are not described herein.

[0016] Next, the loop divider 350 divides the clock signal CK0 to generate a feedback clock signal CKBK, wherein the divisor of the loop divider 350 is adjustable. The flip-flop 380 receives an output enable signal OE and, triggered by the feedback clock signal CKBK, generates an output enable synchronization signal OESYNC, which controls whether the back-end divider 360 can output the divided signal. For example, when the output enable synchronization signal OESYNC has a logic value of "1", the back-end divider 360 divides the clock signal CK0 to generate a divided clock signal CKDIV; while when the output enable synchronization signal OESYNC has a logic value of "0", the back-end divider 360 will not output the divided clock signal CKDIV. In one embodiment, the output enable signal OE is determined by... Figure 4 The output enable signal is generated by one of the output enable signal generation circuits 400 shown. Figure 4 In this embodiment, the output enable signal generation circuit 400 includes two sampling circuits (using flip-flops 410 and 420 as examples). Flip-flop 410 samples the enable signal EN_OUT based on the synchronization clock signal CKSYNC, and flip-flop 420 samples the output signal of flip-flop 410 based on the synchronization clock signal CKSYNC to generate the output enable signal OE. It should be noted that... Figure 4 The circuit architecture and the number of flip-flops shown are merely illustrative examples and not limitations of the present invention. As long as the output enable signal generation circuit 400 uses the synchronous clock signal CKSYNC to generate the output enable signal OE, such that the synchronous clock signal CKSYNC and the output enable signal OE have a certain phase relationship or a fixed phase relationship, the output enable signal generation circuit 400 can have different designs.

[0017] Next, regarding the back-end frequency divider 360 and the multi-phase clock generation unit 370, after the back-end frequency divider 360 starts the frequency division operation on the clock signal CK0 to generate the divided clock signal CKDIV according to the output enable synchronization signal OESYNC, the multi-phase clock generation unit 370 can use the clock signal CKVCO<7:0> to sample the divided clock signal CKDIV to generate a plurality of clock signals CK_DQ_S0 of different phases, such as 16 clock signals CK_DQ_S0<16:0> of different phases in the present embodiment. For example, the frequency of the divided clock signal CKDIV can be half of the clock signal CKVCO<7:0>, and the multi-phase clock generation unit 370 can internally include 16 sampling circuits for sampling the divided clock signal CKDIV twice using each of the eight clock signals CKVCO<7:0> to generate the 16 clock signals CK_DQ_S0<16:0> of different phases.

[0018] In Figure 3 In the embodiment of the present application, the output enable signal OE is an input signal of the local phase-locked loop 120_1, and is used to control whether the local phase-locked loop 120_1 outputs the 16 clock signals CK_DQ_S0<16:0> of different phases, and the inverter 380 generates the output enable synchronization signal OESYNC by sampling the output enable signal OE using the feedback clock signal CKBK to control the time when the back-end frequency divider 360 outputs the divided clock signal CKDIV. Therefore, because the feedback clock signal CKBK has a fixed phase relationship with the clock signal CK0 output by the oscillator 340, the output enable synchronization signal OESYNC also has a fixed phase relationship with the clock signal CK0, so that the time points when the back-end frequency divider 360 is turned on and turned off can be accurately controlled by the output enable signal OE, and the situation that the back-end frequency divider 360 outputs the divided clock signal CKDIV too early or too late does not occur.

[0019] In an embodiment, the local phase-locked loops 120_2 to 120_5 can have a similar circuit architecture as the local phase-locked loop 120_1, and the output enable signals OE received by the local phase-locked loops 120_1 to 120_5 are generated by the same circuit, such as the output enable signal generation circuit 400, to ensure the correctness of the timing of the clock signals output by the clock signal generation circuit 100.

[0020] The above merely describes the preferred embodiments of the present application, and any equivalent changes and modifications made within the scope of the patent application of the present application shall be included in the scope of the present application.

[0021]

Symbol Description

[0022] 100: clock signal generation circuit

[0023] 110: global phase-locked loop

[0024] 120_1-120_5: local phase-locked loop

[0025] 130_1-130_9, 140_1-140_8, 150_1-150_8, 160_1-160_8: phase adjustment circuit

[0026] 170_1, 170_2: phase adjustment circuit

[0027] 210_1-210_9: multiplexer

[0028] 310: phase frequency detector

[0029] 320: charge pump

[0030] 330: low pass filter

[0031] 340: oscillator

[0032] 350: loop divider

[0033] 360: back-end divider

[0034] 370: multi-phase clock generation unit

[0035] 380: flip-flop

[0036] 400: output enable signal generation circuit

[0037] 410, 420: flip-flop

[0038] CKREF: reference clock signal

[0039] CKSYNC: synchronization clock signal

[0040] CK_DQ_S0: first clock signal

[0041] CK_DQ_S1: second clock signal

[0042] CK_DQ_S2: third clock signal

[0043] CK_DQ_S3: fourth clock signal

[0044] CK_CMD: fifth clock signal

[0045] CK_DQ0-CK_DQ7, CK_DQS, CK_DQ8-CK_DQ15: output clock signal

[0046] CK_DQ16 ~ CK_DQ23, CK_DQ24 ~ CK_DQ31: output clock signals

[0047] CK_DDR, CK_ADD, CK_RX, CK_MC: output clock signals

[0048] CK0: oscillator output clock signal

[0049] CKDIV: divided clock signal

[0050] CKBK: feedback clock signal

[0051] OE: output enable signal

[0052] OESYNC: output enable synchronization signal

[0053] EN_OUT: enable start signal

[0054] Vc: control signal

[0055] Vc': filtered control signal

Claims

1. A clock signal generation circuit, comprising: a global phase-locked loop (G-PLL) configured to receive a reference clock signal to generate a synchronized clock signal; and a plurality of local phase-locked loops (L-PLLs) each configured to receive the synchronized clock signal to generate a plurality of clock signals, respectively, for generating a plurality of output clock signals, wherein the plurality of local phase-locked loops comprises at least a first local phase-locked loop and a second local phase-locked loop, the first local phase-locked loop receiving the synchronization clock signal to generate at least a first clock signal for generating a plurality of first output clock signals; and a second L-PLL configured to receive the synchronized clock signal to generate at least one second clock signal for generating a plurality of second output clock signals, and wherein the clock signal generation circuit further comprises: a plurality of first phase adjustment circuits configured to phase adjust the at least one first clock signal, respectively, to generate the plurality of first output clock signals; and a plurality of second phase adjustment circuits configured to phase adjust the at least one second clock signal, respectively, to generate the plurality of second output clock signals.

2. The clock signal generation circuit of claim 1, wherein the clock signal generation circuit is in a dynamic random access memory (DRAM), and the plurality of first output clock signals are used for transferring a first portion of bits in a data signal, and the plurality of second output clock signals are used for transferring a second portion of bits in the data signal.

3. The clock signal generation circuit of claim 1, wherein the first L-PLL is configured to receive the synchronized clock signal to generate a plurality of first clock signals, the second L-PLL is configured to receive the synchronized clock signal to generate a plurality of second clock signals, and the clock signal generation circuit further comprises: a plurality of first multiplexers, wherein each first multiplexer receives the plurality of first clock signals and selects one of the plurality of first clock signals to generate the plurality of first output clock signals; and a plurality of second multiplexers, wherein each second multiplexer receives the plurality of second clock signals and selects one of the plurality of second clock signals to generate the plurality of second output clock signals.

4. The clock signal generation circuit of claim 1, wherein each of the plurality of L-PLLs receives a same output enable signal to synchronize the plurality of output clock signals.

5. The clock signal generation circuit of claim 1, wherein the plurality of L-PLLs comprises a first L-PLL, and the first L-PLL comprises: a phase frequency detector (PFD) configured to receive the synchronized clock signal and a feedback clock signal to generate a detection result; a charge pump (CP) coupled to the PFD and configured to generate a control signal based on the detection result; a low pass filter (LPF) coupled to the CP and configured to filter the control signal to generate a filtered control signal; an oscillator (OSC) coupled to the LPF and configured to generate an oscillator output clock signal based on the filtered control signal; a loop divider (LD) coupled to the OSC and configured to divide the oscillator output clock signal to generate the feedback clock signal; and a back-end divider (BD) coupled to the OSC and configured to divide the oscillator output clock signal to generate at least one of the plurality of clock signals. ​ ​ 6. The clock signal generation circuit of claim 5, wherein the first local phase-locked loop further comprises: a sampling circuit coupled to the loop divider to sample an output enable signal using the feedback clock signal to generate an output enable synchronization signal; wherein the back-end divider determines whether to output the at least one of the plurality of clock signals based on the output enable synchronization signal.

7. The clock signal generation circuit of claim 6, further comprising: an output enable signal generation circuit to sample an enable start signal using the synchronization clock signal to generate the output enable signal.

8. The clock signal generation circuit of claim 7, wherein each of the plurality of local phase-locked loops receives the same output enable signal to synchronize the plurality of output clock signals.

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