monitor

Abstract

An object of the present invention is to provide a display using a vertical organic light emitting transistor in which voltage fluctuation of a current supply line is reduced. A liquid crystal display device includes: a substrate; a plurality of vertical organic light emitting transistors; a data line that supplies a voltage to a gate electrode of the vertical organic light emitting transistor; a thin film transistor that is connected between the gate electrode of each of the vertical organic light emitting transistors and the data line and controls the supply of voltage to the gate electrode of the vertical organic light emitting transistor; a gate line that is connected to the gate electrode of the thin film transistor and transmits a signal for switching the thin film transistor; and a plurality of current supply lines that are wired outside a formation region of the vertical organic light emitting transistor in a first direction, the current supply lines being in contact with a source electrode of the vertical organic light emitting transistor to supply current to the vertical organic light emitting transistor.

Description

Technical Field

[0001] The present invention relates to a display. Background Art

[0002] In recent years, light source elements using organic semiconductor elements have been put into practical use, and displays using organic semiconductor elements as light source elements have been commercially available. In the development of displays using organic semiconductor elements as light source elements, research on higher brightness, higher definition, lower power consumption, and longer life has been continuously conducted to further improve performance.

[0003] Pixels of conventional displays using organic semiconductor elements as light-emitting elements are made of organic light-emitting diodes (OLEDs) (also referred to as "OLEDs") and transistors that control the current allowed to flow through the organic light-emitting diodes. The organic light-emitting diodes are devices that emit light according to current input from thin-film transistors (TFTs) (also referred to as "TFTs") formed on a substrate into an organic electroluminescent (EL) layer sandwiched between an anode electrode and a cathode electrode.

[0004] However, regarding such a configuration, the following patent document 1 describes a vertical organic light-emitting transistor (VOLET) (also referred to as "VOLET") that adjusts a flowing current by controlling a voltage applied to a gate electrode as an element for reducing the number of control elements and increasing a light-emitting area to increase brightness, and the transistor emits light according to the amount of current flowing through the transistor itself. The following patent document 2 describes a display using a vertical organic light-emitting transistor, and it is expected that the brightness of the display will be significantly increased.

[0005] Reference List

[0006] Patent Literature

[0007] Patent document 1: Patent document 1: WO 2009 / 036071

[0008] Patent document 2: Patent document 2: JP-T-2014-505324

[0009] Patent Document 3: Patent Document 3: JP-A-2018-197864 Summary of the invention

[0010] Technical issues

[0011] In recent years, displays are used not only for home televisions and personal computers, but also for various purposes such as station advertisements and event hall backgrounds. Therefore, in the development of the display of the present invention, along with the above-mentioned performance improvements, enlargement has become a major issue.

[0012] In a display using an organic semiconductor element, an organic light emitting diode, a thin film transistor, and the like forming a pixel are provided in a display unit, and a driver for driving these is provided in an outer edge portion of the display unit. This configuration is currently still adopted as a general configuration in many displays.

[0013] According to this configuration, when the display is enlarged, the transmission distance of the signal output from each driver arranged in the outer edge portion increases in order to control and drive each element over the entire display unit. Then, the wiring connecting the driver and each element becomes longer, and the resistance value of the wiring between the driver and the element becomes larger. For example, when the resistance value of the wiring increases, a voltage drop (also called current resistance drop "IR-Drop") caused by the flow current or signal delay or degradation is caused.

[0014] Specifically, in a current supply line for supplying current to a light-emitting element, when the resistance value of the wiring increases, even in the case where the same voltage is applied to allow current to flow from the current supply unit to each light-emitting element, as the distance from the current supply unit increases, the voltage also decreases according to the resistance value of the wiring and the flowing current. Then, the amount of current actually supplied is reduced relative to the current value required to display image data. Then, when this effect becomes significant, a display defect occurs and the brightness that can be visually discerned by a person gradually decreases. In addition, in many cases, the current supply line is configured to be shared by a group of light-emitting elements arranged in a row. Therefore, when the resistance value of the wiring of the current supply line changes, a brightness difference occurs in each row, and a linear display defect occurs.

[0015] As a method for taking measures against the above problems, it is conceivable to apply a method of detecting the light emitting brightness of each pixel and supplying a voltage to the data line in consideration of the amount of voltage drop as described in Patent Document 3 to the current supply line. However, when a complex circuit is added, the light emitting area is greatly compressed and high brightness is hindered. In addition, since the number of components increases, there is a possibility that a malfunction or defect may occur.

[0016] In addition, using the outer edge portion in which the driver is provided, adding external devices, and the like are conceivable, but enlarging the outer edge portion and adding external devices will limit the usage mode and installation place of the display even if various uses are required.

[0017] Furthermore, a case is conceivable in which an error occurs in a calculation method when a voltage value assuming a change is applied to control by feedback and the like, and there is a considerable possibility that a change in brightness is not corrected and thus cannot be visually discerned as a display defect. Therefore, it is desirable to take measures against display defects based on the structure of the device rather than based on correction of the change in brightness.

[0018] Here, the inventors of the present invention examined displays using vertical organic light emitting transistors and found that the vertical organic light emitting transistors also have the following problems.

[0019] Similar to a field effect transistor, a vertical organic light emitting transistor has a configuration including a source electrode, a gate electrode, and a drain electrode. However, unlike a field effect transistor such as a thin film transistor, a vertical organic light emitting transistor is provided with a light emitting layer including an organic EL layer and an organic semiconductor layer between the source electrode and the drain electrode. Due to the characteristics of the materials of these layers, a vertical organic light emitting transistor is characterized in that, compared with a field effect transistor such as a thin film transistor, the current flowing between the source electrode (anode electrode) and the drain electrode (cathode electrode) is easily affected by the voltage applied between the electrodes.

[0020] That is, a display using vertical organic light emitting transistors is characterized in that the brightness fluctuates more greatly with respect to the voltage drop of the current supply line than in the case of a conventional organic light emitting diode and thin film transistor configuration, and display defects as described above are more likely to appear.

[0021] In view of the above problems, an object of the present invention is to provide a display using a vertical organic light emitting transistor in which voltage fluctuation of a current supply line is reduced.

[0022] Solution to the problem

[0023] A display of the present invention includes: a substrate; a plurality of vertical organic light emitting transistors arranged in an array in a first direction and a second direction orthogonal to the first direction on the substrate, each of the vertical organic light emitting transistors being formed in a third direction orthogonal to the first and second directions from the substrate in the order of a gate electrode, a source electrode and a drain electrode, and having a light emitting layer between the source electrode and the drain electrode; a data line supplying a voltage to the gate electrode of the vertical organic light emitting transistor; a thin film transistor connected between the gate electrode of each of the vertical organic light emitting transistors and the data line and controlling the supply of the voltage to the gate electrode of the vertical organic light emitting transistor; a gate line connected to the gate electrode of the thin film transistor and transmitting a signal for switching between energization and interruption of the thin film transistor; and a plurality of current supply lines wired outside a formation region of the vertical organic light emitting transistor in the first direction and wired in a region at the same distance from the substrate as the gate electrode of the vertical organic light emitting transistor or a region farther from the substrate than the gate electrode with respect to the third direction, the current supply lines being in contact with the source electrode of the vertical organic light emitting transistor to supply current to the vertical organic light emitting transistor.

[0024] The “vertical organic light-emitting transistor formation region” in this specification refers to a region where, when a voltage equal to or higher than a threshold value is applied between the gate electrode and the source electrode of the vertical organic light-emitting transistor, current flows from the source electrode via the light-emitting layer toward the drain electrode to emit light.

[0025] A manufacturing process of a semiconductor is performed so that materials are stacked in a predetermined order on a substrate according to materials, growth directions, and the like, and generally, a wiring layer that connects each element with a layer forming the element itself is separately formed. For this purpose, for example, in a case where a wiring such as a current supply line is produced in the same layer as a metal wiring in a lower layer, the width of the wiring is limited to prevent current leakage with another wiring in the same layer, or the film thickness of the wiring layer is limited to prevent leakage between each wiring caused by foreign matter and the like when intersecting with many wirings via an insulating film and to prevent disconnection due to crossing a wiring step and the like.

[0026] Furthermore, in order to electrically connect the current supply line formed in the lower layer with the source electrode of the vertical organic light emitting transistor, it is necessary to form a contact hole penetrating through the multi-layer insulating film.

[0027] However, from the perspective of wiring width limitations, characteristic variations, and formation accuracy, the contact hole may not be formed so large that it is difficult to reduce the resistance value to a level that hardly contributes to the voltage drop, and there is a problem of contact failure in the contact hole portion.

[0028] Therefore, with the above configuration, the current supply line can obtain low resistance connection because the restrictions on the wiring width and the wiring film thickness are relaxed to enable the production of wiring with lower resistance and also to relax the restrictions on contact holes. In addition, according to the layer configuration, the current supply line and the source electrode of the vertical organic light emitting transistor can be directly connected without contact holes.

[0029] Therefore, the resistance value of the path from the driver supplying current to the source electrode of the vertical organic light emitting transistor is reduced by the amount not passing through the contact hole. Through these effects, the fluctuation of the voltage supplied to the source electrode of the vertical organic light emitting transistor is reduced, and the occurrence of display defects is prevented.

[0030] For a display using an organic light-emitting element, there is a system in which light is emitted via a substrate as a light-emitting system. In this case, in this configuration, preferably, the number of wirings, thin-film transistors, and the like located on a side closer to the substrate than the vertical organic light-emitting transistor is as small as possible so as not to block the light emitted from the light-emitting layer. A system in which light is emitted via a substrate is also called a "bottom emission system", and has the advantages of easy wiring connection between electrodes and easy manufacturing. A system in which light is emitted to a side opposite to the substrate is also called a "top emission system", and the above configuration can also form a display of a top emission system.

[0031] With the above configuration, the current supply line is not formed on the side closer to the substrate than the gate electrode of the vertical organic light emitting transistor, and a wider light emitting area is ensured. Therefore, the display having the above configuration also has the effect of higher brightness than the conventional display.

[0032] In the display, a light emitting layer of the vertical organic light emitting transistors is formed throughout the plurality of vertical organic light emitting transistors, and a formed bank layer may be disposed between the current supply line and the light emitting layer.

[0033] Furthermore, in the display, when viewed from a third direction, the bank layer may be formed between the source electrode and the light emitting layer and in a region different from the gate electrode.

[0034] The current supply line is a line that supplies current to the source electrode, and when the current supply line and the light emitting layer are energized, there is a possibility that light is emitted regardless of the voltage applied to the gate electrode.

[0035] Therefore, with the above configuration, the light emitting layer and the current supply line are not energized, unintended current including leakage current is prevented, and unintended light emission is prevented.

[0036] Note that a layer other than the bank layer may be included between the current supply line and the light emitting layer. For example, a configuration in which an electrode material made of carbon nanotubes (CNT) is formed on the surface layer and a source electrode serves as a base is conceivable. In this case, a bank layer and a source electrode made of carbon nanotubes are formed between the current supply line and the light emitting layer.

[0037] In the display, an organic resin layer may be disposed between the current supply line and the gate electrode of the vertical organic light emitting transistor.

[0038] Furthermore, in the display, the organic resin layer may be formed between the gate electrode of the vertical organic light emitting transistor and the source electrode of the vertical organic light emitting transistor to overlap with a peripheral end portion of the gate electrode of the vertical organic light emitting transistor when viewed from a third direction.

[0039] When each layer is observed from a third direction, the peripheral end of each layer in this specification is the outermost peripheral area having a specific width from the edge. The width of the peripheral end overlapping with the organic resin layer is in the range of tens or hundreds of nanometers to several micrometers. More specifically, from the perspective of ensuring the light-emitting area, reducing the size of the thin film transistor, leakage current and parasitic capacitance, and similar factors, the width is preferably in the range of 200 nanometers to 5 micrometers, and more preferably in the range of 500 nanometers to 2 micrometers.

[0040] When a gate electrode and the like exist nearby, the current supply line has a risk of generating leakage current. For example, when leakage current is generated to the gate electrode, the voltage of the gate electrode fluctuates to approach the source electrode voltage, that is, the voltage of the current supply line.

[0041] Even in the case where a current supply line is formed in a layer different from the gate electrode via an insulating film, parasitic capacitance is generated when the gate electrode and the current supply line overlap each other, and voltage fluctuations may affect a voltage, or a larger current may be required when charging the electrode.

[0042] Then, in the vertical organic light emitting transistor, the voltage supplied from the data line to the gate electrode slightly fluctuates to obtain a predetermined brightness, and the vertical organic light emitting transistor does not emit light at the predetermined brightness.

[0043] When the direction of stacking on the substrate is upward, as described above, the vertical organic light emitting transistor is formed above the thin film transistor. In the layer formed on the upper side of the thin film transistor, large irregularities and edges are formed due to the shape of the thin film transistor. When irregularities are formed to cross the layer or edges are formed to divide the layer, a leakage current path is formed, thereby possibly generating leakage current from the current supply line.

[0044] With the above configuration, it is possible to prevent leakage current and parasitic capacitance generated in a layer formed on the substrate side of the current supply line from being generated.

[0045] In addition, when the current supply line is formed by stacking on the upper side of the thin film transistor, the organic resin layer also has the effect of covering the irregularities and edges formed by the thin film transistor and flattening the surface. Therefore, compared with the related art, another layer including wiring can be formed on the flattened surface, so that the quality of the wiring and the like can be prevented from changing, and the yield can be improved.

[0046] Note that the organic resin layer is preferably formed of a material having a lower dielectric constant than the dielectric constant of the insulating film layer formed between the gate electrode and the source electrode of the vertical organic light emitting transistor in order to further prevent leakage current and parasitic capacitance. The organic resin layer may not be configured to contact the current supply line and the gate electrode of the vertical organic light emitting transistor.

[0047] The organic resin layer in this specification is formed as an insulating film to cover a portion of the layer in order to reduce leakage current and parasitic capacitance, and thus may be referred to as an "overcoat layer".

[0048] The display may include at least one auxiliary line that is wired in the second direction and connects at least two of the plurality of current supply lines.

[0049] Furthermore, in the display, the auxiliary line may be formed in the same layer as the current supply line.

[0050] With the above configuration, the current supply lines are wired in a lattice shape, and thus the resistance value from the driver supplying current to the source electrode of each vertical organic light emitting transistor is reduced. Even when wiring degradation or disconnection occurs in some current supply lines, the vertical organic light emitting transistor connected to the current supply line in which the failure has occurred is supplied with current from another current supply line via the auxiliary line.

[0051] In addition, by forming the current supply line and the auxiliary line in the same layer, the current supply line and the auxiliary line are directly connected without passing through the contact hole. Therefore, the resistance value from the driver to the source electrode of the vertical organic light emitting transistor can be reduced.

[0052] In the display, a bank layer may be provided between the current supply line and the light emitting layer.

[0053] With the above configuration, as in the case of the above-mentioned current supply line, there is no possibility that the light-emitting layer and the auxiliary line are energized, and the generation of unexpected light emission and unexpected current including leakage current can be prevented. Therefore, the leakage current generated from the auxiliary line is almost eliminated, and the influence on the amount of current flowing through the current supply line is also reduced. Therefore, the voltage fluctuation of the current supply line is further reduced.

[0054] In the display, source electrodes of the vertical organic light emitting transistors may be formed across at least two or more of the vertical organic light emitting transistors.

[0055] With the above configuration, not the current supply line wired with a predetermined width but the source electrode is used as the current supply line, and the current supplied from the driver to each vertical organic light emitting transistor is supplied to each vertical organic light emitting transistor, thereby causing the current to spread. Therefore, the resistance value from the driver to the source electrode of each vertical organic light emitting transistor is greatly reduced.

[0056] In addition, for example, in a region where many contact holes can be formed adjacent to the driver, the resistance value generated between the current supply line and the source electrode of each vertical organic light-emitting transistor can be minimized by connecting to a layer forming the source electrode of the vertical organic light-emitting transistor.

[0057] When the above configuration is adopted, from the perspective of reducing the resistance value from the driver to each vertical organic light-emitting transistor, the material constituting the source electrode is preferably formed of a material having lower resistance than the material of the current supply line formed as wiring (e.g., carbon nanotubes).

[0058] Advantageous Effects of the Invention

[0059] According to the present invention, a display using a vertical organic light emitting transistor in which voltage fluctuation of a current supply line is reduced is realized. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] Figure 1 is a schematic configuration diagram of a portion of one embodiment of a display.

[0061] Figure 2 yes Figure 1 Circuit diagram of the light emitting unit in area A1 of the display shown.

[0062] Figure 3A is a top view of a schematic component configuration of a light emitting unit and its surroundings according to one embodiment.

[0063] Figure 3B is to show that the current supply line 12 has been Figure 3A Figure 2. Off-state diagram removed.

[0064] Figure 4 is along Figure 3A A cross-sectional view taken along line AA' is shown.

[0065] Figure 5A is a schematic diagram showing the periphery of a vertical organic light emitting transistor of the display in the middle of the manufacturing process as viewed from the +Z side.

[0066] Figure 5B is a schematic diagram showing the periphery of a vertical organic light emitting transistor of the display in the middle of the manufacturing process as viewed from the +Z side.

[0067] Figure 5C is a schematic diagram showing the periphery of a vertical organic light emitting transistor of the display in the middle of the manufacturing process as viewed from the +Z side.

[0068] Figure 5D is a schematic diagram showing the periphery of a vertical organic light emitting transistor of the display in the middle of the manufacturing process as viewed from the +Z side.

[0069] Figure 5E is a schematic diagram showing the periphery of a vertical organic light emitting transistor of the display in the middle of the manufacturing process as viewed from the +Z side.

[0070] Fig. 5F is a schematic diagram showing the periphery of a vertical organic light emitting transistor of the display in the middle of the manufacturing process as viewed from the +Z side.

[0071] Figure 5G is a schematic diagram showing the periphery of a vertical organic light emitting transistor of the display in the middle of the manufacturing process as viewed from the +Z side.

[0072] Figure 5H is a schematic diagram showing the periphery of a vertical organic light emitting transistor of the display in the middle of the manufacturing process as viewed from the +Z side.

[0073] Fig.5I is a schematic diagram showing the periphery of a vertical organic light emitting transistor of the display in the middle of the manufacturing process as viewed from the +Z side.

[0074] Figure 6 is a top view of a schematic component configuration of a light emitting unit and its surroundings according to one embodiment.

[0075] Figure 7 is along Figure 6 A cross-sectional view taken along line BB' is shown.

[0076] Figure 8 is along Figure 6 A cross-sectional view taken along line BB' is shown.

[0077] Fig. 9 is a cross-sectional view of a schematic element configuration of a light emitting unit and its periphery according to another embodiment, taken along a YZ plane.

[0078] Explanation of symbols

[0079] 1: Display

[0080] 10: Light-emitting unit

[0081] 11: Data cable

[0082] 12: Current supply line

[0083] 13: Gate line

[0084] 14: Auxiliary lines

[0085] 14c, 21c: contact holes

[0086] 15a: Source driver

[0087] 15b: Current supply unit

[0088] 15c: Gate Driver

[0089] 20: Vertical organic light-emitting transistor

[0090] 20a: Organic semiconductor layer

[0091] 20c: Organic EL layer

[0092] 20d, 21d: drain electrode layer

[0093] 20g, 21g: Gate electrode layer

[0094] 20h: Gate insulation film layer

[0095] 20s, 21s: Source electrode layer

[0096] 21: Thin Film Transistor

[0097] 21a: Oxide semiconductor layer

[0098] 23: Capacitor

[0099] 24: Dike layer

[0100] 30: Substrate

[0101] 31: Surface layer

[0102] 32: Organic resin layer

[0103] A1: Area

[0104] A-A', B-B': line

[0105] X: Direction / First Direction

[0106] Y: Direction / Second Direction

[0107] Z: Direction / Third direction DETAILED DESCRIPTION

[0108] Hereinafter, the configuration of the display of the present invention will be described with reference to the accompanying drawings. Note that the following drawings are schematically shown, and the dimensional ratios and numbers in the drawings are not necessarily consistent with the actual dimensional ratios and numbers.

[0109] First embodiment

[0110] Figure 1 1 is a schematic configuration diagram of a portion of an embodiment of the display 1. Figure 1 As shown in FIG. 1 , the display 1 of the present embodiment includes light emitting units 10 , data lines 11 , current supply lines 12 , gate lines 13 and auxiliary lines 14 . The light emitting units 10 are arranged in an array and each includes a vertical organic light emitting transistor 20 to be described later.

[0111] In addition, the display 1 includes in the outer edge portion: a source driver 15a, which supplies a voltage corresponding to the image data displayed on the gate electrode of the vertical organic light-emitting transistor 20 to the data line 11; a current supply unit 15b, which supplies current to the current supply line 12 and to the source electrode of the vertical organic light-emitting transistor 20; and a gate driver 15c, which outputs a control signal of the thin film transistor 21 to the gate line 13.

[0112] Figure 2 yes Figure 1 FIG. 1 is a detailed circuit diagram of the light emitting unit 10 in the area A1 of the display 1. Figure 2 As shown in FIG. 1 , the light emitting unit 10 includes a vertical organic light emitting transistor 20, a thin film transistor 21 for controlling voltage supply to a gate electrode of the vertical organic light emitting transistor 20, and a capacitor 23 formed between a source electrode and a gate electrode of the vertical organic light emitting transistor 20. Figure 1 and Figure 2 In the description, the direction in which the current supply line 12 is wired is referred to as an X direction (first direction), and the direction in which the auxiliary line 14 is wired is referred to as a Y direction (second direction).

[0113] The data line 11 is a wiring that applies a voltage output from the source driver 15a to the gate electrode of the vertical organic light emitting transistor 20 via the thin film transistor 21 so as to adjust the light emission brightness of the vertical organic light emitting transistor 20 according to the image to be displayed. In the present embodiment, the data line 11 is formed in the X direction, but may be formed in the Y direction.

[0114] The plurality of current supply lines 12 are wired outside the formation region of the vertical organic light emitting transistors 20 in the X direction to be connected to corresponding groups of the vertical organic light emitting transistors 20 arranged in the X direction. Each current supply line 12 supplies the current output from the current supply unit 15 b to the source electrode of each vertical organic light emitting transistor 20 included in the group of the vertical organic light emitting transistors 20.

[0115] The gate line 13 is connected to the gate electrode of the thin film transistor 21, transmits a control signal output from the gate driver 15c to the gate electrode of the thin film transistor 21, and turns on / off the thin film transistor 21 to control the conduction between the gate electrode of the vertical organic light emitting transistor 20 and the data line 11. In the present embodiment, the gate line 13 is formed in the Y direction, but may be formed in the X direction.

[0116] The auxiliary line 14 is wired in the Y direction between the light emitting units 10 arranged in the X direction, and connects the plurality of current supply lines 12. Note that the auxiliary line 14 may not be formed between all the light emitting units 10 arranged in the X direction. In the present embodiment, the current supply line 12 is formed in the X direction, and the auxiliary line 14 is formed in the Y direction. However, the current supply line 12 may be formed in the Y direction, and the auxiliary line 14 may be formed in the X direction.

[0117] The capacitor 23 is a voltage holding element provided between the gate electrode and the source electrode of the vertical organic light emitting transistor 20 to maintain a displayed image for a predetermined time while the thin film transistor 21 is in an off state.

[0118] Next, the structure of each element formed on the substrate will be described. Figure 3A is a top view of a schematic configuration of components of a light emitting unit 10 and its surroundings according to an embodiment, and Figure 3B is a point in which the current supply line 12 has been Figure 3A Figure 2. ... Figure 4 is along Figure 3A The cross-sectional view taken along the line AA' is shown. Figure 3B and Figure 4 As shown in FIG. 1 , a group of vertical organic light emitting transistors 20 and thin film transistors 21 are formed in a region divided by a data line 11 and a gate line 13 .

[0119] Figure 3A and Figure 3B The vertical organic light emitting transistor 20 shown in FIG. 1 is shown by cutting away a portion of a region also referred to as a formation region as described above. Figure 4As shown in , the drain electrode layer 20 d , the light emitting layer (organic semiconductor layer 20 a , organic EL layer 20 c ), the source electrode layer 20 s , and the like of the vertical organic light emitting transistor 20 of the present embodiment are formed throughout the plurality of vertical organic light emitting transistors 20 .

[0120] The substrate 30 is transparent to light, and emits light emitted from the vertical organic light emitting transistor 20 to the outside. Specific materials will be described later.

[0121] In the following description, the direction in which the data line 11 and the current supply line 12 are wired is referred to as the X direction (first direction), the direction in which the gate line 13 is wired is referred to as the Y direction (second direction), and the direction orthogonal thereto is referred to as the Z direction (third direction). When expressing a direction, when a positive direction and a negative direction are to be distinguished, a positive sign and a negative sign are used to describe the direction (e.g., "+Z direction" and "-Z direction"), and when a direction is to be expressed without distinguishing between a positive direction and a negative direction, the direction is simply described as the "Z direction".

[0122] In the configuration of the vertical organic light-emitting transistor 20, the following layers are formed from the +Z side: a drain electrode layer 20d, corresponding to a cathode electrode; an organic EL layer 20c and an organic semiconductor layer 20a, forming a light-emitting layer; a source electrode layer 20s, configured to apply a conductive material containing carbon (in this embodiment, carbon nanotubes) to the surface of the surface layer 31; and a gate electrode layer 20g, located on the -Z side via a gate insulating film layer 20h made of a dielectric.

[0123] In the vertical organic light-emitting transistor 20 having the above configuration, when voltage is applied to the gate electrode layer 20g, the Schottky barrier between the organic semiconductor layer 20a and the source electrode layer 20s changes, and when the voltage exceeds a predetermined threshold, current flows from the source electrode layer 20s to the organic semiconductor layer 20a and the organic EL layer 20c to emit light.

[0124] In order to electrically insulate the organic semiconductor layer 20a from the current supply line 12, a bank layer 24 is formed between the organic semiconductor layer 20a and the current supply line 12. Figure 4 The X direction is not shown in the figure, but the source electrode layer 20s is applied to the XY plane on the +Z side of the current supply line 12, and is formed to be in direct contact with the current supply line 12. That is, the bank layer 24 is formed between the organic semiconductor layer 20a and the current supply line 12, and the organic semiconductor layer 20a is electrically insulated from the current supply line 12 (source electrode layer 20s).

[0125] In the current supply line 12, an organic resin layer 32 for electrically insulating the substrate 30 side (-Z side) is formed. Here, in order to prevent leakage current from being generated from the current supply line 12, the organic resin layer 32 in the present embodiment is made of a material having a lower dielectric constant than the material constituting the gate insulating film layer 20h, but may be made of a material having a higher dielectric constant than the material constituting the gate insulating film layer 20h. The specific material constituting the organic resin layer 32 will be described later.

[0126] Furthermore, to prevent leakage current from being generated between the source electrode layer 20s and the gate electrode layer 20g, the organic resin layer 32 in this embodiment is more desirably formed between the source electrode layer 20s and the gate electrode layer 20g to overlap with the peripheral end of the gate electrode layer 20g.

[0127] In the display 1 of this embodiment, the substrate 30 is made of a material that is transparent to visible light, and the gate electrode layer 20g and the source electrode layer 20s are configured to have a gap through which visible light can pass, so that light emitted from the organic EL layer 20c is emitted to the outside via the substrate 30 to display an image.

[0128] In the thin film transistor 21, the source electrode layer 21s and the drain electrode layer 21d are connected through the oxide semiconductor layer 21a, and the gate electrode layer 21g is formed below the oxide semiconductor layer 21a through an insulating film layer or a dielectric layer. When a voltage is applied to the gate electrode layer 21g, a channel is formed in the oxide semiconductor layer 21a, and the source electrode layer 21s and the drain electrode layer 21d are energized.

[0129] In the thin film transistor 21 , the source electrode layer 21 s is connected to the data line 11 , and the drain electrode layer 21 d is connected to the gate electrode layer 20 g of the vertical organic light emitting transistor 20 .

[0130] like Figure 3B As shown in FIG. 1 , the vertical organic light emitting transistor 20 is formed to almost fill the entire area divided by the data line 11 and the gate line 13 to increase brightness. The thin film transistor 21 is formed as small as possible at the corner of the divided area to have little influence on the light emitting area of ​​the vertical organic light emitting transistor 20.

[0131] although FIG. 3A to FIG. 4 The capacitor 23 is not shown, however Figure 3AAs shown in , the vertical organic light emitting transistor 20 of the present embodiment is arranged so that the source electrode layer 20s and the gate electrode layer 20g face each other, with the gate insulating film layer 20h interposed therebetween. Therefore, the vertical organic light emitting transistor 20 includes the capacitor 23 as a parasitic element, and the capacitor 23 can also perform a voltage maintenance function. In the capacitor 23 as a parasitic element thus described, when the capacitance value is insufficient, another capacitor may be additionally formed.

[0132] Hereinafter, materials used for each layer will be exemplified and listed.

[0133] As the gate lines 13 and the auxiliary lines 14, aluminum (Al), titanium (Ti), molybdenum (Mo), tungsten (W), niobium (Nb), magnesium (Mg), silver (Ag), copper (Cu), alloys thereof, and the like may be used.

[0134] As the substrate 30, a glass material, a plastic material such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyimide, or the like may be used.

[0135] As the drain electrode layer 20d of the vertical organic light emitting transistor 20, single-layer or multi-layer graphene, carbon nanotubes, aluminum (Al), lithium fluoride (LiF), molybdenum oxide (Mo) X O Y ), indium tin oxide (ITO), zinc oxide (ZnO), magnesium (Mg), silver (Ag), gold (Au) and alloys of combinations of other substances, and the like.

[0136] As the gate electrode layer 20g of the vertical organic light-emitting transistor 20, for example, zinc oxide (ZnO), indium oxide (InO) or the like doped with metals such as aluminum (Al), tin (Sn), yttrium (Y), scandium (Sc) or gallium (Ga) may be used. 2 O 3 ), tin dioxide (SnO 2 ) and metal-doped oxides such as cadmium oxide (CdO), undoped transparent conductive oxides, and combinations thereof; aluminum (Al), gold (Au), silver (Ag), platinum (Pt), cadmium (Cd), nickel (Ni), tantalum (Ta), and combinations thereof; p- or n-doped silicon (Si) and gallium arsenide (GaAs); and the like.

[0137] As the gate insulating film layer 20h between the surface layer 31 and the gate electrode layer 20g of the vertical organic light emitting transistor 20, for example, silicon oxide (SiO X ), aluminum oxide (Al2 O 3 ), silicon nitride (Si 3 N 4 ), yttrium oxide (Y 2 O 3 ), lead titanate (PbTiO X ), aluminum titanate (AlTiO X ), glass, polyparaxylene polymer, polystyrene, polyimide, polyvinylphenol, polymethyl methacrylate and fluoropolymer and other organic compounds and the like.

[0138] As the organic semiconductor layer 20a of the vertical organic light-emitting transistor 20, the following can be used: linear condensed polycyclic aromatic compounds (or acene compounds), such as naphthalene, anthracene, rubrene, tetracene, pentacene and hexacene and their derivatives; pigments, such as (for example) copper phthalocyanine (CuPc) series compounds, azo compounds, perylene series compounds and their derivatives; low molecular weight compounds, such as (for example) hydrazone compounds, triphenylmethane series compounds, diphenylmethane series compounds, distyrene series compounds, allyl vinyl compounds, pyrazoline series compounds, triphenylamine derivatives (triphenylamine) derivatives; derivative, TPD), arylamine compounds, low molecular weight amine derivatives (a-NPD), 2,2',7,7'-tetrakis(diphenylamino)-9,9'-spirobifluorene (spiro-TAD), N,N'-di(1-naphthyl)-N,N'-diphenyl-4,4'-diamonobiphenyl (spiro-NPB), 4,4',4'-tris[N-3methylphenyl-N-phenylamino]triphenylamine (mMTD ATA), 2,2',7,7'-tetrakis(2,2-diphenylvinyl)-9,9-spirobifluorene (spiro-DPVBi), 4,4'-bis(2,2-diphenylvinyl)biphenyl (DPVBi), (8-quinolinolato)aluminum (Alq), tris(8-quinolinolato)aluminum (Alq3), tris(4-methyl-8quinolinolato)aluminum (Almq3) and their derivatives;Polymer compounds such as, for example, polythiophene, poly(p-phenylenevinylene) (PPV), biphenyl-containing polymers, dialkoxy-containing polymers, alkoxyphenyl PPV, phenyl PPV, phenyl / dialkoxy PPV copolymers, poly(2-methoxy-5-(2'-ethylhexyloxy)-1,4-phenylenevinylene) (MEH-PPV), poly(ethylenedioxythiophene) (PEDOT), poly(styrenesulfonic acid) acid, PSS), poly(aniline), poly(PAM), poly(N-vinylcarbazole), poly(vinylpyrene), poly(vinylanthracene), pyrene formaldehyde resin, halogenated ethylcarbazole formaldehyde resin and its modified products; n-type transport of organic small molecules, such as 5,5-diperfluorohexylcarbonyl-2,2:5,2:5,2-quaterthiophene (DFHCO-4T), α,ω-diperfluorohexylquaterthiophene (DFH- 4T), 5,5"'-bis(perfluorophenylcarbonyl)-2,2':5',2":5",2"'-tetrathiophene (DFCO-4T), poly{[N,N'-bis(2-octyldodecanol)naphthalene-1,4,5,8-bis-(dicarboximide)-2,6-diyl]-5,5'-(2,2'-bithiophene)}(P(NDI2OD-T2)), N,N'-bis(n-octyl)-x:y, dicyanoacetyl-3, 4,9,10-bis(dicarboximide) (PDI8-CN2), N,N'-1H,1H-perfluorobutyl dicyanoperylene imide (PDIF-CN2), fluorinated copper phthalocyanine (F16CuPc), fullerene, naphthalene, perylene and oligothiophene derivatives, oligomers, polymers, aromatic compounds with thiophene rings, such as thieno[3,2-b]thiophene, dinaphthyl[2,3-b:2',3'-f]thieno[3,2-b] Thiophene (dinaphthyl[2,3-b:2',3'-f]thieno[3,2-b]thiophene, DNTT) and 2-decyl-7phenyl[1]benzothieno[3,2-b][1]benzothiophene (2-decyl-7phenyl[1]benzothieno[3,2-b][1]benzothiophene, BTBT); and analogs. ;

[0139] Here, as the vertical organic light emitting transistor 20, by appropriately selecting an organic semiconductor having a suitable energy level, a hole injection layer, a hole transport layer, an organic EL layer, an electron transport layer, an electron injection layer, and the like generally used for an organic light emitting diode (OLED) display can be suitably used. Then, by selecting a material constituting the above-mentioned organic EL layer 20c, the color of the light to be emitted to the outside is adjusted to emit light of colors such as red, green, and blue. In addition, the vertical organic light emitting transistor 20 may be configured to emit white light, or may be configured to select and emit light of a desired color using a color filter using the same vertical organic light emitting transistor 20.

[0140] The surface layer 31 is a layer formed on the gate insulating film layer 20h for the purpose of fixing the source electrode layer 20s (specifically, the CNT layer). The material for forming the surface layer 31 can be formed by applying a composition containing a binder resin formed of a silane coupling material, an acrylic resin, and the like.

[0141] As the bank layer 24, inorganic insulating materials such as silicon oxide (SiO), silicon nitride (Si 3 N 4 ), aluminum oxide (Al 2 O 3 ) and aluminum nitride (AlN); organic insulating materials such as polyimide resin, siloxane resin, acrylic resin and novolac resin; and the like.

[0142] As the organic resin layer 32, a photosensitive material having an insulating property, for example, an organic insulating material such as a polyimide resin, a siloxane resin, an acrylic resin, a novolac resin, and the like can be used.

[0143] As the oxide semiconductor layer 21a included in the thin film transistor 21, an In-Ga-Zn-O semiconductor, a Zn-O semiconductor (ZnO), an In-Zn-O semiconductor (In-Zn-O-based semiconductor, IZO (registered trademark)), a Zn-Ti-O semiconductor (Zn-Ti-O-based semiconductor, ZTO), a Cd-Ge-O semiconductor, a Cd-Pb-O semiconductor, CdO (cadmium oxide), a Mg-Zn-O semiconductor, an In-Sn-Zn-O semiconductor (for example, In 2 O 3 -SnO 2 -ZnO), In-Ga-Sn-O based semiconductors and the like.

[0144] In the present embodiment, the thin film transistor 21 is a thin film transistor made of an oxide semiconductor, but may be a thin film transistor made of amorphous silicon. The thin film transistor 21 may be a p-type or an n-type. In addition, as a specific configuration, any configuration of a staggered type, an inverted staggered type, a coplanar type, an inverted coplanar type, and the like may be adopted.

[0145] As the vertical organic light emitting transistor 20 , the vertical organic light emitting transistor 20 described in Patent Documents 1 and 2 may also be employed, and furthermore, the configuration of Patent Document 3 may also be employed.

[0146] Next, the fabrication process of each layer will be briefly described. FIG. 5A to FIG. 5I 2 is a schematic diagram showing the periphery of a vertical organic light emitting transistor 20 of the display 1 in the middle of the manufacturing process as viewed from the +Z side. Hereinafter, each step will be described with reference to the accompanying drawings.

[0147] Description will be given with reference to a drawing in which three vertical organic light emitting transistors 20 arranged in the Y direction are formed so that the positional relationship with adjacent vertical organic light emitting transistors 20 and the structure between the vertical organic light emitting transistors 20, that is, the structure outside the formation area can be understood.

[0148] Note that the outer portion of the illustrated region may not repeat in the same pattern. Figure 5D As shown in the figures and similar figures, the thin film transistor 21 is formed on the (+X, -Y) side relative to the center portion in the X direction in the entire display 1, but may be formed in any pattern on the -X side, for example, on the (-X, +Y) side.

[0149] like Figure 5A As shown in FIG. 1 , first, a substrate 30 is prepared (step S1 ).

[0150] After step S1, Figure 5B As shown in FIG. 1 , the gate electrode layer 21 g of the thin film transistor 21 and the gate line 13 connected to the gate electrode layer 21 g are formed on the substrate 30 (step S2 ).

[0151] After step S2, an insulating film (not shown) is formed over the entire region, and Figure 5C As shown in , the oxide semiconductor layer 21 a is formed on the insulating film on the +Z side of the gate electrode layer 21 g of the thin film transistor 21 (step S3 ).

[0152] Here, "formed over the entire region" means formed over the entire image display region in which the vertical organic light emitting transistor 20 is formed, and does not mean formed over the entire outer edge portion in which the driver is provided. This also applies to the following description.

[0153] After step S3, Figure 5DAs shown in FIG. 2 , the drain electrode layer 21d and the data line 11 are formed on the oxide semiconductor layer 21a of the thin film transistor 21 while the drain electrode layer 21d and the data line 11 are separated from each other in the Y direction (step S4). The data line 11 constitutes the source electrode layer 21s of the thin film transistor 21 in the portion overlapping with the oxide semiconductor layer 21a in the Z direction.

[0154] After step S4, a passivation film (not shown) is formed over the entire region, and then, as shown in FIG. Figure 5E As shown in FIG. 5 , a contact hole 21 c is formed, and the drain electrode layer 21 d of the thin film transistor 21 is connected to the gate electrode layer 20 g of the vertical organic light emitting transistor 20 via the contact hole 21 c (step S5 ).

[0155] After step S5, Fig. 5F As shown in , the gate electrode layer 20g of the vertical organic light emitting transistor 20 is formed (step S6).

[0156] After step S6, the gate insulating film layer 20h of the vertical organic light emitting transistor 20 is formed over the entire area, and the surface layer 31 is formed on the gate insulating film layer 20h, and through-hole holes are opened on appropriate areas outside the pixel area for interconnection and contact of various conductive layers (step S7). The gate insulating film layer 20h and the surface layer 31 are formed over the entire area in the pixel area, and when the layers are shown, the entire configuration of the underlying layer may not be confirmed, and therefore Figure 5G to Figure 5I The layers are not shown.

[0157] After step S7, Figure 5G As shown in FIG. 1 , an organic resin layer 32 is formed on the surface layer 31 outside the formation region of the vertical organic light emitting transistor 20 (step S8). Note that Figure 5G The region indicated by the dotted line in FIG. 3 indicates the entire gate electrode layer 20g of the vertical organic light emitting transistor 20. That is, the organic resin layer 32 is formed to overlap with the peripheral end portion of the gate electrode layer 20g of the vertical organic light emitting transistor 20 in the Z direction. In the present embodiment, the organic resin layer 32 is configured so that the width of the overlapping region is 2 micrometers from the outer edge of the gate electrode layer 20g except for the region in which the thin film transistor 21 is formed.

[0158] After step S8, Figure 5H As shown in , the current supply line 12 is formed on the organic resin layer 32 in the X direction, and the auxiliary line 14 is formed to connect the current supply line 12 in the Y direction (step S9). In the present embodiment, in the case where the current supply line 12 and the auxiliary line 14 are formed in different layers, a contact hole 14c is also formed to connect the layers. As for the formation position and configuration of the contact hole 14c, the contact hole 14c can be formed at any position in a suitable shape or number.

[0159] After step S9 , contact holes for connecting the source electrode are opened at predetermined positions of the current supply line 12 by photolithography (step S10 ).

[0160] After step S10, a source electrode layer 20s of the vertical organic light emitting transistor 20 made of carbon nanotubes is formed over the entire region (step S11). In the source electrode layer 20s, all configurations of the underlying layers may not be confirmed, and therefore, the following Fig.5I The source electrode layer is not shown.

[0161] After step S11, Fig.5I As shown in FIG. 1 , a bank layer 24 is formed (step S12 ).

[0162] After step S12, an organic semiconductor layer 20a, an organic EL layer 20c and a drain electrode layer 20d to be a light-emitting layer are formed over the entire region, and FIG. 3A to FIG. 4 The configuration shown in .

[0163] The display 1 having the above configuration is formed by the manufacturing process as described above, the current supply line 12 is connected by the auxiliary line 14, and the voltage value of the connection portion of another connected current supply line 12 is shared at the connection portion with the auxiliary line 14. That is, even when an extreme voltage drop occurs in a portion due to a change in the resistance value of the current supply line 12, the voltage is increased by another current supply line 12 connected to the auxiliary line 14. As in the present embodiment, as the number of connection portions between the current supply line 12 and the auxiliary line 14 increases, the voltage of the current supply line 12 becomes uniform over the entire display 1.

[0164] In this way, the voltages of the current supply lines 12 connected by the auxiliary lines 14 are uniformized. Therefore, in each current supply line 12, the display 1 with improved display quality in which a local voltage drop is less likely to occur and display defects are less likely to be visually discerned can be realized.

[0165] In the present embodiment, the owners of the drain electrode layer 20d, the organic semiconductor layer 20a, the organic EL layer 20c and the source electrode layer 20s of the vertical organic light emitting transistor 20 are formed throughout the plurality of vertical organic light emitting transistors 20 , but the owners of the layers may be formed for each vertical organic light emitting transistor 20 .

[0166] In addition, when each layer is formed for each vertical organic light emitting transistor 20 and leakage current is not generated from the current supply line 12 , the bank layer 24 and the organic resin layer 32 may not be formed.

[0167] Second embodiment

[0168] The configuration of the second embodiment of the display 1 of the present invention will be explained focusing on the parts different from the first embodiment.

[0169] Figure 6 1 is a top view of a schematic component configuration of a light emitting unit 10 and its surroundings according to an embodiment different from the first embodiment. Figure 6 As shown in , the current supply line 12 and the auxiliary line 14 may not be connected by using the contact hole 14c, but may be integrally formed in the same layer from the same material. In addition, the current supply line 12 and the auxiliary line 14 may be formed in the same layer and formed from different materials, or may be formed in different layers and formed from the same material.

[0170] Figure 7 is along Figure 6 The cross-sectional view taken along the line BB' is shown. Figure 7 As shown in FIG. 8 , the auxiliary line 14 may be configured to be sandwiched between the bank layer 24 and the organic resin layer 32 .

[0171] With the above configuration, even in the auxiliary line 14 formed integrally with the current supply line 12 , leakage current generated between the organic semiconductor layer 20 a and the organic EL layer 20 c can be prevented.

[0172] Note that the bank layer 24 may be formed between the source electrode layer 20s and the organic semiconductor layer 20a in a region different from the gate electrode layer 20g when viewed from the Z direction. In addition, in the second embodiment, when each layer such as the drain electrode layer 20d is formed for each vertical organic light emitting transistor 20 and leakage current from the auxiliary line 14 hardly occurs, the bank layer 24 and the organic resin layer 32 may not be formed.

[0173] Figure 8 is along Figure 6 The cross-sectional view taken along the line BB' is different from Figure 7 .like Figure 8 As shown in FIG. 1 , the organic resin layer 32 may be formed on the same plane as the gate electrode layer 20g. In this configuration, contact holes for connecting the source electrode layer 20s of the vertical organic light emitting transistor 20 to the current supply line 12 are formed in the surface layer 31 and the gate insulating film layer 20h.

[0174] In addition, in the case of such a configuration, as long as the distance between the gate electrode layer 20g of the vertical organic light emitting transistor 20 and the current supply line 12 is large enough on the XY plane, the organic resin layer 32 may not be formed, and the gate electrode layer 20g of the vertical organic light emitting transistor 20 and the current supply line 12 may be formed on the same plane. The current supply line 12 may be a multi-layer structure including a transparent conductive layer formed simultaneously with the gate electrode layer 20g and a more conductive metal layer formed directly above or below the transparent conductive layer. Such a multi-layer structure will further reduce the resistance value of the current supply line 12.

[0175] In the second embodiment, even when Figure 4 When viewed in the cross section of the YZ plane shown in , the arrangement relationship of the positions at which the bank layer 24, the source electrode layer 20s, the current supply line 12, the organic resin layer 32, the surface layer 31, and the gate insulating film layer 20h are formed is also the same in the Z direction. Note that the arranged layers do not necessarily need to overlap each other, so that the organic resin layer 32 is formed on the -Z side of the auxiliary line 14 and the organic resin layer 32 is not formed on the -Z side of the current supply line 12.

[0176] Another embodiment

[0177] Hereinafter, another embodiment will be described.

[0178] <1> Fig. 9 is a cross-sectional view of a schematic element configuration of a light emitting unit 10 and its periphery according to another embodiment, taken along the YZ plane. Fig. 9 As shown in , the organic resin layer 32 may not be formed in the portion between the gate electrode layer 20g and the source electrode layer 20s, that is, it may not overlap with the peripheral end of the gate electrode layer 20g. In addition, the organic resin layer 32 may not be formed at all between the gate electrode layer 20g and the source electrode layer 20s.

[0179] <2> The configuration, material, and manufacturing process of the above-described display 1 in each embodiment are merely examples, and the present invention is not limited to each of the above-described configurations and each of the illustrated configurations.

Claims

1. A display, comprising: substrate; a plurality of vertical organic light emitting transistors arranged in an array on the substrate in a first direction and in a second direction orthogonal to the first direction, wherein each of the vertical organic light emitting transistors is formed in a third direction orthogonal to the first direction and the second direction from the substrate in the order of a gate electrode, a source electrode and a drain electrode, and has a light emitting layer between the source electrode and the drain electrode; a data line for supplying a voltage to the gate electrode of the vertical organic light emitting transistor; a thin film transistor connected between the gate electrode of each of the vertical organic light emitting transistors and the data line and controlling supply of a voltage to the gate electrode of the vertical organic light emitting transistor; a gate line connected to the gate electrode of the thin film transistor and transmitting a signal for switching between power on and power off of the thin film transistor; as well as A plurality of current supply lines are wired outside a formation region of the vertical organic light-emitting transistor in the first direction and are wired in a region at the same distance from the substrate as the gate electrode of the vertical organic light-emitting transistor or in a region farther from the substrate than the gate electrode with respect to the third direction, the current supply lines being in contact with the source electrode of the vertical organic light-emitting transistor to supply current to the vertical organic light-emitting transistor.

2. The display according to claim 1, wherein The light emitting layer of the vertical organic light emitting transistor is formed throughout the plurality of vertical organic light emitting transistors, and A bank layer is provided between the current supply line and the light emitting layer. 3 . The display according to claim 2 , wherein the bank layer is formed between the source electrode and the light emitting layer and in a region different from the gate electrode when viewed from the third direction. 4 . The display according to claim 1 , wherein an organic resin layer is provided between the current supply line and the gate electrode of the vertical organic light emitting transistor. 5 .

5. The display according to claim 4, wherein the organic resin layer is formed between the gate electrode of the vertical organic light emitting transistor and the source electrode of the vertical organic light emitting transistor so as to overlap with a peripheral end portion of the gate electrode of the vertical organic light emitting transistor when viewed from the third direction. 6 . The display according to claim 1 , further comprising at least one auxiliary line which is wired in the second direction and connects at least two of the plurality of current supply lines. 7 . The display according to claim 6 , wherein the auxiliary line is formed in the same layer as the current supply line. The display according to claim 6 , further comprising a bank layer between the auxiliary line and the light emitting layer. 9 . The display according to claim 1 , wherein source electrodes of the vertical organic light emitting transistors are formed throughout at least two or more of the vertical organic light emitting transistors.

10. A display according to any one of claims 1 to 3, wherein an organic resin layer is arranged between the thin film transistor and the gate electrode of the vertical organic light emitting transistor; a conductive wire is outside the light emitting area and separated from the gate electrode of the vertical organic light emitting transistor, and the conductive wire is formed on the top of the organic resin layer together with the gate electrode during the same processing step, and becomes part of the current supply line as a multilayer structure including more than one conductive layer; the conductive layers in the multilayer structure can be separated by various insulating layers and connected by through holes in certain places, or can be directly in contact.

11. A display according to claim 6, wherein the auxiliary line is a multi-layer structure including a conductive layer formed simultaneously during the same processing steps as the existing layers, the existing layers including the data line, the gate electrode of the vertical organic light-emitting transistor and the current supply line; the conductive layers in the multi-layer structure can be separated by various insulating layers and connected at certain locations by through-holes, or can be directly in contact.

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