Multi-terminal multilayer capacitors

Abstract

The multi-terminal stacked capacitor (1) comprises: a plurality of first vias (21) and a plurality of second vias (22), which are arranged inside a first internal electrode (11) and a second internal electrode (12) and pass through in the stacking direction; a first slit (31) formed to extend between a first insulating portion (111) insulating the second vias (22) from the first internal electrode (11) and the first vias (21); and a second slit (32) formed to extend between a second insulating portion (121) insulating the first vias (21) from the second internal electrode (12) and the second vias (22). The first vias (21) are arranged to electrically connect a plurality of regions of the first internal electrode (11) divided by the first slit (31), and the second vias (22) are arranged to electrically connect a plurality of regions of the second internal electrode (12) divided by the second slit (32).

Description

Technical Field

[0001] The present invention relates to a multi-terminal stacked capacitor. Background Art

[0002] Various technologies have been proposed to achieve low ESL (equivalent series inductance) in capacitors. For example, Patent Document 1 discloses a stacked capacitor array comprising: a capacitor body; a first internal electrode and a second internal electrode, arranged alternately and oppositely with each layer of stacked dielectric layers sandwiched therebetween; a first external terminal and a second external terminal, formed on at least one of the upper and lower surfaces of the body; and a first conductive via and a second conductive via, formed in the stacking direction of the body and connected to the first and second external terminals, respectively. In particular, in order to reduce ESL in this stacked capacitor array, the first conductive via and the second conductive via are arranged (alternated) so that the magnetic fields induced by the current flowing through the internal electrodes connected thereto cancel each other out.

[0003] Furthermore, Patent Document 2 discloses a multilayer capacitor in which, to achieve low ESL, internal electrodes and external terminal electrodes are connected via through-hole conductors. In the internal electrodes, which are electrically insulated from the through-hole conductors, island-shaped cutouts are formed where the through-hole conductors penetrate. In this multilayer capacitor, cutout-connecting portions are formed to connect multiple island-shaped cutouts to each other and to connect the outer portions of each internal electrode to the island-shaped cutouts. In other words, the cutout-connecting portions are formed to divide (split) the internal electrodes into multiple, mutually insulated regions.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Laid-Open No. 2006-135333

[0007] Patent Document 2: Japanese Patent Application Laid-Open No. 2002-160467 Summary of the Invention

[0008] Problems to be solved by the invention

[0009] However, in the stacked capacitor array described in Patent Document 1, multiple vias are conductively connected to internal electrodes, and therefore there is a problem that, for example, a decrease in capacitance (effective value) may occur due to the skin effect in a high-frequency region.

[0010] Furthermore, in the multilayer capacitor described in Patent Document 2, since the internal electrodes are cut off and connected, they are divided (split) into multiple regions. This can degrade characteristics such as capacitance and ESR (equivalent series resistance), and reduce the mechanical strength of the device. These problems are particularly pronounced when vias are arranged at a narrow pitch.

[0011] The present invention has been made to solve the above-mentioned problems, and an object thereof is to provide a multi-terminal multilayer capacitor capable of maintaining low ESL in a high-frequency region, suppressing a decrease in capacitance (effective value), and ensuring the mechanical strength of the element.

[0012] Technical solutions to solve problems

[0013] The multi-terminal multilayer capacitor according to the present invention is characterized by comprising: first internal electrodes and second internal electrodes alternately stacked with dielectric layers interposed therebetween; a plurality of first vias arranged inside the first and second internal electrodes in a plan view, electrically connected to the first internal electrodes and insulated from the second internal electrodes, and penetrating in the stacking direction of the first and second internal electrodes; a plurality of second vias arranged inside the first and second internal electrodes in a plan view, electrically connected to the second internal electrodes and insulated from the first internal electrodes, and penetrating in the stacking direction of the first and second internal electrodes; and a first slit formed so as to extend between a first insulating portion and the first vias. The first insulating portion is formed around the second via hole passing through the first internal electrode to insulate the second via hole from the first internal electrode; the second slit is formed to extend between the second insulating portion and the second via hole, and the second insulating portion is formed around the first via hole passing through the second internal electrode to insulate the first via hole from the second internal electrode; a plurality of first external terminals are connected to each of the plurality of first via holes; and a plurality of second external terminals are connected to each of the plurality of second via holes, the first via hole being configured to electrically connect the plurality of regions when the first internal electrode is divided into the plurality of regions by the first slit, and the second via hole being configured to electrically connect the plurality of regions when the second internal electrode is divided into the plurality of regions by the second slit.

[0014] According to the multilayer capacitor of the present invention, the first via is configured to electrically connect the multiple regions when the first internal electrode is divided into multiple regions by the first slit, and the second via is configured to electrically connect the multiple regions when the second internal electrode is divided into multiple regions by the second slit. Therefore, it is possible to avoid the first internal electrode and the second internal electrode being divided (split) into multiple regions that are insulated from each other. Moreover, when a voltage is applied to the first external terminal and the second external terminal, a common voltage is applied to the first internal electrode and the second internal electrode respectively through the conductive connection with the first via and the second via. Therefore, compared with the case where the internal electrodes are electrically divided (split), the capacitance can be increased. In addition, because the multi-terminal multilayer capacitor is composed of two conductors as a whole, the generation of unnecessary resonant modes at high frequencies can be suppressed.

[0015] In addition, the first slit is formed to extend between the first insulating portion and the first via, and the first insulating portion is formed around the second via that passes through the first internal electrode to insulate the second via from the first internal electrode. The second slit is formed to extend between the second insulating portion and the second via, and the second insulating portion is formed around the first via that passes through the second internal electrode to insulate the first via from the second internal electrode. Therefore, when the first and second vias are observed in a cross-section including the center of the first and second vias and the first and second slits, the path of the conductor surface along the axial direction of the first and second vias becomes shorter. As a result, the impedance along the axial direction of the first and second vias can be reduced. As a result, the voltage drop observed in the axial direction of the first and second vias becomes smaller, which can mitigate the decrease in capacitance in the high-frequency region (i.e., the frequency characteristics of the capacitance become flatter). In addition, the effect of reducing ESR and ESL can be achieved.

[0016] Furthermore, the plurality of first vias are arranged inside the first and second internal electrodes when viewed from above, and the plurality of second vias are arranged inside the first and second internal electrodes when viewed from above. In other words, the first and second vias are not arranged at the outer edges of the first and second internal electrodes. Therefore, the outer edges (peripheries) of the first and second internal electrodes are not divided by the first and second slits. Consequently, the mechanical strength of the device can be ensured.

[0017] Effects of the Invention

[0018] As a result of the above, according to the present invention, it is possible to maintain low ESL in a high-frequency region, suppress a decrease in capacitance (effective value), and ensure the mechanical strength of the element. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a perspective view showing the structure of the multi-terminal multilayer capacitor according to the first embodiment.

[0020] Figure 2 It is along Figure 1 Cross-sectional view along line II-II.

[0021] Figure 3 It is along Figure 1 Cross-sectional view along line III-III.

[0022] Figure 4 This is a diagram showing an equivalent circuit of the multi-terminal multilayer capacitor according to the first embodiment.

[0023] Figure 5 It is an exploded perspective view showing the internal structure of the multi-terminal multilayer capacitor according to the first embodiment.

[0024] 6( a ) and 6 ( b ) are plan views showing the structures of first and second internal electrodes, respectively, constituting the multi-terminal multilayer capacitor according to the first embodiment.

[0025] 7( a ) and 7 ( b ) are graphs showing impedance characteristics and ESR characteristics of the multi-terminal multilayer capacitor according to the first embodiment and a comparative example, respectively.

[0026] 8( a ) and 8 ( b ) are graphs showing capacitance characteristics and ESL characteristics of the multi-terminal multilayer capacitor according to the first embodiment and a comparative example, respectively.

[0027] 9( a ) and 9 ( b ) are plan views showing the structures of first and second internal electrodes, respectively, constituting a multi-terminal multilayer capacitor according to a second embodiment.

[0028] 10( a ) and 10 ( b ) are graphs showing impedance characteristics and ESR characteristics of the multi-terminal multilayer capacitor according to the second embodiment and a comparative example, respectively.

[0029] 11( a ) and 11 ( b ) are graphs showing capacitance characteristics and ESL characteristics of the multi-terminal multilayer capacitor according to the second embodiment and a comparative example, respectively.

[0030] 12( a ) and 12 ( b ) are plan views showing the structures of first and second internal electrodes, respectively, constituting a multi-terminal multilayer capacitor according to a third embodiment.

[0031] 13( a ) and 13 ( b ) are plan views showing the structures of first and second internal electrodes, respectively, constituting a multi-terminal multilayer capacitor according to a fourth embodiment.

[0032] 14( a ) and 14 ( b ) are plan views showing the structures of first and second internal electrodes, respectively, constituting a multi-terminal multilayer capacitor according to a fifth embodiment.

[0033] 15( a ) and 15 ( b ) are plan views showing the structures of first and second internal electrodes, respectively, constituting a multi-terminal multilayer capacitor according to a sixth embodiment.

[0034] Figure 16 It is an exploded perspective view showing the internal structure of a multi-terminal multilayer capacitor according to a sixth embodiment.

[0035] 17( a ) and 17 ( b ) are graphs showing impedance characteristics and ESR characteristics of the multi-terminal multilayer capacitor according to the sixth embodiment and a comparative example, respectively.

[0036] 18( a ) and 18 ( b ) are graphs showing capacitance characteristics and ESL characteristics of the multi-terminal multilayer capacitor according to the sixth embodiment and a comparative example, respectively.

[0037] 19( a ) and 19 ( b ) are plan views showing the structures of first and second internal electrodes, respectively, constituting the multi-terminal multilayer capacitor according to the seventh embodiment.

[0038] 20( a ) and 20 ( b ) are plan views showing the structures of first and second internal electrodes, respectively, constituting the multi-terminal multilayer capacitor according to the eighth embodiment.

[0039] 21( a ) and 21 ( b ) are plan views showing the structures of first and second internal electrodes, respectively, constituting the multi-terminal multilayer capacitor according to the ninth embodiment.

[0040] 22( a ) and 22 ( b ) are plan views showing the structures of first and second internal electrodes, respectively, constituting the multi-terminal multilayer capacitor according to the tenth embodiment.

[0041] 23( a ) and 23 ( b ) are plan views showing the structures of first and second internal electrodes, respectively, constituting the multi-terminal multilayer capacitor according to the eleventh embodiment.

[0042] 24( a ) and 24 ( b ) are plan views showing the structures of first and second internal electrodes, respectively, constituting the multi-terminal multilayer capacitor according to the twelfth embodiment. DETAILED DESCRIPTION

[0043] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In addition, in the drawings, the same reference numerals are used for the same or equivalent parts. In addition, in each figure, the same reference numerals are used for the same elements, and repeated descriptions are omitted.

[0044] (First embodiment)

[0045] First, use Figures 1 to 5 6( a ) and 6 ( b ) illustrate the structure of the multi-terminal multilayer capacitor 1 according to the first embodiment. Figure 1 It is a perspective view showing the structure of the multi-terminal multilayer capacitor 1 . Figure 2 It is along Figure 1 Cross-sectional view along line II-II. Figure 3 It is along Figure 1 Cross-sectional view along line III-III. Figure 4 1 is a diagram showing an equivalent circuit of the multi-terminal multilayer capacitor 1. Here, tiny L (inductance) and R (resistance) are parasitic at the first external terminal 41 and the second external terminal 42. Figure 4 In the equivalent circuit shown, these parasitic L and R are lumped into ESL and ESR, and their direct representation is omitted. Figure 5 6( a ) and 6 ( b ) are plan views showing the structures of the first internal electrode 11 and the second internal electrode 12 constituting the multi-terminal multilayer capacitor 1 , respectively.

[0046] The multi-terminal multilayer capacitor 1 includes, for example, a multilayer body 10 formed in a rectangular parallelepiped shape and nine external terminals 41 and 42 (more specifically, four first external terminals 41 and five second external terminals 42 ) formed on the top surface (upper surface) of the multilayer body 10 .

[0047] The laminate 10 is constructed by alternately stacking first and second internal electrodes 11 and 12 opposite each other with a plurality of rectangular dielectric layers (insulator layers) 13 interposed therebetween. The dielectric layers 13 are formed, for example, from a dielectric ceramic primarily composed of BaTiO3, CaTiO3, SrTiO3, CaZrO3, or the like. Furthermore, minor components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds may be added to these primary components.

[0048] The first internal electrode 11 and the second internal electrode 12 are formed in, for example, a rectangular thin film shape and are each formed of, for example, Ni, Cu, Ag, Pd, an Ag-Pd alloy, Au, or the like.

[0049] A plurality of (four in the present embodiment) first via holes 21 are formed in the stacked body 10. The plurality of first via holes 21 are arranged on the inner side of the first internal electrode 11 and the second internal electrode 12 (i.e., not in contact with the outer edge) when viewed from above, are electrically connected (conductive) to the first internal electrode 11 and insulated from the second internal electrode 12, and penetrate the stacked body 10 in the stacking direction (thickness direction) of the stacked body 10.

[0050] Similarly, a plurality of (five in the present embodiment) second vias 22 are formed in the stack 10. These plurality of second vias 22 are arranged on the inner side of the first internal electrode 11 and the second internal electrode 12 (i.e., not in contact with the outer edge) when viewed from above, are electrically connected (conductive) to the second internal electrode 12 and insulated from the first internal electrode 11, and penetrate the stack 10 in the stacking direction (thickness direction) of the stack 10.

[0051] A plurality of (four) first external terminals 41 are connected to the ends of each of the plurality of (four) first vias 21. Similarly, a plurality of (five) second external terminals 42 are connected to the ends of each of the plurality of (five) second vias 22. The first external terminals 41 and the second external terminals 42 are formed of a conductive material primarily composed of silver, for example.

[0052] In the present embodiment, the first external terminals 41 (first vias 21 ) and the second external terminals 42 (second vias 22 ) are arranged alternately in a matrix in a plan view.

[0053] An annular first insulating portion (opening) 111 is formed on the first inner electrode 11. This first insulating portion (opening) 111 is formed around the second via 22 that penetrates the first inner electrode 11, and insulates the second via 22 from the first inner electrode 11. Furthermore, a linear first slit (gap) 31 is formed so as to extend between the first insulating portion 111 and the first via 21.

[0054] Similarly, the second inner electrode 12 is provided with an annular second insulating portion (opening) 121. This second insulating portion (opening) 121 is formed around the first via 21 penetrating the second inner electrode 12, insulating the first via 21 from the second inner electrode 12. Furthermore, a linear second slit (gap) 32 is formed extending between the second insulating portion 121 and the second via 22.

[0055] In this embodiment, the first slits 31 and the second slits 32 are formed in a 3-row 3-column grid pattern (a checkerboard grid pattern). The shapes of the first slits 31 and the second slits 32 are not limited to 3 rows and 3 columns and can be arbitrarily set according to necessary conditions, etc. (the same applies hereinafter). Furthermore, in this embodiment, the first slits 31 and the second slits 32 are formed so as to overlap (align) when viewed from above.

[0056] Here, the first vias 21 are arranged so as to electrically connect (conduct) the first inner electrode 11 into a plurality of regions (five regions in the present embodiment) when the first slit 31 divides the first inner electrode 11 into these regions. Consequently, the first inner electrode 11 becomes a single inner electrode with the same potential. Similarly, the second vias 22 are arranged so as to electrically connect (conduct) the second inner electrode 12 into a plurality of regions (five regions in the present embodiment) when the second inner electrode 12 is divided into these regions by the second slit 32. Consequently, the second inner electrode 12 becomes a single inner electrode with the same potential.

[0057] By configuring as described above, according to this embodiment, the first via 21 is configured to electrically connect (conduct) the multiple (five) regions of the first internal electrode 11 when the first slit 31 divides the multiple regions, and the second via 22 is configured to electrically connect (conduct) the multiple (five) regions of the second internal electrode 12 when the second slit 32 divides the multiple regions. This prevents the first and second internal electrodes 11, 12 from being divided (split) into multiple, mutually insulated regions. Furthermore, when a voltage is applied to the first and second external terminals 41, 42, a common voltage is applied to the first and second internal electrodes 11, 12 through their respective conductive connections with the first and second vias 21, 22. Consequently, capacitance can be increased compared to a case where the internal electrodes are electrically divided (split). Furthermore, because the multi-terminal multilayer capacitor 1 is constructed entirely of two conductors, the generation of unwanted resonant modes at high frequencies can be suppressed.

[0058] Furthermore, according to this embodiment, the first slit 31 is formed to extend between the first insulating portion 111, which insulates the second via 22 from the first internal electrode 11, and the first via 21. The second slit 32 is formed to extend between the second insulating portion 121, which insulates the first via 21 from the second internal electrode 12, and the second via 22. Therefore, when observing the first and second vias 21, 22 in a cross-section including the centers of the first and second vias 21, 22 and the first and second slits 31, 32, the path of the conductor surface along the axial direction of the first and second vias 21, 22 is shortened. This reduces the impedance along the axial direction of the first and second vias 21, 22. Consequently, the voltage drop observed in the axial direction of the first and second vias 21, 22 is reduced, mitigating the decrease in capacitance in the high-frequency region (i.e., flattening the capacitance frequency characteristics). Furthermore, this reduces ESR and ESL.

[0059] Furthermore, according to this embodiment, the plurality of first vias 21 and the plurality of second vias 22 are arranged inwardly of the first and second internal electrodes 11, 12 in a plan view (i.e., not in contact with their outer edges). In other words, the first and second vias 21, 22 are not arranged at the outer edges of the first and second internal electrodes 11, 12. Therefore, the outer edges (peripheries) of the first and second internal electrodes 11, 12 are not interrupted by the first and second slits 31, 32. Consequently, the mechanical strength and flatness of the device can be maintained.

[0060] As a result of the above, according to the present embodiment, it is possible to maintain low ESL in a high-frequency region, suppress a decrease in capacitance (effective value), and ensure the mechanical strength of the element.

[0061] Here, the impedance characteristics and ESR characteristics of the multi-terminal stacked capacitor 1 involved in this embodiment and the comparative example are shown in Figure 7(a) and Figure 7(b), respectively. In addition, as a comparative example, a multi-terminal stacked capacitor without the first slit 31 and the second slit 32 was used (the same below). Figure 7(a) shows the impedance characteristics (simulation results) of the multi-terminal stacked capacitor 1 and the comparative example, and Figure 7(b) shows the ESR characteristics (simulation results) of the multi-terminal stacked capacitor 1 and the comparative example. The horizontal axis of the graph of Figure 7(a) is frequency (Hz), and the vertical axis is impedance (Ω). In addition, the horizontal axis of the graph of Figure 7(b) is frequency (Hz), and the vertical axis is ESR (Ω).

[0062] As shown in FIG7(a), the multi-terminal multilayer capacitor 1 was confirmed to have a lower impedance (particularly, the impedance around 100 MHz) compared to the comparative example. Furthermore, as shown in FIG7(b), the multi-terminal multilayer capacitor 1 was confirmed to have a lower ESR compared to the comparative example.

[0063] Next, the capacitance characteristics and ESL characteristics of the multi-terminal stacked capacitor 1 and the comparative example are shown in Figure 8(a) and Figure 8(b), respectively. Figure 8(a) shows the capacitance characteristics (simulation results) of the multi-terminal stacked capacitor 1 and the comparative example, and Figure 8(b) shows the ESL characteristics (simulation results) of the multi-terminal stacked capacitor 1 and the comparative example. The horizontal axis of the graph in Figure 8(a) is frequency (Hz), and the vertical axis is capacitance (F). In addition, the horizontal axis of the graph in Figure 8(b) is frequency (Hz), and the vertical axis is ESL (H). As shown in Figure 8(a), it has been confirmed that although a decrease in capacitance is observed in the high-frequency region (particularly, the region above 10 MHz) in the comparative example, according to the multi-terminal stacked capacitor 1, the capacitance does not decrease even in the high-frequency region (particularly, the region above 10 MHz). In addition, as shown in Figure 8(b), it has been confirmed that according to the multi-terminal stacked capacitor 1, the ESL can be maintained low.

[0064] (Second embodiment)

[0065] In the multi-terminal multilayer capacitor 1 according to the first embodiment described above, the first slits 31 and the second slits 32 are formed in a lattice pattern. However, as shown in Figures 9(a) and 9(b), the first slits 31B and the second slits 32B may be formed as three straight lines extending parallel to the contours of the first internal electrode 11B and the second internal electrode 12B. Figures 9(a) and 9(b) are plan views respectively showing the structures of the first internal electrode 11B and the second internal electrode 12B constituting the multi-terminal multilayer capacitor according to the second embodiment.

[0066] In this embodiment, the first slit 31B and the second slit 32B are also formed to overlap (align) when viewed from above. In this case, the first internal electrode 11B and the second internal electrode 12B do not have any electrically disconnected (divided) regions. The remaining structure is identical or equivalent to that of the multi-terminal multilayer capacitor 1 according to the first embodiment described above, and therefore, a detailed description thereof will be omitted here.

[0067] Here, the impedance characteristics and ESR characteristics of the multi-terminal multilayer capacitor involved in this embodiment and the comparative example are shown in Figures 10(a) and 10(b), respectively. Figure 10(a) shows the impedance characteristics (simulation results) of the multi-terminal multilayer capacitor and the comparative example, and Figure 10(b) shows the ESR characteristics (simulation results) of the multi-terminal multilayer capacitor and the comparative example. The horizontal axis of the graph in Figure 10(a) is frequency (Hz), and the vertical axis is impedance (Ω). In addition, the horizontal axis of the graph in Figure 10(b) is frequency (Hz), and the vertical axis is ESR (Ω).

[0068] As shown in Figure 10(a), it was confirmed that the impedance (particularly, the impedance around 100 MHz) of the multi-terminal multilayer capacitor was reduced compared to the comparative example. Furthermore, as shown in Figure 10(b), it was confirmed that the ESR of the multi-terminal multilayer capacitor was reduced compared to the comparative example. In other words, it was confirmed that the multi-terminal multilayer capacitor according to the second embodiment can also achieve the same effects as the multi-terminal multilayer capacitor 1 according to the first embodiment described above.

[0069] Next, the capacitance characteristics and ESL characteristics of the multi-terminal stacked capacitor and the comparative example are shown in Figures 11(a) and 11(b), respectively. Figure 11(a) shows the capacitance characteristics (simulation results) of the multi-terminal stacked capacitor and the comparative example, and Figure 11(b) shows the ESL characteristics (simulation results) of the multi-terminal stacked capacitor and the comparative example. The horizontal axis of the graph in Figure 11(a) is frequency (Hz), and the vertical axis is capacitance (F). In addition, the horizontal axis of the graph in Figure 11(b) is frequency (Hz), and the vertical axis is ESL (H).

[0070] As shown in Figure 11(a), it was confirmed that while a decrease in capacitance was observed in the high-frequency region (particularly, the region above 10 MHz) in the comparative example, the capacitance of the multi-terminal multilayer capacitor did not decrease even in the high-frequency region (particularly, the region above 10 MHz). Furthermore, as shown in Figure 11(b), it was confirmed that the multi-terminal multilayer capacitor was able to maintain a low ESL. In other words, it was confirmed that the multi-terminal multilayer capacitor according to the second embodiment could achieve the same effects as the multi-terminal multilayer capacitor 1 according to the first embodiment described above.

[0071] (Third embodiment)

[0072] In the multi-terminal multilayer capacitor according to the second embodiment described above, the first slits 31B and the second slits 32B are formed as three straight lines, overlapping each other. However, as shown in Figures 12(a) and 12(b), a configuration may be employed in which the direction in which the second slits 32C extend is rotated 90° relative to the direction in which the first slits 31B extend. Figures 12(a) and 12(b) are plan views, respectively, showing the structures of the first internal electrode 11B and the second internal electrode 12C that constitute the multi-terminal multilayer capacitor according to the third embodiment.

[0073] That is, when viewed from above, the first slit 31B and the second slit 32C are configured to be orthogonal. Therefore, in this embodiment, when viewed from above, the first slit 31B and the second slit 32C do not overlap (i.e., do not coincide with) each other. Furthermore, in this case, the first and second internal electrodes 11B and 12C do not have electrically disconnected (divided) regions. The remaining structure is identical or equivalent to that of the multi-terminal multilayer capacitor according to the second embodiment described above, and therefore, a detailed description thereof will be omitted.

[0074] According to this embodiment, when viewed from above, the first slit 31B and the second slit 32C do not overlap with each other (i.e., are inconsistent), so the magnetic field entering and exiting the first slit 31B and the second slit 32C becomes non-linearly distributed (i.e., deviates from the optimal condition), but can achieve an effect roughly equivalent to that of the multi-terminal stacked capacitor involved in the above-mentioned second embodiment.

[0075] (Fourth embodiment)

[0076] In the multi-terminal multilayer capacitor 1 according to the first embodiment described above, the widths of the first slit 31 and the second slit 32 are fixed. However, as shown in FIG13(a), the first slit 31D may be formed into a tapered shape that narrows toward the first via 21. Similarly, the second slit 32D may be formed into a tapered shape that narrows toward the second via 22. FIG13(a) and FIG13(b) are top views respectively showing the structures of the first internal electrode 11D and the second internal electrode 12D that constitute the multi-terminal multilayer capacitor according to the fourth embodiment. The remaining structure is identical or equivalent to that of the multi-terminal multilayer capacitor 1 according to the first embodiment described above, and therefore, a detailed description thereof will be omitted here.

[0077] According to this embodiment, by forming the first and second slits 31D and 32D into a tapered shape, it is possible to reliably achieve electrical connection between the first and second internal electrodes 11D and 12D and the first and second vias 21 and 22, thereby reducing the effects of positional shifts and the like. Furthermore, when the element is fired during the manufacturing process, the element shrinks similarly. However, by forming the first and second slits 31D and 32D into a tapered shape, it is possible to maintain the shapes of the first and second slits 31D and 32D well even after firing.

[0078] (Fifth embodiment)

[0079] The multi-terminal multilayer capacitor 1 according to the first embodiment may be configured such that land patterns are provided at the connection portions between the first and second vias 21 and 22 and the first and second slits 31 and 32 .

[0080] More specifically, as shown in Figure 14(a), the connection portion between the first inner electrode 11E and the first via 21 is formed in an annular shape. That is, an annular first land pattern 112E is formed around the first via 21 that penetrates the first inner electrode 11E. Similarly, the connection portion between the second inner electrode 12E and the second via 22 is formed in an annular shape. That is, an annular second land pattern 122E is formed around the second via 22 that penetrates the second inner electrode 12E. Furthermore, Figures 14(a) and 14(b) are top views, respectively, showing the structures of the first inner electrode 11E and the second inner electrode 12E that constitute the multi-terminal multilayer capacitor according to the fifth embodiment.

[0081] Furthermore, the first slit 31E is formed to connect the first insulating portion 111 and the first land pattern 112E (first via 21). Similarly, the second slit 32E is formed to connect the second insulating portion 121 and the second land pattern 122E (second via 22). Furthermore, the diameters of the first and second land patterns 112E and 122E are larger than the widths of the first and second slits 31E and 32E, and larger than the diameters of the first and second vias 21 and 22. The remaining structure is identical or equivalent to that of the multi-terminal multilayer capacitor 1 according to the first embodiment described above, and therefore, a detailed description thereof will be omitted.

[0082] According to this embodiment, by providing the first land pattern 112E and the second land pattern 122E, the first and second inner electrodes 11E, 12E and the first and second vias 21, 22 can be reliably connected and the influence of positional deviation can be reduced.

[0083] (Sixth embodiment)

[0084] In the multi-terminal multilayer capacitor according to the second embodiment described above, the first external terminals 41 (first vias 21) and the second external terminals 42 (second vias 22) are alternately arranged. However, as shown in FIG. 15(a), FIG. 15(b), and FIG. Figure 16 As shown, the structure is as follows, that is, when viewed from above, a plurality of (three in this embodiment) first external terminals 41 (first vias 21) are arranged in a straight line (i.e., arranged with the same polarity), and a plurality of (three in this embodiment) second external terminals 42 (second vias 22) are arranged in a straight line (i.e., arranged with the same polarity). In addition, Figures 15(a) and 15(b) are top views respectively showing the structures of the first internal electrode 11F and the second internal electrode 12F constituting the multi-terminal multilayer capacitor 1F involved in the sixth embodiment. In addition, Figure 16 It is an exploded perspective view showing the internal structure of the multi-terminal multilayer capacitor 1F.

[0085] In this case, a plurality of (three) first external terminals 41 (first vias 21) arranged in a straight line and a plurality of (three) second external terminals 42 (second vias 22) arranged in a straight line are alternately arranged (nine terminals). The remaining structure is identical or equivalent to that of the multi-terminal multilayer capacitor 1 according to the first embodiment described above, and therefore, a detailed description thereof will be omitted here.

[0086] By arranging the first external terminal 41 (first via 21) and the second external terminal 42 (second via 22) as described above (i.e., by arranging the first external terminal 41 and the second external terminal 42 with the same polarity), and by designing the land pattern of the mounting substrate to match the arrangement of the first external terminal 41 and the second external terminal 42, installation on linear lines such as microstrip lines and coplanar lines becomes easier (possible). In particular, when the first external terminal 41 and the second external terminal 42 are arranged in three rows, a ground-signal-ground (GSG) arrangement is achieved, resulting in a structure in which feedthrough capacitors are connected and monolithic. This facilitates handling during installation.

[0087] Here, the impedance characteristics and ESR characteristics of the multi-terminal multilayer capacitor 1F according to the present embodiment and the comparative example are shown in Figures 17(a) and 17(b), respectively. Figure 17(a) shows the impedance characteristics (simulation results) of the multi-terminal multilayer capacitor 1F and the comparative example, and Figure 17(b) shows the ESR characteristics (simulation results) of the multi-terminal multilayer capacitor 1F and the comparative example. The horizontal axis of the graph in Figure 17(a) is frequency (Hz), and the vertical axis is impedance (Ω). Furthermore, the horizontal axis of the graph in Figure 17(b) is frequency (Hz), and the vertical axis is ESR (Ω).

[0088] As shown in Figure 17(a), it was confirmed that the impedance (particularly, the impedance below 100 MHz) of the multi-terminal multilayer capacitor 1F was reduced compared to the comparative example. Furthermore, as shown in Figure 17(b), it was confirmed that the ESR of the multi-terminal multilayer capacitor 1F was reduced compared to the comparative example. In other words, it was confirmed that the multi-terminal multilayer capacitor 1F according to the sixth embodiment can also achieve the same effects as the multi-terminal multilayer capacitor according to the second embodiment described above.

[0089] Next, the capacitance characteristics and ESL characteristics of the multi-terminal multilayer capacitor 1F and the comparative example are shown in Figures 18(a) and 18(b), respectively. Figure 18(a) shows the capacitance characteristics (simulation results) of the multi-terminal multilayer capacitor 1F and the comparative example, and Figure 18(b) shows the ESL characteristics (simulation results) of the multi-terminal multilayer capacitor 1F and the comparative example. The horizontal axis of the graph in Figure 18(a) is frequency (Hz), and the vertical axis is capacitance (F). Furthermore, the horizontal axis of the graph in Figure 18(b) is frequency (Hz), and the vertical axis is ESL (H).

[0090] As shown in Figure 18(a), it was confirmed that while the capacitance decreased in the high-frequency range (particularly, the range above 10 MHz) in the comparative example, the capacitance of the multi-terminal multilayer capacitor 1F did not decrease even in the high-frequency range (particularly, the range above 10 MHz). Furthermore, as shown in Figure 18(b), it was confirmed that the ESL of the multi-terminal multilayer capacitor 1F, while slightly higher than that of the comparative example, was maintained at a relatively low level. In other words, it was confirmed that the multi-terminal multilayer capacitor 1F according to the sixth embodiment can achieve substantially the same effects as the multi-terminal multilayer capacitor according to the second embodiment described above.

[0091] (Seventh embodiment)

[0092] The structure may also be as follows, that is, for the multi-terminal stacked capacitor 1F involved in the above-mentioned sixth embodiment, as shown in Figures 19(a) and 19(b), when viewed from above, a plurality of (two in the present embodiment) first external terminals 41 (first vias 21) are arranged in a straight line (i.e., arranged with the same polarity), a plurality of (three in the present embodiment) second external terminals 42 (second vias 22) are arranged in a straight line (i.e., arranged with the same polarity), and the plurality of (two) first external terminals 41 (first vias 21) arranged in a straight line and the plurality of (3) second external terminals 42 (second vias 22) arranged in a straight line are alternately and zigzag-shaped (i.e., offset by half a pitch) (7 terminals).

[0093] Furthermore, in this embodiment, the first slits 31G are formed in a direction oblique to the contour of the first internal electrode 11G, and the second slits 32G are formed in a direction oblique to the contour of the second internal electrode 12G. Furthermore, Figures 19(a) and 19(b) are top views respectively showing the structures of the first internal electrode 11G and the second internal electrode 12G constituting the multi-terminal multilayer capacitor according to the seventh embodiment. The remaining structure is identical or equivalent to that of the multi-terminal multilayer capacitor 1 (according to the first embodiment) described above, and therefore, a detailed description thereof will be omitted here.

[0094] By arranging the first external terminal 41 (first via 21) and the second external terminal 42 (second via 22) as described above (i.e., by arranging the first external terminal 41 and the second external terminal 42 with the same polarity), and by designing the land pattern of the mounting substrate to match the arrangement of the first external terminal 41 and the second external terminal 42, mounting on a linear line such as a microstrip line or a coplanar line becomes easier (possible). In particular, when the first external terminal 41 and the second external terminal 42 are arranged in three rows, a ground-signal-ground (GSG) arrangement is achieved, resulting in a structure in which feedthrough capacitors are connected and monolithic. This facilitates mounting.

[0095] The multi-terminal multilayer capacitor according to this embodiment can also achieve the same effects as those of the multi-terminal multilayer capacitor 1F according to the sixth embodiment described above.

[0096] (Eighth embodiment)

[0097] In the multi-terminal multilayer capacitor according to the seventh embodiment described above, the shape of the second slit 32H of the second inner electrode 12H may be made bilaterally symmetrical (left-right inverted) with respect to the first slit 31G, as shown in Figures 20(a) and 20(b). Figures 20(a) and 20(b) are plan views respectively showing the structures of the first inner electrode 11G and the second inner electrode 12H constituting the multi-terminal multilayer capacitor according to the eighth embodiment.

[0098] In this embodiment, the first slit 31G and the second slit 32H do not overlap (ie, do not coincide) with each other in a plan view. The remaining structure is identical or the same as that of the multi-terminal multilayer capacitor according to the seventh embodiment described above, and therefore detailed description is omitted here.

[0099] By arranging the first external terminal 41 (first via 21) and the second external terminal 42 (second via 22) as described above (i.e., by arranging the first external terminal 41 and the second external terminal 42 with the same polarity), and by designing the land pattern of the mounting substrate to match the arrangement of the first external terminal 41 and the second external terminal 42, installation on linear lines such as microstrip lines and coplanar lines becomes easier (possible). In particular, when the first external terminal 41 and the second external terminal 42 are arranged in three rows, a ground-signal-ground (GSG) arrangement is achieved, resulting in a structure in which feedthrough capacitors are connected and monolithic. This facilitates handling during installation.

[0100] According to this embodiment, the surface path between the first and second vias 21, 22 and the first and second internal electrodes 11G, 12H is lengthened, and the current path through the first and second slits 31G, 32H is no longer the shortest. This increases the impedance and ESR of the current path, and increases the Joule losses of the multi-terminal multilayer capacitor as a whole. However, when using capacitors for decoupling power circuits, there are design methods that actively increase ESR to suppress noise, so this embodiment is effective in such situations.

[0101] (Ninth embodiment)

[0102] In the multi-terminal stacked capacitor involved in the above-mentioned seventh embodiment, the following structure is set, that is, a plurality of (two) first external terminals 41 (first vias 21) arranged in a straight line and a plurality of (3) second external terminals 42 (second vias 22) arranged in a straight line are arranged alternately and in a zigzag manner (i.e., staggered by half a pitch), but it can also be set as shown in Figures 21(a) and 21(b), that is, a plurality of (3) first external terminals 41 (first vias 21) arranged in a straight line and a plurality of (two) second external terminals 42 (second vias 22) arranged in a straight line are arranged alternately and in a zigzag manner (i.e., staggered by half a pitch) (8 terminals).

[0103] Furthermore, in this embodiment, a first slit 31J is formed in a direction oblique to the contour of the first internal electrode 11J (in a Y-shape), and a second slit 32J is formed in a direction oblique to the contour of the second internal electrode 12J (in a Y-shape). Figures 21(a) and 21(b) are top views, respectively, showing the structures of the first internal electrode 11J and the second internal electrode 12J that constitute the multi-terminal multilayer capacitor according to the ninth embodiment. The remaining structure is identical or equivalent to that of the multi-terminal multilayer capacitor according to the seventh embodiment described above, and therefore, a detailed description thereof will be omitted here.

[0104] By arranging the first external terminal 41 (first via 21) and the second external terminal 42 (second via 22) as described above (i.e., by arranging the first external terminal 41 and the second external terminal 42 with the same polarity), and by designing the land pattern of the mounting substrate to match the arrangement of the first external terminal 41 and the second external terminal 42, installation on linear lines such as microstrip lines and coplanar lines becomes easier (possible). In particular, when the first external terminal 41 and the second external terminal 42 are arranged in three rows, a ground-signal-ground (GSG) arrangement is achieved, resulting in a structure in which feedthrough capacitors are connected and monolithic. This facilitates handling during installation.

[0105] The multi-terminal multilayer capacitor according to this embodiment can also achieve the same effects as those of the multi-terminal multilayer capacitor according to the seventh embodiment described above.

[0106] (10th embodiment)

[0107] In the multi-terminal multilayer capacitor 1F according to the sixth embodiment described above, a structure (3×3 (3 rows and 3 columns) = 9 terminals) is employed, in which a plurality (3) of first external terminals 41 (first vias 21) arranged in a straight line and a plurality (3) of second external terminals 42 (second vias 22) arranged in a straight line are arranged alternately. However, as shown in FIG22(a) and FIG22(b), a structure (5×5 (5 rows and 5 columns) = 25 terminals) may be employed, in which a plurality (5) of first external terminals 41 (first vias 21) arranged in a straight line and a plurality (5) of second external terminals 42 (second vias 22) arranged in a straight line are arranged alternately. Furthermore, FIG22(a) and FIG22(b) are top views respectively showing the structures of the first internal electrode 11K and the second internal electrode 12K constituting the multi-terminal multilayer capacitor according to the tenth embodiment. The other structures are identical or the same as those of the multi-terminal multilayer capacitor 1F according to the sixth embodiment described above, and therefore detailed descriptions thereof are omitted here.

[0108] According to the multi-terminal multilayer capacitor of this embodiment, the areas of the first inner electrode 11K and the second inner electrode 12K are increased, thereby increasing the capacitance of the multi-terminal multilayer capacitor as a whole.

[0109] (11th embodiment)

[0110] In the multi-terminal multilayer capacitor 1F according to the sixth embodiment described above, the widths of the first slit 31F and the second slit 32F are fixed. However, as shown in FIG23(a), the first slit 31L may be formed into a tapered shape that narrows toward the first via 21. Similarly, the second slit 32L may be formed into a tapered shape that narrows toward the second via 22. FIG23(a) and FIG23(b) are top views respectively showing the structures of the first internal electrode 11L and the second internal electrode 12L that constitute the multi-terminal multilayer capacitor according to the eleventh embodiment. The remaining structure is identical or equivalent to that of the multi-terminal multilayer capacitor 1F according to the sixth embodiment described above, and therefore, a detailed description thereof will be omitted here.

[0111] According to this embodiment, by forming the first and second slits 31L and 32L into a tapered shape, it is possible to reliably achieve electrical connection between the first and second internal electrodes 11L and 12L and the first and second vias 21 and 22, thereby reducing the influence of positional shifts and the like. Furthermore, when the element is fired during the manufacturing process, the element undergoes similar shrinkage. However, by forming the first and second slits 31L and 32L into a tapered shape, it is possible to maintain the shapes of the first and second slits 31L and 32L even after firing.

[0112] (12th embodiment)

[0113] The multi-terminal multilayer capacitor 1F according to the sixth embodiment may be configured such that land patterns are provided at the connection portions between the first and second vias 21 and 22 and the first and second slits 31F and 32F.

[0114] More specifically, as shown in FIG24(a), the connection portion between the first inner electrode 11M and the first via 21 is formed in an annular shape. That is, an annular first land pattern 112M is formed around the first via 21 that penetrates the first inner electrode 11M. Similarly, the connection portion between the second inner electrode 12M and the second via 22 is formed in an annular shape. That is, an annular second land pattern 122M is formed around the second via 22 that penetrates the second inner electrode 12M. Furthermore, FIG24(a) and FIG24(b) are top views, respectively, showing the structures of the first inner electrode 11M and the second inner electrode 12M that constitute the multi-terminal multilayer capacitor according to the twelfth embodiment.

[0115] Furthermore, the first slit 31M is formed to connect the first insulating portion 111 and the first land pattern 112M (first via 21). Similarly, the second slit 32M is formed to connect the second insulating portion 121 and the second land pattern 122M (second via 22). The remaining structure is identical or equivalent to that of the multi-terminal multilayer capacitor 1F according to the sixth embodiment described above, and therefore, a detailed description thereof will be omitted here.

[0116] According to the present embodiment, by providing the first land pattern 112M and the second land pattern 122M, the first and second inner electrodes 11M, 12M and the first and second vias 21, 22 can be reliably connected and the influence of positional deviation can be reduced.

[0117] While the embodiments of the present invention have been described above, the present invention is not limited to the aforementioned embodiments and various modifications are possible. For example, the number and arrangement (arrangement) of the first and second vias 21 and 22 and the first and second external terminals 41 and 42, as well as the shape and arrangement of the first and second slits 31 and 32, are merely examples and can be arbitrarily set according to necessary conditions.

[0118] Description of Reference Numerals

[0119] 1. 1F: Multi-terminal stacked capacitor;

[0120] 10: laminate;

[0121] 13: dielectric layer;

[0122] 11, 11B, 11D, 11E, 11F, 11G, 11J, 11K, 11L, 11M: first inner electrode;

[0123] 12, 12B, 12C, 12D, 12E, 12F, 12G, 12H, 12J, 12K, 12L, 12M: second inner electrode;

[0124] 111: First insulating part;

[0125] 121: Second insulating portion;

[0126] 112E, 112M: 1st connection plate pattern;

[0127] 122E, 122M: 2nd connection plate pattern;

[0128] 21: First via;

[0129] 22: Second via;

[0130] 31, 31B, 31D, 31E, 31G, 31J, 31K, 31L, 31M: 1st slit;

[0131] 32, 32B, 32C, 32D, 32E, 32G, 32H, 32J, 32K, 32L, 32M: 2nd slit;

[0132] 41: 1st external terminal;

[0133] 42: 2nd external terminal.

Claims

1. A multi-terminal stacked capacitor, characterized in that: have: The first internal electrodes and the second internal electrodes are alternately stacked with dielectric layers interposed therebetween; a plurality of first via holes, arranged inside the first and second internal electrodes in a plan view, electrically connected to the first internal electrodes and insulated from the second internal electrodes, and penetrating the first and second internal electrodes in a stacking direction; a plurality of second via holes, arranged inside the first and second internal electrodes in a plan view, electrically connected to the second internal electrodes and insulated from the first internal electrodes, and penetrating the first and second internal electrodes in a stacking direction; a first slit formed to extend between a first insulating portion and the first via hole, wherein the first insulating portion is formed around the second via hole penetrating the first internal electrode to insulate the second via hole from the first internal electrode; a second slit formed to extend between a second insulating portion and the second via hole, wherein the second insulating portion is formed around the first via hole penetrating the second internal electrode to insulate the first via hole from the second internal electrode; a plurality of first external terminals connected to each of the plurality of first vias; as well as a plurality of second external terminals connected to the plurality of second vias, The first via hole is provided to electrically connect the plurality of regions when the first internal electrode is divided into the plurality of regions by the first slit. The second via hole is provided to electrically connect the plurality of regions when the second inner electrode is divided into the plurality of regions by the second slit. The first slit is formed in a tapered shape that becomes narrower toward the first via hole. The second slit is formed in a tapered shape that becomes narrower toward the second via hole.

2. The multi-terminal multilayer capacitor according to claim 1, wherein In a plan view, the first external terminals and the second external terminals are alternately arranged in a matrix.

3. The multi-terminal multilayer capacitor according to claim 1, wherein In a plan view, the plurality of first external terminals are arranged in a straight line. In a plan view, the plurality of second external terminals are arranged in a straight line. The plurality of first external terminals arranged in a straight line and the plurality of second external terminals arranged in a straight line are alternately arranged.

4. The multi-terminal multilayer capacitor according to any one of claims 1 to 3, wherein: The first slits and the second slits are formed in a lattice shape.

5. The multi-terminal multilayer capacitor according to claim 1, wherein In a plan view, the plurality of first external terminals are arranged in a straight line. In a plan view, the plurality of second external terminals are arranged in a straight line. The plurality of first external terminals arranged in a straight line and the plurality of second external terminals arranged in a straight line are alternately and staggered at half a pitch. The first slit is formed in a direction inclined with respect to the contour of the first internal electrode. The second slit is formed in a direction inclined with respect to the contour of the second internal electrode.

6. The multi-terminal multilayer capacitor according to any one of claims 1 to 3, wherein: The first slit and the second slit are formed to overlap each other in a plan view.

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