A method for testing on-conduction resistance

Abstract

The application provides a method for testing on-resistance. The method is characterized in that a high-power high-precision standard resistor is connected in series with a probe card end between a testing machine and a wafer supporting table or a testing machine end on a path between the testing machine and the wafer supporting table to form a "pseudo" Kelvin four-wire testing loop. The voltage measurement loop can work in an optimal working zone, and the measurement errors caused by the wafer supporting table self-resistance R1 and the contact resistance R2 between the wafer supporting table and the wafer back surface can be further eliminated, so that the overall testing precision and the adaptability of the whole system are improved to cope with the accurate measurement of different products. Therefore, the traditional "pseudo" Kelvin four-wire method testing cannot accurately reflect the real resistance value of the measured device, and the problem of great challenge to the accuracy of the measured resistance value is avoided. dson The test value uniformity is poor and the overall test value is large, so that the real resistance value of the measured device cannot be accurately reflected, and the problem of great challenge to the accuracy of the measured resistance value is avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor integrated circuit testing, and particularly relates to a method for improving the precision of micro on-resistance testing in discrete device wafer level testing. BACKGROUND

[0002] In the process of semiconductor discrete device wafer testing (Chip Probing, CP), on-resistance (RDSON) is a key testing parameter. In order to obtain an accurate on-resistance RDSON test value, Kelvin four-wire method is used for testing. Ideal Kelvin four-wire method testing can obtain an extremely accurate on-resistance RDSON test value, but in actual CP testing, due to hardware constraints, "pseudo" Kelvin four-wire method testing inevitably occurs, which causes the on-resistance RDSON test value on the wafer surface to have poor uniformity and the overall test value to be too large. The simplified schematic diagram of ideal Kelvin four-wire method testing and the simplified schematic diagram of "pseudo" Kelvin four-wire method testing are shown in Figure 1a and 1b respectively: wherein in ideal Kelvin four-wire method testing, the test points of the voltage and current loops are close to the two ends of the measured device R; in "pseudo" Kelvin four-wire method testing, there can be a small R m1 or R m2 resistance between the test points of the voltage and current loops and the two ends of the measured device R, and when actually measuring, these two small R m1 or R m2 resistance values are also introduced into the measured value, which causes the measured resistance R of the measured device to be larger than the actual resistance.

[0003] The schematic diagram of on-resistance RDSON testing in the actual process of semiconductor discrete device wafer testing is as shown in Figure 2As shown: Kelvin four-wire SL (low voltage measurement loop line) and FL (low current loop line) of the probe card are directly connected to the source of the wafer; FH (high current loop line) and SH (high voltage measurement loop line) are directly connected to the Chuck of the Prober, and then connected to the drain of the wafer through the surface of the Chuck. As can be seen from the figure, due to the existence of the Chuck resistance R1 and the contact resistance R2 between the Chuck and the back of the wafer, the actual device R0 is tested by the "pseudo" Kelvin four-wire method, so the on-resistance RDSON of the wafer in the wafer surface is poor in uniformity and the overall test value is large, which cannot accurately reflect the true resistance value of the measured device. And with the continuous innovation of semiconductor manufacturing process and the continuous improvement of production technology, the on-resistance of discrete devices has entered the milliohm level, and there are already mass-produced products below 5 milliohm. The "pseudo" Kelvin four-wire method test poses a great challenge to the accurate measurement of the on-resistance RDSON of such ultra-small on-resistance discrete devices. SUMMARY

[0004] The purpose of the present application is to provide a test method for on-resistance, to solve the problem that in the current CP test process, due to the very small on-resistance of discrete devices which has entered the milliohm level, the traditional "pseudo" Kelvin four-wire method test has poor uniformity of the test value of the ultra-small on-resistance Rdson in the wafer surface and the overall test value is large, which cannot accurately reflect the true resistance value of the measured device, and poses a great challenge to the accuracy of the measured resistance.

[0005] To solve the above technical problems, the present application provides a test method for on-resistance, which is applied to a wafer test system, the test system comprising a test machine, a Chuck and a probe card, the test method comprising the following steps:

[0006] providing a to-be-tested wafer and a standard resistance, placing the to-be-tested wafer on the Chuck, and connecting the Chuck carrying the to-be-tested wafer, the test machine, the probe card and the standard resistance in series to form a voltage loop and a current loop through four leads;

[0007] performing wafer test on the to-be-tested wafer to determine the on-resistance of the to-be-tested wafer in the wafer test by the "pseudo" Kelvin four-wire method through the voltage loop and the current loop.

[0008] Further, the leads in series in the voltage loop are high voltage loop leads SH and low voltage loop leads SL, and the leads in series in the current loop are high current loop leads FH and low current loop leads FL;

[0009] The low-voltage loop lead SL and the low-current loop lead FL are directly connected to the source end of the wafer under test through the probe card, and the high-current loop lead FH and the high-voltage loop lead SH are directly connected to the wafer support table of the test machine to be connected to the drain end of the wafer under test through the surface of the wafer support table.

[0010] Further, in the voltage loop and the current loop, the standard resistance is connected in series at the probe card end between the test machine table and the wafer support table.

[0011] Further, in the voltage loop and the current loop, the standard resistance is connected in series at the test machine table end on the test machine table path.

[0012] Further, the wafer under test is subjected to wafer testing to determine the on-resistance of the wafer under test in wafer testing by the "pseudo" Kelvin four-wire method through the voltage loop and the current loop, and the step comprises:

[0013] A first voltage and a first current are respectively applied to the GS end and the DS end of the wafer under test, and the wafer under test is subjected to first wafer testing to obtain the bias resistance R o ffset , of the wafer testing system. offset The bias resistance R

[0014] A second voltage and a second current are respectively applied to the GS end and the DS end of the wafer under test, and the wafer under test is further subjected to non-first wafer testing, and the on-resistance is obtained by using a preset on-resistance calculation formula, wherein the first current is less than the second current.

[0015] Further, the second current is at least 5 times the first current.

[0016] Further, when the standard resistance is connected in series at the probe card end between the test machine table and the wafer support table, the calculation formula of the bias resistance can be:

[0017] R offset 1=R1+R2+Ra=K*R cp 1+(1-K)Ra;

[0018] And the calculation formula of the preset on-resistance can be:

[0019] R dson =R cp 2-R offset 1;

[0020] R2=R1+R2=K*(R1-Rai); wherein R1 is the resistance of the wafer support table itself, R2 is the contact resistance between the wafer to be tested and the wafer support table, R cp 1 is a test value obtained when the wafer to be tested is tested for the first time, R cp 2 is a test value obtained when the wafer to be tested is tested for the first time, K is a coefficient, and the value of K ranges from 0 to 1, R dson 2 is a test value obtained when the wafer to be tested is tested for the first time, K is a coefficient, and the value of K ranges from 0 to 1, R

[0021] Further, when the standard resistance is connected in series on the test machine table end of the wafer support table path, the voltage loop and the current loop further comprise relays K1, K2,..., K11,..., Kn connected in parallel between the test machine table and the wafer support table, and the standard resistance comprises one of resistances Ra1, Ra2,..., Rai,..., Ran connected in series with the relays K2,..., K10, K12,..., Kn, respectively.

[0022] Further, the resistance values of the resistances Ra1, Ra2,..., Ran connected in series with each relay K1, K2,..., K11,..., Kn can be adjusted in the range of 1 mΩ to 1 Ω.

[0023] Further, during the first wafer test and the non-first wafer test, the relays K1 and K11 are in an open state, and one of the relays K2,..., K10, K12,..., Kn is in a closed state; and during other wafer test items of the wafer to be tested, the relays K1 and K11 are in a closed state, and the relays K2,..., K10, K12,..., Kn are in an open state.

[0024] Further, the calculation formula of the bias resistance can also be:

[0025] R offset 2=R1+R2=K*(R cp 1-Rai);

[0026] The calculation formula of the preset on-resistance can also be:

[0027] R dson =R cp 2-R offset 2-Rai;

[0028] wherein R1 is the resistance of the wafer support table itself, R2 is the contact resistance between the wafer to be tested and the wafer support table, R cp1 is a test value obtained when a first test is performed on the wafer to be tested, the R cp 2 is a test value obtained when a non-first test is performed on the wafer to be tested, K is a coefficient, and the value range of K is 0-1, the R dson is an on-resistance of the wafer to be tested in wafer testing, and Rai is a standard resistance, which is one of Ra1, Ra2,..., Ran with a value greater than or equal to zero, and the value of i is 1, 2,..., n.

[0029] Further, the resistance range of the standard resistance Rai needs to satisfy the formula: Vmax*20%<I*(Rai+R0)<Vmax*80% or at least satisfy the formula I*(Rai+R0)﹤=Vmax and I*I*Rai﹤=P; wherein Vmax can be a measured source range voltage when a test machine tests the on-resistance, I can be a current corresponding to the measured source range voltage, and P can be a maximum power of the standard resistance Rai.

[0030] Further, when the R0 satisfies the formula Vmax*20%<I*R0<Vmax*80% or the Rai does not satisfy the formula I*I*Rai﹤=P, in the first wafer test and the non-first wafer test, the relays K1 and K11 are in a closed state; and in other wafer test items of the wafer to be tested, the relays K1 and K11 are in a closed state, and the relays K2,..., K10, K12,..., Kn are in an open state.

[0031] Compared with the prior art, the technical scheme of the present application has at least one of the following beneficial effects:

[0032] In the test method of the on-resistance provided by the application, firstly, the wafer to be tested is placed on the wafer supporting table, and the wafer supporting table carrying the wafer to be tested, the test machine table, the probe card and the standard resistance are connected in series to form a voltage loop and a current loop through four leads; then, the wafer to be tested is tested to determine the on-resistance of the wafer to be tested in wafer testing by using the "pseudo" Kelvin four-wire method through the voltage loop and the current loop. The application forms a "pseudo" Kelvin four-wire test loop by connecting high-power and high-precision standard resistances in series at the probe card end between the test machine table and the wafer supporting table and at the test machine table end on the test machine table path, can make the measurement source voltage measurement loop work in the best working zone, further eliminate the measurement error caused by the wafer supporting table itself resistance R1 and the contact resistance R2 between the wafer supporting table and the wafer back surface, and thus improve the overall test precision and the adaptability of the whole system to cope with the accurate measurement of different products. Therefore, the problem that the traditional "pseudo" Kelvin four-wire method test cannot accurately reflect the real resistance value of the measured device due to the very small on-resistance of the discrete device in the CP test process, which is already in the milliohm level, the poor test value uniformity and the overall test value being too large, and the emergence of the problem of great challenge to the accuracy of the measured resistance are avoided. dson The test value uniformity is poor and the overall test value is too large, so that the real resistance value of the measured device cannot be accurately reflected, and the problem of great challenge to the accuracy of the measured resistance occurs. BRIEF DESCRIPTION OF DRAWINGS

[0033] Figure 1a Simplified schematic diagram of the ideal Kelvin four-wire method test of the application;

[0034] Figure 1b Simplified schematic diagram of the "pseudo" Kelvin four-wire method test of the application;

[0035] Figure 2 Simplified schematic diagram of the "pseudo" Kelvin four-wire method test of the application in the actual wafer test on-resistance RDSON of the semiconductor discrete device in an embodiment;

[0036] Figure 3 Flowchart of the on-resistance test method in an embodiment of the application;

[0037] Figure 4 Schematic diagram of the "pseudo" Kelvin four-wire method test of the on-resistance test method provided in an embodiment of the application in the test process, in which the standard resistance is connected in series at the probe card end;

[0038] Figure 5 Schematic diagram of the "pseudo" Kelvin four-wire method test of the on-resistance test method provided in an embodiment of the application in the test process, in which the standard resistance is connected in series at the test machine table end;

[0039] In the drawings, the reference signs are as follows:

[0040] ATE - Automatic Test Equipment; R0 - Resistance of the wafer under test;

[0041] R1 - Resistance of the wafer support stage itself; R2 - Contact resistance between the wafer support stage and the back of the wafer;

[0042] Ra / Ra2~Ran – Standard resistor; R dson - Measure the on-resistance of the wafer during wafer testing. Detailed Implementation

[0043] As described in the background section, during the chip probing (CP) process for semiconductor discrete devices, the on-resistance (R) is... dson The on-resistance RDSON is a key test parameter. To obtain accurate on-resistance RDSON values, the Kelvin four-wire method is used. An ideal Kelvin four-wire method can yield extremely accurate on-resistance R. dson The test value is accurate, but in actual CP testing, due to hardware constraints, "pseudo" Kelvin four-wire method testing inevitably occurs, causing the on-resistance R in the wafer plane to be incorrect. dson The test values ​​have poor uniformity and are generally too large. The simplified schematic diagrams of the ideal Kelvin four-line method and the "pseudo" Kelvin four-line method are shown below. Figure 1a and 1b As shown: In the ideal Kelvin four-wire method test, the test points of the voltage and current loops are in close contact with both ends of the device under test (R); in the "pseudo" Kelvin four-wire method test, there may be a small gap between the test points of the voltage and current loops and the ends of the device under test (R). m1 Or R m2 Resistance, in actual measurement, these two small R's m1 Or R m2 The resistance value can also be included in the measured value, causing the final measured resistance R of the device under test to be larger than its actual resistance.

[0044] During actual wafer testing of semiconductor discrete devices, the on-resistance R dson The schematic diagram during testing is as follows Figure 2 As shown: The SL (low voltage return path) and FL (low current return path) of the Kelvin four-wire probe are directly connected to the source of the wafer via a probe card; the FH (high current return path) and SH (high voltage return path) are directly connected to the substrate of the probe tester, and then connected to the drain on the back of the wafer via the substrate surface. It is clear from the diagram that due to the substrate's own resistance R1 and the contact resistance R2 between the substrate and the back of the wafer, the test of the device under test (DUT) R0 is actually a "pseudo" Kelvin four-wire test. Therefore, the on-resistance R within the wafer surface is... dsonThe test value is not uniform and the overall test value is large, which cannot accurately reflect the real resistance of the measured device. With the continuous innovation of semiconductor manufacturing process and the continuous improvement of production technology, the on-resistance of discrete devices has entered the milliohm level, and there are already mass-produced products below 5 milliohm. The "pseudo" Kelvin four-wire method test poses a great challenge to the accurate measurement of the on-resistance R dson of the ultra-small on-resistance discrete device.

[0045] Therefore, the purpose of the present application is to provide a test method for on-resistance to solve the problem that the on-resistance of discrete devices has entered the milliohm level, and the traditional "pseudo" Kelvin four-wire method test for the on-resistance RDSON of the wafer surface is not uniform and the overall test value is large, which cannot accurately reflect the real resistance of the measured device and poses a great challenge to the accuracy of the measured resistance.

[0046] The test method for on-resistance provided by the present application will be further described below in combination with the drawings and specific embodiments. The advantages and features of the present application will be clearer according to the following description. It should be noted that the drawings are very simplified and use non-precise proportions, only for the purpose of facilitating and clarifying the description of the embodiments of the present application. In the following description, many specific details are set forth in order to provide a thorough understanding of the present application, but the present application can also be implemented in other ways different from those described herein, therefore the present application is not limited by the specific embodiments disclosed below.

[0047] As shown in the present application and claims, unless the context clearly indicates otherwise, "one", "a", "an" and / or "the" do not refer to the singular, but also include the plural. Generally, the terms "include" and "contain" only indicate the inclusion of the steps and elements explicitly identified, and these steps and elements do not constitute an exclusive list, and the method or device can also contain other steps or elements. In the detailed description of the embodiments of the present application, the cross-sectional view of the device structure will be partially enlarged without general proportion, and the described schematic diagram is only an example, which should not limit the scope of protection of the present application. In addition, the three-dimensional spatial dimensions of length, width and depth should be included in actual production.

[0048] For a better understanding of the present application, reference can be made to Figure 3 , Figure 3 The flowchart of the on-resistance test method in an embodiment of the present application is shown in Figure 3 The test method for on-resistance provided by the present application can be applied to a wafer test system, and the test system can specifically include a test machine, a wafer holder and a probe card. Specifically, the test method provided by the present application can at least include the following steps:

[0049] Step S100, providing a to-be-tested wafer and a standard resistance, placing the to-be-tested wafer on the wafer supporting table, and connecting the wafer supporting table carrying the to-be-tested wafer, the testing machine table, the probe card and the standard resistance in series to form a voltage loop and a current loop through four leads;

[0050] Step S200, performing wafer testing on the to-be-tested wafer to determine the on-resistance of the to-be-tested wafer in wafer testing by using the "pseudo" Kelvin four-wire method through the voltage loop and the current loop.

[0051] First, the on-resistance testing method provided by the present application will be described in detail. For details, please refer to Figures 4-5 , the on-resistance testing method provided by the present application is a "pseudo" Kelvin four-wire method. Figure 4 is a schematic diagram of the testing principle of the on-resistance testing method provided by an embodiment of the present application in which the standard resistance is connected in series at the end of the probe card in the testing process. Figure 5 is a schematic diagram of the testing principle of the on-resistance testing method provided by an embodiment of the present application in which the standard resistance is connected in series at the end of the testing machine table in the testing process.

[0052] Embodiment 1: the standard resistance Ra is connected in series at the end of the probe card

[0053] In step S100, referring to Figure 4 , a to-be-tested wafer is provided, and the to-be-tested wafer includes a plurality of to-be-tested chips. Specifically, in this embodiment, the material of the wafer is selected from single crystal silicon, polycrystalline silicon or amorphous silicon; the wafer can also be at least one of the following materials: silicon (Si), germanium (Ge), silicon-germanium (SiGe), silicon-carbon (SiC), silicon-germanium-carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III / V compound semiconductors; the wafer can also be a ceramic substrate such as aluminum oxide, a quartz or glass substrate or other semiconductor materials. For example, in this embodiment of the present application, the wafer is silicon.

[0054] The wafer to be tested is placed on the chuck table in a wafer testing system including a testing machine, a chuck table and a probe card, and the chuck table carrying the wafer to be tested, the testing machine, the probe card and the standard resistance are connected in series to form a voltage loop and a current loop through four leads. Specifically, in the embodiment, the testing machine is an integrated circuit (IC) automatic test equipment (ATE), the voltage loop connected through the leads is a Kelvin plus current loop, and the current loop is a Kelvin voltage measuring loop; the leads connected in series in the voltage loop are a high-voltage loop lead SH and a low-voltage loop lead SL, and the leads connected in series in the current loop are a high-current loop lead FH and a low-current loop lead FL; wherein the low-voltage loop lead SL and the low-current loop lead FL are directly connected to the source end of the wafer to be tested through the probe card, and the high-current loop lead FH and the high-voltage loop lead SH are directly connected to the chuck table of the testing machine to be connected to the drain end of the wafer to be tested through the surface of the chuck table; the connected testing system is suitable for Kelvin four-wire method testing. Specifically, due to the existence of the chuck table resistance R1 and the contact resistance R2 between the chuck table and the wafer back surface, a "pseudo" Kelvin four-wire method test is formed when the resistance R0 of the device under test is tested.

[0055] In step S200, with continued reference to Figure 4 In the voltage loop and the current loop, the standard resistance Ra is connected in series at the probe card end between the testing machine and the chuck table.

[0056] In the embodiment, the standard resistance can be exemplarily a high-precision and high-power standard resistance. Then after the voltage loop and the current loop are formed, a first voltage and a first current are respectively applied to the GS end and the DS end of the wafer to be tested, and a first wafer test is performed on the wafer to be tested to obtain a test value R cp 1. In the embodiment, the first current is set to be small, so that the semiconductor device formed on the wafer can work in the amplification region, and at this time the resistance R0 of the wafer under test (which can also be referred to as the die under test) itself is small and easy to calculate R cp 1 = R0 + R1 + R2 + Ra.

[0057] Exemplarily, since the resistance R0, R1 and R2 in the formula R cp 1 = R0 + R1 + R2 + Ra are all relatively small, the formula can be simplified by introducing a coefficient K as follows: R1 + R2 = (R cp 1 - Ra) * K, that is, the bias resistance R offset1 is the sum of the self-resistance R1 of the wafer supporting table, the contact resistance R2 between the wafer to be tested and the wafer supporting table.

[0058] R1 is the test value obtained when the wafer to be tested is tested for the first time. cp 1 is the bias resistance of the wafer testing system, and specifically, the bias resistance R1 is calculated according to the following formula: offset

[0059] R1 = R1 + R2 + Ra = K * R1 + (1-K) Ra offset cp 1 + (1-K) Ra

[0060] R1 is the self-resistance of the wafer supporting table, R2 is the contact resistance between the wafer to be tested and the wafer supporting table, and R1 is the test value obtained when the wafer to be tested is tested for the first time. cp The value of the coefficient K can refer to the test value of the functional test (FT), and preferably, the value of the coefficient K ranges from 0 to 1.

[0061] Then, a second voltage and a second current are applied to the GS end and the DS end of the wafer to be tested, respectively, and further non-first wafer testing (for example, second wafer testing, third wafer testing or other multiple wafer testing) is performed on the wafer to be tested to obtain a test value R2, and the on-resistance is obtained by using a preset on-resistance calculation formula; for example, the preset on-resistance calculation formula is: R cp 2 = R1 + R2 + Ra = K * R1 + (1-K) Ra dson 2 - R1 cp 2 = R1 + R2 + Ra = K * R1 + (1-K) Ra offset 1; wherein the first current in the two wafer tests is less than the second current, and preferably, the second current is at least 5 times the first current.

[0062] In the above on-resistance testing process, because the standard resistance Ra connected in series to the probe card end has a small resistance value, such as 100 mR, the influence of such a small resistance value on other wafer test items (such as VTH, BV, ID, etc.) can be ignored. However, because there is Ra in the loop, it can ensure that the voltage measurement loop works in the best working zone, thereby improving the measurement accuracy; after obtaining a suitable K value, the measurement error caused by R1 and R2 can be further eliminated, the test value of the wafer test CP can be wirelessly approximated to the FT test value, and the wafer on-resistance R ds on The uniformity of the test value is poor.

[0063] Optionally, when the standard resistance Ra is connected in series to the probe card end, the calculation formula of the bias resistance can also be: ​​

[0064] R offset 2 = R1 + R2 = K * (R cp 1 - Rai);

[0065] And the preset on-resistance calculation formula is:

[0066] R dson = R cp 2 - R offset 2 - Rai;

[0067] Wherein, R1 is the piece of the table itself resistance, R2 is the contact resistance between the wafer and the piece of the table, the R cp 1 is the test value obtained when the first test of the wafer under test, the R cp 2 is the test value obtained when the non-first test of the wafer under test, K is the coefficient, and the value range of K is 0-1, R dson is the on-resistance of the wafer under test in the wafer test, Rai is the standard resistance, Rai is one of Ra1, Ra2,..., Ran with the value greater than or equal to zero, and the value of i is 1, 2,..., n.

[0068] Embodiment 2: the test machine table end of the standard resistance Ra is connected to the test machine table and the piece of the table passage.

[0069] In step S100, referring to Figure 5 , a wafer under test is provided, and the wafer under test includes a plurality of chips to be tested. Specifically, in the embodiment, the material of the wafer is selected from single crystal silicon, polycrystalline silicon or amorphous silicon; the wafer can also be at least one of the following materials: silicon (Si), germanium (Ge), silicon-germanium (SiGe), silicon carbide (SiC), silicon-germanium-carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III / V compound semiconductors; the wafer can also be a ceramic substrate such as aluminum oxide, a quartz or glass substrate, or other semiconductor materials. For example, in the embodiment of the present application, the wafer is silicon.

[0070] The wafer to be tested is placed on the wafer support table in a wafer testing system including a testing machine, a wafer support table and a probe card, and the wafer support table carrying the wafer to be tested, the testing machine, the probe card and the standard resistance are connected in series to form a voltage loop and a current loop through four leads. Specifically, in the embodiment, the testing machine is an integrated circuit (IC) automatic test equipment (ATE), the voltage loop connected through the leads is a Kelvin plus current loop, and the current loop is a Kelvin measure voltage loop; the leads connected in series in the voltage loop are a high voltage loop lead SH and a low voltage loop lead SL, and the leads connected in series in the current loop are a high current loop lead FH and a low current loop lead FL; wherein the low voltage loop lead SL and the low current loop lead FL are directly connected to the source end of the wafer to be tested through the probe card, and the high current loop lead FH and the high voltage loop lead SH are directly connected to the wafer support table of the testing machine to be connected to the drain end of the wafer to be tested through the surface of the wafer support table; the testing system connected is suitable for Kelvin four-wire method testing. Specifically, due to the existence of the contact resistance R2 between the wafer support table and the back surface of the wafer and the resistance R1 of the wafer support table itself, a "pseudo" Kelvin four-wire method test is formed when the resistance R0 of the device to be tested is tested.

[0071] In step S200, with continued reference to Figure 5 In the voltage loop and the current loop, the standard resistance is connected in series at the testing machine end on the path between the testing machine and the wafer support table. In this case, the testing structure provided by the present application Figure 5 In the testing structure in the above embodiment, a relay K1 and a relay K11 are further added to the loop from the high current loop lead FH and the high voltage loop lead SH of the testing machine to the wafer support table, respectively; and the FH and the SH are short-circuited at the testing machine end and connected to the relays K2,..., K10, K12,..., Kn, respectively.

[0072] In the embodiment, when the standard resistance is connected in series at the end of the test machine on the path between the test machine and the wafer holder, the voltage loop and the current loop further comprise relays K1, K2,..., K11,..., Kn connected in parallel between the test machine and the wafer holder, so as to control which of the high-precision standard resistances Ra1, Ra2,..., Rai,..., Ran with different resistance values connected in series with each of the relays K2,..., K10, K12,..., Kn respectively is connected in the test process by means of each relay respectively, i.e. the standard resistance in the embodiment 2 is one of the resistances Ra1, Ra2,..., Ran. For example, the resistance values of the resistances Ra1, Ra2,..., Ran connected in series with each of the relays K1, K2,..., K11,..., Kn can be adjusted in the range of 1 mΩ to 1 Ω.

[0073] Specifically, the test value R cp 1 of the wafer in the first test is calculated as follows:

[0074] R offset 2 = R1 + R2 = K * (R cp 1 - Rai);

[0075] wherein R1 is the resistance of the wafer holder itself, R2 is the contact resistance between the wafer to be tested and the wafer holder, R cp 1 is the test value of the wafer to be tested in the first test, R cp 2 is the test value of the wafer to be tested in the non-first test, and K is a coefficient and its value ranges from 0 to 1.

[0076] Then, a second voltage and a second current are applied to the GS end and the DS end of the wafer to be tested respectively, and the wafer to be tested is further tested in the non-first wafer test (for example, the second wafer test, the third wafer test or other multiple wafer tests) to obtain a test value R cp 2, and the on-resistance is calculated by using a preset on-resistance calculation formula: R dson 2 = R cp 2 - Rai; offset 2 - Rai; wherein the first current in the two wafer tests is less than the second current, and preferably, the second current is at least 5 times the first current. R dson is the on-resistance of the wafer to be tested in the wafer test, and Rai is one of Ra1, Ra2,..., Ran with a value greater than or equal to zero, and i is 1, 2,..., n.

[0077] In the present embodiment, during the first wafer test and the non-first wafer test, the relays K1 and K11 are in the open state, and only one of the relays K2, K10, K12,..., Kn is in the closed state; after the present test item is finished, the Kn relay is opened, and the K1 and K11 relays are closed, thus not affecting other test items. For example, during other wafer test items of the wafer under test, the relays K1 and K11 are in the closed state, and the relays K2, K10, K12,..., Kn are in the open state. In the present embodiment, the subsequent R offset is calculated and used in a manner similar to that in Embodiment 1.

[0078] Specifically, in the present embodiment, for the on-resistance R dson of the product under test, only the standard resistance Ra is connected in series during the on-resistance R dson test, and the bias resistance R offset is defined as R offset = R1+R2= (R cp 1-Ra)*K; then, the K1 and K11 relays are directly closed during the formal R dson test, thus adapting to the measurement of products with large current. Therefore, in the present embodiment, when the standard resistance is connected in series at the test machine end, the measurement source can be made to work in the optimal working zone to improve the overall test precision; meanwhile, multiple sets of relays and combinations of different resistance values of the standard resistance are provided, thus improving the adaptability of the entire system and further coping with the accurate measurement of different products.

[0079] It should be noted that when the resistance R0 of the wafer under test is large, and the second current value is large, in order to avoid the power of the loop being too large and burning the device, the resistance value of the standard resistance Rai can be set to 0, i.e., the standard resistance is not added to the loop, and the on-resistance of the wafer under test during the wafer test can still be obtained through multiple tests using the voltage loop and the current loop provided by the present application.

[0080] For example, when the R0 satisfies the formula Vmax*20% < I*R0 < Vmax*80% (i.e., the resistance R0 of the measured die itself is large, and thus the circuit loop does not access the Rai), or the Rai does not satisfy the formula I*I*Rai << P (i.e., the current of the loop is too large to cause a large power), during the first wafer test and the non-first wafer test, the relays K1 and K11 are in the closed state; and during other wafer test items of the measured wafer, the relays K1 and K11 are in the closed state, and the relays K2,..., K10, K12,..., Kn are in the open state.

[0081] In the above two embodiments, the R offset on-resistance R cp 1test item, and set a suitable system standard evaluation test range (Standard Performance Evaluation Corporation, SPEC), and the suitable SPEC range of the R cp 1test item is Ra~1.1Ra, i.e., the test item is set to stop testing after a test failure, so that the entire test system can be checked and monitored, and greater losses caused by a damaged test system can be avoided.

[0082] In summary, in the on-resistance test method provided in the present application, first, the measured wafer is placed on the wafer support, and the wafer support carrying the measured wafer, the test machine, the probe card, and the standard resistance are connected in series to form a voltage loop and a current loop through four leads; then, wafer testing is performed on the measured wafer, so as to determine the on-resistance of the measured wafer in wafer testing by using the "pseudo" Kelvin four-wire method through the voltage loop and the current loop. The present application forms a "pseudo" Kelvin four-wire test loop by connecting high-power and high-precision standard resistances in series at the probe card end between the test machine and the wafer support and at the test machine end on the test machine and wafer support path, can make the measurement source voltage measurement loop work in the best working zone, further eliminate the measurement error caused by the wafer support self-resistance R1 and the wafer support and wafer back contact resistance R2, and thus improve the overall test precision and the adaptability of the entire system to cope with accurate measurement of different products. Therefore, the problem that the on-resistance of the discrete device is very small and has entered the milliohm level in the CP test process is avoided, the traditional "pseudo" Kelvin four-wire method test has poor uniformity of the on-resistance R dson test value and the overall test value is large, which cannot accurately reflect the true resistance value of the measured device, and the problem of great challenge to the accuracy of the measured resistance.

[0083] It should be noted that in the embodiments of the present application provided by the present application, an electronic device is also provided, comprising a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory complete mutual communication through the communication bus, the memory is used for storing a computer program, and the processor is used for executing the program stored in the memory to implement the test method of the on-resistance provided by the embodiments of the present application.

[0084] In addition, other implementation manners of the test method of the on-resistance implemented by the processor executing the program stored in the memory are the same as the implementation manners mentioned in the foregoing method embodiment part, and will not be repeated here.

[0085] In yet another embodiment provided by the present application, a computer readable storage medium is also provided, and the computer readable storage medium stores instructions, and when the instructions are executed on a computer, the computer executes the test method of the on-resistance of any one of the foregoing embodiments.

[0086] In the foregoing embodiments, all or part of the embodiments can be implemented by software, hardware, firmware or any combination thereof. When implemented by software, all or part of the embodiments can be implemented in the form of a computer program product. The computer program product comprises one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network or other programmable device. The computer instructions can be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center through a wired (such as coaxial cable, optical fiber, digital subscriber line) or wireless (such as infrared, wireless, microwave, etc.) manner. The computer readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. integrated with one or more available media. The available medium can be a magnetic medium (such as a floppy disk, a hard disk, a magnetic tape), an optical medium or a semiconductor medium (such as a solid state disk) and the like.

[0087] It is to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting; it is not intended to exclude myriad other embodiments of the present application that other present or future devices perform the same function under a different name. It must be noted that, as used in the specification and the appended claims, the singular forms "a," "an" and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to "a component" can include a plurality of such components. In this specification and in the claims, the term "when" should be understood to mean "whereupon" or "upon" when used in close proximity to defining an action in conjunction with one or more other actions or events, such as, for example, "when A happens, B happens" or "when A occurs, B occurs." The terms "program" or software are used herein in a generic sense to refer to any type of computer code or set of computer-executable instructions that can be employed to program a computer or other processor configuration to implement various aspects associated with the present application. Additionally, the term "coupled" is used herein to express a relationship between or among multiple elements and / or components in a manner that can be internal or external, temporary or permanent, directly or indirectly, wired or wireless, or some combination of the above. Unless otherwise indicated herein, the terms "determining" (or "identifying") and "creating" (or "generating") are used interchangeably herein to refer to any process of analysis, calculation, processing, or manipulation of information, data, or signals by a device, system, or apparatus, whether performed by human intervention or without human intervention.

[0088] Each of the various embodiments in the present specification is described in a relevant manner, and the same or similar parts among the various embodiments can be referred to each other. Each of the various embodiments focuses on the difference from other embodiments. In particular, for the device, electronic device, and computer-readable storage medium embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the part of the method embodiment.

[0089] The preferred embodiments of the present application have been described above with the aid of drawing provided only by way of example and are not intended to limit the scope of the present application. Modifications, improvements, and other embodiments, which are within the spirit and scope of the present application, are included in the scope of the present application.

Claims

1. A method for testing on-resistance, characterized in that, The method is applied to a wafer testing system, which includes a testing machine, a wafer carrier, and a probe card. The testing method includes the following steps: A wafer to be tested and a standard resistor are provided. The wafer to be tested is placed on the wafer support stage, and the wafer support stage, the test stage, the probe card and the standard resistor are connected in series to form a voltage loop and a current loop through four leads. The wafer under test is subjected to wafer testing to determine the on-resistance of the wafer under test in the wafer testing process using the "pseudo" Kelvin four-wire method through the voltage and current loops. The leads in the voltage loop connected in series are the high-voltage loop lead SH and the low-voltage loop lead SL, and the leads in the current loop connected in series are the high-current loop lead FH and the low-current loop lead FL. The low-voltage loop lead SL and the low-current loop lead FL are directly connected to the source end of the wafer under test through the probe card, while the high-current loop lead FH and the high-voltage loop lead SH are directly connected to the wafer support stage of the test machine, so as to connect to the drain end on the back side of the wafer under test through the surface of the wafer support stage. In the voltage circuit and the current circuit, the standard resistor is connected in series at the probe card terminal between the test bench and the substrate stage; or; In the voltage circuit and the current circuit, the standard resistor is connected in series at the test machine end on the path between the test machine and the substrate stage; The steps of performing wafer testing on the wafer under test, and determining the on-resistance of the wafer under test in the wafer test using the "pseudo" Kelvin four-wire method through the voltage and current loops, include: A first voltage and a first current are applied to the GS and DS terminals of the wafer under test, respectively, and the wafer under test is subjected to its first wafer test to obtain the bias resistance R of the wafer test system. offset , wherein, the R offset It is the sum of the resistance R1 of the substrate stage and the contact resistance R2 between the wafer under test and the substrate stage; A second voltage and a second current are applied to the GS terminal and DS terminal of the wafer under test, respectively, and a non-first wafer test is performed on the wafer under test. The on-resistance is obtained using a preset on-resistance calculation formula, wherein the first current is less than the second current. When the standard resistor is connected in series with the probe card between the testing machine and the substrate stage, the formula for calculating the bias resistor is: R offset 1=R1+R2+Ra=K*R cp 1+(1-K)Ra; The formula for calculating the preset on-resistance is: R dson =R cp 2-R offset 1; Among them, R offset R1 is the bias resistor when the standard resistor is connected in series with the probe card between the test bench and the wafer stage; R2 is the resistance of the wafer stage itself; Ra is the first standard resistor, and the value of Ra is greater than zero; K is a coefficient, and the value of K is 0~1; R cp 1 represents the test value obtained during the initial test of the wafer under test, R. cp 2 represents the test value obtained during non-first testing of the wafer under test, R. dson The on-resistance of the wafer under test during wafer testing; When the standard resistor is connected in series at the test machine end on the path between the test machine and the substrate, the voltage circuit and the current circuit also include relays K1, K2, ..., K11, ..., Kn connected in parallel between the test machine and the substrate, and the standard resistor includes one of resistors Ra1, Ra2, ..., Ra11, ..., Ran, which are connected in series with the relays K1, K2, ..., K11, ..., Kn respectively, where n is the total number of relays; When the standard resistor is connected in series at the test machine end on the path between the test machine and the substrate stage, the formula for calculating the bias resistor is: R offset 2=R1+R2=K*(R cp 1-Rai); The formula for calculating the preset on-resistance is: R dson =R cp 2-R offset 2-Rai; Among them, R offset 2 is the bias resistor when the standard resistor is connected in series at the test machine end on the path between the test machine and the substrate stage; Rai is the second standard resistor; Rai is one of Ra1, Ra2, ..., Ran with a value greater than or equal to zero; and i takes the value 1, 2, ..., n.

2. The method for testing on-resistance as described in claim 1, characterized in that, The second current is at least 5 times the first current.

3. The method for testing conduction resistance as described in claim 1, characterized in that, When the standard resistor is connected in series at the test machine end on the path between the test machine and the wafer stage, during the first wafer test and the non-first wafer test, the relays K1 and K11 are both in the off state, and one of the relays K2, ..., K10, K12, ..., Kn is in the on state; and, in other wafer test items of the wafer to be tested, the relays K1 and K11 are in the on state, while the relays K2, ..., K10, K12, ..., Kn are all in the off state.

4. The method for testing on-resistance as described in claim 1, characterized in that, When the standard resistor is connected in series at the test machine end on the path between the test machine and the wafer stage, the adjustable resistance range of the resistors Ra1, Ra2, ..., Ran connected in series corresponding to each of the relays K1, K2, ..., K11, ..., Kn is 1 mΩ to 1 Ω.

5. The method for testing on-resistance as described in claim 1, characterized in that, When the standard resistor is connected in series at the test machine end on the path between the test machine and the wafer stage, the resistance value range of the second standard resistor Rai satisfies the following formula: Vmax * 20% < I * (Rai + R0) < Vmax * 80%; I * (Rai + R0) <= Vmax; I * I * Rai <= P; Where, Vmax is the measurement source range voltage when the test machine measures the on-resistance, I is the current corresponding to the measurement source range voltage, P is the maximum power of the standard resistor Rai, and R0 is the true on-resistance of the wafer to be tested itself.

6. The method for testing conduction resistance as described in claim 5, characterized in that, When R0 satisfies the formula Vmax * 20% < I * R0 < Vmax * 80% or Rai does not satisfy the formula I * I * Rai <= P, during the first wafer test and the non-first wafer test, the relays K1 and K11 are both in the on state; and, in other wafer test items of the wafer to be tested, the relays K1 and K11 are in the on state, while the relays K2, ..., K10, K12, ..., Kn are all in the off state.

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