Array substrate, driving method thereof and display device

Abstract

An embodiment of the present invention provides an array substrate, a driving method thereof, and a display device. By adopting an odd-even cross single drive design for a dual gate product, and alternately electrically connecting pixel units in the same row to a first type of gate line and a second type of gate line, pixel units in different rows are electrically connected to different first types of gate lines and different second types of gate lines, and pixel units in adjacent rows of pixel units located in the same column are electrically connected to different types of gate lines, the pixel units can be driven in a column inversion manner, so that the brightness of pixel units in the same row is alternately set to bright and dark, and the brightness of pixel units in adjacent rows of pixel units located in the same column is different, so that the overall brightness of the display area can be uniform, and no vertical stripes will be generated. Therefore, the pixel structure design provided by the embodiment of the present invention can improve the problem that the pixel structure in the related art is prone to green on the left and red on the right, and vertical stripes are undesirable.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to an array substrate, a driving method thereof, and a display device. Background Art

[0002] Thin Film Transistor Liquid Crystal Displays (TFT-LCDs) feature compact size, low power consumption, high image quality, zero radiation, and portability. They have experienced rapid development in recent years, gradually replacing traditional cathode ray tube (CRT) displays and dominating the current flat-panel display market. Currently, TFT-LCDs are widely used in a variety of large, medium, and small-sized products, encompassing nearly every major electronic product in today's information society, including LCD TVs, high-definition digital TVs, computers (desktop and laptop), mobile phones, tablets, navigation systems, in-car displays, projection displays, camcorders, digital cameras, electronic watches, calculators, electronic instruments, meters, public displays, and virtual displays. Summary of the Invention

[0003] Embodiments of the present invention provide an array substrate, a driving method thereof, and a display device, for improving the problem of vertical stripes in a liquid crystal display.

[0004] The embodiments of the present invention provide an array substrate, a driving method thereof, and a display device. The specific solutions are as follows:

[0005] An embodiment of the present invention provides an array substrate, comprising a display area and a non-display area surrounding the display area; the display area comprises: a plurality of pixel units distributed in an array, and a plurality of gate lines extending in a row direction and arranged in a column direction; the non-display area comprises a first gate driving circuit and a second gate driving circuit located at both ends of the gate lines;

[0006] The plurality of gate lines include a plurality of first-type gate lines and a plurality of second-type gate lines, each of the first-type gate lines is electrically connected to the first gate driving circuit, and each of the second-type gate lines is electrically connected to the second gate driving circuit;

[0007] The pixel units in the same row are alternately electrically connected to the first type of gate lines and the second type of gate lines, the pixel units in different rows are electrically connected to different first type of gate lines and different second type of gate lines, and the pixel units in the same column in adjacent rows are electrically connected to different types of gate lines.

[0008] In some embodiments, in the array substrate provided by the embodiments of the present invention, at least one column of pixel units constitutes a group; wherein,

[0009] For the pixel units in odd rows, the pixel units in an even group of the same row are electrically connected to the first type of gate lines, and the pixel units in an odd group of the same row are electrically connected to the second type of gate lines;

[0010] For the pixel units in the even rows, the pixel units in the odd array of the same row are electrically connected to the first type of gate lines, and the pixel units in the even array of the same row are electrically connected to the second type of gate lines.

[0011] In some embodiments, in the array substrate provided by the embodiments of the present invention, at least one column of pixel units constitutes a group; wherein,

[0012] For the pixel units in odd rows, the pixel units in an odd group of the same row are electrically connected to the first type of gate lines, and the pixel units in an even group of the same row are electrically connected to the second type of gate lines;

[0013] For the pixel units in even rows, the pixel units in an even array in the same row are electrically connected to the first type of gate lines, and the pixel units in an odd array in the same row are electrically connected to the second type of gate lines.

[0014] In some embodiments, in the array substrate provided by the embodiments of the present invention, each column of pixel units forms a group, or each two adjacent columns of pixel units form a group.

[0015] In some embodiments, in the array substrate provided by the embodiments of the present invention, the first-type gate lines and the second-type gate lines electrically connected to the pixel units in the same row are respectively located on both sides of the pixel units;

[0016] Alternatively, the first-type gate line and the second-type gate line electrically connected to the pixel unit are located on the same side of the pixel unit.

[0017] In some embodiments, in the array substrate provided by an embodiment of the present invention, the display area further includes a plurality of data lines extending along the column direction and arranged along the row direction, and the plurality of data lines and the plurality of gate lines define the plurality of pixel units;

[0018] Each pixel unit includes a plurality of sub-pixels of different colors, and the sub-pixels in the same column have the same color; the sub-pixels in the same column are electrically connected to the same data line, and the sub-pixels in different columns are electrically connected to different data lines; wherein,

[0019] The non-display area further includes a driving chip having a plurality of pads, and the first ends of the data lines corresponding to at least two columns of sub-pixels with the same polarity and color are electrically connected to the same pad.

[0020] In some embodiments, in the above-mentioned array substrate provided by an embodiment of the present invention, the first end of the data line corresponding to the sub-pixel in the Nth column is electrically connected to the first end of the data line corresponding to the sub-pixel in the N+6nth column, where N and n are both natural numbers.

[0021] In some embodiments, in the array substrate provided by an embodiment of the present invention, the second ends of the data lines electrically connected to the same pad are electrically connected.

[0022] Accordingly, an embodiment of the present invention provides a display device, comprising: an array substrate and an opposing substrate arranged opposite to each other, a liquid crystal layer located between the array substrate and the opposing substrate, and a backlight module located on the light incident side of the array substrate; wherein the array substrate is the above-mentioned array substrate provided in an embodiment of the present invention.

[0023] Accordingly, an embodiment of the present invention provides a driving method for driving the array substrate provided by the embodiment of the present invention, comprising:

[0024] In one frame time, scanning voltage is loaded on the gate lines row by row, and data voltage is loaded on the pixel units in a column-inverted manner, so that the brightness of the pixel units in the same row is alternately set to bright and dark, and the brightness of the pixel units in the same column in adjacent rows is different. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A schematic diagram of a pixel arrangement provided in the related art;

[0026] Figure 2 This is another pixel arrangement schematic diagram provided in the related art;

[0027] Figure 3 This is another pixel arrangement schematic diagram provided in the related art;

[0028] Figure 4 This is another pixel arrangement schematic diagram provided in the related art;

[0029] Figure 5 for Figure 4 Schematic diagram of driving the pixel shown;

[0030] Figure 6 This is another pixel arrangement schematic diagram provided in the related art;

[0031] Figure 7 for Figure 6 Schematic diagram of driving the pixel shown;

[0032] Figure 8 A schematic diagram of an array substrate provided by the present invention;

[0033] Figure 9for Figure 8 Schematic diagram of the local enlarged structure in;

[0034] Figure 10 A schematic diagram of another array substrate provided by the present invention;

[0035] Figure 11 for Figure 10 Schematic diagram of the local enlarged structure in;

[0036] Figure 12 for Figure 8 Schematic diagram of the corresponding display area display effect;

[0037] Figure 13 for Figure 10 Schematic diagram of the corresponding display area display effect;

[0038] Figure 14 A schematic diagram of another array substrate provided by the present invention;

[0039] Figure 15 A schematic diagram of another array substrate provided by the present invention;

[0040] Figure 16 A schematic structural diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0041] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. And in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0042] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words “include” or “comprise” and the like used in this disclosure mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. The words “connect” or “connected” and the like are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. “Inside”, “outside”, “upper”, “lower” and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0043] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual scale and are only for the purpose of illustrating the present disclosure. The same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions.

[0044] like Figure 1 As shown, Figure 1 This is a schematic diagram of a dot inversion pixel arrangement of a dual-gate product in the related art. However, the dot inversion driving method causes the voltage on the data lines (D1, D2, ...) to be constantly reversed between positive and negative, resulting in high power consumption. Figure 2 Yes Figure 1 An improvement made, namely Figure 2 Using column inversion drive mode, compared with Figure 1 The dot inversion structure has low power consumption, but in the same frame, adjacent polarities are arranged alternately as ++, --, ++, --, which makes the brightness uneven and creates the risk of bad shaking head patterns. Figure 2 To solve the problem of bad head wrinkles, we designed Figure 3 The pixel driving method shown is Figure 3 The point inversion driving method still has the problem of high power consumption.

[0045] In order to solve the above Figure 1-Figure 3 Various problems arise, the pixel structure used by Dual Gate products is as follows Figure 4 As shown, but if Figure 4 The pixel structure adopts Figure 5 In the odd-even cross single drive design shown, the gate lines of odd rows (G(1), G(3), G(5)...) are driven by the gate drive circuit on the left, and the gate lines of even rows (G(2), G(4), G(6)...) are driven by the gate drive circuit on the right, for example. Figure 5 In the first red sub-pixel R and the first green sub-pixel G on the left side of the first row, R is driven by the proximal end of G(1), and G is driven by the distal end of G(2). Due to the influence of gate line delay, etc., there are differences in their coupling to the data lines (D1, D2...), resulting in an inconsistency in the voltage difference (ΔVp) between the pixel voltages corresponding to R and G and the data line voltage. The ΔVp of the R pixel is large (display brightness is darker), and the ΔVp of the G pixel is small (display brightness is brighter), resulting in a greenish display on the left side; the first G pixel on the right side of the first row is driven by the proximal end of G(2), and the first R pixel on the right side of the first row is driven by the distal end of G(1), resulting in a large ΔVp of the G pixel (display brightness is darker), and a small ΔVp of the R pixel (display brightness is brighter), resulting in a reddish display on the right side. Thus Figure 4 The pixel structure shown uses Figure 5 The problem of green on the left and red on the right will occur when driving with odd-even cross single drive.

[0046] To improve Figure 4 The pixel structure shown is green on the left and red on the right. Currently, there are products on the market that use Figure 6 The pixel architecture shown, but if Figure 6 The pixel structure adopts Figure 7 When the odd-even cross single drive design is shown, although there is no Figure 4 The left green and right red problem, but according to Figure 7 In the pixel architecture shown, the first column of pixels (R, G, B) and the second column of pixels (R, G, B) on the left side of the panel are driven by the far end of G(2), and the ΔVp is small, so the display brightness is brighter. The third column of pixels (R, G, B) and the fourth column of pixels (R, G, B) are driven by the near end of G(1), and the ΔVp is large, so the display brightness is darker. The display brightness on the left side of the panel will be bright, dark, bright, and dark alternately distributed. The display brightness on the right side of the panel is opposite to that on the left side, so vertical stripes are easily generated on both sides of the panel.

[0047] To improve Figure 5 、 Figure 7 To solve the problems of left-green and right-red defects and vertical stripe defects caused by the odd-even cross single drive design, an embodiment of the present invention provides an array substrate, such as Figures 8-11 As shown, Figure 8 and Figure 10 Schematic diagrams of two pixel structures of the array substrate. Figure 9 for Figure 8 Schematic diagram of the local structure in Figure 11 for Figure 10 The partial structural diagram in FIG. 1 shows an array substrate including a display area and a non-display area surrounding the display area; the display area includes: a plurality of pixel units P distributed in an array, and a plurality of gate lines (G(1), G(2), G(3) ... G(2n), where n is a natural number) extending along a row direction X and arranged along a column direction Y; the non-display area includes a first gate driving circuit 100 and a second gate driving circuit 200 located at both ends of the gate lines;

[0048] The plurality of gate lines include a plurality of first-type gate lines (G(1), G(3), G(5) ... G(2n-1)) and a plurality of second-type gate lines (G(2), G(4), G(6) ... G(2n)), each of the first-type gate lines is electrically connected to the first gate driving circuit 100, and each of the second-type gate lines is electrically connected to the second gate driving circuit 200;

[0049] The pixel units in the same row are alternately electrically connected to the first type of gate line and the second type of gate line, for example, the pixel units P in the first row are alternately electrically connected to the first type of gate line G(1) and the second type of gate line G(2), the pixel units P in the second row are alternately electrically connected to the first type of gate line G(3) and the second type of gate line G(4), and the pixel units P in the third row are alternately electrically connected to the first type of gate line G(5) and the second type of gate line G(6); the pixel units in different rows are electrically connected to different first type of gate lines and different second type of gate lines, for example, the pixel units P in the first row are electrically connected to the first type of gate line G(1), the pixel units P in the second row are electrically connected to the first type of gate line G(3), and the pixel units P in the first row are alternately electrically connected to the second type of gate line G (2) is electrically connected, the second row of pixel units P is electrically connected to the second type of gate line G(4); and the pixel units located in the same column in adjacent rows of pixel units are electrically connected to different types of gate lines, for example, the first column of pixel units P in the first row of pixel units P is electrically connected to the second type of gate line G(2), and the first column of pixel units P in the second row of pixel units P is electrically connected to the first type of gate line G(3); for example, the first column of pixel units P in the second row of pixel units P is electrically connected to the first type of gate line G(3), and the first column of pixel units P in the third row of pixel units P is electrically connected to the second type of gate line G(6).

[0050] Specifically, the pixel units in the same row in the embodiment of the present invention are alternately electrically connected to the first type of gate lines and the second type of gate lines, that is, the pixel structure of the present invention adopts a dual gate structure. The dual gate structure can reduce the total number of driver chips (ICs) used to drive the data lines, and is particularly suitable for high PPI products.

[0051] The above-mentioned array substrate provided by the embodiment of the present invention adopts an odd-even cross single drive design for a dual gate product, and pixel units in the same row are alternately electrically connected to the first type of gate line and the second type of gate line, pixel units in different rows are electrically connected to different first type of gate lines and different second type of gate lines, and pixel units in the same column of adjacent rows are electrically connected to different types of gate lines. In this way, the pixel units can be driven in a column inversion manner, so that the brightness of pixel units in the same row is alternately set to bright and dark, and the brightness of pixel units in the same column of adjacent rows is different. For example, the brightness of pixel units in the first row is alternately set to bright, dark, bright, and dark, the brightness of pixel units in the second row is alternately set to dark, bright, dark, and bright, the brightness of pixel units in the third row is alternately set to bright, dark, bright, and dark, and the brightness of pixel units in the fourth row is alternately set to dark, bright, dark, and bright. Therefore, the overall brightness of the display area is uniform and no vertical stripes are generated. Therefore, the pixel structure design provided by the embodiment of the present invention can improve the brightness of the pixel units. Figure 5 and Figure 7 The pixel structure shown is prone to problems such as blue on the left and red on the right, and vertical stripes.

[0052] It should be noted that the single-drive design means that only one end of a gate line is electrically connected to the gate drive circuit (GOA), and the odd-even cross single-drive design means that all odd-numbered rows of gate lines are electrically connected to the same GOA, and all even-numbered rows of gate lines are electrically connected to another GOA.

[0053] In a specific implementation, in the above array substrate provided in the embodiment of the present invention, if Figures 8-11 As shown, at least one column of pixel units constitutes a group; optionally, Figure 8 and Figure 9 As shown, each column of pixel units is a group, for example, the first column of pixel units P is a group, the second column of pixel units P is a group, the third column of pixel units P is a group, ...; Figure 10 and Figure 11 As shown, every two adjacent columns of pixel units form a group, for example, the first and second columns of pixel units P form a group, the third and fourth columns of pixel units P form a group, the fifth and sixth columns of pixel units P form a group, ...; wherein,

[0054] For the pixel units in odd rows, the pixel units in the even array of the same row are electrically connected to the first type of gate lines, and the pixel units in the odd array of the same row are electrically connected to the second type of gate lines; specifically, Figure 8 and Figure 9 As shown, for example, the even-group pixel units (second column, fourth column, sixth column...) in the first row of pixel units P are electrically connected to the first type of gate line G(1), and the odd-group pixel units (first column, third column, fifth column...) in the first row of pixel units P are electrically connected to the second type of gate line G(2); for example, the even-group pixel units (second column, fourth column, sixth column...) in the third row of pixel units P are electrically connected to the first type of gate line G(5), and the odd-group pixel units (first column, third column, fifth column...) in the third row of pixel units P are electrically connected to the second type of gate line G(6); Figure 10 and Figure 11 As shown, for example, the even-group pixel units (the third and fourth columns, the seventh and eighth columns, ...) in the first row of pixel units P are electrically connected to the first type of gate line G (1), and the odd-group pixel units (the first and second columns, the fifth and sixth columns, ...) in the first row of pixel units P are electrically connected to the second type of gate line G (2); for example, the even-group pixel units (the third and fourth columns, the seventh and eighth columns, ...) in the third row of pixel units P are electrically connected to the first type of gate line G (5), and the odd-group pixel units (the first and second columns, the fifth and sixth columns, ...) in the third row of pixel units P are electrically connected to the second type of gate line G (6);

[0055] For pixel units in even rows, the pixel units in the odd array of the same row are electrically connected to the first type of gate lines, and the pixel units in the even array of the same row are electrically connected to the second type of gate lines; specifically, Figure 8 and Figure 9 As shown, for example, the odd-group pixel units (first column, third column, fifth column...) in the second row of pixel units P are electrically connected to the first type of gate line G (3), and the even-group pixel units (second column, fourth column, sixth column...) in the second row of pixel units P are electrically connected to the second type of gate line G (4); for example, the odd-group pixel units (first column, third column, fifth column...) in the fourth row of pixel units P are electrically connected to the first type of gate line G (7), and the even-group pixel units (second column, fourth column, sixth column...) in the fourth row of pixel units P are electrically connected to the second type of gate line G (8); Figure 10 and Figure 11 As shown, for example, the odd-group pixel units (the first and second columns, the fifth and sixth columns...) in the second row of pixel units P are electrically connected to the first type of gate line G(3), and the even-group pixel units (the third and fourth columns, the seventh and eighth columns...) in the second row of pixel units P are electrically connected to the second type of gate line G(4); for example, the odd-group pixel units (the first and second columns, the fifth and sixth columns...) in the fourth row of pixel units P are electrically connected to the first type of gate line G(7), and the even-group pixel units (the third and fourth columns, the seventh and eighth columns...) in the fourth row of pixel units P are electrically connected to the second type of gate line G(8).

[0056] Specifically, according to Figure 8 The pixel structure shown adopts an odd-even cross single drive design, for example, Figure 8 The first group of pixel units P in the first row (pixel units in the first column) are driven by the far-end G(2), and the ΔVp of the pixel units is small (the display brightness is brighter). The second group of pixel units P in the first row (pixel units in the second column) are driven by the near-end G(1), and the ΔVp of the pixel units is large (the display brightness is darker). Similarly, the pixel units P in the first row present an alternating display effect of bright and dark. For example Figure 8 The first group of pixel units P in the second row (the first column of pixel units) is driven by the proximal G(3), and the ΔVp of the pixel units is large (display brightness is darker). The second group of pixel units P in the second row (the second column of pixel units) is driven by the distal G(4), and the ΔVp of the pixel units is small (display brightness is brighter). Similarly, the pixel units P in the second row present a display effect of alternating dark and bright. Figure 12 As shown, Figure 12 for Figure 8 The corresponding display area display effect diagram, that is, each row of pixels is designed with a bright and dark cross design in units of one pixel, and the next row is designed with a dark and bright cross design, so the overall display brightness of the panel is uniform and no vertical stripes are produced. Figure 8 The pixel structure shown can improve the issues of left-cyan and right-red pixels and vertical stripes.

[0057] Specifically, according to Figure 10The pixel structure shown adopts an odd-even cross single drive design, for example, Figure 10 The first group of pixel units P in the first row (pixel units in the first and second columns) are driven by G(2) at the far end, and the ΔVp of these pixel units is small (the display brightness is brighter). The second group of pixel units P in the first row (pixel units in the third and fourth columns) are driven by G(1) at the near end, and the ΔVp of these pixel units is large (the display brightness is darker). Similarly, the pixel units P in the first row present an alternating display effect of bright and dark. For example Figure 10 The first group of pixel units P in the second row (pixel units in the first and second columns) are driven by G(3) at the near end, and the ΔVp of the pixel units is large (display brightness is darker). The second group of pixel units P in the second row (pixel units in the third and fourth columns) are driven by G(4) at the far end, and the ΔVp of the pixel units is small (display brightness is brighter). Similarly, the pixel units P in the second row present a display effect of alternating dark and bright. Figure 13 As shown, Figure 13 for Figure 10 The corresponding display area display effect diagram, that is, the pixels are designed with two pixel units in each row for bright and dark alternation, and the next row is designed with dark and bright alternation, so the overall display brightness of the panel is uniform and no vertical stripes are produced. Figure 10 The pixel structure shown can improve the issues of left-cyan and right-red pixels and vertical stripes.

[0058] It should be noted that the embodiments of the present invention Figure 8 Each column of pixel units is a group. Figure 10 In the example above, two adjacent columns of pixel units are grouped together. Of course, in a specific implementation, three or more adjacent columns of pixel units may be grouped together, and the present invention is not limited thereto.

[0059] In a specific implementation, in the above array substrate provided in the embodiment of the present invention, if Figure 14 and Figure 15 As shown, at least one column of pixel units constitutes a group; optionally, Figure 14 As shown, each column of pixel units is a group; Figure 15 As shown, every two adjacent columns of pixel units form a group; wherein,

[0060] For the pixel units in odd rows, the pixel units in the odd array of the same row are electrically connected to the first type of gate lines, and the pixel units in the even array of the same row are electrically connected to the second type of gate lines; specifically, Figure 14 As shown, for example, the odd-group pixel units (first column, third column, fifth column...) in the first row of pixel units P are electrically connected to the first type of gate line G(1), and the even-group pixel units (second column, fourth column, sixth column...) in the first row of pixel units P are electrically connected to the second type of gate line G(2), and so on; Figure 15As shown, for example, the odd-group pixel units (the first and second columns, the fifth and sixth columns, ...) in the first row of pixel units P are electrically connected to the first type of gate line G(1), and the even-group pixel units (the third and fourth columns, the seventh and eighth columns, ...) in the first row of pixel units P are electrically connected to the second type of gate line G(2), and so on;

[0061] For pixel units in even rows, the pixel units in the even array of the same row are electrically connected to the first type of gate lines, and the pixel units in the odd array of the same row are electrically connected to the second type of gate lines; specifically, Figure 14 As shown, for example, the even-group pixel units (second column, fourth column, sixth column...) in the second row of pixel units P are electrically connected to the first type of gate line G (3), the odd-group pixel units (first column, third column, fifth column...) in the second row of pixel units P are electrically connected to the second type of gate line G (4), and so on; Figure 15 As shown, for example, the even-group pixel units (the third and fourth columns, the seventh and eighth columns, ...) in the second row of pixel units P are electrically connected to the first-type gate line G (3), the odd-group pixel units (the first and second columns, the fifth and sixth columns, ...) in the second row of pixel units P are electrically connected to the second-type gate line G (4), and so on.

[0062] It should be noted that Figure 14 Can be achieved with Figure 8 The same display effect, Figure 14 and Figure 8 The difference lies in whether the odd-numbered arrays are electrically connected to the first-type gate lines or the second-type gate lines, and whether the even-numbered arrays are electrically connected to the first-type gate lines or the second-type gate lines. Figure 15 Can be achieved with Figure 10 The same display effect, Figure 15 and Figure 10 The difference lies in whether the odd-numbered arrays are electrically connected to the first or second type of gate lines, and whether the even-numbered arrays are electrically connected to the first or second type of gate lines. However, the common point is that each row of pixel units is alternately electrically connected to the first and second type of gate lines, and the connection method of the next row is the opposite of that of the previous row.

[0063] It should be noted that for the odd-even crossover single-drive design, the panel is divided into two halves. For the left half, the first type of gate lines belong to the near-end drive, while for the right half, the first type of gate lines belong to the far-end drive; for the left half, the second type of gate lines belong to the far-end drive, while for the right half, the second type of gate lines belong to the near-end drive; therefore, the display brightness of the left half of the panel is symmetrical with that of the right half.

[0064] In a specific implementation, in the above array substrate provided by an embodiment of the present invention, the first type of gate lines and the second type of gate lines electrically connected to the same pixel unit are respectively located on both sides of the pixel unit; specifically, Figures 8-11、 Figure 14 and Figure 15 As shown, the first-class gate line G(1) and the second-class gate line G(2) electrically connected to the first row of pixel units P are respectively located on both sides of the first row of pixel units P, the first-class gate line G(3) and the second-class gate line G(4) electrically connected to the second row of pixel units P are respectively located on both sides of the second row of pixel units P, and the first-class gate line G(5) and the second-class gate line G(6) electrically connected to the third row of pixel units P are respectively located on both sides of the third row of pixel units P, that is, there are two gate lines between two adjacent rows of pixel units, forming a dual gate product.

[0065] Of course, in a specific implementation, in the above array substrate provided by the embodiment of the present invention, the first type of gate lines and the second type of gate lines electrically connected to the same pixel units may also be located on the same side of the pixel units; specifically, Figures 8-11 、 Figure 14 and Figure 15 The first type of gate line and the second type of gate line electrically connected to the same row of pixel units can be located on the upper side or the lower side of the pixel units. For example, the first type of gate line G(1) and the second type of gate line G(2) electrically connected to the first row of pixel units P can be located on the upper side of the first row of pixel units P at the same time, and the first type of gate line G(3) and the second type of gate line G(4) electrically connected to the second row of pixel units P can be located on the upper side of the second row of pixel units P at the same time. Of course, the first type of gate line G(1) and the second type of gate line G(2) electrically connected to the first row of pixel units P can also be located on the lower side of the first row of pixel units P at the same time, and the first type of gate line G(3) and the second type of gate line G(4) electrically connected to the second row of pixel units P can be located on the lower side of the second row of pixel units P at the same time; and so on.

[0066] In a specific implementation, in the above array substrate provided in the embodiment of the present invention, if Figures 8-11 、 Figure 14 and Figure 15 As shown, the display area further includes a plurality of data lines (D1, D2, D3, ...) extending along the column direction Y and arranged along the row direction X. The plurality of data lines and the plurality of gate lines define a plurality of pixel units P;

[0067] Each pixel unit P may include multiple sub-pixels of different colors. For example, each pixel unit P includes a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B. The sub-pixels in the same column have the same color. For example, a column of red sub-pixels R, a column of green sub-pixels G, and a column of blue sub-pixels B are arranged in sequence. The sub-pixels in the same column are electrically connected to the same data line, and the sub-pixels in different columns are electrically connected to different data lines. For example, the red sub-pixels R in the first column are all electrically connected to the data line D1, the green sub-pixels G in the second column are all electrically connected to the data line D2, and the blue sub-pixels B in the third column are all electrically connected to the data line D3.

[0068] The non-display area also includes a driver chip (e.g., IC1 and IC2), which has a plurality of pads (not shown), and the first ends of the data lines corresponding to at least two columns of sub-pixels with the same polarity and the same color are electrically connected to the same pad. Specifically, Figure 8 and Figure 10 The sub-pixels can adopt a column inversion driving method, that is, the polarity of the sub-pixels in the same column is the same, and the polarity of the sub-pixels in adjacent columns is different. For example, the red sub-pixels R in the first column are positive, the green sub-pixels G in the second column are negative, the blue sub-pixels B in the third column are positive, the red sub-pixels R in the fourth column are negative, the green sub-pixels G in the fifth column are positive, and the blue sub-pixels B in the sixth column are negative, that is, the positive and negative polarities are arranged alternately. By electrically connecting the first ends of the data lines corresponding to at least two columns of sub-pixels with the same polarity and the same color to the same pad, the number of driving chips can be saved, the cost can be reduced, and the binding defects can be reduced.

[0069] Alternatively, as Figures 8-11 、 Figure 14 and Figure 15 As shown, the first end of the data line corresponding to the sub-pixel in the Nth column is electrically connected to the first end of the data line corresponding to the sub-pixel in the N+6nth column, where N and n are both natural numbers. For example, if N and n are both 1, the first end of the data line D1 corresponding to the sub-pixel in the first column (R) is electrically connected to the first end of the data line D7 corresponding to the sub-pixel in the seventh column (R), the first end of the data line D2 corresponding to the sub-pixel in the second column (R) is electrically connected to the first end of the data line D8 corresponding to the sub-pixel in the eighth column (R), and the first end of the data line D3 corresponding to the sub-pixel in the third column (R) is electrically connected to the first end of the data line D9 corresponding to the sub-pixel in the ninth column (R).

[0070] Of course, n is not limited to 1. For example, N is 1 and n is 2, that is, the first end of the data line D1 corresponding to the first column of sub-pixels (R) is electrically connected to the first end of the data line D13 corresponding to the thirteenth column of sub-pixels (R), the first end of the data line D2 corresponding to the second column of sub-pixels (R) is electrically connected to the first end of the data line D14 corresponding to the fourteenth column of sub-pixels (R), the first end of the data line D3 corresponding to the third column of sub-pixels (R) is electrically connected to the first end of the data line D15 corresponding to the fifteenth column of sub-pixels (R); and so on.

[0071] It should be noted that if Figure 8 、 Figure 10 、 Figure 14 and Figure 15 As shown, two driver chips (IC1 and IC2) are used as an example, but the present invention is not limited thereto. One or more driver chips may be selected according to the size of the panel. Of course, the dual-gate design provided in the embodiment of the present invention may reduce the number of driver chips.

[0072] In a specific implementation, in the above array substrate provided in the embodiment of the present invention, if Figure 8 、 Figure 10 、 Figure 14 and Figure 15 As shown, the second ends of the data lines electrically connected to the same pad are electrically connected, for example, the second end of the data line D1 is electrically connected to the second end of the data line D7, the second end of the data line D2 is electrically connected to the second end of the data line D8, and the second end of the data line D3 is electrically connected to the second end of the data line D9. This can reduce the resistance of the data lines and improve the display effect.

[0073] In a specific implementation, in the above array substrate provided in the embodiment of the present invention, if Figures 8-11 、 Figure 14 and Figure 15 As shown, each sub-pixel includes a transistor T and a pixel electrode 300, the gate of the transistor T is electrically connected to the corresponding gate line, the first electrode of the transistor T is electrically connected to the corresponding data line, and the second electrode of the transistor T is electrically connected to the pixel electrode 300. Optionally, the gate of the transistor T is integrally provided with the gate line, the first electrode of the transistor T is integrally provided with the data line, and the second electrode of the transistor T is partially electrically connected to the pixel electrode.

[0074] Optionally, the transistor T may be a P-type transistor or an N-type transistor, and the transistor T may be a bottom-gate transistor, a top-gate transistor, or a dual-gate transistor, etc., which are not limited here. In the present invention, the first electrode of the transistor T may be a source electrode, and the second electrode may be a drain electrode, or the first electrode of the transistor T may be a drain electrode, and the second electrode may be a source electrode, which are not limited here. The transistor T also includes an active layer, and the material of the active layer may be amorphous silicon (a-Si), polycrystalline silicon (poly), oxide (Oxide, such as indium gallium zinc oxide IGZO), etc. Optionally, a gate insulating layer (GI) may be provided between the layer where the gate of the transistor T is located and the active layer, and the material of the gate insulating layer may be at least one of inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.

[0075] Optionally, the material of the pixel electrode includes transparent conductive materials such as indium tin oxide (ITO) and indium zinc oxide (IZO).

[0076] Optionally, the material of the gate line may include metals such as molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), and nickel (Ni), and the gate line may be a single-layer structure or a stacked-layer structure, for example, the gate line is a single-layer structure composed of a molybdenum metal layer.

[0077] Optionally, the material of the data line may include metals such as molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), and nickel (Ni), and the data line may be a single-layer structure or a stacked-layer structure. For example, the data line 104 may be a stacked-layer structure consisting of a titanium metal layer / aluminum metal layer / titanium metal layer.

[0078] In specific implementation, Figure 8 、 Figure 10 、 Figure 14 and Figure 15 As shown, the first gate drive circuit 100 may include a plurality of cascaded first shift registers, and the second gate drive circuit 200 may include a plurality of cascaded second shift registers. The first scanning voltage output end of each first shift register 100 is electrically connected to the corresponding first type of gate line, and the second scanning voltage output end of each second shift register 200 is electrically connected to the corresponding second type of gate line. The first gate drive circuit 100 and the second gate drive circuit 200 alternately output scanning voltages to achieve row-by-row scanning of the gate lines.

[0079] Optionally, the structure of the shift register in the first gate driving circuit 100 and the second gate driving circuit 200 is the same as that in the related art, and can realize the signal shifting function. The present invention does not give a detailed example of the structure of the shift register.

[0080] It should be noted that other essential components of the array substrate are well understood by those skilled in the art and are not described in detail herein and should not be construed as limiting the present invention.

[0081] Based on the same inventive concept, an embodiment of the present invention provides a driving method for the array substrate, comprising:

[0082] In one frame time, scanning voltage is applied to the gate lines row by row, and data voltage is applied to the pixel units in a column-inverted manner, so that the brightness of the pixel units in the same row is alternately set to bright and dark, and the brightness of the pixel units in the same column in adjacent rows is different.

[0083] See also Figure 8 and Figure 10, the same row of pixel units corresponds to two gate line drivers, and when both gate lines are turned on, all pixel electrodes 300 in the first row will be written with data voltages (equivalent to the sub-pixels including the pixel electrodes 300 being lit). Specifically, when the first type of gate line G (1) is loaded with a scanning voltage, the data voltage on the data line electrically connected to the even group of pixel units P is written into the pixel electrodes 300 of the even group of pixel units P; when the second type of gate line G (2) is loaded with a scanning voltage, the data voltage on the data line electrically connected to the odd group of pixel units P is written into the pixel electrodes 300 of the odd group of pixel units P; when the first type of gate line G (3) is loaded with a scanning voltage, the data voltage on the data line electrically connected to the odd group of pixel units P is written into the pixel electrodes 300 of the even group of pixel units P; when the second type of gate line G (4) is loaded with a scanning voltage, the data voltage on the data line electrically connected to the even group of pixel units P is written into the pixel electrodes 300 of the odd group of pixel units P; in this way, the polarity of the data voltage loaded on the same data line is the same, and the polarity of the data voltage loaded on adjacent data lines is opposite. In this way, within one frame time, the scanning voltage is applied to the gate lines row by row, and the data voltage is applied to the pixel units in a column-inverted manner, so that the brightness of the pixel units in the same row is alternately set to bright and dark, and the brightness of the pixel units in the same column in adjacent rows is different. The overall display brightness of the panel is as follows: Figure 12 and Figure 13 As shown, the overall display brightness of the panel is uniform and no vertical stripes are produced.

[0084] Based on the same inventive concept, an embodiment of the present invention provides a display device, such as Figure 16 As shown, it includes: an array substrate 001 and an opposite substrate 002 arranged opposite to each other, a liquid crystal layer 003 located between the array substrate 001 and the opposite substrate 002, and a backlight module 004 located on the light incident side of the array substrate 001; wherein the array substrate 001 is provided in an embodiment of the present invention Figure 8 and Figure 10 Since the principle of the display device to solve the problem is similar to that of the above array substrate, the implementation of the display device can refer to the embodiment of the above array substrate, and the repeated parts will not be repeated.

[0085] In some embodiments, in the above-mentioned display device provided by the embodiment of the present invention, the backlight module 004 can be a direct-type backlight module or an edge-type backlight module. Optionally, the edge-type backlight module may include a light bar, a stacked reflective sheet, a light guide plate, a diffuser, a prism group, etc., and the light bar is located on one side of the thickness direction of the light guide plate. The direct-type backlight module may include a matrix light source, a reflective sheet, a diffuser and a brightening film stacked on the light-emitting side of the matrix light source, etc., and the reflective sheet includes an opening arranged directly opposite to the position of each lamp bead in the matrix light source. The lamp beads in the light bar and the lamp beads in the matrix light source can be light-emitting diodes (LEDs), such as micro light-emitting diodes (Mini LED, Micro LED, etc.).

[0086] Submillimeter or even micron-scale micro-LEDs are self-luminous devices, just like organic light-emitting diodes (OLEDs). Like organic light-emitting diodes, they have a series of advantages such as high brightness, ultra-low latency, and ultra-large viewing angles. And because inorganic light-emitting diodes emit light based on metal semiconductors with more stable properties and lower resistance, they have the advantages of lower power consumption, greater resistance to high and low temperatures, and longer service life compared to organic light-emitting diodes that emit light based on organic matter. And when micro-LEDs are used as backlight sources, more precise dynamic backlight effects can be achieved. While effectively improving screen brightness and contrast, they can also solve the glare phenomenon caused by traditional dynamic backlighting between bright and dark areas of the screen, thereby optimizing the visual experience.

[0087] In some embodiments, the above-mentioned display device provided by the embodiments of the present invention can be: a projector, a 3D printer, a virtual reality device, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, a smart watch, a fitness wristband, a personal digital assistant, and any other product or component with a display function.

[0088] An embodiment of the present invention provides an array substrate, a driving method thereof, and a display device. By adopting an odd-even cross single drive design for a dual-gate product, pixel units in the same row are alternately electrically connected to a first type of gate line and a second type of gate line, pixel units in different rows are electrically connected to different first types of gate lines and different second types of gate lines, and pixel units in adjacent rows of pixel units located in the same column are electrically connected to different types of gate lines. In this way, the pixel units can be driven in a column inversion manner, so that the brightness of pixel units in the same row is alternately set to bright and dark, and the brightness of pixel units in adjacent rows of pixel units located in the same column is different, so that the overall brightness of the display area can be uniform, and no vertical stripes will be generated. Therefore, the pixel structure design provided by the embodiment of the present invention can improve the problem that the pixel structure in the related art is prone to green on the left and red on the right, and vertical stripes are undesirable.

[0089] Although the present invention has described preferred embodiments, it should be understood that those skilled in the art may make various changes and modifications to the embodiments without departing from the spirit and scope of the embodiments of the present invention. Thus, if such changes and modifications fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. An array substrate, characterized in that: The invention comprises a display area and a non-display area surrounding the display area; the display area comprises: a plurality of pixel units distributed in an array, and a plurality of gate lines extending along the row direction and arranged along the column direction; the non-display area comprises a first gate driving circuit and a second gate driving circuit located at both ends of the gate lines; the display area further comprises a plurality of data lines extending along the column direction and arranged along the row direction, the plurality of data lines and the plurality of gate lines defining the plurality of pixel units; each of the pixel units comprises a plurality of sub-pixels of different colors, and the colors of the sub-pixels in the same column are the same; the sub-pixels in the same column are electrically connected to the same data line, and the sub-pixels in different columns are electrically connected to different data lines; wherein the non-display area further comprises a driving chip, the driving chip having a plurality of pads, and the first ends of the data lines corresponding to the sub-pixels of the same polarity and the same color in at least two columns are electrically connected to the same pad; The plurality of gate lines include a plurality of first-type gate lines and a plurality of second-type gate lines, each of the first-type gate lines is electrically connected to the first gate driving circuit, and each of the second-type gate lines is electrically connected to the second gate driving circuit; The pixel units in the same row are alternately electrically connected to the first type of gate lines and the second type of gate lines, the pixel units in different rows are electrically connected to different first type of gate lines and different second type of gate lines, and the pixel units in the same column in adjacent rows are electrically connected to different types of gate lines.

2. The array substrate according to claim 1, wherein: At least one column of the pixel units constitutes a group; wherein, For the pixel units in odd rows, the pixel units in an even group of the same row are electrically connected to the first type of gate lines, and the pixel units in an odd group of the same row are electrically connected to the second type of gate lines; For the pixel units in the even rows, the pixel units in the odd array of the same row are electrically connected to the first type of gate lines, and the pixel units in the even array of the same row are electrically connected to the second type of gate lines.

3. The array substrate according to claim 1, wherein: At least one column of the pixel units constitutes a group; wherein, For the pixel units in odd rows, the pixel units in an odd group of the same row are electrically connected to the first type of gate lines, and the pixel units in an even group of the same row are electrically connected to the second type of gate lines; For the pixel units in even rows, the pixel units in an even array in the same row are electrically connected to the first type of gate lines, and the pixel units in an odd array in the same row are electrically connected to the second type of gate lines.

4. The array substrate according to claim 2 or 3, wherein: Each column of pixel units forms a group, or each two adjacent columns of pixel units form a group.

5. The array substrate according to claim 1, wherein: The first type of gate lines and the second type of gate lines electrically connected to the pixel units in the same row are respectively located on two sides of the pixel units; Alternatively, the first-type gate line and the second-type gate line electrically connected to the pixel unit are located on the same side of the pixel unit.

6. The array substrate according to claim 1, wherein: The first end of the data line corresponding to the sub-pixel in the Nth column is electrically connected to the first end of the data line corresponding to the sub-pixel in the N+6nth column, where N and n are both natural numbers.

7. The array substrate according to claim 1, wherein: The second ends of the data lines electrically connected to the same pad are electrically connected.

8. A display device, characterized in that: include: An array substrate and an opposite substrate are arranged opposite to each other, a liquid crystal layer is located between the array substrate and the opposite substrate, and a backlight module is located on the light incident side of the array substrate; wherein the array substrate is the array substrate according to any one of claims 1 to 7.

9. A driving method for driving the array substrate according to any one of claims 1 to 7, characterized in that: include: In one frame time, scanning voltage is loaded on the gate lines row by row, and data voltage is loaded on the pixel units in a column-inverted manner, so that the brightness of the pixel units in the same row is alternately set to bright and dark, and the brightness of the pixel units in the same column in adjacent rows is different.

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