A memory power consumption prediction method based on 3D-NUMA architecture

Abstract

The application belongs to the technical field of memory power consumption prediction, and discloses a memory power consumption prediction method based on a 3D- NUMA architecture. When the memory power consumption is predicted, the present situation and future development trend of the computer architecture are considered, and a memory power consumption prediction method based on the 3D- NUMA architecture is provided. The access rate of the memory bank is taken as the input, the power consumption of the memory bank is taken as the output, and the power model of the memory bank is established between the two. Based on the Non-Uniform Access (non-uniform access) of the NUMA, according to the characteristics that the access delay of the core is different when the core accesses the memory bank at different distances, the new access rate can be obtained by correcting the access delay and the voltage and frequency of the memory bank and the core, and then the power model is used to predict the power consumption of the new memory bank.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of memory power consumption prediction, and particularly relates to a memory power consumption prediction method based on a 3D-NUMA architecture. BACKGROUND

[0002] In modern processor structures, processor cores and memories work together, and with the increasing demand for computer performance, the limited interconnection line bandwidth gradually becomes a bottleneck that inhibits the development of computer performance, and the 3D stacked core-memory system and the NUMA architecture of non-uniform memory access can well solve this problem. However, due to the close stacking between the core and the memory layer, the power density of the core and the memory is significantly improved, and the energy consumed by the processor is finally converted into heat energy, so that the thermal coupling effect is also significantly increased. Therefore, the power consumption of the memory cannot be ignored at this time. In order to carry out the research smoothly, it is an important prerequisite for carrying out the experiment to obtain the power consumption information of the memory conveniently and quickly. Unlike obtaining performance data, the process of obtaining power consumption data is more complex, and the methods are more diverse. In view of the above problems, if an effective method for predicting the power consumption of the memory can be found, it can play a good reference role in the future research of 3D-NUMA architecture.

[0003] The 2D packaging technology commonly used in today's computers separately packages the multi-processor core and the memory on different chips, and then the processor core performs uniform memory access (UMA, Uniform Memory Access) on the memory through off-chip interconnection lines. With the development of technology, the number of CPU cores is increasing, and the limited bandwidth of the interconnection line gradually becomes the performance bottleneck of the 2D processor, and the 2.5D and 3D packaging core-memory system and the non-uniform memory access architecture (NUMA, Non-Uniform Memory Access) can well solve this problem. However, the closer vertical integration of the core and the memory into the same chip will significantly improve the power density of the processor and the memory.

[0004] Power consumption has always been a hot topic in the field of computer hardware. The increase in power density can affect the normal operation of the processor chip, restrict the further expansion of on-chip resources, increase the operating cost of the computing system, and affect the use effect of mobile devices. In traditional 2D flat design, the power consumption of the core is much higher than that of the memory, so the power consumption of the memory has not attracted much attention. With the gradual entry of 3D structure into people's field of vision, due to the high-density packaging technology, the power density is significantly improved compared to 2D structure, so the power consumption of the memory cannot be ignored at this time.

[0005] Compared with the traditional 2D flat design (Core with external 2D Uniform access memory), the 3D-NUMA architecture (Stacked architecture with core and 3D Non-uniform access memory) has many advantages, including reducing memory access latency, increasing memory bandwidth, and reducing energy consumption.

[0006] However, due to the tighter vertical stacking structure, the power density of the processor core (Cores) and the memory is significantly improved, and the converted heat cannot be effectively dissipated, which will cause serious thermal coupling effect, and thus related thermal problems (such as local hot spots, etc.) will be generated. In addition, since DRAM is very sensitive to high temperature and temperature change, the thermal problem of 3D stacking structure is more prominent compared to traditional 2D structure, and the power consumption of the memory cannot be ignored.

[0007] Therefore, in order to carry out research, it is an important prerequisite for the development of experiments to conveniently and quickly predict the power consumption information of the memory. Compared with obtaining performance data, the process of obtaining power consumption data is more complex and the methods are more diverse. Compared with obtaining the power consumption data of the processor, it is more difficult to obtain the power consumption data of the memory. For the power consumption of the processor, it can be obtained through simulator-based research, such as through Wattch, McPAT, MacSim, etc. Simulators can also obtain it through measurement-based research, such as directly using PowerMon2 and other power consumption measurement devices to measure the power consumption of the processor. For the acquisition of memory power consumption, especially for the prediction of memory power consumption in 3D-NUMA architecture, there is no unified solution in the industry.

[0008] In view of the above problems, if an effective method for predicting memory power consumption can be found, it can serve as a good reference in future research on 3D-NUMA architecture.

[0009] Through the above analysis, the problems and defects of the prior art are:

[0010] (1) Due to the closer vertical stack structure, the power consumption density of processor cores (Cores) and memory is significantly improved, and the converted heat cannot be effectively dissipated, thereby causing serious thermal coupling effect, and thereby causing related thermal problems (such as generating local hot spots, etc.).

[0011] (2) In addition, since DRAM is very sensitive to high temperature and temperature change, the thermal problem of 3D stack structure is more prominent than that of traditional 2D structure, and the power consumption of memory cannot be ignored.

[0012] (3) The prediction method of memory power consumption is not mature at present, especially for the core-memory system of such a novel 3D-NUMA architecture. SUMMARY

[0013] In view of the problems of the prior art, the present application provides a memory power consumption prediction method based on 3D-NUMA architecture.

[0014] The present application is implemented in this way, a memory power consumption prediction method based on 3D-NUMA architecture, comprising:

[0015] Step 1: According to the access rate of memory bank and the power consumption of memory bank, a power model of memory bank is established between the two;

[0016] Step 2: Run a benchmark, specify a core to access the nearest set of memory banks vertically stacked with it, and measure the access rate of the memory banks, while recording the access delay when accessing the set of memory banks;

[0017] Step 3: Based on the characteristics of Non-Uniform Access (Non-Uniform Access) of NUMA, when the core accesses memory banks of different distances, the access delay is different; Based on the new access delay and other key parameter information (V, f value of memory bank and core), the access delay of the memory bank is corrected;

[0018] Step four: send the access rate of the new memory bank into the power model of the previously established memory bank to predict the power consumption of the new memory bank.

[0019] Further, the power model of the memory bank is established between the access rate of the memory bank and the power consumption of the memory bank, the input of which is the access rate (read-write times per second) of the memory bank, and the output is the power consumption (watt) of the memory bank.

[0020] In combination with the technical solutions and the solved technical problems described above, the technical solutions to be protected by the application have the following advantages and positive effects:

[0021] First, in view of the technical problems existing in the prior art and the difficulty in solving the problems, the technical solutions to be protected by the application and the results and data obtained during the research and development process are closely combined to analyze in detail and profoundly how the technical solutions solve the technical problems and some creative technical effects brought after the problems are solved. The specific description is as follows:

[0022] When the memory power consumption is predicted, the present situation and the future development trend of the computer architecture are considered, a memory power consumption prediction method is proposed based on the 3D-NUMA architecture, the access rate of the memory bank is taken as the input, the power consumption of the memory bank is taken as the output, and the power model of the memory bank is established between the two. Based on the Non-Uniform Access (non-uniform access) of the NUMA architecture, according to the characteristics that the access delay of the core is different when accessing the memory bank of different distances, the new access rate can be obtained according to the access delay, the real-time voltage and frequency of the memory bank and the core, and then the power model is used to predict the power consumption of the new memory bank.

[0023] Second, from the perspective of the product or as a whole, the technical solutions to be protected by the application have the following technical effects and advantages:

[0024] The application considers the current situation and future development trend of computer architecture, and proposes a memory power consumption prediction method based on 3D-NUMA architecture.

[0025] Third, as the creative evidence of the invention claim, it is also reflected in the following important aspects:

[0026] (1) The expected income and commercial value of the technical scheme of the application after transformation are:

[0027] The application considers the current situation and future development trend of computer architecture, and proposes a memory power consumption prediction method based on 3D-NUMA architecture. The access rate of memory bank is taken as the input, and the power consumption of memory bank is taken as the output, and the power model of memory bank is established between the two. Based on the Non-Uniform Access (non-uniform access) of NUMA, according to the characteristics that the access delay of core is different when accessing memory banks of different distances, the new access rate can be corrected according to the access delay, the real-time voltage and frequency of memory bank and core, and then the power consumption of the new memory bank is predicted through the power model.

[0028] Based on the application scheme, in the future processor design and research of 3D-NUMA architecture, it can play a good design reference role, and to a certain extent, it can improve the chip yield problem caused by the power consumption of memory.

[0029] (2) The technical scheme of the application fills the domestic and foreign industry technical blank:

[0030] At present, there is no mature method for obtaining and predicting the power consumption of memory in 3D-NUMA architecture at home and abroad. The application innovatively establishes a power consumption prediction model according to limited parameters, which can quickly predict the power consumption of memory bank and provide real-time correction feedback mechanism, and to a certain extent, it also ensures the accuracy of the prediction under the premise of fast prediction.

[0031] (3) The technical scheme of the present application solves the technical problem that people have been eager to solve but have failed to obtain success:

[0032] With the increasing demand for computer performance, 3D architecture and NUMA architecture computers gradually into people's vision, those can be ignored problem, such as memory power consumption, can no longer be ignored. And there is no mature prediction method at home and abroad, the present application provides a fast prediction of memory bank power consumption method. BRIEF DESCRIPTION OF DRAWINGS

[0033] Figure 1 is the memory power consumption prediction method based on 3D-NUMA architecture provided by the embodiment of the present application.

[0034] Figure 2 is the memory power consumption prediction method based on 3D-NUMA architecture provided by the embodiment of the present application.

[0035] Figure 3 is the 3D-NUMA physical structure schematic diagram provided by the embodiment of the present application.

[0036] Figure 4 is the UMA, NUMA architecture schematic diagram provided by the embodiment of the present application. DETAILED DESCRIPTION

[0037] In order to make the purpose, technical scheme and advantages of the present application more clear, the following will be further described in detail. It should be understood that the specific embodiments described herein are only used to explain the present application, and are not used to limit the present application.

[0038] In order to make those skilled in the art fully understand how to realize the present application, this part is an explanatory embodiment of the technical scheme of the claims.

[0039] As shown in Figure 1 , 2 The present application provides a memory power consumption prediction method based on 3D-NUMA architecture, comprising the following steps:

[0040] S101, according to the access rate of memory bank (access rate) and the power consumption of memory bank, the power model of memory bank is established between the two;

[0041] S102, running a benchmark, specifying a core to access the nearest group of memory banks vertically stacked with it, and measuring the access rate of the memory bank, while recording the access delay when accessing the group of memory banks;

[0042] For example, take Core1 as an example, specify Core1 to access the nearest group of Memory banks vertically stacked with it (assuming to access Memory bank-1), record the access rate and access delay of Core1 when accessing Memory bank-1. Figure 3 For example, take Core1 as an example, specify Core1 to access the nearest group of Memory banks vertically stacked with it (assuming to access Memory bank-1), record the access rate and access delay of Core1 when accessing Memory bank-1.

[0043] S103, based on the characteristics of Non-Uniform Access (Non-Uniform Access) of NUMA, when a core accesses memory banks of different distances, the access delay is different; based on the new access delay and some other key parameter information (V, f value of memory bank and core) to correct the access delay of the memory bank;

[0044] Figure 4 NUMA and UMA architectures are described in general.

[0045] S104, send the new memory bank access rate into the previously established memory bank power model to predict the power consumption of the new memory bank.

[0046] The application provides a memory bank power model established between the access rate of the memory bank and the power consumption of the memory bank, which takes the access rate of the memory bank (read / write times per second) as input and takes the power consumption of the memory bank (watt) as output.

[0047] The application provides a memory bank power model established between the access rate of the memory bank and the power consumption of the memory bank, which takes the access rate of the memory bank (read / write times per second) as input and takes the power consumption of the memory bank (watt) as output.

[0048] In order to prove the creativity and technical value of the technical scheme of the application, this part is an application embodiment of the technical scheme of the claim on a specific product or related technology.

[0049] The present application considers the current situation and future development trend of computer architecture when performing memory power consumption prediction, and proposes a memory power consumption prediction method based on 3D-NUMA architecture.

[0050] It should be noted that the embodiments of the present application can be realized by hardware, software or a combination of software and hardware. The hardware part can be realized by special logic; the software part can be stored in a memory and executed by a suitable instruction execution system, such as a microprocessor or a specially designed hardware. Those skilled in the art can understand that the above-mentioned devices and methods can be realized by computer executable instructions and / or included in processor control code, such as carrier media, such as magnetic disk, CD or DVD-ROM, programmable memory, such as read-only memory (firmware), or data carrier, such as optical or electronic signal carrier. The device and its modules of the present application can be realized by hardware circuit, such as ultra-large scale integrated circuit or gate array, semiconductor, such as logic chip, transistor, or programmable hardware device, such as field programmable gate array, programmable logic device, etc., can also be realized by software executed by various types of processors, and can also be realized by the combination of the above hardware circuit and software, such as firmware.

[0051] The embodiments of the present application have achieved some positive effects in research and development or use, and indeed have great advantages compared with the prior art. The following content is described in combination with the data and graphs of the test process.

[0052] The present application considers the current situation and future development trend of computer architecture when performing memory power consumption prediction, and proposes a memory power consumption prediction method based on 3D-NUMA architecture. The access rate of memory bank is input, and the power consumption of memory bank is output, and the power model of memory bank is established between the two. Based on the Non-Uniform Access of NUMA, according to the different characteristics of the access delay of the core when accessing memory banks of different distances, the new access rate can be corrected according to the access delay and the real-time voltage and frequency of the memory bank and the core, and then the power model is used to predict the power consumption of the new memory bank.

[0053] Since the 3D-NUMA architecture is not currently a mainstream processor architecture, but it can be predicted that with the development of technology and the increasing demand for computer performance, processors of this architecture will certainly become mainstream in the future. At present, there is no mature method for predicting and obtaining the memory power consumption of this architecture at home and abroad, but based on the theoretical analysis of this architecture, it can be judged that the scheme of the present application can provide fast prediction of the memory bank, and the V / f value of the core / memory bank is corrected in real time. Such a feedback mechanism also ensures the accuracy of the prediction to a certain extent.

[0054] The above is only a specific embodiment of the present application, but the protection scope of the present application is not limited thereto. Any modification, equivalent replacement and improvement made by any person skilled in the art within the technical range disclosed by the present application, as long as it is within the spirit and principles of the present application, should be covered within the protection scope of the present application.

Claims

1. A memory power consumption prediction method based on a 3D-NUMA architecture, characterized in that, The memory power consumption prediction method based on the 3D-NUMA architecture comprises the following steps: Step one: a power model of the memory bank is established between the access rate of the memory bank and the power consumption of the memory bank; Step two: a benchmark is run, a core is designated to access a nearest set of memory banks vertically stacked with the core, the access rate of the memory bank is measured, and the access delay when accessing the set of memory banks is recorded; Step three: based on the non-uniform access characteristic of NUMA, the access delay of the core when accessing memory banks of different distances is different; the access delay of the memory bank is corrected based on the new access delay and other key parameter information, the key parameter information is the voltage and frequency values of the memory bank and the core; the new access rate is corrected through the new access delay and the voltage and frequency values of the memory bank and the core, and then the power consumption of the memory bank is predicted through the previously established power model of the memory bank; Step four: the new access rate of the memory bank is sent into the previously established power model of the memory bank to predict the power consumption of the new memory bank.

2. The method of claim 1, wherein the 3D-NUMA based memory power prediction method is characterized by, The power model of the memory bank is established between the access rate of the memory bank and the power consumption of the memory bank, the input is the access rate of the memory bank, and the output is the power consumption of the memory bank.

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