A data packet transmission method for network on chip and rapidio device
By defining the data transmission format and NWRITE packet format between the on-chip network and RapidIO devices, the problems of high packet transmission latency and low efficiency are solved, achieving efficient data transmission and supporting rapid expansion and integration of devices such as digital signal processors.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- 58TH RES INST OF CETC
- Filing Date
- 2023-01-10
- Publication Date
- 2026-05-15
AI Technical Summary
The RapidIO protocol suffers from high packet transmission latency and low transmission efficiency, especially when reading and writing large amounts of data, which requires splitting the data into multiple requests, leading to a decrease in system performance.
It specifies the data transmission format in the on-chip network and the AXI request data payload format received/sent by the conversion interface. It defines that the data packet consists of a header micro-fragment, a body micro-fragment, and a tail micro-fragment. Data transmission is carried out through NWRITE packets to ensure data volume and address alignment and supports multiple notification information packet formats.
It enables efficient communication between the on-chip network and RapidIO devices, reduces data packet transmission latency, and improves system performance.
Smart Images
Figure CN116089353B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit communication technology, and in particular to a data packet transmission method for on-chip networks and RapidIO devices. Background Technology
[0002] As integrated circuits enter the post-Moore's Law era, the traditional approach of increasing the integration density of individual chips is drastically increasing chip manufacturing costs in order to meet the growing computing demands of artificial intelligence, big data, and other applications. Furthermore, with the shrinking of process dimensions, the cost and development cycle of developing monolithic application-specific integrated circuits (ASICs) have become extremely high. The end of Moore's Law will increase the demand for and use of application-specific chips, and the combination of dedicated accelerators and specific processors to meet the increasingly stringent power, yield, and performance requirements of specific applications such as cloud infrastructure, network infrastructure, the Internet of Things (IoT), and edge computing is also crucial. In this context, building an integrated, high-performance network to achieve efficient communication between multiple functional units and multiple chips is particularly important.
[0003] Over the past 20 years, Network-on-Chip (NoC) technology has undergone extensive research and significant development, especially in building large and complex systems, where it has become an indispensable system component, replacing traditional bus-based interconnect structures. RapidIO is an open interconnect technology standard widely used in embedded systems. RapidIO devices (such as DSPs) are crucial components of multi-die integrated microsystems. In RapidIO, data write transfers often use NWRITE packets or SWRITE packets suitable for large data stream write transfers. For read transfers, read requests can only be initiated with NREAD packets, and read data is returned with RESPONSE packets. The RapidIO protocol limits the payload of data packets to a maximum of 256 bytes. This data volume is far smaller than the maximum data payload capacity of data packets in interconnect die packet transmission protocols. This forces large-volume read transactions to be split into several NREAD requests, and read response data also needs to be returned in the form of multiple RESPONSE packets. Each split introduces more packet transmission latency, significantly reducing the efficiency of large-volume read and write transfers and impacting system performance. Summary of the Invention
[0004] The purpose of this invention is to provide a data packet transmission method for on-chip networks and RapidIO devices, so as to solve the problems of high data packet transmission latency and low transmission efficiency in the background art, realize the efficient communication between on-chip networks and RapidIO devices, and efficiently expand and integrate RapidIO devices such as digital signal processors.
[0005] To address the aforementioned technical problems, this invention provides a data packet transmission method for on-chip networks and RapidIO devices, specifying the data transmission format in the on-chip network and the data payload format of AXI requests received / sent by the conversion interface.
[0006] In one implementation, data transmission in the on-chip network is specified to be performed in units of data packets, and the data transmitted on one data link in the on-chip network within one clock cycle is defined as a micro-slice, the data bit width of which is 154 bits, and each data packet is composed of several micro-slices;
[0007] Each data packet contains a header fragment, several body fragments, and a tail fragment. The header fragment stores all the valid information of the current data packet to mark the start position of the data packet. The body fragments are used to load the valid data payload. The tail fragments are used to mark the end position of the data packet.
[0008] In one implementation, the AXI requests received by the conversion interface through the RapidIO device are all converted from NWRITE packets. The received NWRITE packets are divided into NWRITE initial configuration packets, NWRITE request packets, and NWRITE write packets. The NWRITE initial configuration packets are used to configure various information after each reset. The NWRITE request packets are used to initiate a request and contain various control information required to initiate the request. The NWRITE write packets are used to provide write data in write-related requests.
[0009] In one implementation, the data payload format of the NWRITE initial configuration packet requires that the data size must be an integer multiple of a double word, and the address must be aligned with the double word boundary. The data payload of the NWRITE initial configuration packet contains a total of 5 double words. Bits 31 to 0 of the first double word are the read response AXI address; bits 35 to 32 are the on-chip network ID; bits 36 to 62 are interrupt information; the highest bit, bit 63, is 1 to distinguish the initial configuration packet from other packet types; the first word of the second double word is the AXI address information for the retransmission failure notification; the third to fifth double words represent the AXI address information for different types of notifications.
[0010] In one implementation, the data payload format of the NWRITE request packet requires that the data size must be an integer multiple of a double word, and the address must be aligned with the double word boundary. The data payload of the NWRITE request packet contains a total of 3 double words. The highest bit of the first double word is 0 to distinguish the initial configuration packet from other packet types. Bits 16 to 13 are the event type; bits 12 to 9 are the transaction ID; bits 8 to 0 are the data length; the second double word is a 64-bit primary address, and the third double word is a 64-bit secondary address.
[0011] In one implementation, the data payload format of the NWRITE write data packet requires that the data size must be an integer multiple of a double word, and the address must be aligned with the double word boundary; the data payload of the NWRITE write data packet is the data that the write request wants to write; a write-related request consists of a request packet and several write data packets, and the length and number of the NWRITE write data packets are not fixed, but for a specific write-related request, the data size contained in the NWRITE write data packet matches the length field information of the corresponding NWRITE request packet.
[0012] In one implementation, the conversion interface sends various types of data information to the RapidIO device via the AXI bus. This data information is converted into NWRITE packets by IP. The data payload format of the sent NWRITE packets is divided into NWRITE read response data packets and NWRITE notification information packets of various types. The data payload format of the NWRITE read response data packet requires that the data size must be an integer multiple of a double word, and the address must be aligned with the double word boundary. The payload format of the NWRITE read response data packet includes the transaction ID, data length, starting address of the read response data, read response data, and verification result.
[0013] NWRITE's various notification packets mainly include retransmission failure notifications, occupancy release notifications, DMA end notifications, shared write notifications, write request information notifications, and request accepted notifications, and the data payload format is in double-word data units.
[0014] In one implementation, bits 63 to 61 of the retransmission failure notification are the notification type, bits 3 to 0 are the transaction ID, bits 7 to 4 are the event type, and bits 60 to 8 are reserved bits, which are set to 0.
[0015] In the occupancy release notification, bits 63 to 61 are the notification type, bits 3 to 0 are the transaction ID, bits 7 to 4 are the event type, and bits 60 to 8 are reserved bits, which are set to 0.
[0016] In the DMA end notification, bits 63 to 61 are the notification type, bits 3 to 0 are the transaction ID, and bits 60 to 4 are reserved bits, which are set to 0.
[0017] The shared write notification contains two double-word data. In the first double-word data, bits 63 to 61 are the notification type, bits 8 to 0 are the length information, bits 12 to 9 are the transaction ID, and bits 60 to 13 are reserved bits, which are set to 0. The second double-word data is the address of the shared data, which serves as the main address for the read request to obtain the shared data.
[0018] Bits 63 to 61 of the write request information notification are the notification type, bits 31 to 0 are the AXI write address that sent the write request, bits 40 to 32 are the length information, bit 41 is the error flag bit, when this bit is 1 it indicates that the write data verification failed, when this bit is 0 it indicates that the write data verification passed, and bits 60 to 42 are reserved bits, set to 0;
[0019] In the notification that the request has been accepted, bits 63 to 61 represent the notification type, bits 3 to 0 represent the transaction ID, bits 7 to 4 represent the event type, and bits 60 to 8 represent reserved bits, which are set to 0.
[0020] In the data packet transmission method for on-chip networks and RapidIO devices provided by this invention, the data transmission format in the on-chip network and the data payload format of AXI requests received / sent by the conversion interface are specified. This invention solves the problem of efficient communication between on-chip networks and RapidIO devices, enabling efficient and rapid expansion and integration of RapidIO devices such as digital signal processors, supporting efficient communication between on-chip networks and RapidIO devices, and reducing data packet transmission latency. Attached Figure Description
[0021] Figure 1 This is a schematic diagram of a data packet transmission method for on-chip networks and RapidIO devices proposed in this invention;
[0022] Figure 2 This is a schematic diagram of the data packet format.
[0023] Figure 3 This is a schematic diagram of the data payload format of the NWRITE initial configuration package;
[0024] Figure 4 This is a diagram illustrating the NWRITE request packet data payload format;
[0025] Figure 5 This is a diagram illustrating the NWRITE write packet payload format;
[0026] Figure 6 This is a schematic diagram of the NWRITE read response packet payload format;
[0027] Figure 7 This is a schematic diagram of the data payload format of various notification information packets in NWRITE. Detailed Implementation
[0028] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a further detailed explanation of the data packet transmission method for on-chip networks and RapidIO devices proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.
[0029] This invention provides a data packet transmission method for on-chip networks and RapidIO devices, the structure of which is as follows: Figure 1 As shown, the data transmission format in the on-chip network is specified; simultaneously, the data payload format of AXI requests received / sent by the conversion interface is specified. Specific design details are as follows:
[0030] P1. Data Transmission Format Definition
[0031] This invention specifies that data transmission in the on-chip network is performed in units of data packets, such as... Figure 2 As shown, a data segment is defined as the data transmitted on a data link in the network within one clock cycle. The data bit width is 154 bits, and each data packet consists of several segments. All data packets contain a header segment, several body segments, and a tail segment. The header segment stores all valid information of the current data packet to mark the start position of the data packet, the body segments are used to load the valid data payload, and the tail segment marks the end position of the data packet.
[0032] P2.NWRITE packet data payload format definition
[0033] The AXI requests received by the conversion interface through the RapidIO device are all converted from NWRITE packets. The received NWRITE packets are divided into NWRITE initial configuration packets, NWRITE request packets, and NWRITE write packets. Among them, the NWRITE initial configuration packet is used to configure various information after each reset; the NWRITE request packet is used to initiate a request and contains various control information required to initiate the request; the NWRITE write packet is used to provide write data in write-related requests.
[0034] The data payload format of the NWRITE initial configuration package is as follows: Figure 3As shown, the data size must be an integer multiple of the double word, and the address must be aligned with the double word boundary. Figure 3 The NWRITE initial configuration packet payload is drawn in units of double-word data (64 bits). The payload consists of 5 double-word data. Bits 31 to 0 of the first double-word data are the AXI address for the read response; bits 35 to 32 are the NoCID; bits 36 to 62 are interrupt information; and the highest bit, bit 63, is 1 to distinguish the initial configuration packet from other packet types. The first word of the second double-word data is the AXI address information for the retransmission failure notification; the third to fifth double-word data represent the AXI address information for different types of notifications.
[0035] The NWRITE request packet data payload format is as follows: Figure 4 As shown, the data size must be an integer multiple of the double word, and the address must be aligned with the double word boundary. The NWRITE packet payload of the request packet type contains three double words. The highest bit of the first double word is 0, distinguishing it from initial configuration packets and other packet types; bits 16-13 represent the event type; bits 12-9 represent the transaction ID; and bits 8-0 represent the data length. The second double word is a 64-bit primary address, and the third double word is a 64-bit secondary address.
[0036] NWRITE write packet payload format is as follows: Figure 5 As shown, the data size must be an integer multiple of a double word, and the address must be aligned with the double word boundary. The data payload of the NWRITE packet of the write data packet type is the data that the write request wants to write. A write-related request consists of a request packet and several write data packets. The length and number of NWRITE packets of the write data packet type are not fixed, but for a specific write-related request, the amount of data contained in the write data packets should match the NWRITE length field information of the corresponding request packet.
[0037] The conversion interface sends various types of data to the RapidIO device via the AXI bus. This data is converted into NWRITE packets by IP. The payload format of the sent NWRITE packets includes read response packets and various notification information packets. The NWRITE read response packet payload format is as follows: Figure 6 As shown, the data volume must be an integer multiple of the double word, and the address must be aligned with the double word boundary. The NWRITE packet data payload format of the read response includes the transaction ID, data length, starting address of the read response data, read response data, and verification result.
[0038] NWRITE notification packets mainly include retransmission failure notifications, occupancy release notifications, DMA end notifications, shared write notifications, write request notifications, and request accepted notifications. The data payload format for each is as follows: Figure 7 As shown, since the RABIP used here uses double words as the data unit for packets, therefore... Figure 7 The data is also drawn in units of double-word data (64 bits). Figure 7 The data format is both the format of the NWRITE packet data payload and the data format of the wdata signal (64-bit) sent by the AXIW channel.
[0039] Please continue reading. Figure 7 In the retransmission failure notification, bits 63-61 represent the notification type, bits 3-0 represent the transaction ID, bits 7-4 represent the event type, and bits 60-8 are reserved bits, which can be set to 0. In the occupancy release notification, bits 63-61 represent the notification type, bits 3-0 represent the transaction ID, bits 7-4 represent the event type, and bits 60-8 are reserved bits, which can be set to 0. In the DMA end notification, bits 63-61 represent the notification type, bits 3-0 represent the transaction ID, and bits 60-4 are reserved bits, which can be set to 0. The shared write notification contains two double-word data entries. In the first double-word data entry, bits 63-61 represent the notification type, bits 8-0 represent length information, and bits 12 represent the length information. Bit 9 is the transaction ID, bits 60-13 are reserved bits and can be set to 0; the second double-word data is the address of the shared data, which serves as the main address for the read request to obtain the shared data; bits 63-61 of the write request information notification are the notification type, bits 31-0 are the AXI write address that sent the write request, bits 40-32 are the length information, bit 41 is the error flag bit, when this bit is 1 it indicates that the write data verification failed, when this bit is 0 it indicates that the write data verification passed, bits 60-42 are reserved bits and can be set to 0; bits 63-61 of the request accepted notification are the notification type, bits 3-0 are the transaction ID, bits 7-4 are the event type, bits 60-8 are reserved bits and can be set to 0.
[0040] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.
Claims
1. A method for data packet transmission between on-chip networks and RapidIO devices, characterized in that, Specify the data transmission format in the on-chip network and specify the data payload format of AXI requests received / sent by the conversion interface; The AXI requests received by the conversion interface through the RapidIO device are all converted from NWRITE packets. The received NWRITE packets are divided into NWRITE initial configuration packets, NWRITE request packets, and NWRITE write packets. Among them, the NWRITE initial configuration packet is used to configure various information after each reset; the NWRITE request packet is used to initiate a request and contains various control information required to initiate the request; the NWRITE write packet is used to provide write data in write-related requests. The NWRITE initial configuration packet's data payload format requires the data size to be an integer multiple of a double word, and the address must be aligned with the double word boundary. The NWRITE initial configuration packet's data payload contains a total of 5 double words. Bits 31 to 0 of the first double word are the read response AXI address; bits 35 to 32 are the on-chip network ID; bits 36 to 62 are interrupt information; the highest bit, bit 63, is 1, used to distinguish the initial configuration packet from other packet types; the first word of the second double word is the AXI address information for retransmission failure notification; the third to fifth double words represent the AXI address information for different types of notifications.
2. The data packet transmission method for on-chip networks and RapidIO devices as described in claim 1, characterized in that, The data transmission in the on-chip network is specified to be carried out in units of data packets, and the data transmitted on one data link in the on-chip network within one clock cycle is defined as a micro-slice. The data bit width of the micro-slice is 154 bits, and each data packet is composed of several micro-slices. Each data packet contains a header fragment, several body fragments, and a tail fragment. The header fragment stores all the valid information of the current data packet to mark the start position of the data packet. The body fragments are used to load the valid data payload. The tail fragments are used to mark the end position of the data packet.
3. The data packet transmission method for on-chip networks and RapidIO devices as described in claim 1, characterized in that, The NWRITE request packet's payload format requires the data size to be an integer multiple of a double word, and the address must be aligned with the double word boundary. The NWRITE request packet's payload contains three double words: the highest bit of the first double word is 0, distinguishing it from other packet types; bits 16-13 represent the event type; bits 12-9 represent the transaction ID; bits 8-0 represent the data length; the second double word is a 64-bit primary address, and the third double word is a 64-bit secondary address.
4. The data packet transmission method for on-chip networks and RapidIO devices as described in claim 1, characterized in that, The NWRITE write packet's data payload format requires the data size to be an integer multiple of a double word, and the address must be aligned with the double word boundary. The data payload of the NWRITE write packet is the data that the write request wants to write. A write-related request consists of a request packet and several write packets. The length and number of NWRITE write packets are not fixed, but for a specific write-related request, the amount of data contained in the NWRITE write packet matches the length field information of the corresponding NWRITE request packet.
5. The data packet transmission method for on-chip networks and RapidIO devices as described in claim 1, characterized in that, The conversion interface sends various types of data to the RapidIO device via the AXI bus. This data is converted into NWRITE packets by IP. The payload format of the sent NWRITE packets is divided into NWRITE read response packets and NWRITE notification packets of various types. The payload format of the NWRITE read response packets requires that the data size must be an integer multiple of a double word, and the address must be aligned with the double word boundary. The payload format of the NWRITE read response packets includes the transaction ID, data length, starting address of the read response data, read response data, and verification result. NWRITE notification packets include retransmission failure notifications, occupancy release notifications, DMA end notifications, shared write notifications, write request information notifications, and request accepted notifications, with the data payload formatted in double-word units.
6. The data packet transmission method for on-chip networks and RapidIO devices as described in claim 5, characterized in that, In the retransmission failure notification, bits 63-61 are the notification type, bits 3-0 are the transaction ID, bits 7-4 are the event type, and bits 60-8 are reserved bits, which are set to 0. In the occupancy release notification, bits 63-61 are the notification type, bits 3-0 are the transaction ID, bits 7-4 are the event type, and bits 60-8 are reserved bits, which are set to 0. In the DMA end notification, bits 63-61 are the notification type, bits 3-0 are the transaction ID, and bits 60-4 are reserved bits, which are set to 0. The shared write notification contains two double-word data. In the first double-word data, bits 63 to 61 are the notification type, bits 8 to 0 are the length information, bits 12 to 9 are the transaction ID, and bits 60 to 13 are reserved bits, which are set to 0. The second double-word data is the address of the shared data, which serves as the main address for the read request to obtain the shared data. Bits 63 to 61 of the write request information notification are the notification type, bits 31 to 0 are the AXI write address that sent the write request, bits 40 to 32 are the length information, bit 41 is the error flag bit, when this bit is 1 it indicates that the write data verification failed, when this bit is 0 it indicates that the write data verification passed, and bits 60 to 42 are reserved bits, set to 0; In the notification that the request has been accepted, bits 63-61 represent the notification type, bits 3-0 represent the transaction ID, bits 7-4 represent the event type, and bits 60-8 represent the reserved bits, which are set to 0.