Semiconductor structure and forming method thereof, stacking structure and wafer stacking method

Abstract

Embodiments of the present disclosure provide a semiconductor structure and a method for forming the same, a stacked structure, and a wafer stacking method, wherein the semiconductor structure includes: a top metal layer and a buffer layer; the top metal layer is located in a first dielectric layer on the surface of a semiconductor substrate, and the top metal layer penetrates the first dielectric layer; the buffer layer is located between the top metal layer and the first dielectric layer.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and is related to, but not limited to, a semiconductor structure and a forming method thereof, a stacking structure, and a wafer stacking method. Background Art

[0002] With the development of highly integrated semiconductors, multi-wafer stacking typically uses a hybrid bonding process to achieve inter-wafer bonding. Currently, the copper bond pads used in hybrid bonding are manufactured using a Damascene process. To ensure bonding yield and electrical connectivity between wafers, the surfaces to be bonded must be flattened to a certain degree while also ensuring that any concavities or convexities in the copper bond pads are below 10 nanometers (nm) or 5nm, making the process extremely challenging.

[0003] In the prior art, during wafer stacking, copper bonding pads undergo thermal expansion and diffusion during bonding to form a complete stacked structure. However, if the planarization process fails to control the copper bonding pad protrusions or depressions to less than 10nm or 5nm, voids may form between the stacking interfaces during wafer bonding, or wafer delamination may occur, leading to bond failure. Furthermore, the barrier layer surrounding the bonding pads may also crack during bonding, increasing the risk of leakage in the wafer stack and making it difficult to scale down the bond pitch. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a semiconductor structure and a method for forming the same, a stacking structure, and a wafer stacking method.

[0005] In a first aspect, an embodiment of the present disclosure provides a semiconductor structure, comprising: a top metal layer and a buffer layer;

[0006] Wherein, the top metal layer is located in the first dielectric layer on the surface of the semiconductor substrate, and the top metal layer penetrates the first dielectric layer;

[0007] The buffer layer is located between the top metal layer and the first dielectric layer.

[0008] In some embodiments, the buffer layer includes a buffer material; the buffer material includes at least one or any combination of an organic material, an inorganic material, and a composite material.

[0009] In some embodiments, the first dielectric layer includes a first trench and a second trench that penetrate each other; wherein the opening size of the first trench is larger than the opening size of the second trench;

[0010] The top metal layer includes a first top metal layer located in the first trench and a second top metal layer located in the second trench.

[0011] In some embodiments, a top surface of the buffer layer is flush with a top surface of the first top metal layer.

[0012] In some embodiments, the semiconductor structure further includes a bonding layer; the bonding layer is located between the buffer layer and the first dielectric layer, and / or between the top metal layer and the first dielectric layer.

[0013] In some embodiments, the bonding layer includes a bonding material; the bonding material includes at least one or any combination of silicon oxide, silicon nitride, silicon carbon nitride, and silicon oxynitride.

[0014] In some embodiments, the bonding strength between the buffer layers is greater than the bonding strength between the bonding layers.

[0015] In some embodiments, the elastic modulus of the buffer layer is smaller than the elastic modulus of the bonding layer.

[0016] In some embodiments, the semiconductor structure further includes a second dielectric layer located on the surface of the semiconductor substrate and an underlying metal layer located in the second dielectric layer; wherein the first dielectric layer is located above the second dielectric layer;

[0017] The bottom metal layer is connected to the second top metal layer.

[0018] In some embodiments, the semiconductor structure further includes an etch stop layer located between the first dielectric layer and the second dielectric layer;

[0019] Wherein, the second trench penetrates the etch stop layer.

[0020] In some embodiments, the semiconductor structure further includes: a barrier layer; the barrier layer is located on the outer sidewall and bottom of the top metal layer.

[0021] In a second aspect, an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, the method comprising:

[0022] A semiconductor substrate is provided, wherein a first dielectric layer is formed on a surface of the semiconductor substrate; the first dielectric layer includes a first trench, and the depth of the first trench is less than the thickness of the first dielectric layer;

[0023] forming an initial buffer layer on the surface of the first dielectric layer and the inner wall of the first trench;

[0024] removing a portion of the initial buffer layer and a portion of the first dielectric layer at the bottom of the first trench to form a second trench and a buffer layer penetrating the first dielectric layer;

[0025] Filling the first trench and the second trench with metal material to form a top metal layer.

[0026] In some embodiments, before forming the first dielectric layer, the method further includes:

[0027] forming a second dielectric layer on the surface of the semiconductor substrate;

[0028] forming a bottom metal layer in the second dielectric layer;

[0029] An initial etch stop layer is formed on the surfaces of the second dielectric layer and the bottom metal layer; the second top metal layer is connected to the bottom metal layer, and the initial etch stop layer is located between the first dielectric layer and the second dielectric layer.

[0030] In some embodiments, the method comprises:

[0031] Before forming the initial buffer layer, forming an initial bonding layer on the surface of the first dielectric layer and inside the first trench;

[0032] removing a portion of the initial buffer layer, a portion of the initial bonding layer, a portion of the first dielectric layer, and a portion of the initial etch stop layer at the bottom of the first trench to form a second trench penetrating the first dielectric layer and the initial etch layer;

[0033] The remaining initial buffer layer, the remaining initial bonding layer and the remaining initial etch stop layer form the buffer layer, the bonding layer and the etch stop layer respectively.

[0034] In some embodiments, the top metal layer includes a first top metal layer located in the first trench, and a second top metal layer located in the second trench;

[0035] Filling the first trench and the second trench with metal material to form a top metal layer includes:

[0036] forming a barrier layer and a seed layer in sequence on inner walls of the buffer layer and the bonding layer in the first trench, and on inner walls of the first dielectric layer and the etch stop layer in the second trench;

[0037] Electroplating the metal material on the surface of the seed layer to form the first top metal layer and the second top metal layer;

[0038] The first top metal layer and the buffer layer are planarized until the surface of the bonding layer is exposed.

[0039] In a third aspect, an embodiment of the present disclosure provides a stacked structure, comprising: a first wafer and a second wafer stacked face to face; the first wafer and the second wafer both have at least the above-mentioned semiconductor structure;

[0040] The top metal layer of the first wafer is aligned with the top metal layer of the second wafer, the buffer layer of the first wafer is aligned with the buffer layer of the second wafer, and the bonding layer of the first wafer is aligned with the bonding layer of the second wafer.

[0041] In some embodiments, the bonding strength between the buffer layers is greater than the bonding strength between the bonding layers.

[0042] In some embodiments, the elastic modulus of the buffer layer is smaller than the elastic modulus of the bonding layer.

[0043] In a fourth aspect, an embodiment of the present disclosure provides a wafer stacking method, the method comprising:

[0044] Providing a first wafer and a second wafer having the above-mentioned semiconductor structure;

[0045] The first wafer and the second wafer are aligned face to face to achieve stacking of the first wafer and the second wafer.

[0046] In some embodiments, the first wafer and the second wafer each include a top metal layer located in a first dielectric layer, a buffer layer located between the top metal layer and the first dielectric layer, and a bonding layer located between the buffer layer and the first dielectric layer; wherein the first dielectric layer is located on the surface of the first wafer and the second wafer, respectively;

[0047] The step of aligning the first wafer and the second wafer face to face to achieve stacking of the first wafer and the second wafer includes:

[0048] The top metal layer, buffer layer and bonding layer of the first wafer are respectively aligned face-to-face with the top metal layer, buffer layer and bonding layer of the second wafer to achieve stacking of the first wafer and the second wafer.

[0049] The semiconductor structure and its formation method, stacked structure, and wafer stacking method provided by the embodiments of the present disclosure include: a top metal layer and a buffer layer; the top metal layer is located in a first dielectric layer on the surface of the semiconductor substrate and extends through the first dielectric layer; and the buffer layer is located between the top metal layer and the first dielectric layer. Because the semiconductor structure provided by the embodiments of the present disclosure includes a buffer layer located between the top metal layer and the first dielectric layer, the buffer layer can effectively accommodate lateral expansion caused by diffusion of the top metal layer during the semiconductor structure bonding process. This prevents longitudinal expansion caused by excessive restriction of lateral expansion of the top metal layer, which can lead to delamination between the semiconductor structures. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In the accompanying drawings (which are not necessarily drawn to scale), like reference numerals may describe similar components in different views. Like reference numerals with different letter suffixes may represent different examples of similar components. The accompanying drawings generally illustrate various embodiments discussed herein by way of example and not limitation.

[0051] Figure 1a Schematic diagram of a semiconductor structure in related art;

[0052] Figure 1b Schematic diagram of a semiconductor stacking structure in related art;

[0053] Figure 2 A schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure;

[0054] Figure 3 A schematic flow chart of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0055] Figures 4a to 4g A schematic diagram of the semiconductor structure manufacturing process provided by the embodiment of the present disclosure

[0056] Figure 5 A schematic diagram of the stacking structure provided in an embodiment of the present disclosure;

[0057] Figure 6 A schematic flow chart of a wafer stacking method according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0058] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0059] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0060] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0061] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. However, when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part exists in the present disclosure.

[0062] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0063] Before describing in detail the semiconductor structure and the method for forming the same provided by the embodiments of the present disclosure, the formation process of the semiconductor structure in the related art is first described.

[0064] Figure 1a is a schematic diagram of a semiconductor structure in related technology, such as Figure 1a As shown, the semiconductor structure 10 in the related art includes a silicon substrate 100 , a dielectric layer 101 on the surface of the silicon substrate 100 , a copper bond 102 in the dielectric layer 101 , and a barrier layer 103 around the copper bond 102 . Figure 1b is a schematic diagram of a semiconductor stacking structure in related art, such as Figure 1b As shown, in the related art, two semiconductor structures 10 are stacked face to face, and the stacking between the two semiconductor structures is achieved through the copper bonding bonds 102 of each semiconductor structure.

[0065] However, the copper bonding pads for hybrid bonding are currently made using the Damascus process. In order to ensure the bonding yield and electrical connection between semiconductor structures, the surface to be bonded needs to be flattened to a certain degree, while ensuring that the depression or protrusion of the copper bonding pad is less than 10nm or 5nm, which has extremely high process difficulty. In the related art, during the semiconductor stacking process, the copper bonding pad undergoes thermal expansion and diffusion during bonding to form a complete stacking structure. However, if the flattening process does not control the protrusion or depression of the copper bonding pad to less than 10nm or 5nm, then a void H (such as a hole) will be formed between the stacking interfaces during the semiconductor structure bonding process. Figure 1b as shown), or, along Figure 1b Delamination occurs in the direction indicated by the middle arrow, resulting in bonding failure. In addition, the barrier layer 103 may also break during the bonding process, thus increasing the risk of electrical leakage in the semiconductor structure and making it difficult to scale down the bonding pitch.

[0066] Based on the problems existing in the related art, the embodiments of the present disclosure provide a semiconductor structure and a method for forming the same, a stacked structure, and a wafer stacking method. The semiconductor structure includes: a top metal layer and a buffer layer; the top metal layer is located in a first dielectric layer on the surface of a semiconductor substrate, and the top metal layer extends through the first dielectric layer; and the buffer layer is located between the top metal layer and the first dielectric layer. Because the semiconductor structure provided by the embodiments of the present disclosure includes a buffer layer located between the top metal layer and the first dielectric layer, the buffer layer can effectively accommodate lateral expansion caused by diffusion of the top metal layer during the bonding process between the two semiconductor structures. This prevents excessive longitudinal expansion due to the limited lateral expansion of the top metal layer, which can lead to delamination between the semiconductor structures.

[0067] The present disclosure provides a semiconductor structure. Figure 2 A schematic diagram of the semiconductor structure provided in the embodiment of the present disclosure is shown in FIG. Figure 2 As shown, the semiconductor structure 20 includes a top metal layer 201 and a buffer layer 202 .

[0068] The top metal layer 201 is located in the first dielectric layer 203 on the surface of the semiconductor substrate 200 and penetrates the first dielectric layer 203 ; the buffer layer 202 is located between the top metal layer 201 and the first dielectric layer 203 .

[0069] The semiconductor substrate 200 may be a silicon substrate. The semiconductor substrate may also include other semiconductor elements, such as germanium (Ge), or semiconductor compounds, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), or indium antimonide (InSb), or other semiconductor alloys, such as silicon germanium (SiGe), gallium arsenic phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP), or combinations thereof. The first dielectric layer 203 may include materials such as silicon dioxide and carbon-doped silicon oxide. The top metal layer 201 includes a metal material, which may be at least one of tungsten (W), cobalt (Co), copper (Cu), and aluminum (Al), or a combination of at least two of these materials.

[0070] The buffer layer 202 includes a buffer material. The buffer material includes at least one of an organic material, an inorganic material, and a composite material, or a combination of at least two materials. For example, the buffer material may be polyimide (PI), benzocyclobutene (BCB), porous silicon oxide, or a mixture of organic matter and silicon oxide.

[0071] In the embodiment of the present disclosure, the presence of the buffer layer allows space to accommodate the lateral volume changes of the top metal layer during the subsequent semiconductor structure bonding process, preventing excessive longitudinal expansion due to the restricted lateral volume changes of the top metal layer, which in turn causes delamination and leads to bonding failure of the semiconductor structure.

[0072] In some embodiments, see Figure 2 The first dielectric layer 203 includes a first trench and a second trench that penetrate each other; the opening size of the first trench is larger than the opening size of the second trench. Correspondingly, the top metal layer 201 includes a first top metal layer 201a located in the first trench and a second top metal layer 201b located in the second trench.

[0073] In the embodiment of the present disclosure, the buffer layer 202 is located between the first top metal layer 201 a and the corresponding first dielectric layer, and the top surface of the buffer layer 202 is flush with the top surface of the first top metal layer 201 a.

[0074] In some embodiments, see Figure 2The semiconductor structure 20 further includes a bonding layer 204. The bonding layer 204 is located between the buffer layer 202 and the first dielectric layer 203, and / or between the top metal layer 201 and the first dielectric layer 202. The elastic modulus of the buffer layer 202 is smaller than the elastic modulus of the bonding layer 204, and the bonding strength of the buffer layer 202 is greater than the bonding strength of the bonding layer 204.

[0075] In the embodiment of the present disclosure, the bonding layer with a barrier effect wraps the top metal layer, which can effectively prevent the diffusion of metal materials in the top metal layer and reduce the leakage of the semiconductor structure.

[0076] In some embodiments, the elastic modulus of the buffer layer is smaller than the elastic modulus of the bonding layer, that is, the buffer layer is more easily deformed than the bonding layer. In this way, providing a buffer layer between the bonding layer and the top metal layer can effectively accommodate the lateral volume change of the top metal layer and prevent excessive longitudinal expansion due to the restricted lateral volume change of the top metal layer, thereby preventing stratification.

[0077] In some embodiments, the bonding strength between buffer layers is greater than the bonding strength between bonding layers. By setting a buffer layer between the bonding layer and the top metal layer, not only can the bonding failure of the semiconductor structure be prevented, but the bonding strength between the semiconductor structures can also be further improved.

[0078] In some embodiments, the bonding layer includes a bonding material; the bonding material includes at least one or a combination of at least two materials selected from silicon oxide, silicon nitride, silicon carbon nitride, and silicon oxynitride. For example, the bonding material may be silicon oxide, carbon-doped silicon oxide, silicon nitride, or silicon oxynitride.

[0079] In some embodiments, see Figure 2 The semiconductor structure 20 further includes a second dielectric layer 205 located on the surface of the semiconductor substrate 200 and a bottom metal layer 206 located in the second dielectric layer 205; wherein the first dielectric layer 203 is located above the second dielectric layer 205. In the embodiment of the present disclosure, the bottom metal layer 206 is connected to the second top metal layer 201b.

[0080] In some embodiments, see Figure 2 The semiconductor structure 20 further includes an etch stop layer 207 located between the first dielectric layer 203 and the second dielectric layer 205 ; wherein the second trench penetrates the etch stop layer 207 .

[0081] In some embodiments, see Figure 2The semiconductor structure 20 further includes a barrier layer 208, which is located on the outer sidewalls and bottom of the top metal layer 201. For example, the barrier layer 208 is located between the buffer layer 202 and the top metal layer 201, between the bonding layer 204 and the top metal layer 201, between the first dielectric layer 203 and the top metal layer 201, between the etch stop layer 207 and the second top metal layer 201b, and between the bottom metal layer 206 and the second dielectric layer 205.

[0082] The material of the barrier layer can be metal tantalum, tantalum nitride, metal titanium, titanium nitride, etc.

[0083] In the embodiment of the present disclosure, the barrier layer is used to prevent the diffusion of the metal material filled in the first trench and the second trench, which may cause leakage of the semiconductor structure.

[0084] The semiconductor structure provided by the embodiment of the present disclosure includes a buffer layer located between the top metal layer and the first dielectric layer. The buffer layer can effectively accommodate the lateral expansion caused by the diffusion of the top metal layer during the bonding process of the semiconductor structure. In this way, it can prevent the longitudinal expansion caused by excessive restriction of the lateral expansion of the top metal layer, thereby preventing the delamination between the semiconductor structures.

[0085] The present disclosure provides a method for manufacturing a semiconductor structure. Figure 3 A schematic diagram of a process for manufacturing a semiconductor structure provided by an embodiment of the present disclosure is shown in FIG. Figure 3 As shown, the method for manufacturing a semiconductor structure includes the following steps:

[0086] Step S301: providing a semiconductor substrate, wherein a first dielectric layer is formed on a surface of the semiconductor substrate; the first dielectric layer includes a first trench, and a depth of the first trench is less than a thickness of the first dielectric layer.

[0087] In the embodiment of the present disclosure, the semiconductor substrate may be a silicon substrate, or may include other semiconductor compounds. The first dielectric layer may include materials such as silicon dioxide, carbon-doped silicon oxide, etc.

[0088] The first trench is located on the surface of the first dielectric layer, and the first trench does not penetrate the first dielectric layer.

[0089] Step S302 : forming an initial buffer layer on the surface of the first dielectric layer and the inner wall of the first trench.

[0090] In the disclosed embodiments, the initial buffer layer includes a buffer material; the buffer material includes at least one of an organic material, an inorganic material, and a composite material, or any combination thereof. For example, the buffer material may be polyimide, benzocyclobutene, porous silicon oxide, or a mixture of organic and silicon oxide.

[0091] In the embodiment of the present disclosure, the first initial buffer layer can be formed by any suitable deposition process, for example, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, a spin coating process or a coating process.

[0092] Step S303 : removing a portion of the initial buffer layer and a portion of the first dielectric layer at the bottom of the first trench to form a second trench and a buffer layer penetrating the first dielectric layer.

[0093] In the disclosed embodiment, a portion of the initial buffer layer and a portion of the first dielectric layer at the bottom of the first trench may be removed by a dry etching process, such as a plasma etching process, a reactive ion etching process, or an ion milling process, to form a second trench penetrating the first dielectric layer and the buffer layer.

[0094] Step S304 : filling the first trench and the second trench with metal material to form a top metal layer.

[0095] In the embodiment of the present disclosure, the metal material of the top metal layer includes at least one or any combination of tungsten, cobalt, copper and aluminum.

[0096] Figures 4a to 4g This is a schematic diagram of the semiconductor structure manufacturing process provided by the embodiment of the present disclosure. Figures 4a to 4g The method for manufacturing the semiconductor structure provided by the embodiment of the present disclosure is further described in detail.

[0097] First, you can refer to Figure 4a and 4b , performing step S301, providing a semiconductor substrate, wherein a first dielectric layer is formed on the surface of the semiconductor substrate; the first dielectric layer includes a first trench.

[0098] In some embodiments, before forming the first dielectric layer, the method for manufacturing a semiconductor structure includes:

[0099] Step S10: forming a second dielectric layer on the surface of the semiconductor substrate.

[0100] The second dielectric layer may include materials such as silicon dioxide, carbon-doped silicon oxide, etc. In the embodiment of the present disclosure, the second dielectric layer may be formed by any suitable deposition process.

[0101] Step S11: forming a bottom metal layer in the second dielectric layer.

[0102] The bottom metal layer includes a metal material, which may be at least one of tungsten, cobalt, copper, and aluminum, or any combination thereof. In the disclosed embodiment, the bottom metal layer is formed within the second dielectric layer by etching the second dielectric layer to form a recess, which is then filled with a metal material. The top surface of the bottom metal layer is flush with the top surface of the second dielectric layer.

[0103] In some embodiments, before filling the groove with metal material to form the bottom metal layer, the method for manufacturing the semiconductor structure further includes: forming a barrier layer on the inner wall of the groove to prevent the metal material of the bottom metal layer from diffusing into the second dielectric layer.

[0104] Step S12: forming an initial etch stop layer on the surfaces of the second dielectric layer and the bottom metal layer.

[0105] In the embodiment of the present disclosure, the initial etch stop layer may be a silicon nitride layer or other material layer.

[0106] In some embodiments, after forming the initial etch stop layer, the method for fabricating a semiconductor structure includes:

[0107] Step S13: forming a first dielectric layer on the surface of the initial etch stop layer.

[0108] In the embodiment of the present disclosure, the material of the second dielectric layer may be the same as or different from the material of the first dielectric layer.

[0109] like Figure 4a As shown, a second dielectric layer 401, an underlying metal layer 402 located in the second dielectric layer, a barrier layer 407 located between the underlying metal layer 402 and the second dielectric layer 402, an initial etch stop layer 403a located on the surfaces of the second dielectric layer 401 and the underlying metal layer 402, and a first dielectric layer 404 located on the surface of the initial etch stop layer 403a are formed on the surface of the semiconductor substrate 400.

[0110] Step S14: etching the first dielectric layer to form a first trench.

[0111] In the embodiment of the present disclosure, the first dielectric layer 404 can be etched by a dry etching process or a wet etching process to form the following Figure 4b As shown in the first trench A1, the opening size of the first trench A1 is wl.

[0112] Next, you can refer to Figure 4c and 4d , executing step S302, forming an initial buffer layer on the surface of the first dielectric layer and the inner wall of the first trench.

[0113] In some embodiments, before forming the initial buffer layer, the method for forming a semiconductor structure includes:

[0114] An initial bonding layer is formed on the surface of the first dielectric layer and inside the first trench.

[0115] The initial bonding layer includes a bonding material; the bonding material includes at least one or any combination of silicon oxide, silicon nitride, silicon carbon nitride and silicon oxynitride.

[0116] In the embodiment of the present disclosure, a bonding material is deposited on the surface of the first dielectric layer and the inner wall of the first trench by any suitable deposition method, for example, an atomic layer deposition process, to form an initial bonding layer.

[0117] like Figure 4c As shown, a bonding material is deposited on the surface of the first dielectric layer 404 and the inner wall of the first trench A1 to form an initial bonding layer 405 a . The initial bonding layer 405 a does not fill the first trench A1 .

[0118] The initial buffer layer includes a buffer material with a relatively low elastic modulus. After the initial bonding layer is formed, the buffer material is deposited on the surface of the initial bonding layer to form the initial buffer layer. The buffer material includes at least one of an organic material, an inorganic material, and a composite material, or any combination thereof.

[0119] like Figure 4d As shown, a bonding material is deposited on the surface of the initial bonding layer 405 a to form an initial buffer layer 406 a . The initial buffer layer 406 a does not fill the first trench A1 .

[0120] Next, you can refer to Figure 4e , executing step S303 , removing a portion of the initial buffer layer and a portion of the first dielectric layer at the bottom of the first trench, forming a second trench and a buffer layer penetrating the first dielectric layer.

[0121] In some embodiments, step S303 may be implemented by the following steps:

[0122] A portion of the initial buffer layer, a portion of the initial bonding layer, a portion of the first dielectric layer and a portion of the initial etch stop layer at the bottom of the first trench is removed to form a second trench penetrating the first dielectric layer and the initial etch stop layer.

[0123] A portion of the initial buffer layer 406a, a portion of the initial bonding layer 405a, a portion of the first dielectric layer 404a and a portion of the initial etch stop layer 403a at the bottom of the first trench A1 are removed to form Figure 4e A second trench A2 is shown extending through the first dielectric layer and the initial etch-stop layer. The opening dimension of the second trench A2 is w2, and the opening dimension w2 of the second trench A2 is smaller than the opening dimension w1 of the first trench A1. The remaining initial buffer layer, the remaining initial bonding layer, and the remaining initial etch-stop layer form a buffer layer 406, a bonding layer 405, and an etch-stop layer 403, respectively.

[0124] In the embodiment of the present disclosure, the process of forming the first groove and the second groove using the Damascus process does not increase the additional mask cost compared to the prior art.

[0125] Next, you can refer to Figure 4f and 4g , executing step S304, filling the first trench and the second trench with metal material to form a top metal layer.

[0126] In some embodiments, the top metal layer includes a first top metal layer located in the first trench and a second top metal layer located in the second trench; step S304 can be implemented by the following steps:

[0127] Step S3041 : forming a barrier layer and a seed layer in sequence on the inner wall of the first trench and the inner walls of the buffer layer, the bonding layer and the first dielectric layer in the second trench.

[0128] Step S3042: electroplating a metal material on the surface of the seed layer to form a first top metal layer and a second top metal layer.

[0129] In the embodiment of the present disclosure, the seed layer may be a seed crystal of a metal material, and the seed layer may be deposited by physical vapor deposition.

[0130] Combine Figure 4e and Figure 4f As shown, a barrier layer 407 and a seed layer (not shown in the figure) are formed in sequence on the inner walls of the buffer layer 405 and the bonding layer 406 in the first trench A1, and the inner walls of the first dielectric layer 404 and the etch stop layer 403 in the second trench A2, and a first top metal layer 408a located in the first trench A1 and a second top metal layer 408b located in the second trench A2 are formed on the surface of the seed layer. The first top metal layer 408a and the second top metal layer 408b together form a top metal layer 408, and the second top metal layer 408b is connected to the bottom metal layer 402.

[0131] Step S3043: performing a planarization process on the first top metal layer and the buffer layer until the surface of the bonding layer is exposed.

[0132] In the embodiment of the present disclosure, the top metal layer 408 is planarized by chemical mechanical polishing (CMP) until the surface of the bonding layer 406 is exposed, forming a Figure 4g The semiconductor structure shown.

[0133] The manufacturing method of the semiconductor structure in the embodiment of the present disclosure is similar to that of the semiconductor structure in the above-mentioned embodiment. For the technical features not fully disclosed in the embodiment of the present disclosure, please refer to the above-mentioned embodiment for understanding, and no further details will be given here.

[0134] The method for manufacturing a semiconductor structure provided by the embodiment of the present disclosure can form a buffer layer located between the top metal layer and the first dielectric layer through a simple deposition process. The buffer layer can effectively accommodate the lateral expansion caused by the diffusion of the top metal layer during the bonding process of the semiconductor structure, thereby preventing the occurrence of delamination between the semiconductor structures. In addition, the embodiment of the present disclosure can improve the bonding strength between the semiconductor structures through the buffer layer, and reduce the requirements for the flatness of the bonding interface. Therefore, the difficulty of the manufacturing process of the semiconductor structure is also reduced.

[0135] The embodiment of the present disclosure provides a stacking structure. Figure 5 A schematic diagram of the stacking structure provided in the embodiment of the present disclosure is shown in FIG. Figure 5 As shown, the stacked structure 50 includes: a first wafer 501 and a second wafer 502 stacked face to face. The first wafer 501 includes a top metal layer 5012 located within a first dielectric layer 5011, a buffer layer 5013 located between the top metal layer 5012 and the first dielectric layer 5011, and a bonding layer 5014 located between the buffer layer 5013 and the first dielectric layer 5011. The second wafer 502 includes a top metal layer 5022 located within a first dielectric layer 5021, a buffer layer 5023 located between the top metal layer 5022 and the first dielectric layer 5021, and a bonding layer 5024 located between the buffer layer 5023 and the first dielectric layer 5021.

[0136] In the embodiment of the present disclosure, the top metal layer 5012 of the first wafer 501 in the stacked structure 50 is aligned with the top metal layer 5022 of the second wafer 502, the buffer layer 5013 of the first wafer 501 is aligned with the buffer layer 5023 of the second wafer 502, and the bonding layer 5014 of the first wafer 501 is aligned with the bonding layer 5024 of the second wafer 502.

[0137] In the embodiment of the present disclosure, the first wafer 501 and the second wafer 502 both have the semiconductor structure described in the above embodiment. For the technical features not disclosed in detail in the embodiment of the present disclosure, please refer to the above embodiment for understanding, and no further details will be given here.

[0138] The stacking structure provided by the embodiment of the present disclosure can improve the bonding strength between the two wafers and thereby improve the stability of the stacking structure because the top metal layer, buffer layer and bonding layer of the first wafer are completely aligned with the top metal layer, buffer layer and bonding layer of the second wafer respectively.

[0139] In addition, the present disclosure also provides a wafer stacking method. Figure 6 A schematic diagram of the process of the wafer stacking method provided in the embodiment of the present disclosure is shown in FIG. Figure 6 As shown, the stacking method includes the following steps:

[0140] Step S601: provide a first wafer and a second wafer.

[0141] In the embodiments of the present disclosure, the first wafer and the second wafer both have the semiconductor structure of the above embodiments. For example, the first wafer and the second wafer both include a top metal layer located in the first dielectric layer, a buffer layer located between the top metal layer and the first dielectric layer, and a bonding layer located between the buffer layer and the first dielectric layer; wherein the first dielectric layer is located on the surfaces of the first wafer and the second wafer, respectively.

[0142] Step S602 : Align the first wafer and the second wafer face to face to achieve stacking of the first wafer and the second wafer.

[0143] In some embodiments, step S602 may be implemented by the following steps:

[0144] Step S6021: Align the top metal layer, buffer layer and bonding layer of the first wafer face-to-face with the top metal layer, buffer layer and bonding layer of the second wafer respectively, so as to achieve stacking of the first wafer and the second wafer.

[0145] The manufacturing method of the stacking structure in the embodiment of the present disclosure is similar to the stacking structure in the above embodiment. For the technical features not fully disclosed in the embodiment of the present disclosure, please refer to the above embodiment for understanding, and no further details will be given here.

[0146] In the stacking method provided by the embodiment of the present disclosure, during the bonding process of the first wafer and the second wafer, the top metal layer, buffer layer and bonding layer of the first wafer are completely aligned with the top metal layer, buffer layer and bonding layer of the second wafer, respectively. In this way, the bonding strength between the two wafers can be improved, thereby improving the stability of the stacking structure formed.

[0147] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in non-targeted ways. The device embodiments described above are merely illustrative. For example, the division of the units is merely a logical functional division. In actual implementation, there may be other division methods, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the components shown or discussed are coupled or directly coupled to each other.

[0148] The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0149] The features disclosed in several method or device embodiments provided in this disclosure may be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0150] The above are only some implementations of the embodiments of the present disclosure, but the scope of protection of the embodiments of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the embodiments of the present disclosure should be included in the scope of protection of the embodiments of the present disclosure. Therefore, the scope of protection of the embodiments of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A semiconductor structure, characterized in that include: top metal layer, buffer layer, bonding layer, and barrier layer; Wherein, the top metal layer is located in the first dielectric layer on the surface of the semiconductor substrate, and the top metal layer penetrates the first dielectric layer; The buffer layer is located between the top metal layer and the first dielectric layer, and the material of the buffer layer is different from the material of the first dielectric layer; The bonding layer is located between the buffer layer and the first dielectric layer, and between the top metal layer and the first dielectric layer; The barrier layer is located on the outer sidewall and bottom of the top metal layer, and is respectively located between the buffer layer and the top metal layer, between the bonding layer and the top metal layer, and between the first dielectric layer and the top metal layer.

2. The semiconductor structure according to claim 1, wherein: The buffer layer includes a buffer material; the buffer material includes at least one of an organic material, an inorganic material and a composite material, or any combination thereof.

3. The semiconductor structure according to claim 2, wherein: The first dielectric layer includes a first trench and a second trench that penetrate each other; wherein the opening size of the first trench is larger than the opening size of the second trench; The top metal layer includes a first top metal layer located in the first trench and a second top metal layer located in the second trench.

4. The semiconductor structure according to claim 3, wherein: A top surface of the buffer layer is flush with a top surface of the first top metal layer.

5. The semiconductor structure according to claim 1, wherein: The bonding layer includes a bonding material; the bonding material includes at least one of silicon oxide, silicon nitride, silicon carbon nitride and silicon oxynitride, or any combination thereof. The semiconductor structure according to claim 1 , wherein: The bonding strength between the buffer layers is greater than the bonding strength between the bonding layers.

7. The semiconductor structure according to claim 1, wherein: The elastic modulus of the buffer layer is smaller than the elastic modulus of the bonding layer.

8. The semiconductor structure according to claim 3, wherein: The semiconductor structure further includes a second dielectric layer located on the surface of the semiconductor substrate and an underlying metal layer located in the second dielectric layer; wherein the first dielectric layer is located above the second dielectric layer; The bottom metal layer is connected to the second top metal layer.

9. The semiconductor structure according to claim 8, wherein: The semiconductor structure further includes an etch stop layer located between the first dielectric layer and the second dielectric layer; Wherein, the second trench penetrates the etch stop layer.

10. A method for manufacturing a semiconductor structure, characterized in that: The method comprises: A semiconductor substrate is provided, wherein a first dielectric layer is formed on a surface of the semiconductor substrate; the first dielectric layer includes a first trench, and the depth of the first trench is less than the thickness of the first dielectric layer; forming an initial bonding layer on the surface of the first dielectric layer and inside the first trench; forming an initial buffer layer on the surface of the initial bonding layer, wherein the material of the buffer layer is different from the material of the first dielectric layer; removing a portion of the initial buffer layer, a portion of the initial bonding layer, and a portion of the first dielectric layer at the bottom of the first trench to form a second trench penetrating the first dielectric layer, and the remaining initial buffer layer and the remaining initial bonding layer forming a buffer layer and a bonding layer, respectively; Filling the first trench and the second trench with metal material to form a top metal layer; The top metal layer includes a first top metal layer located in the first trench and a second top metal layer located in the second trench; Filling the first trench and the second trench with metal material to form a top metal layer includes: forming a barrier layer and a seed layer in sequence on inner walls of the buffer layer and the bonding layer in the first trench and on inner walls of the first dielectric layer in the second trench; Electroplating the metal material on the surface of the seed layer to form the first top metal layer and the second top metal layer; performing a planarization process on the first top metal layer and the buffer layer until the surface of the bonding layer is exposed; The barrier layers are respectively located between the buffer layer and the top metal layer, between the bonding layer and the top metal layer, and between the first dielectric layer and the top metal layer.

11. The method according to claim 10, characterized in that Before forming the first dielectric layer, the method further includes: forming a second dielectric layer on the surface of the semiconductor substrate; forming a bottom metal layer in the second dielectric layer; An initial etch stop layer is formed on the surfaces of the second dielectric layer and the bottom metal layer; the second top metal layer is connected to the bottom metal layer, and the initial etch stop layer is located between the first dielectric layer and the second dielectric layer.

12. The method according to claim 11, characterized in that The method comprises: removing a portion of the initial buffer layer, a portion of the initial bonding layer, a portion of the first dielectric layer, and a portion of the initial etch-stop layer at the bottom of the first trench to form a second trench penetrating the first dielectric layer and the initial etch-stop layer; The remaining initial etch stop layer forms an etch stop layer.

13. A stacking structure, characterized in that: include: A first wafer and a second wafer stacked face to face; each of the first wafer and the second wafer has at least the semiconductor structure according to any one of claims 1 to 9; The top metal layer of the first wafer is aligned with the top metal layer of the second wafer, the buffer layer of the first wafer is aligned with the buffer layer of the second wafer, and the bonding layer of the first wafer is aligned with the bonding layer of the second wafer.

14. The stacking structure according to claim 13, wherein: The bonding strength between the buffer layers is greater than the bonding strength between the bonding layers.

15. The stacking structure according to claim 13, wherein: The elastic modulus of the buffer layer is smaller than the elastic modulus of the bonding layer.

16. A wafer stacking method, characterized in that: The method comprises: Providing a first wafer and a second wafer having the semiconductor structure according to any one of claims 1 to 9; The first wafer and the second wafer are aligned face to face to achieve stacking of the first wafer and the second wafer.

17. The method according to claim 16, characterized in that The first wafer and the second wafer each include a top metal layer located in a first dielectric layer, a buffer layer located between the top metal layer and the first dielectric layer, and a bonding layer located between the buffer layer and the first dielectric layer; wherein the first dielectric layer is located on the surface of the first wafer and the second wafer, respectively; The step of aligning the first wafer and the second wafer face to face to achieve stacking of the first wafer and the second wafer includes: The top metal layer, buffer layer and bonding layer of the first wafer are respectively aligned face-to-face with the top metal layer, buffer layer and bonding layer of the second wafer to achieve stacking of the first wafer and the second wafer.

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