Method for manufacturing a gate electrode

Abstract

This invention provides a method for fabricating a gate, comprising, after etching a polysilicon layer to form the gate, performing a first isotropic etching to remove the native oxide on the gate sidewalls, and performing a second isotropic etching to remove the stripe morphology on the gate sidewalls. This invention adds two isotropic etching steps after the gate etching, and by controlling the etching parameters of these two steps, avoids stripe phenomena on the gate sidewalls, thereby improving the gate sidewall morphology and enhancing device stability.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more particularly to a method for fabricating a gate. Background Technology

[0002] RFLDMOS (Radio Frequency Lateral Double-diffused MOSFET) has advantages such as high operating frequency, high voltage withstand, high output power, high gain, and high linearity, and is widely used in mobile base stations, broadcast television base stations, broadband frequency modulation transmitters, airborne transponders, radar systems, etc.

[0003] Gate morphology has a significant impact on threshold voltage. In the fabrication of RFLDMOS devices, polysilicon gates are formed by etching polysilicon. If the gate morphology after etching is unstable, it will affect the threshold voltage of the device, thereby impacting its performance. However, in the gate of RFLDMOS products, due to polysilicon grain roughness, the sidewall striations of the gate are quite severe during the typical etching process of the gate polysilicon. Figure 1 As shown, a layer of native oxide easily forms on the sidewalls, preventing subsequent polyOE etching from improving this striation morphology and thus complicating the morphology of the etched sidewalls and bottom. Therefore, a gate fabrication method is urgently needed to improve the gate sidewall morphology. Summary of the Invention

[0004] The purpose of this invention is to provide a method for fabricating a gate by adding two isotropic etching steps during the gate etching process to improve the gate sidewall morphology and enhance device stability.

[0005] To achieve the above objectives, the present invention provides a method for fabricating a gate, comprising:

[0006] A substrate is provided on which a gate oxide layer and a polysilicon layer are sequentially formed;

[0007] The gate is formed by etching the polysilicon layer.

[0008] The first isotropic etching is performed to remove the native oxide from the gate sidewalls;

[0009] A second isotropic etching process is performed to remove the stripe morphology of the gate sidewalls.

[0010] Optionally, the process of etching the polysilicon layer to form the gate includes:

[0011] A patterned bottom anti-reflective layer and a photoresist layer are formed on the polysilicon layer;

[0012] The polysilicon layer is etched using a patterned bottom anti-reflective layer and a photoresist layer as a mask.

[0013] Optionally, the etching of the polysilicon layer includes: pre-etching, main etching, landing etching, and over-etching.

[0014] Optionally, the etching gas used in the first isotropic etching includes a fluorine-based gas.

[0015] Optionally, the fluorine-based gas includes one or a combination of at least two of CF4, CH2F2, and CHF3.

[0016] Optionally, the bias power in the first isotropic etching is 50W to 100W.

[0017] Optionally, the etching gas used in the second isotropic etching includes chlorine-based gases.

[0018] Optionally, the chlorine-based gas includes one or a combination of at least two of Cl2, CH2Cl2, and CH3Cl.

[0019] Optionally, the bias power in the second isotropic etching is 50W to 100W.

[0020] Optionally, the thickness of the gate oxide layer is The thickness of the polycrystalline silicon layer is The thickness of the bottom anti-reflective layer is Attached Figure Description

[0021] Figure 1 An electron microscope image of the sidewall morphology of a polysilicon gate.

[0022] Figure 2 A flowchart illustrating a method for fabricating a gate according to an embodiment of the present invention;

[0023] Figures 3A to 3D This is a schematic diagram of the structure of each step in the gate fabrication method provided in an embodiment of the present invention;

[0024] Figure 4 Electron micrograph of the sidewall morphology of a polycrystalline silicon gate fabricated using the gate fabrication method provided by the present invention.

[0025] The attached figures are labeled as follows:

[0026] 100 - Substrate; 101 - Gate oxide layer; 102 - Polysilicon layer; 103 - Bottom anti-reflection layer; 104 - Photoresist layer; 105 - Native oxide. Detailed Implementation

[0027] To make the content of this invention clearer and easier to understand, the following description, in conjunction with the accompanying drawings, further illustrates the invention. Of course, this invention is not limited to this specific embodiment, and common substitutions well-known to those skilled in the art are also covered within the scope of protection of this invention.

[0028] Secondly, the present invention is described in detail using schematic diagrams. When describing the examples of the present invention in detail, for ease of explanation, the schematic diagrams are not enlarged to a certain extent according to the general proportions, and should not be regarded as a limitation of the present invention.

[0029] For ease of description, some embodiments of the present invention may use spatially relative terms such as “above,” “below,” “top,” and “under” to describe the relationship between one element or component and another (or more) elements or components as shown in the accompanying drawings of the embodiments. It should be understood that, in addition to the orientations described in the drawings, the spatially relative terms are also intended to include different orientations of the device during use or operation. For example, if the device in the drawings is flipped, it is described as an element or component “below” or “under” other elements or components, and will subsequently be positioned “above” or “on” other elements or components. The terms “first,” “second,” etc., used below are used to distinguish between similar elements and are not necessarily used to describe a particular order or temporal sequence.

[0030] Figure 2 This is a schematic flowchart of a gate fabrication method provided in this embodiment, as shown below. Figure 2 As shown, the gate fabrication method proposed in this embodiment includes the following steps:

[0031] Step S01: Provide a substrate, and sequentially form a gate oxide layer and a polysilicon layer on the substrate;

[0032] Step S02: Etch the polysilicon layer to form the gate;

[0033] Step S03: Perform a first isotropic etching to remove the native oxide on the gate sidewalls; and,

[0034] Step S04: Perform a second isotropic etching to remove the stripe morphology of the gate sidewall.

[0035] Figures 3A to 3D This is a schematic diagram illustrating the structural steps of a gate fabrication method according to an embodiment of the present invention. Please refer to... Figure 2 As shown, and in combination Figures 3A to 3D The present invention provides a detailed description of the method for fabricating the gate.

[0036] First, refer to Figure 3AAs shown, in step S01, a substrate 100 is provided, and a gate oxide layer 101 and a polysilicon layer 102 are sequentially formed on the substrate 100.

[0037] Specifically, a substrate 100 is provided, which can be single-crystal silicon (Si), single-crystal germanium (Ge), silicon-germanium (GeSi), or silicon carbide (SiC), or silicon-on-insulator (SOI) or germanium-on-insulator (GOI); or it can be other materials, such as gallium arsenide or other III-V compounds. In this embodiment, the substrate 100 is only used as an example of a silicon substrate, and this is only an example; the present invention is not limited thereto.

[0038] Furthermore, this embodiment takes an RFLDMOS (Radio Frequency Lateral Double-diffused MOSFET) as an example. An epitaxial layer is formed within the substrate 100, and a channel region and a drift region are formed within the epitaxial layer. An active region and a body region are formed within the channel region, and a drain region is formed on one side of the drift region. The gate oxide layer (GOX) 101 is formed on the epitaxial layer. The aforementioned epitaxial layer, channel region, active region, body region, drift region, and drain region are formed using conventional methods in RFLDMOS fabrication processes, which will not be elaborated upon here and are not shown in the figures.

[0039] Next, refer to Figure 3A and Figure 3B As shown, step S02 is performed to etch the polysilicon layer 102 to form the gate.

[0040] Specifically, the process of etching the polysilicon layer 102 to form the gate includes:

[0041] A patterned bottom anti-reflection layer 103 and a photoresist layer 104 are formed on the polysilicon layer 102;

[0042] The polysilicon layer 102 is etched using the patterned bottom anti-reflective layer 103 and photoresist layer 104 as a mask.

[0043] The etching of the polysilicon layer 102 includes: pre-etching, main etching, landing etching, and over-etching. Pre-etching (Oxide Breakthrough) removes the natural oxide layer (not shown in the figure) covering the surface of the polysilicon layer to be etched using plasma of etching gas. For example, a fluorine-based gas is used for etching. Main etching uses high-density plasma under low-pressure conditions to interact with the polysilicon layer without damaging the gate oxide layer. For example, Cl2 or HBr gas is used for etching. Landing etching (Soft-landing Etch) ensures high selectivity for the gate oxide layer, preventing damage and allowing the polysilicon etching to reach the etching endpoint (which is automatically detected by an endpoint monitoring device). Over-etching removes etching residues and remaining polysilicon. This step requires sufficient selectivity for the underlying material; a combination of HBr and O2 is generally used to increase the selectivity of the oxide and avoid damage to the gate oxide layer.

[0044] In this embodiment, the gate oxide layer 101, the polysilicon layer 102, the bottom antireflective coating (BARC) 103, and the photoresist layer (PR) 104 are stacked sequentially to form a gate stack film. The thickness of the gate oxide layer is... For example, The gate oxide layer has a slope under the formed gate, and the thickness of the gate oxide layer on the drain side is greater than that on the source side. The thickness of the polysilicon layer is... For example, The thickness of the bottom anti-reflective layer is For example,

[0045] Furthermore, after polysilicon etching, the bottom anti-reflective layer of the target area is removed by etching with a low etch ratio reactive gas. The low etch ratio reactive gas is a gas in which the ratio of the etching rate of the photoresist layer 104 to the etching rate of the bottom anti-reflective layer 103 is 1 to 2, and the low etch ratio reactive gas includes nitrogen. Removing the bottom anti-reflective layer 104 by etching with a low etch ratio reactive gas can reduce the probability of stripes generated in the etched pattern, thereby improving the reliability of the device.

[0046] Next, refer to Figure 3C and Figure 3D As shown, step S03 is performed to perform the first isotropic etching to remove the native oxide of the gate sidewall.

[0047] In the above polysilicon etching process, the striation phenomenon on the sidewalls of the polysilicon gate formed by the main etching is severe, which will form a layer of native oxide 105 on the sidewalls of the gate. This makes it impossible for subsequent over-etching of polysilicon to improve the striation morphology of the sidewalls, thus causing problems for the sidewall and bottom morphology of the gate.

[0048] The first isotropic etching is performed using a low bias power and a fluorine-based etching gas to remove part of the gate oxide layer (GOX) and the native oxide 105 on the polysilicon gate sidewall. The etching selectivity is improved and lateral etching is enhanced by adjusting the etching gas and bias voltage. In this embodiment, the bias power used is, for example, 50W to 100W, and the fluorine-based gas includes one or a combination of at least two of CF4, CH2F2, and CHF3, for example, CF4.

[0049] Etching with a fluorine-based etching gas allows for adjustment of the critical dimension (CD) of the etched gate pattern, resulting in a better etching morphology and improved device reliability. Optionally, in this embodiment, the etching time using the fluorine-based etching gas is, for example, 10 to 40 seconds.

[0050] Next, refer to Figure 3D As shown, step S04 is performed to perform a second isotropic etching to remove the stripe morphology of the gate sidewall.

[0051] After the first isotropic etching, when the gate sidewalls lose the protection of the native oxide 105, a second isotropic etching is used to improve the gate sidewall morphology and remove the striation morphology. The resulting gate sidewall morphology is as follows: Figure 4 As shown, the morphology of the gate sidewall is significantly improved.

[0052] The etching gas used in the second isotropic etching is a chlorine-based gas, which includes one or a combination of at least two of Cl2, CH2Cl2, and CH3Cl. For example, the chlorine-based gas is Cl2, and the bias power used for etching is, for example, 120W to 200W.

[0053] Furthermore, the gate fabrication method provided in this embodiment also includes: forming metal silicides on the source region, drain region, and gate; forming a Faraday shield on the portion of the gate near the drain region and on the portion of the drift region near the gate; the Faraday shield is stepped, which reduces the resistance of the Faraday shield to ground and effectively improves the broadband performance and reliability of the device at high frequencies.

[0054] It should be understood that many other layers may also be present in the gate fabrication method provided in this embodiment, such as spacer elements and / or other suitable components, which are omitted in the figures for simplicity.

[0055] In summary, the present invention provides a method for fabricating a gate in which, after etching the polysilicon layer to form the gate, a first isotropic etching is performed to remove the native oxide on the gate sidewalls, and a second isotropic etching is performed to remove the stripe morphology on the gate sidewalls. The present invention adds two isotropic etching steps after the gate etching, and by controlling the etching parameters of these two isotropic etching steps, the stripe phenomenon on the gate sidewalls is eliminated, the gate sidewall morphology is improved, and the stability of the device is enhanced.

[0056] While the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the invention. Any person skilled in the art can make many possible variations and modifications to the technical solutions of the present invention, or modify them into equivalent embodiments, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the scope of the present invention, shall still fall within the protection scope of the present invention.

Claims

1. A method of fabricating a gate, comprising: include: A substrate is provided on which a gate oxide layer and a polysilicon layer are sequentially formed; The gate is formed by etching the polysilicon layer. The first isotropic etching is performed to remove the native oxide on the gate sidewall. The etching gas used in the first isotropic etching includes fluorine-based gas, and the bias power in the first isotropic etching is 50W~100W. A second isotropic etching process is performed to remove the stripe morphology of the gate sidewall. The etching gas used in the second isotropic etching includes chlorine-based gas, and the bias power in the second isotropic etching is 120W~200W.

2. The method of claim 1, wherein The process of etching the polysilicon layer to form the gate includes: A patterned bottom anti-reflective layer and a photoresist layer are formed on the polysilicon layer; The polysilicon layer is etched using a patterned bottom anti-reflective layer and a photoresist layer as a mask.

3. The method of claim 2, wherein The etching of the polysilicon layer includes: pre-etching, main etching, landing etching, and over-etching.

4. The method for fabricating a gate according to claim 1, characterized in that, The fluorine-based gas includes one or a combination of at least two of CF4, CH2F2, and CHF3.

5. The method of claim 1, wherein The chlorine-based gas includes one or a combination of at least two of Cl2, CH2Cl2, and CH3Cl.

6. The method of claim 2, wherein The thickness of the gate oxide layer is 300 Å to 800 Å, the thickness of the polycrystalline silicon layer is 2000 Å to 3500 Å, and the thickness of the bottom antireflective layer is 300 Å to 2000 Å.

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