Power amplifier circuit

Abstract

Provided is a power amplification circuit that suppresses a decrease in linearity. A first bias circuit that applies a bias to a first amplifier in a first mode and a second mode, and a second bias circuit that applies a bias to a second amplifier in the second mode are included. The first bias circuit includes a first transistor whose collector is connected to a power supply potential, whose emitter is connected to the first amplifier, and whose base is connected to a current source, and a second transistor and a third transistor that are diode-connected and connected between the base of the first transistor and a reference potential. The second bias circuit includes a fourth transistor whose collector is connected to the power supply potential, whose emitter is connected to the second amplifier, and whose base is connected to the current source, and a fifth transistor whose base is connected to the emitter of the fourth transistor, whose collector is connected to the base of the fourth transistor, and whose emitter is connected to the reference potential.

Description

TECHNICAL FIELD

[0001] The present application relates to a power amplification circuit. BACKGROUND

[0002] A high-frequency amplifier provided with a bias circuit having a feedback loop is described in Patent Document 1 below.

[0003] PRIOR ART DOCUMENTS

[0004] PATENT DOCUMENT

[0005] Patent Document 1: Japanese Patent Application Publication No. 2009-165100 SUMMARY

[0006] PROBLEMS TO BE SOLVED BY THE INVENTION

[0007] In a power amplification circuit mounted on a wireless communication terminal device, in order to change the output level in accordance with the distance from a base station to the terminal, it is sometimes necessary to switch the output power. For example, the power amplification circuit sometimes needs to switch the amplification operation in a first output power that is relatively low (hereinafter sometimes referred to as "low power mode") and the amplification operation in a second output power that is relatively high (hereinafter sometimes referred to as "high power mode").

[0008] When the bias circuit described in Patent Document 1 is used to impart bias to the transistor for amplification in both the low power mode and the high power mode, gain compression occurs, the adjacent channel leakage power ratio (ACLR: Adjacent Channel Leakage Power Ratio) deteriorates, and the linearity can decrease.

[0009] The present application was made in view of the above, and aims to suppress a decrease in linearity.

[0010] MEANS FOR SOLVING THE PROBLEM

[0011] The power amplification circuit according to one aspect of the present application includes: a first amplifier that amplifies a high-frequency signal in both a first mode and a second mode in which an output power is relatively higher than in the first mode; a second amplifier that amplifies the high-frequency signal in the second mode; a first bias circuit that applies a bias to the first amplifier in both the first mode and the second mode; and a second bias circuit that applies a bias to the second amplifier in the second mode. The first bias circuit includes: a first transistor whose collector is electrically connected to a power supply potential, whose emitter is electrically connected to the first amplifier, and whose base is electrically connected to a current source; and second and third transistors that are diode-connected and connected in series between the base of the first transistor and a reference potential. The second bias circuit includes: a fourth transistor whose collector is electrically connected to the power supply potential, whose emitter is electrically connected to the second amplifier, and whose base is electrically connected to the current source; and a fifth transistor whose base is electrically connected to the emitter of the fourth transistor, whose collector is electrically connected to the base of the fourth transistor, and whose emitter is electrically connected to the reference potential.

[0012] Effects of the Invention

[0013] According to the present application, it is possible to suppress a decrease in linearity. BRIEF DESCRIPTION OF DRAWINGS

[0014] Figure 1 FIG. 1 is a diagram showing the structure of a power amplification circuit according to an embodiment.

[0015] Figure 2 FIG. 2 is a diagram showing the structure of a driver stage amplifier of the power amplification circuit according to the embodiment.

[0016] Figure 3 FIG. 3 is a diagram showing the structure of a first power stage amplifier of the power amplification circuit according to the embodiment.

[0017] Figure 4 FIG. 4 is a diagram showing the structure of an emitter follower type bias circuit of the power amplification circuit according to the embodiment.

[0018] Figure 5 FIG. 5 is a diagram showing the structure of a feedback type bias circuit of the power amplification circuit according to the embodiment.

[0019] Figure 6 FIG. 6 is a diagram showing the structure of an emitter follower type bias circuit of the power amplification circuit according to the embodiment.

[0020] Figure 7 FIG. 7 is a diagram showing the structure of a power amplification circuit according to a comparative example.

[0021] Figure 8FIG. 1 is a graph showing characteristics of a power amplification circuit of the embodiment and a power amplification circuit of a comparative example.

[0022] Figure 9 FIG. 1 is a graph showing characteristics of a power amplification circuit of the embodiment and a power amplification circuit of a comparative example.

[0023] Figure 10 FIG. 1 is a graph showing characteristics of a power amplification circuit of the embodiment and a power amplification circuit of a comparative example.

[0024] Figure 11 FIG. 1 is a graph showing characteristics of a power amplification circuit of the embodiment and a power amplification circuit of a comparative example.

[0025] Figure 12 FIG. 1 is a graph showing characteristics of a power amplification circuit of the embodiment and a power amplification circuit of a comparative example.

[0026] Figure 13 FIG. 1 is a graph showing characteristics of a power amplification circuit of the embodiment and a power amplification circuit of a comparative example.

[0027] Figure 14 FIG. 1 is a graph showing characteristics of a power amplification circuit of the embodiment and a power amplification circuit of a comparative example.

[0028] Figure 15 FIG. 1 is a graph showing characteristics of a power amplification circuit of the embodiment and a power amplification circuit of a comparative example.

[0029] Figure 16 FIG. 1 is a graph showing characteristics of a power amplification circuit of the embodiment and a power amplification circuit of a comparative example.

[0030] Figure 17 FIG. 1 is a graph showing characteristics of a power amplification circuit of the embodiment and a power amplification circuit of a comparative example.

[0031] BRIEF DESCRIPTION OF DRAWINGS

[0032] 1, 101 power amplification circuit;

[0033] 2, 12 balun;

[0034] 11 driver stage amplifier;

[0035] 13 first power stage amplifier;

[0036] 14 second power stage amplifier;

[0037] 15, 17 emitter follower bias circuit;

[0038] 16, 18 feedback bias circuit;

[0039] 21, 31 first amplifier;

[0040] 22, 32 second amplifier. DETAILED DESCRIPTION

[0041] Hereinafter, embodiments of the power amplification circuit of the present application will be described in detail based on the drawings. Note that the present application is not limited by the embodiments. The embodiments are examples, and partial substitution or combination of the structures shown in different embodiments is of course possible.

[0042] <EMBODIMENT>

[0043] (Circuit configuration)

[0044] Figure 1 is a diagram showing the configuration of the power amplification circuit of the embodiment. The power amplification circuit 1 is a differential amplification circuit that amplifies a high-frequency signal RFin and outputs a differential signal of high-frequency signals PAoutL and PAoutR to both ends of the primary winding of a balun 2.

[0045] In the embodiment, the power amplification circuit 1 is provided as a differential amplification circuit, but the present disclosure is not limited to this. The power amplification circuit 1 can also be a single-ended amplification circuit.

[0046] One end of the primary winding of the balun 2 is connected to the output of a first power stage amplifier 13 described later, and the other end of the primary winding of the balun 2 is connected to the output of a second power stage amplifier 14 described later. One end of the secondary winding of the balun 2 is electrically connected to a reference potential. The reference potential is exemplified by a ground potential, but the present disclosure is not limited to this. A high-frequency signal RFout is output from the other end of the secondary winding of the balun 2.

[0047] The power amplification circuit 1 has an amplification operation at a relatively low first output power (hereinafter, sometimes referred to as "low power mode") and an amplification operation at a relatively high second output power (hereinafter, sometimes referred to as "high power mode").

[0048] The low power mode corresponds to an example of the "first mode" of the present disclosure. The high power mode corresponds to an example of the "second mode" of the present disclosure.

[0049] The power amplification circuit 1 includes a driver stage amplifier 11, a balun 12, a first power stage amplifier 13, a second power stage amplifier 14, emitter follower type bias circuits 15 and 17, and a feedback type bias circuit 16.

[0050] The driver stage amplifier 11 operates in both the low power mode and the high power mode. The driver stage amplifier 11 amplifies the high frequency signal RFin and outputs the high frequency signal RF1 to one end of the primary winding of the balun 12.

[0051] The driver stage amplifier 11 corresponds to an example of the "third amplifier" of the present disclosure.

[0052] Figure 2 is a diagram showing the structure of the driver stage amplifier of the power amplification circuit of the embodiment.

[0053] The driver stage amplifier 11 includes capacitors 41 and 44, resistors 42 and 45, a transistor 43, and a choke coil 46.

[0054] In the present disclosure, each transistor is a bipolar transistor, but the present disclosure is not limited thereto. The bipolar transistor exemplifies a heterojunction bipolar transistor (HBT), but the present disclosure is not limited thereto. The transistor may, for example, also be a field effect transistor (FET). The transistor can also be a multi-finger transistor in which a plurality of unit transistors are electrically connected in parallel. The unit transistor refers to the smallest structure constituting the transistor.

[0055] The index of the transistor 43 can be changed according to the specifications required for the power amplification circuit 1.

[0056] The emitter of the transistor 43 is electrically connected to a reference potential. The high frequency signal RFin is input to the base of the transistor 43 via the capacitor 41. The capacitor 41 is a DC cut capacitor that cuts the DC component of the high frequency signal RFin.

[0057] The base of the transistor 43 is input with the bias current BIAS 11 from the emitter follower type bias circuit 15 (see Figure 1 ).

[0058] The collector of the transistor 43 is electrically connected to the power supply potential Vcc1 via the choke coil 46.

[0059] The capacitor 44 and the resistor 45 are connected in series between the collector of the transistor 43 and the input terminal of the driver stage amplifier 11 to apply negative feedback.

[0060] The transistor 43 amplifies the high frequency signal RFin and outputs the high frequency signal RF1 from the collector to one end of the primary winding of the balun 12 (see Figure 1 ). That is, the output (collector) of the transistor 43 and one end of the primary winding of the balun 12 are connected to each other.

[0061] Referring again to Figure 1 When the low power mode is selected, the other end of the primary winding of the balun 12 is electrically connected to the reference potential. High frequency signals RF2 and RF3 constituting a differential signal are output from both ends of the secondary winding of the balun 12. The differential signal is a signal in which phases are substantially opposite to each other. Note that "substantially opposite" includes not only a case where phases are opposite to each other by 180°, but also a case where phases are opposite to each other by 135° to 225°.

[0062] The first power stage amplifier 13 includes a first amplifier 21 and a second amplifier 22. The first amplifier 21 operates in both the low power mode and the high power mode. The second amplifier 22 operates in the high power mode.

[0063] The first amplifier 21 corresponds to an example of the "first amplifier" of the present disclosure. The second amplifier 22 corresponds to an example of the "second amplifier" of the present disclosure.

[0064] The second power stage amplifier 14 includes a first amplifier 31 and a second amplifier 32. The first amplifier 31 operates in both the low power mode and the high power mode. The second amplifier 32 operates in the high power mode.

[0065] The first amplifier 31 corresponds to an example of the "first amplifier" of the present disclosure. The second amplifier 32 corresponds to an example of the "second amplifier" of the present disclosure.

[0066] Figure 3 is a diagram showing the structure of the first power stage amplifier of the power amplifying circuit of the embodiment.

[0067] Note that the circuit structure of the second power stage amplifier 14 (see Figure 1 ) is the same as that of the first power stage amplifier 13, and thus the description is omitted.

[0068] The first amplifier 21 includes capacitors 51 and 53, a resistor 52, and a transistor 54. The capacitor 51 is provided between the base of the transistor 54 and a node at which the high frequency signal RF2 is input, but can be provided on the side opposite to the transistor 54 of the node at which the high frequency signal RF2 is input. In addition, the capacitor 53 can be omitted.

[0069] The emitter of the transistor 54 is electrically connected to the reference potential. The high frequency signal RF2 is input to the base of the transistor 54 via the capacitor 51. The capacitor 51 is a DC cut capacitor that cuts a DC component of the high frequency signal RF2.

[0070] The emitter follower type bias circuit 17 (see Figure 1) via the resistor 52 to the base of the transistor 54 21 .

[0071] The collector of the transistor 54 is electrically connected to the power supply potential Vcc2 via the choke coil 59.

[0072] The capacitor 53 is connected between the base of the transistor 54 and the reference potential. The capacitor 53 shunts the high-frequency component of the high-frequency signal RF2 to the reference potential.

[0073] The second amplifier 22 includes the capacitors 55 and 57, the resistor 56, and the transistor 58. The capacitor 55 is provided between the base of the transistor 58 and the node from which the high-frequency signal RF2 is input, but can also be provided on the side opposite to the transistor 58 from the node from which the high-frequency signal RF2 is input. In addition, the capacitor 57 can also be omitted.

[0074] The emitter of the transistor 58 is electrically connected to the reference potential. The high-frequency signal RF2 is input to the base of the transistor 58 via the capacitor 55. The capacitor 55 is a DC cut capacitor that cuts the DC component of the high-frequency signal RF2.

[0075] The bias current BIAS is input to the base of the transistor 58 via the resistor 56 from the feedback-type bias circuit 16 (refer to Figure 1 ). 22 .

[0076] The collector of the transistor 58 is electrically connected to the power supply potential Vcc2 via the choke coil 59.

[0077] The capacitor 57 is connected between the base of the transistor 58 and the reference potential. The capacitor 57 shunts the high-frequency component of the high-frequency signal RF2 to the reference potential.

[0078] The transistors 54 and 58 amplify the high-frequency signal RF2 and output the high-frequency signal PAoutL to one end of the primary winding of the balun 2 (refer to Figure 1 ).

[0079] The indices of the transistors 54 and 58 can be changed according to the specifications required of the power amplification circuit 1.

[0080] For example, the index of the transistor 54 can be larger than the index of the transistor 58.

[0081] Thus, in the case where a relatively large output power is required in the low power mode, the power amplification circuit 1 can increase its output power.

[0082] For example, the index of the transistor 54 can be smaller than the index of the transistor 58.

[0083] Thus, the power amplification circuit 1 can reduce the output power in the low power mode and suppress the consumed current. That is, it is easy to obtain a power amplification circuit that can balance power mode switching and consumed current reduction.

[0084] For example, the index of the transistor 54 can also be the same as that of the transistor 58.

[0085] From the viewpoint of symmetry, it is preferable that the index of the transistor 54 in the first amplifier 31 of the second power stage amplifier 14 be the same as that of the transistor 54 in the first amplifier 21 of the first power stage amplifier 13. It is preferable that the index of the transistor 58 in the second amplifier 32 of the second power stage amplifier 14 be the same as that of the transistor 58 in the second amplifier 22 of the first power stage amplifier 13.

[0086] The index of the transistor 43 (see Figure 2 ) in the driver stage amplifier 11 can be the same as that of the transistor 54 in the first amplifier 21 of the first power stage amplifier 13, or can be different. The index of the transistor 43 in the driver stage amplifier 11 can be the same as that of the transistor 58 in the second amplifier 22 of the first power stage amplifier 13, or can be different. Note that in the case where the index of the transistor in the driver stage amplifier is different from that of the transistor in the power stage amplifier, impedance adjustment can be performed separately in the driver stage amplifier and the power stage amplifier. Thus, it is easy to more appropriately perform impedance matching of the power amplification circuit.

[0087] Again referring to Figure 1 , a bias current IB1 is input from an external current source to the emitter follower type bias circuit 15. The emitter follower type bias circuit 15 outputs a bias current BIAS 11 to the driver stage amplifier 11 on the basis of the bias current IB1. The emitter follower type bias circuit 15 outputs the bias current BIAS 11 in both the low power mode and the high power mode.

[0088] The emitter follower type bias circuit 15 corresponds to an example of the "third bias circuit" of the present disclosure.

[0089] Figure 4 is a diagram showing the structure of the emitter follower type bias circuit of the power amplification circuit of the embodiment.

[0090] The emitter follower type bias circuit 15 includes a resistor 61, transistors 62, 63, and 65, and a capacitor 64.

[0091] The transistor 65 corresponds to an example of the "sixth transistor" of the present disclosure. The transistors 62 and 63 correspond to an example of the "seventh transistor and eighth transistor" of the present disclosure.

[0092] A bias current IB1 is input to one end of the resistor 61. The other end of the resistor 61 is electrically connected to the node N1.

[0093] The collector and the base of the transistor 62 are electrically connected to the node N1. That is, the transistor 62 is diode-connected. The emitter of the transistor 62 is electrically connected to the collector and the base of the transistor 63. That is, the transistor 63 is diode-connected. The emitter of the transistor 63 is electrically connected to the reference potential.

[0094] The transistors 62 and 63 generate a fixed voltage. The voltage generated by the transistors 62 and 63 is the voltage of the node N1.

[0095] One end of the capacitor 64 is electrically connected to the node N1. The other end of the capacitor 64 is electrically connected to the reference potential. The capacitor 64 stabilizes the voltage of the node N1.

[0096] The collector of the transistor 65 is electrically connected to the power supply potential Vbat. The base of the transistor 65 is electrically connected to the node N1. The emitter of the transistor 65 is electrically connected to one end of the resistor 42 (refer to Figure 2 ). The transistor 65 outputs a bias current BIAS 11 from the emitter to one end of the resistor 42.

[0097] Again referring to Figure 1 , a bias current IB2 is input from an external current source to the feedback-type bias circuit 16. The feedback-type bias circuit 16 outputs a bias current BIAS 22 to the second amplifier 22 in the first power stage amplifier 13 and a bias current BIAS 32 to the second amplifier 32 in the second power stage amplifier 14, based on the bias current IB2. The feedback-type bias circuit 16 outputs the bias currents BIAS 22 and BIAS 32 in the case of the high-power mode.

[0098] The feedback-type bias circuit 16 corresponds to an example of the "second bias circuit" of the present disclosure.

[0099] Figure 5 is a diagram showing the structure of the feedback-type bias circuit of the power amplification circuit of the embodiment.

[0100] The feedback-type bias circuit 16 includes resistors 71, 75, and 77, transistors 72, 76, and 78, and capacitors 73 and 74. Note that the resistor 71 and the capacitor 74 can not be provided.

[0101] The transistors 76 and 78 each correspond to an example of the "fourth transistor" of the present disclosure. The transistor 72 corresponds to an example of the "fifth transistor" of the present disclosure.

[0102] A bias current IB2 is input to one end of a resistor 71. The other end of the resistor 71 is electrically connected to a node N2.

[0103] The collector of a transistor 72 is electrically connected to the node N2. The emitter of the transistor 72 is electrically connected to a reference potential. A capacitor 73 is electrically connected between the collector and the base of the transistor 72. The capacitor 73 shunts a high frequency signal.

[0104] One end of a capacitor 74 is electrically connected to the node N2. The other end of the capacitor 74 is electrically connected to the reference potential. The capacitor 74 stabilizes the voltage of the node N2.

[0105] The collector of a transistor 76 is electrically connected to a power supply potential Vbat. The base of the transistor 76 is electrically connected to the node N2. The emitter of the transistor 76 is electrically connected to one end of a resistor 56 (refer to Figure 3 ) in the second power stage amplifier 22. A resistor 75 is electrically connected between the emitter of the transistor 76 and the base of the transistor 72.

[0106] A negative feedback is applied between the emitter and the base of the transistor 76 in the path of the emitter of the transistor 76 → the resistor 75 → the base of the transistor 72 → the collector of the transistor 72 → the node N2 → the base of the transistor 76. The transistor 76 outputs a bias current BIAS 22 from the emitter to one end of the resistor 56 in the second power stage amplifier 22.

[0107] The collector of a transistor 78 is electrically connected to the power supply potential Vbat. The base of the transistor 78 is electrically connected to the node N2. The emitter of the transistor 78 is electrically connected to one end of the resistor 56 (refer to Figure 3 ) in the second power stage amplifier 32. A resistor 77 is electrically connected between the emitter of the transistor 78 and the base of the transistor 72.

[0108] A negative feedback is applied between the emitter and the base of the transistor 78 in the path of the emitter of the transistor 78 → the resistor 77 → the base of the transistor 72 → the collector of the transistor 72 → the node N2 → the base of the transistor 78. The transistor 78 outputs a bias current BIAS 32 from the emitter to one end of the resistor 56 in the second power stage amplifier 32.

[0109] Referring again to Figure 1 , a bias current IB3 is input from an external current source to the emitter follower bias circuit 17. The emitter follower bias circuit 17 outputs a bias current BIAS 21 to the first amplifier 21 in the first power stage amplifier 13 and a bias current BIAS 31The emitter follower type bias circuit 17 outputs the bias current BIAS 21 and BIAS 31 .

[0110] The emitter follower type bias circuit 17 corresponds to an example of the "first bias circuit" of the present disclosure.

[0111] Figure 6 is a diagram showing the structure of the emitter follower type bias circuit of the power amplification circuit of the embodiment.

[0112] The emitter follower type bias circuit 17 includes a resistor 81, transistors 82, 83, 85, and 86, and a capacitor 84.

[0113] The transistors 85 and 86 respectively correspond to an example of the "first transistor" of the present disclosure. The transistors 82 and 83 correspond to an example of the "second transistor and third transistor" of the present disclosure.

[0114] The bias current IB3 is input to one end of the resistor 81. The other end of the resistor 81 is electrically connected to the node N3.

[0115] The collector and base of the transistor 82 are electrically connected to the node N3. That is, the transistor 82 is diode-connected. The emitter of the transistor 82 is electrically connected to the collector and base of the transistor 83. That is, the transistor 83 is diode-connected. The emitter of the transistor 83 is electrically connected to the reference potential.

[0116] The transistors 82 and 83 generate a fixed voltage. The voltage generated by the transistors 82 and 83 is the voltage of the node N3.

[0117] One end of the capacitor 84 is electrically connected to the node N3. The other end of the capacitor 84 is electrically connected to the reference potential. The capacitor 84 stabilizes the voltage of the node N3.

[0118] The collector of the transistor 85 is electrically connected to the power supply potential Vbat. The base of the transistor 85 is electrically connected to the node N3. The emitter of the transistor 85 is electrically connected to one end of the resistor 52 (refer to Figure 3 ) in the first amplifier 21. That is, the transistor 85 and the resistor 52 in the first amplifier 21 are emitter-follower-connected. The transistor 85 outputs the bias current BIAS 21 from the emitter to one end of the resistor 52 in the first amplifier 21.

[0119] The collector of the transistor 86 is electrically connected to the power supply potential Vbat. The base of the transistor 86 is electrically connected to the node N3. The emitter of the transistor 86 is electrically connected to one end of the resistor 52 (refer to Figure 2The other end of the resistor 52 is electrically connected to the emitter of the transistor 86. That is, the transistor 86 and the resistor 52 in the first amplifier 31 are connected in an emitter follower connection. The transistor 86 outputs a bias current BIAS from the emitter to one end of the resistor 52 in the first amplifier 31 31 .

[0120] In the power amplification circuit 1 of the embodiment, the emitter follower type bias circuit 15 and the emitter follower type bias circuit 17 are provided as different bias circuits.

[0121] Thus, the power amplification circuit 1 can individually control the drive stage amplifier 11 and the first power stage amplifier 13 and the second power stage amplifier 14. In the drive stage amplifier and the power stage amplifiers, their amplification rates and the like are also mostly different, and thus, by individually controlling them as such, they act in appropriate states, respectively, and it is easy to improve the characteristics.

[0122] (Comparative Example)

[0123] Figure 7 is a view showing the structure of the power amplification circuit of the comparative example.

[0124] The power amplification circuit 101 of the comparative example includes the feedback type bias circuit 18 instead of the emitter follower type bias circuit 17, as compared with the power amplification circuit 1 (refer to Figure 1 ) of the embodiment.

[0125] The feedback type bias circuit 18 outputs the bias currents BIAS 21 and BIAS 31 in both the low power mode and the high power mode.

[0126] The structure of the feedback type bias circuit 18 is the same as that of the feedback type bias circuit 16, and thus, the illustration and the description are omitted.

[0127] (Comparison between the Embodiment and the Comparative Example)

[0128] Figure 8 to Figure 13 is a view showing the characteristics of the power amplification circuit of the embodiment and the power amplification circuit of the comparative example.

[0129] Figure 8 is a view showing the relationship between the gain and the output power of the drive stage amplifier 11 of the power amplification circuit 1 and the power amplification circuit 101 in the case of the high power mode. In Figure 8 , the vertical axis represents the gain of the drive stage amplifier 11, and the horizontal axis represents the output power of the drive stage amplifier 11.

[0130] The waveform 111 shows the relationship between the gain and the output power of the driver stage amplifier 11 of the power amplification circuit 1. The waveform 112 shows the relationship between the gain and the output power of the driver stage amplifier 11 of the power amplification circuit 101.

[0131] The power amplification circuit 1 and the power amplification circuit 101 each have the emitter follower type bias circuit 15, and thus, it is possible to extend the power to a high output power.

[0132] Figure 9 FIG. 7 is a graph showing the relationship between the gain and the output power of the first power stage amplifier 13 and the second power stage amplifier 14 of the power amplification circuit 1 and the power amplification circuit 101 in the case of the high power mode. In Figure 9 , the vertical axis represents the gain of the first power stage amplifier 13 and the second power stage amplifier 14, and the horizontal axis represents the output power of the first power stage amplifier 13 and the second power stage amplifier 14.

[0133] The waveform 113 shows the relationship between the gain and the output power of the first power stage amplifier 13 and the second power stage amplifier 14 of the power amplification circuit 1. The waveform 114 shows the relationship between the gain and the output power of the first power stage amplifier 13 and the second power stage amplifier 14 of the power amplification circuit 101.

[0134] In the power amplification circuit 101, the feedback type bias circuit 18 outputs the bias current BIAS 21 and the bias current BIAS 31 to the first amplifier 21 and the first amplifier 31. In order to maintain the linearity on the characteristics of the feedback type bias circuit 18, as shown in the waveform 114, the gain compression is applied to the first amplifier 21 and the first amplifier 31, and the gain at the high output power has a tendency to slowly decrease. This relates to the deterioration of the distortion characteristics in the vicinity of the linear power region.

[0135] On the other hand, in the power amplification circuit 1, in order to improve the linearity in the vicinity of the linear power region, as shown in Figure 8 , the emitter follower type bias circuit 17, which is capable of extending the power to a high output power, outputs the bias current BIAS 31 21 and the bias current BIAS 31 to the first amplifier 21 and the first amplifier 31. Thus, in the power amplification circuit 1, as shown in the waveform 113, the gain compression is weaker, and the gain is higher in the case of the high output power, as compared with the waveform 114.

[0136] Figure 10 FIG. 8 is a graph showing the relationship between the gain and the output power of the entire power amplification circuit 1 and the power amplification circuit 101 in the case of the high power mode. In Figure 10In FIG. 11, the vertical axis indicates the gain of the power amplifier circuit 1 and the power amplifier circuit 101 as a whole, and the horizontal axis indicates the output power of the power amplifier circuit 1 and the power amplifier circuit 101 as a whole.

[0137] The waveform 115 shows the relationship between the gain and the output power of the power amplifier circuit 1 as a whole. The waveform 116 shows the relationship between the gain and the output power of the power amplifier circuit 101 as a whole.

[0138] As described above, in the power amplifier circuit 1, the gain of the first power stage amplifier 13 and the second power stage amplifier 14 is higher than that of the power amplifier circuit 101. Therefore, in the power amplifier circuit 1 as a whole, the gain is higher in the case of high output power as shown by the waveform 115, compared with the waveform 116.

[0139] Figure 11 FIG. 12 is a graph showing the relationship between the gain and the output power of the driver stage amplifier 11 of the power amplifier circuit 1 and the power amplifier circuit 101 in the case of the low power mode. In FIG. 12, the vertical axis indicates the gain of the driver stage amplifier 11, and the horizontal axis indicates the output power of the driver stage amplifier 11. Figure 11

[0140] The waveform 117 shows the relationship between the gain and the output power of the driver stage amplifier 11 of the power amplifier circuit 1. The waveform 118 shows the relationship between the gain and the output power of the driver stage amplifier 11 of the power amplifier circuit 101.

[0141] The power amplifier circuit 1 and the power amplifier circuit 101 each have the emitter follower type bias circuit 15, and therefore, it is possible to extend the power to high output power.

[0142] Figure 12 FIG. 13 is a graph showing the relationship between the gain and the output power of the first power stage amplifier 13 and the second power stage amplifier 14 of the power amplifier circuit 1 and the power amplifier circuit 101 in the case of the low power mode. In FIG. 13, the vertical axis indicates the gain of the first power stage amplifier 13 and the second power stage amplifier 14, and the horizontal axis indicates the output power of the first power stage amplifier 13 and the second power stage amplifier 14. Figure 12

[0143] The waveform 119 shows the relationship between the gain and the output power of the first power stage amplifier 13 and the second power stage amplifier 14 of the power amplifier circuit 1. The waveform 120 shows the relationship between the gain and the output power of the first power stage amplifier 13 and the second power stage amplifier 14 of the power amplifier circuit 101.

[0144] In the power amplifier circuit 101, the feedback type bias circuit 18 outputs the bias current BIAS 21 ​​and bias current BIAS 31 In order to maintain linearity on the characteristics of the feedback-type bias circuit 18, gain compression is applied to the first amplifier 21 and the first amplifier 31, and the gain at the time of high output power has a tendency to slowly decrease. This relates to deterioration of the distortion characteristics in the vicinity of the linear power region.

[0145] On the other hand, in the power amplification circuit 1, in order to improve linearity in the vicinity of the linear power region, the emitter follower-type bias circuit 17 outputs bias currents BIAS 21 and bias current BIAS 31 Therefore, in the power amplification circuit 1, as shown in waveform 119, compared with waveform 120, the gain compression is weak and the gain is high in the case of high output power.

[0146] Figure 13 is a graph showing the relationship between the gain and the output power of the power amplification circuit 1 and the power amplification circuit 101 in the low power mode. In Figure 13 , the vertical axis represents the gain of the power amplification circuit 1 and the power amplification circuit 101 as a whole, and the horizontal axis represents the output power of the power amplification circuit 1 and the power amplification circuit 101 as a whole.

[0147] Waveform 121 shows the relationship between the gain and the output power of the power amplification circuit 1 as a whole. Waveform 122 shows the relationship between the gain and the output power of the power amplification circuit 101 as a whole.

[0148] As described above, in the power amplification circuit 1, compared with the power amplification circuit 101, the gain of the first power stage amplifier 13 and the second power stage amplifier 14 is high. Therefore, in the power amplification circuit 1 as a whole, as shown in waveform 121, compared with waveform 122, the gain is high in the case of high output power.

[0149] Figure 14 to Figure 17 is a graph showing the circuit simulation results of the power amplification circuit of the embodiment and the power amplification circuit of the comparative example.

[0150] Figure 14 is a graph showing the relationship between the gain and the output power of the power amplification circuit 1 and the power amplification circuit 101 as a whole. In Figure 14 , the vertical axis represents the gain of the power amplification circuit 1 and the power amplification circuit 101 as a whole, and the horizontal axis represents the output power of the power amplification circuit 1 and the power amplification circuit 101 as a whole.

[0151] Waveform 131 shows the relationship between the gain and the output power of the power amplification circuit 1 as a whole. Waveform 132 shows the relationship between the gain and the output power of the power amplification circuit 101 as a whole.

[0152] In the power amplification circuit 1, as shown in waveform 131, the gain becomes higher in the case of high output power compared with waveform 132.

[0153] Figure 15 is a graph of circuit simulation results showing the relationship between AM-AM and output power of the entire power amplification circuit 1 and power amplification circuit 101. In Figure 15 , the vertical axis represents AM-AM of the entire power amplification circuit 1 and power amplification circuit 101, and the horizontal axis represents output power of the entire power amplification circuit 1 and power amplification circuit 101.

[0154] Waveform 133 shows the relationship between AM-AM and output power of the entire power amplification circuit 1. Waveform 134 shows the relationship between AM-AM and output power of the entire power amplification circuit 101.

[0155] In the power amplification circuit 1, as shown in waveform 133, the AM-AM becomes higher in the case of high output power compared with waveform 134. That is, the power amplification circuit 1 improves the distortion characteristic compared with the power amplification circuit 101.

[0156] Figure 16 is a graph of circuit simulation results showing the relationship between P3dB and frequency of a high frequency signal of the entire power amplification circuit 1 and power amplification circuit 101. In Figure 16 , the vertical axis represents P3dB (size of output power when the gain is decreased by 3dB gain from the maximum value of the gain) of the entire power amplification circuit 1 and power amplification circuit 101, and the horizontal axis represents frequency of a high frequency signal.

[0157] Waveform 135 shows the relationship between P3dB and frequency of a high frequency signal of the entire power amplification circuit 1. Waveform 136 shows the relationship between P3dB and frequency of a high frequency signal of the entire power amplification circuit 101.

[0158] In the power amplification circuit 1, as described above, the AM-AM is improved, as a result of which, as shown in waveform 135, P3dB becomes higher compared with waveform 136. Therefore, the linearity of the power amplification circuit 1 is improved.

[0159] Figure 17 is a graph of circuit simulation results showing the relationship between ACLR and output power of the entire power amplification circuit 1 and power amplification circuit 101. In Figure 17 , the vertical axis represents ACLR of the entire power amplification circuit 1 and power amplification circuit 101, and the horizontal axis represents output power.

[0160] The waveform 137 shows the relationship between the ACLR and the output power of the entire power amplification circuit 1. The waveform 138 shows the relationship between the ACLR and the output power of the entire power amplification circuit 101.

[0161] In the power amplification circuit 1, the ACLR is improved, for example, in the region 139 as compared with the waveform 138 as shown in the waveform 137.

[0162] (Summary)

[0163] (1) In the power amplification circuit 101 of the comparative example, only the feedback-type bias circuits 16 and 18 impart bias to the first amplifiers 21 and 31 and the second amplifiers 22 and 32. In this case, in the high-power mode, gain compression occurs in order to maintain linearity, the gain at high power decreases, and the ACLR deteriorates. Also, in the low-power mode, gain compression occurs, and the ACLR deteriorates.

[0164] Also, in the power amplification circuit 1 (refer to Figure 1 ), the case where the feedback-type bias circuit 16 is replaced with the emitter-follower-type bias circuit is studied. That is, the case where only the emitter-follower-type bias circuit imparts bias to the first amplifiers 21 and 31 and the second amplifiers 22 and 32 is studied. In this case, in the low-power mode, good linearity is obtained. However, in the high-power mode, gain expansion occurs, and the ACLR deteriorates.

[0165] Thus, in the power amplification circuit 1, in the low-power mode, the emitter-follower-type bias circuit 17 imparts bias to the first amplifiers 21 and 31 and the second amplifiers 22 and 32. Also, in the high-power mode, the feedback-type bias circuit 16 and the emitter-follower-type bias circuit 17 impart bias to the first amplifiers 21 and 31 and the second amplifiers 22 and 32.

[0166] That is, the power amplification circuit 1 uses the emitter-follower-type bias circuit 17 that is less likely to cause gain compression in the low-power mode. Also, the power amplification circuit 1 uses the feedback-type bias circuit 16 that is likely to cause gain compression in addition to the emitter-follower-type bias circuit 17 that is likely to cause gain expansion in the high-power mode. Thus, the power amplification circuit 1 combines the advantages of both the feedback-type bias circuit 16 and the emitter-follower-type bias circuit 17, and can achieve high linearity in the low-power region to the high-power region.

[0167] (2) It can also be that the index of the transistor 54 in the first amplifiers 21 and 31 is larger than the index of the transistor 58 in the second amplifiers 22 and 32.

[0168] Thus, the power amplification circuit 1 can increase the output power in the low-power mode.

[0169] (3) Also, the index of the transistor 54 in the first amplifiers 21 and 31 can be made smaller than the index of the transistor 58 in the second amplifiers 22 and 32.

[0170] Thus, the power amplification circuit 1 can suppress the consumption current in the low power mode.

[0171] (4) The feedback-type bias circuit 16 has a feature that gain compression is easily generated, and the emitter follower-type bias circuit 17 has a feature that gain expansion is easily generated. This feature can be used to determine the distribution of the indexes of the transistors 54 and 58.

[0172] (5) The power amplification circuit 1 can be a multi-stage structure of the driver stage amplifier 11 and the first and second power stage amplifiers 13 and 14.

[0173] Thus, the linearity of the power amplification circuit 1 is difficult to decrease.

[0174] (6) The emitter follower-type bias circuit 15 and the emitter follower-type bias circuit 17 can be provided as different bias circuits.

[0175] Thus, the power amplification circuit 1 can individually control the driver stage amplifier 11 and the first and second power stage amplifiers 13 and 14.

[0176] Note that the above-described embodiments are used to make the present application easy to understand, and are not intended to limit the interpretation of the present application. The present application can be changed / modified within the scope of the gist thereof, and equivalents thereof are also included in the present application.

Claims

1. A power amplification circuit comprising: a first amplifier that amplifies a high-frequency signal in both a first mode and a second mode in which output power is relatively high to the first mode; a second amplifier that amplifies a high-frequency signal in the second mode; a first bias circuit that applies bias to the first amplifier in both the first mode and the second mode; and a second bias circuit that applies bias to the second amplifier in the second mode, the first bias circuit includes: a first transistor whose collector is electrically connected to a power supply potential, whose emitter is electrically connected to the first amplifier, and whose base is electrically connected to a current source; and a second transistor and a third transistor that are diode-connected and connected in series between the base of the first transistor and a reference potential, the second bias circuit includes: a fourth transistor whose collector is electrically connected to a power supply potential, whose emitter is electrically connected to the second amplifier, and whose base is electrically connected to a current source; and a fifth transistor whose base is electrically connected to the emitter of the fourth transistor, whose collector is electrically connected to the base of the fourth transistor, and whose emitter is electrically connected to a reference potential.

2. The power amplification circuit according to claim 1, wherein the first amplifier and the second amplifier each include a multiple-finger transistor that amplifies a high-frequency signal, an index of the multiple-finger transistor in the first amplifier is larger than an index of the multiple-finger transistor in the second amplifier.

3. The power amplification circuit according to claim 1, wherein the first amplifier and the second amplifier each include a multiple-finger transistor that amplifies a high-frequency signal, an index of the multiple-finger transistor in the first amplifier is smaller than an index of the multiple-finger transistor in the second amplifier.

4. The power amplification circuit according to any one of claims 1 to 3, wherein the power amplification circuit further comprises: a third amplifier that is provided in a stage preceding the first amplifier and the second amplifier, amplifies a high-frequency signal in both the first mode and the second mode; and a third bias circuit that applies bias to the third amplifier in both the first mode and the second mode, the third bias circuit includes: a sixth transistor whose collector is electrically connected to a power supply potential, whose emitter is electrically connected to the third amplifier, and whose base is electrically connected to a current source; and a seventh transistor and an eighth transistor that are diode-connected and connected in series between the base of the sixth transistor and a reference potential.

5. The power amplification circuit according to claim 4, wherein the first bias circuit and the third bias circuit are different bias circuits.

6. The power amplification circuit according to claim 4, wherein the third amplifier includes a multiple-finger transistor that amplifies a high-frequency signal, ​ The index of the multiple-finger transistor within the third amplifier is different from the index of the multiple-finger transistor within the first amplifier and the index of the multiple-finger transistor within the second amplifier.

7. The power amplification circuit of claim 5, wherein, the third amplifier includes a multiple-finger transistor that amplifies a high frequency signal, the index of the multiple-finger transistor within the third amplifier is different from the index of the multiple-finger transistor within the first amplifier and the index of the multiple-finger transistor within the second amplifier.

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