Digital synthesis dynamic voltage comparator based on misalignment voltage calibration technique

Abstract

The application discloses a digital comprehensive dynamic voltage comparator based on a disordered voltage calibration technology, comprising a comparison unit composed of two three-input NAND gates and a disordered voltage calibration unit, wherein: the three-input NAND gates are cross-coupled to realize fast comparison of positive input voltage and negative input voltage, the disordered voltage calibration unit detects output voltage of the comparison unit when the input end Vin + is short-circuited and generates a calibration voltage, and the calibration voltage is inputted into the comparison unit after being operated with the input voltage to form a negative feedback to reduce disordered voltage. ‑ The application completely uses digital standard units to realize a dynamic voltage comparator circuit based on cross-coupling of two three-input NAND gates and fusion of the disordered voltage calibration technology, and has the advantages of small area, low power consumption, automatic layout synthesis and small disordered voltage and the like.

Description

Technical Field

[0001] This invention relates to a technology in the field of semiconductor devices, specifically a digital integrated dynamic voltage comparator based on offset voltage calibration technology. - Voltage - Comparators (DVCs). Background Technology

[0002] Traditional analog-based dynamic voltage comparators exhibit low offset voltage, but they have large layout areas, cannot be automatically synthesized, and cannot fully utilize the advantages brought by advancements in semiconductor technology. Fully synthesizable digital-based dynamic voltage comparators, such as those based on cross-coupled three-input NAND gates, offer advantages like small area, low parasitic capacitance, and low power consumption. However, due to issues like asymmetrical layout during automatic synthesis, they exhibit larger offset voltages compared to analog-based dynamic voltage comparators, impacting comparator accuracy.

[0003] A search of existing technologies revealed that X. Zou and S. Nakatake disclosed a synthesizable dynamic voltage comparator circuit with rail-to-rail common-mode voltage input range, implemented entirely using standard digital cells, in their paper "A Fully Synthesizable, 0.3V, 10nW Rail-to-rail Dynamic Voltage Comparator." Figure 1 As shown. It utilizes metal - oxides - The switching characteristics of MOSFETs MP3 and MP4 disconnect the direct connection between the power supply and the output nodes. During the comparator phase, the MOSFET whose gate voltage reaches the power supply voltage first completely blocks the current flowing from the power supply to the corresponding drain. Therefore, MP3 and MP4 effectively prevent both output nodes from being pulled up to a high voltage together when the common-mode input is low, thereby improving the common-mode input range. However, the additional use of MOSFETs MP3 and MP4 in this prior art to obtain the rail-to-rail common-mode voltage range introduces a very large offset voltage. Summary of the Invention

[0004] This invention addresses the shortcomings of existing technologies with large offset voltage by proposing a digitally synthesized dynamic voltage comparator based on offset voltage calibration technology. It utilizes entirely digital standard cells to implement a dynamic voltage comparator circuit based on two three-input NAND gates with cross-coupling and offset voltage calibration technology. It is implemented entirely using digital methods and has advantages such as small area, low power consumption, automatic layout synthesis, and small offset voltage.

[0005] This invention is achieved through the following technical solution:

[0006] This invention relates to a digital integrated dynamic voltage comparator based on offset voltage calibration technology, comprising: a comparator unit consisting of two three-input NAND gates and an offset voltage calibration unit, wherein: the three-input NAND gates achieve fast comparison of positive and negative input voltages through cross-coupling, and the offset voltage calibration unit detects the input terminal Vin. + With Vin - The output voltage when short-circuited is used to generate a calibration voltage. This voltage is then ORed with the input voltage and used as the input to the comparison unit, forming negative feedback to reduce the offset voltage.

[0007] The comparison unit includes two mirror-symmetric, cross-coupled three-input NAND gates.

[0008] The offset voltage calibration unit includes: a pair of accumulators mirrored together, a multiplexer, a tri-state gate, and several buffers serving as delay units.

[0009] This invention relates to a calibration method based on the above-mentioned digital integrated dynamic voltage comparator, comprising:

[0010] Step 1, connect the input terminal Vin of the dynamic voltage comparator. + and Vin - When the comparator clock signal CLK_CMP transitions from low to high, the presence of the comparator input offset voltage causes the output voltage Vout of the dynamic voltage comparator to change. + and Vout - They are no longer all at high levels and begin to separate from each other;

[0011] Step 2: The mirror-symmetric accumulator detects the positive and negative output voltages of the dynamic voltage comparator when the input is shorted. When the comparator calibration clock signal CLK_CMP_cali changes from low to high, the accumulator accumulates and outputs the result based on the output of the dynamic voltage comparator.

[0012] Step 3: The multiplexer (MUX) selects the calibration voltage control clock signal CLK_Vcali_ctr after passing through a corresponding number of delay units as the tri-state gate control signal based on the accumulator output. This signal controls the charging time of the tri-state gate's output capacitor, generating the dynamic voltage comparator calibration voltage Vcali. + and Vcali - ;

[0013] Step 4: Use the dynamic voltage comparator calibration voltage Vcali generated in Step 3. + and Vcali - Compared with the input voltage Vin of the dynamic voltage comparator respectively - and Vin + An OR operation is performed to form negative feedback, and after several comparison cycles, the input offset voltage is finally calibrated.

[0014] Technical effect

[0015] Compared with existing technologies, this invention comprehensively solves the problem that fully digitally synthesized dynamic voltage comparators suffer from large offset voltages due to layout mismatches, leading to decreased comparator accuracy. Because the layout of dynamic voltage comparators changes under different processes and synthesis methods, and there is a certain gap between simulation and the actual physical chip, it is impossible to obtain the exact offset voltage of the dynamic voltage comparator. However, the offset voltage calibration technology of this invention can achieve offset voltage calibration within a relatively large and reasonable range. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of an existing dynamic voltage comparator;

[0017] Figure 2 This is a schematic diagram of the structure of the present invention;

[0018] Figure 3 This is the clock timing diagram of the dynamic voltage comparator calibration circuit of the present invention;

[0019] Figure 4 This is a graph showing the signal changes during the calibration phase when the offset voltage Vos > 0.

[0020] (a) is the output voltage Vout at the positive terminal of the dynamic voltage comparator. + (b) is the output voltage Vout at the negative terminal of the dynamic voltage comparator. - (c) represents the positive terminal calibration voltage Vcali. + (d) represents the negative terminal calibration voltage Vcali. - . Detailed Implementation

[0021] like Figure 2As shown in the figure, this embodiment relates to a low-offset, synthesizable dynamic voltage comparator implemented entirely by digital methods, incorporating offset voltage calibration technology. It includes: a comparator unit composed of two three-input NAND gates and an offset voltage calibration unit. The three-input NAND gates are cross-coupled to form positive feedback, enabling rapid comparison of the positive and negative input voltages. The offset voltage calibration unit detects the input Vin of the dynamic voltage comparator using a 4-bit accumulator. + With Vin - When short-circuited, the output voltage is used by the accumulator to generate a 4-bit multiplexer control signal based on the output voltage of the dynamic voltage comparator. This signal is then used to select the calibration voltage control clock CLK_Vcali_ctr signal after passing through the corresponding delay unit to control the tri-state gate TRI. + TRI - The output capacitor is charged to generate a calibration voltage Vcali. + and Vcali - , respectively with input voltage Vin - and Vin + After performing an OR operation, the result is used as the input to the comparison unit, forming negative feedback and thus reducing the offset voltage.

[0022] The comparison unit includes two mirror-symmetrically arranged three-input NAND gates, wherein: the output of the first three-input NAND gate is connected to the c input of the second three-input NAND gate, and the output of the second three-input NAND gate is connected to the c input of the first three-input NAND gate to form cross-coupling; the b inputs of the first and second three-input NAND gates are connected to the comparator clock signal CLK_CMP; the a inputs of the first and second three-input NAND gates are respectively connected to the outputs of the first and second OR gates; and the b input of the first OR gate and the output of the second three-input NAND gate serve as positive inputs and outputs Vin. + and Vout + The b-input terminal of the second OR gate and the output terminal of the first three-input NAND gate are respectively used as inverting inputs and outputs Vin. - and Vout - The input terminals a of the second and first OR gates are respectively used as the calibration voltage Vcali. + and Vcali - The input terminal is connected to the positive and negative output terminals of the offset voltage calibration unit to form a feedback loop.

[0023] The offset voltage calibration unit includes: a pair of accumulators mirrored together, a multiplexer, a tri-state gate, and several buffers serving as delay units, wherein: the inputs of the negative accumulator and the positive accumulator are respectively connected to the positive and negative outputs Vout of the comparison unit. + and Vout -Each input is connected to the output of the inverter after passing through the inverter. The output of the accumulator is connected to the control signal input of the corresponding multiplexer. The data input of the multiplexer is connected to the output of the corresponding delay unit. The control signal inputs of the negative and positive tri-state gates are connected to the outputs of the corresponding multiplexers. The data signal inputs are connected to the outputs of the inverter after passing through the comparator clock. The outputs are connected to the corresponding capacitors.

[0024] This embodiment relates to a calibration method for the aforementioned dynamic voltage comparator, including:

[0025] Step 1, Vin + and Vin - When short-circuited, due to the existence of the offset voltage Vos, when the comparator clock signal CLK_CMP changes from low level to high level, the positive and negative outputs of the comparator quickly separate, that is, one end outputs the power supply voltage VDD, and the other end outputs GND.

[0026] When the offset voltage Vos > 0, the positive terminal of the comparator outputs Vout. + VDD is the negative terminal, and Vout is the output. - For GND.

[0027] Step 2: When the comparator offset voltage calibration clock signal CLK_CMP_cali changes from low to high, the input of the negative accumulator is Vout. - After inversion, the voltage value of the signal is VDD, so the accumulator output increases from 0000 to 0001, while the positive accumulator output remains 0000. The negative accumulator controls the multiplexer to output the calibration voltage control clock signal CLK_Vcali_ctr after a delay unit. The positive accumulator controls the multiplexer to output the calibration voltage control clock signal CLK_Vcali_ctr. The positive and negative multiplexers are connected to the control signal input terminals of the corresponding tri-state gates, respectively, controlling the tri-state gates to charge their corresponding output capacitors. Since CLK_Vcali_ctr is inverted from CLK_CMP, according to the working principle of tri-state gates, the positive tri-state gate TRI... + Unable to charge the positive terminal output capacitor, i.e., the positive terminal calibration voltage Vcali. + The voltage value is GND; the negative terminal is a tri-state gate TRI. - The negative terminal output capacitor can be charged to generate the calibration voltage Vcali. - The charging time is the delay time of one delay unit.

[0028] Because the output capacitors of the tri-state gates on both the positive and negative terminals are large, a delay unit can only delay Vcali. - The voltage value is slightly greater than the positive voltage of GND.

[0029] Step 3, calibrate the positive terminal voltage Vcali respectively. + With negative input voltage Vin - Perform OR operation and calibrate the negative terminal voltage Vcali - With positive input voltage Vin + Perform an OR operation to reduce the impact of the offset voltage Vos.

[0030] Step 4: Repeat steps 2 and 3. The output of the negative accumulator continues to increase, and the charging time of the negative output capacitor by the negative tri-state gate is longer, Vcali - Gradually increase the voltage until the output voltages at the positive and negative terminals of the dynamic voltage comparator flip, i.e., the positive terminal outputs Vout. + GND is the negative terminal, and Vout is the output. - VDD, complete calibration.

[0031] Since the offset voltage range can be estimated in practice, in this embodiment, based on the input transistor size and parasitic capacitance, the offset voltage range is roughly calculated to be approximately 10mV. - The voltage is between 30mV and 30mV, so different delay unit outputs can be selected by adjusting the multiplexer, and a relatively accurate calibration can be completed using a 4-bit control word. In other cases, the number of delay units and the number of bits of the multiplexer control word can be adjusted according to actual needs to achieve calibration of different accuracies.

[0032] The simulation results, obtained using Cadence, are as follows: Figure 4 As shown, the calibration process is simulated when the input offset voltage Vos = 10mV. Figure 4 In the first comparison cycle shown, Vout + The output voltage values ​​are VDD and Vout. - The output voltage value is GND, Vcali + The output voltage value is GND, Vcali - The output voltage is slightly higher than the positive voltage of GND. After several comparison cycles, Vcali... - Gradually increase until Vcali - When the voltage is 134mV, the positive and negative output terminals Vout of the dynamic voltage comparator + and Vout - The output voltage value flips, i.e., Vout + Output GND, Vout - Output VDD; calibration is now complete. After that, Vcali... - The effect remains unchanged. This invention successfully counteracts the influence of offset voltage Vos on the output of the dynamic voltage comparator by introducing offset voltage calibration technology, thus realizing a digital integrated dynamic voltage comparator based on offset voltage calibration technology.

[0033] The above-described specific implementations can be partially adjusted by those skilled in the art in different ways without departing from the principles and purpose of the present invention. The scope of protection of the present invention is defined by the claims and is not limited to the above-described specific implementations. All implementation schemes within the scope of the claims are bound by the present invention.

Claims

1. A digital integrated dynamic voltage comparator based on offset voltage calibration technology, characterized in that, include: The system includes a comparison unit consisting of two three-input NAND gates and an offset voltage calibration unit. The three-input NAND gates are cross-coupled to achieve rapid comparison of the positive and negative input voltages. The offset voltage calibration unit detects the positive input voltage Vin. + With negative input Vin - The output voltage when shorted is used to generate a calibration voltage, which is then compared with the positive input Vin. + Negative input Vin - After performing an OR operation, it is used as the input to the comparison unit to form negative feedback to reduce the offset voltage; The comparison unit includes two mirror-symmetric, cross-coupled three-input NAND gates; The offset voltage calibration unit includes: a pair of accumulators mirrored together, a multiplexer, a tri-state gate, and several buffers serving as delay units, wherein: the positive-inverting output Vout of the comparison unit... + After inversion, it is connected to the input of the positive accumulator, and the inverted output Vout of the comparator unit is... - After inversion, the signal is connected to the input of the negative accumulator. The output of the negative accumulator is connected to the control signal input of the negative multiplexer. The output of the positive accumulator is connected to the control signal input of the positive multiplexer. The data input of the positive multiplexer is connected to each delay unit corresponding to the positive buffer. The data input of the negative multiplexer is connected to each delay unit corresponding to the negative buffer. The control signal input of the negative tri-state gate is connected to the output of the negative multiplexer. The control signal input of the positive tri-state gate is connected to the output of the positive multiplexer. The data signal inputs of both the positive and negative tri-state gates are connected to the inverted comparator clock CLK_CMP. The outputs of both the positive and negative tri-state gates are grounded through a capacitor.

2. The digital integrated dynamic voltage comparator based on offset voltage calibration technology according to claim 1, characterized in that, The comparison unit includes two mirror-symmetrically arranged three-input NAND gates, wherein: the output of the first three-input NAND gate is connected to the c input of the second three-input NAND gate, and the output of the second three-input NAND gate is connected to the c input of the first three-input NAND gate to form cross-coupling; the b inputs of the first and second three-input NAND gates are connected to the comparator clock CLK_CMP; the a input of the first three-input NAND gate is connected to the output of the first OR gate; the a input of the second three-input NAND gate is connected to the output of the second OR gate; and the b input of the first OR gate serves as the positive input Vin. + The output of the second and third input NAND gate is used as the positive output Vout. + The b input of the second OR gate is used as the negative input Vin. - The output of the first three-input NAND gate is used as the inverting output Vout. - The input terminal 'a' of the second OR gate serves as the positive terminal for calibrating the voltage Vcali. + The input terminal is connected to the output terminal of the positive tri-state gate to form a feedback loop, and the input terminal 'a' of the first OR gate serves as the negative calibration voltage Vcali. - The input terminal is connected to the output terminal of the negative tri-state gate to form a feedback loop.

3. A calibration method for a digital integrated dynamic voltage comparator based on offset voltage calibration technology as described in claim 1 or 2, characterized in that, include: Step 1: Input Vin, the positive terminal of the dynamic voltage comparator. + With negative input Vin - When the comparator clock CLK_CMP transitions from low to high, the presence of the comparator input offset voltage causes the inverted output Vout of the dynamic voltage comparator to be affected. + and inverted output Vout - They are no longer all at high levels and begin to separate from each other; Step 2: The mirror-symmetric accumulator detects the positive and negative output voltages of the dynamic voltage comparator when the input is shorted. When the comparator calibration clock CLK_CMP_cali changes from low to high, the accumulator accumulates and outputs the result based on the output of the dynamic voltage comparator. Step 3: The multiplexer selects the signal after the calibration voltage control clock CLK_Vcali_ctr has passed through a corresponding number of delay units based on the accumulator output as the tri-state gate control signal. This signal controls the charging time of the tri-state gate's output capacitor, generating the positive terminal calibration voltage Vcali of the dynamic voltage comparator. + and negative terminal calibration voltage Vcali - ; Step 4: Apply the positive terminal calibration voltage Vcali generated in Step 3. + With the negative input Vin of the dynamic voltage comparator - Perform an OR operation to calibrate the negative terminal voltage Vcali. - With the positive input Vin of the dynamic voltage comparator + An OR operation is performed to form negative feedback, and after several comparison cycles, the input offset voltage is finally calibrated.

4. The calibration method according to claim 3, characterized in that, specifically include: Step 1, input the positive terminal into Vin + With negative input Vin - When short-circuited, due to the existence of offset voltage Vos, when the comparator clock CLK_CMP changes from low level to high level, the positive and negative outputs of the comparator quickly separate, that is, one end outputs the power supply voltage VDD, and the other end outputs GND. Step 2: When the comparator offset voltage calibration clock CLK_CMP_cali changes from low to high, the input of the negative accumulator is the inverted output Vout. - After inversion, the signal's voltage value is VDD, causing the negative accumulator output to increase from 0000 to 0001, while the positive accumulator output remains 0000. The negative accumulator controls the negative multiplexer to output the calibration voltage control clock CLK_Vcali_ctr after a delay unit, and the positive accumulator controls the positive multiplexer to output the calibration voltage control clock CLK_Vcali_ctr. The positive and negative multiplexers are connected to the control signal inputs of their respective tri-state gates, controlling the tri-state gates to charge their corresponding output capacitors. Since the calibration voltage control clock CLK_Vcali_ctr is inverted compared to the comparator clock CLK_CMP, according to the tri-state gate's operating principle, the positive tri-state gate cannot charge the positive output capacitor, i.e., the positive calibration voltage Vcali... + The voltage value is GND; the negative terminal tri-state gate charges the negative terminal output capacitor to generate the negative terminal calibration voltage Vcali. - The charging time is the delay time of one delay unit, so that the negative terminal calibration voltage Vcali can be adjusted. - The voltage value is slightly greater than the positive voltage of GND; Step 3, calibrate the positive terminal voltage Vcali + With negative input Vin - Perform an OR operation to calibrate the negative terminal voltage Vcali. - With positive input Vin + Perform an OR operation to reduce the impact of the offset voltage Vos; Step 4: Repeat steps 2 and 3. The output of the negative accumulator continues to increase, the charging time of the negative output capacitor by the negative tri-state gate is longer, and the negative calibration voltage Vcali... - Gradually increase the voltage until the output voltages at the positive and negative terminals of the dynamic voltage comparator flip, i.e., the positive output Vout. + GND is the inverted output Vout. - VDD, complete calibration.

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