A successive approximation analog-to-digital converter based on correlated multi-sampling technique

Abstract

The application provides a successive approximation analog-to-digital converter based on a correlated multi-sampling technology, and belongs to the field of integrated circuit design. The total number of capacitors can be effectively reduced by replacing the traditional capacitor array structure with a correlated multi-sampling structure. Since the capacitance value of each capacitor in the multi-sampling structure is the same, matching is not required on the layout. The layout area and complexity are greatly reduced. The correlated multi-sampling module is realized through a simple switched capacitor circuit, and no additional circuit is required.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design, specifically relating to a novel successive approximation analog-to-digital converter structure. Background Technology

[0002] An analog-to-digital converter (ADC) acts as a bridge between analog and digital signals, converting continuous analog signals into digital signals that a computer can store and process. It has become an indispensable part of today's digital world, widely used in various integrated circuit systems, such as medical systems, testing equipment, and image and video systems.

[0003] However, the speed and accuracy of an ADC are two crucial performance indicators that are mutually restrictive and require trade-offs during the design phase. The most common ADC architectures include Flash ADCs, Pipeline ADCs, and Successive Approximation Analog-to-Digital Converters (SAR) ADCs. Flash ADCs are the fastest, but the number of comparators increases exponentially with resolution, thus limiting their achievable resolution due to power consumption and area constraints. Pipeline ADCs offer high resolution and fast conversion speeds, but their complex structure results in larger area and higher power consumption, and their performance is also affected by non-ideal factors. In practical applications, SAR ADCs are typically used in systems with limited power supplies, such as portable devices, due to their low power consumption, small size, and simple implementation.

[0004] In SAR ADCs, the digital-to-analog converter (DAC) is a crucial component. DACs are broadly classified into three types: voltage-scaled, current-scaled, and charge-scaled (CDAC). Due to the superior matching performance of capacitors compared to resistors in MOS technology, charge-scaled DACs are currently the most widely used DACs in SAR ADCs. They primarily utilize the charge on a capacitor array to store input information, then successively redistribute this charge to complete the binary search algorithm. Furthermore, CDACs do not require additional sample-and-hold circuitry, as they themselves act as a sample-and-hold circuit for sampling and holding the input signal, and they have a smaller area while maintaining the same matching accuracy. Therefore, charge-scaled DACs are widely used in SAR ADC designs.

[0005] The capacitor required to achieve an N-bit precision DAC array is 2. NAs accuracy increases, the total number of sampling capacitors in a SAR ADC increases exponentially, and the capacitor area also grows exponentially with increasing accuracy. For example, in a 10-bit single-ended SAR ADC, the total number of capacitors in the DAC module is 1024 unit capacitors. However, at high frequencies, larger capacitors lead to higher power consumption, so the unit capacitors need to be quite small. The selection of unit capacitors is also limited by DAC output voltage settling time, thermal noise, capacitor matching, and minimum design rules. Good capacitor matching is crucial for ADC accuracy. Due to layout, parasitic capacitance exists on the top plate of the capacitor array. Even with a common-centroid layout rule, matching will affect ADC performance. A large number of unit capacitors occupy most of the layout space, limiting the accuracy of the SAR ADC.

[0006] It is evident that in traditional SAR ADCs, achieving high precision leads to an exponential increase in the number of capacitors in the DAC, resulting in significant power consumption. How to achieve high precision in traditional SAR ADCs while simultaneously reducing the number of capacitors used in the DAC has become a pressing issue for its development and application.

[0007] This invention proposes using a correlated multisampling structure to achieve charge redistribution and further comparison. Replacing the traditional capacitor array structure with a correlated multisampling structure effectively reduces the total number of capacitors. Since each capacitor in the multisampling structure has the same capacitance value, matching is not required on the layout. This significantly reduces layout area and complexity. The correlated multisampling module is implemented using a simple switched-capacitor circuit, requiring no additional circuitry. Summary of the Invention

[0008] This invention introduces a correlated multiple sampling (CMS) structure based on a traditional single-ended SAR ADC, utilizing switched capacitors to achieve charge redistribution in the capacitor array. Correlated double sampling (CDS) samples the signal twice, then performs difference processing on the sampling results. CDS not only subtracts a constant reset level but also reduces correlation noise during reset and propagation times, such as flicker (1 / f) noise. Compared to CDS, correlated multiple sampling (CMS) combines CDS and averaging. This effectively reduces thermal noise. Analog CMS is achieved by accumulating M (M>2) consecutive samples using an analog integrator, but this is limited by dynamic range. Digital CMS requires multiple analog-to-digital conversions, demanding high ADC speed and resulting in higher power consumption. The CMS module used in this invention employs a passive switched capacitor structure.

[0009] The approach adopted to implement CMS is to simulate correlated multiple sampling readout, which includes an averaging part and a subtraction part. The averaging part is divided into two regions, A and B, with identical structures, for averaging the reference voltage and storing the average value on a capacitor. The subtractor is used to subtract the two average values ​​generated by regions A and B of the averaging part to obtain the final output value.

[0010] This leverages the advantage that each capacitor in correlated multisampling is identical, and also reduces 1 / f noise and thermal noise from the input reference voltage. The total number of capacitors in the binary-weighted array is 2. N The present invention uses a total of 2N+2 unit capacitors (N being the resolution) in the related multisampling module. Therefore, the present invention reduces the total number of capacitor arrays, and since the capacitor values ​​are equal, no matching is required on the layout, thus reducing the layout area and complexity.

[0011] The aforementioned correlated multisampling relies on analog averaging using switched capacitors. Consider two capacitors C1 and C2, each holding voltages V1 and V2 respectively, as follows: Figure 1 As shown. By closing the switch S connecting the two capacitors, capacitors C1 and C2 share charge. Due to the law of conservation of charge, the two capacitors have a common voltage V, expressed as follows:

[0012]

[0013] To achieve the above and other objectives, this invention proposes a successive approximation analog-to-digital converter (ADC) based on correlated multiple sampling (CMS) technology, comprising a sample-and-hold circuit, a comparator, and a SAR logic control module. First, the sample-and-hold circuit samples and holds the input analog signal. Then, it compares the sampled analog voltage with the voltage of the CMS. If the output voltage of the CMS is higher than the sampled voltage, the comparator output is low, and the SAR logic control circuit controls the sampling switch in the CMS, reducing the CMS voltage by 1 / 2 Vref. Then, the sampled analog voltage is compared again with the DAC voltage. Finally, based on the comparison result, the next cycle of the CMS will generate a voltage of 3 / 4 Vref or 1 / 4 Vref. This process continues until all code values ​​have been converted.

[0014] SARADCs employing the charge redistribution principle have a capacitor DAC architecture based on the traditional binary weighted capacitor DAC architecture, requiring 2 N Unit capacitance (C) u (N is the resolution of the ADC), and in the order [1, 1, 2, ..., 2) N-2 ,2 N-1 The weights are arranged accordingly. For example... Figure 2 As shown, the total charge on the DAC after sampling through the top plate is

[0015] Q=(V in -V ref )×2 N ×C u , V x =V in

[0016] Disconnect the sampling switch and ground the switch S with the largest capacitive weight. Due to the charge conservation of the DAC capacitor array, there is n-1 .

[0017] (V in -V ref )×2 N ×C u =V x ×2 N-1 ×C u +(V x -V ref )×2 N-1 ×C u

[0018] Solving gives

[0019] V x =V in -Vref / 2

[0020] If the output result of the comparator is 0, it means V in >Vref / 2. If the output result of the comparator is 1, it means V in <Vref / 2. The SAR logic control module controls the switches S n-1 and S n-2 to be turned off and on. And so on in a loop until N-bit comparison results are obtained.

[0021] The described CMS structure includes an averaging part and a subtraction part. The averaging part is divided into an averaging part area A and an averaging part area B with exactly the same structure for averaging the reference voltage and storing the average value on a capacitor; the subtractor is used to subtract the two average values generated by the averaging part area A and the averaging part area B and obtain the final output value.

[0022] Both the described averaging part area A and the averaging part area B each include N + 2 identical capacitors C1 - C N+2 and 2N + 3 switches S1 - S 2N+3 . The left side of S1 is connected to the reference voltage Vref of the ADC, the right side is connected to the upper plate of C1, and the lower plates of C1 - C N+2 are all grounded; the left side of S2 is connected to the upper plate of C1, and the right side is connected to C outThe upper plate of S3; S3 connects to the upper plate of C1 on the left and to the upper plate of C2 on the right; S4 connects to the upper plate of C2 on the left and to the upper plate of C on the right. out The upper plate; repeating in a regular pattern, S 2N+1 The left side connects to the upper plate of C1, and the right side connects to C. N+1 The upper electrode plate; S 2N+2 Left side connects C N+1 The upper electrode plate, connected to C on the right side out The upper electrode plate.

[0023] The subtraction section consists of SF-based buffers B1, B2, and B3, and switch S. a S b S out1 S out2 and bootstrap capacitor C s Composition, B1 input connection C outa The upper plate of the output is connected to switch S. a On the left side, switch S a The right side of C S The upper plate of B2; the input connection of C. outb The upper plate of the circuit is connected to another switch S for output. b On the left side, switch S b The right side of C s The lower plate; bootstrap capacitor C s The lower electrode plate is connected to a switch S. out2 The other side of the switch is grounded, C s The upper plate is also connected to a switch S. out1 The other side of the switch is connected to the input of B3. The output of B3 is the output of the entire module. That is, the subtractor will subtract the two average values ​​of the final outputs of the average part A and B to obtain the final output value.

[0024] To achieve the 1 / 2Vref, 3 / 4Vref, 1 / 4Vref, etc. generated by charge redistribution in the DAC capacitor array, this invention utilizes a capacitor array with CMS functionality. Furthermore, taking an 8-bit SAR ADC as an example, the CMS section requires 21 unit capacitors and 42 switches.

[0025] Compared with the prior art, the present invention has the following beneficial effects:

[0026] (1) The total number of capacitors is small;

[0027] (2) No capacitor matching is required;

[0028] (3) After N samplings, the random noise of the circuit is reduced. Multiple sampling can achieve significant noise reduction. Attached Figure Description

[0029] Figure 1 Simulated averaging is performed using two capacitors and a switch.

[0030] Figure 2 SARADC based on charge redistribution principle

[0031] Figure 3 The SAR ADC structure diagram of the present invention.

[0032] Figure 4 Waveform of binary search algorithm.

[0033] Figure 5 The CMS structure of this invention.

[0034] Figure 6 Timing diagram. Detailed Implementation

[0035] (1) Figure 1 It uses two capacitors and a switch to perform simulated averaging based on the principle of charge redistribution.

[0036] (2) Figure 2 This is a schematic diagram of a SARADC circuit for a capacitor-type DAC.

[0037] (3) Figure 3 It is a CMS-based SAR ADC structure. The input signal is processed by the CMS module and then compared with a reference voltage. The comparison structure passes through SAR logic and then returns to the CMS switching switch for the next comparison.

[0038] (4) SAR ADCs typically use a binary search algorithm to quantize the ADC input voltage. Figure 4 Example waveform diagram for quantization of an 8-bit SAR ADC binary search algorithm. First, the sampled input signal is compared to Vref / 2. If the signal is higher than Vref / 2, it will be compared to 3 / 4 Vref in the next cycle; otherwise, it will be compared to 1 / 4 Vref. In the third cycle, Vref / 8 is added to or subtracted from the DAC output voltage based on the comparison result, and this binary search is performed for the remaining conversion cycles. This can also be achieved by adding or subtracting a binary fraction of Vref from the input signal.

[0039] (5) Figure 5 This represents the specific structure diagram of the CMS, which includes an averaging section and a subtraction section.

[0040] The average part consists of N+2 identical capacitors C1-C N+2 S1-S is composed of 2N+3 switches. 2N+3In this embodiment, the average portion A includes 7 identical capacitors: C 1a -C 6a C outa It also includes 13 switches: S 1a -S 12a S outa The average portion, region B, comprises seven identical capacitors: C 1b -C 6b C outb It also includes 13 switches: S 1b -S 12b S outb The connection relationship is taken as an example of the average part, region A: S 1a The left side is connected to the ADC reference voltage Vref, and the right side is connected to C. 1a The upper electrode plate, C 1a The lower electrode plate is grounded; S 2a Left side connects C 1a The upper electrode plate, connected to C on the right side ouat The upper electrode plate; S 3a Left side connects C 1a The upper electrode plate, connected to C on the right side 2a The upper electrode plate; S 4a Left side connects C 2a The upper electrode plate, connected to C on the right side outa The upper electrode plate; with S 3a C 2a S 4a This connection pattern repeats until S 11a Left side connects C 1a The upper electrode plate, connected to C on the right side 6a The upper electrode plate; S 12a Left side connects C 6a The upper electrode plate, connected to C on the right side outa The upper electrode plate. The average part is divided into two parts, region A and region B, with completely identical structures.

[0041] The subtraction section consists of SF-based buffers B1, B2, and B3, and switch S. a S b S out1 S out2 and bootstrap capacitor C s Composition, B1 input connection C outa The upper plate of the output is connected to switch S. a On the left side, switch S a The right side of C S The upper plate of B2; the input connection of C. outb The upper plate of the circuit is connected to another switch S for output. b On the left side, switch S b The right side of Cs The lower plate; bootstrap capacitor C s The lower electrode plate is connected to a switch S. out2 The other side of the switch is grounded, C s The upper plate is also connected to a switch S. out1 The other side of the switch is connected to the input of B3. The output of B3 is the output of the entire module. That is, the subtractor will subtract the two average values ​​of the final outputs of the average part A and B to obtain the final output value.

[0042] The specific implementation is as follows:

[0043] ① First close S 1a In C 1a The capacitor maintains a voltage Vref.

[0044] ② Close S outa and S outb , making C outa and C outb When the charge stored on the upper plate of the capacitor is cleared, the voltage across the capacitor is zero.

[0045] ③ Closed S 2a To calculate the average, open is for C outa Maintain a voltage of 1 / 2Vref across the capacitor; close S. a and S out1 Output 1 / 2Vref;

[0046] ④ The sampled / held input signal VIN is compared with 1 / 2Vref. The comparison result is used by the SAR logic control module to switch the CMS module and start the second comparison.

[0047] ⑤ Generate 1 / 4Vref: The voltage 1 / 2Vref generated in the first comparison remains at C. 1a First, close S. outa Let C outa The stored charge is cleared. Then S is closed again. 2a Connecting C 1a and C outa Perform an average; turn on S 2a In C outa Maintain a voltage of 1 / 4Vref across the capacitor; close S. a and S out1 Output 1 / 4Vref;

[0048] 3 / 4Vref: using capacitor C s The voltage difference between the upper and lower plates is not consistent. The upper plate is affected by the 1 / 4 Vref generated in step 5 above, while the lower plate is affected by the voltage difference generated by closing switch S. 1b S 2b In Coutb Maintain voltage Vref; first close S. out2 , will C S The charge stored in the capacitor is cleared; S is closed. b , making C s The lower plate maintains voltage Vref. S is closed. out1 This causes a difference in voltage between the upper and lower plates, resulting in a 3 / 4 Vref.

[0049] ⑥ The generated 1 / 4Vref (or 3 / 4Vref) is compared with VIN, and the comparison result is then used to control the CMS module through SAR logic to perform the next comparison;

[0050] ⑦ Similarly, the method for generating 1 / 8Vref is the same as in step 5: first close S outa Let C outa The charge on the upper plate is cleared to zero; then S is closed again. 2a Connecting C 1a and C outa Averaging is performed. 3 / 8 Vref can be obtained by subtracting 1 / 8 Vref generated from the average of region A and 1 / 4 Vref generated from the average of region B.

[0051] ⑧ Following steps 1-7, adjust Vref continuously until all code values ​​are converted to obtain the final output.

[0052] (6) Figure 6 Timing diagram for controlling the switching on and off of the CMS module.

Claims

1. A successive approximation analog-to-digital converter based on correlation multiple sampling technology, characterized in that, Includes CMS, sample-and-hold circuit, comparator and SAR logic control module; The CMS includes an averaging section and a subtraction section. The averaging section is divided into two identically structured averaging section A and averaging section B for averaging the reference voltage and storing the average value on a capacitor. The subtractor is used to subtract the two average values ​​generated by averaging section A and averaging section B to obtain the final output value. Both the average portion A and the average portion B each include N+2 identical capacitors C1-C2. N+2 S1-S is composed of 2N+3 switches. 2N+3 S1 is connected to the ADC reference voltage Vref on the left and to the upper plate of C1 on the right. C1-C N+2 The lower plates of both are grounded; the left side of S2 is connected to the upper plate of C1, and the right side is connected to C. out The upper plate of S3; S3 connects to the upper plate of C1 on the left and to the upper plate of C2 on the right; S4 connects to the upper plate of C2 on the left and to the upper plate of C on the right. out The upper plate; repeating in a regular pattern, S 2N+1 The left side connects to the upper plate of C1, and the right side connects to C. N+1 The upper electrode plate; S 2N+2 Left side connects C N+1 The upper electrode plate, connected to C on the right side out The upper electrode plate; N is the resolution of the ADC; The subtraction section consists of SF-based buffers B1, B2, and B3, and switch S. a S b S out1 S out2 and bootstrap capacitor C s Composition, B1 input connection C outa The upper plate of the output is connected to switch S. a On the left side, switch S a The right side of C S The upper plate of B2; the input connection of C. outb The upper plate of the circuit is connected to another switch S for output. b On the left side, switch S b The right side of C s The lower plate; bootstrap capacitor C s The lower electrode plate is connected to a switch S. out2 The other side of the switch is grounded, C s The upper electrode plate is also connected to a switch S. out1 The other side of the switch is connected to the input of B3. The output of B3 is the output of the entire module. That is, the subtractor will subtract the two average values ​​of the final outputs of the average part A and B to obtain the final output value.

2. The successive approximation analog-to-digital converter based on correlation multiple sampling technology according to claim 1, characterized in that, The successive approximation analog-to-digital converter (ADC) operates as follows: First, the sample-and-hold circuit samples and holds the input analog signal. Then, it compares the sampled analog voltage with the voltage of the CMS. If the output voltage of the CMS is higher than the sampled voltage, the comparator output is low, and the SAR logic control circuit controls the sampling switch in the CMS, reducing the CMS voltage by 1 / 2 Vref. Then, the sampled analog voltage is compared again with the voltage of the DAC. Finally, based on the comparison result, the next cycle of the CMS will generate a voltage of 3 / 4 Vref or 1 / 4 Vref. This process continues until all code values ​​have been converted. SARADCs employing the charge redistribution principle have a capacitor DAC architecture based on the traditional binary weighted capacitor DAC architecture, requiring 2 N Unit capacitance C u And in [1, 1, 2, ..., 2] N-2 ,2 N-1 The weights are arranged according to the ], and the total charge on the DAC after sampling through the top plate is Q = (V in -V ref )×2 N ×C u V x =V in Turn off the sampling switch and turn on the switch S with the largest capacitance weight. n-1 Grounded; due to the charge conservation of the DAC capacitor array, therefore, (V in -V ref )×2 N ×C u =V x ×2 N-1 ×2 N-1 ×C u +(V x -V ref )×2 N-1 ×C u Solving V x =V in -Vref / 2 If the comparator output result is 0, it means that V in > Vref / 2. If the comparator output result is 1, it means that V in < Vref / 2; The SAR logic control module controls the switches S n-1 and S n-2 to be turned off and on; and so on in a loop until an N-bit comparison result is obtained.

Images