An apparatus and method for extracting avalanche diode avalanche signals.

Abstract

This invention discloses a device for extracting avalanche diode avalanche signals, comprising an avalanche signal preprocessing circuit, a delay unit, a first D flip-flop, a second D flip-flop, and an AND gate. The avalanche signal preprocessing circuit receives the original simulated avalanche signal as input, and its output is connected to both the delay unit and the first D flip-flop. The output of the delay unit is connected to the second D flip-flop. The outputs of the first and second D flip-flops are connected to the input of the AND gate, and the output of the AND gate outputs the detection result of the avalanche signal. The advantage of this invention is that by delaying the preprocessed avalanche signal and simultaneously sampling the signals before and after the delay using the D flip-flops, cases where an avalanche has already occurred before reaching the input of the delay unit and cases where an avalanche has not yet occurred after passing through the delay unit are completely removed through an AND operation.

Description

Technical Field

[0001] This invention relates to the field of quantum communication, and in particular to an apparatus and method for extracting avalanche signals from an avalanche diode. Background Technology

[0002] Currently, commercial quantum key distribution (QKD) is based on infrared single-photon detection using mature InGaAs / InP avalanche photodiodes. InGaAs / InP avalanche photodiodes offer advantages such as small size, low power consumption, easy integration, easily achievable cooling temperatures, and high detection repetition rates, making them an increasingly popular research area. To achieve weak light signal detection at the single-photon level, the APD often needs to operate in Geiger mode to respond to a single photon. However, the avalanche triggered by a single charge carrier cannot stop naturally. To protect the APD and to allow it to respond to the photon signal again for the next detection, the bias voltage across the APD needs to be quickly reduced below the avalanche voltage to suppress the avalanche and restore the APD to detection mode. In QKD applications, the photon arrival time is predictable; therefore, gate pulse control circuits are typically used to suppress avalanches. This method not only rapidly restores APD detection and improves its operating speed but also significantly reduces detector false counts.

[0003] The smaller the time jitter in the detection results of a single-photon detector, the narrower the distribution of the measured values ​​on the time axis, and the higher the detector's time resolution and detection accuracy. To accurately measure the response time distribution of a single photon, we generally select the full width at half maximum (FWHM) of the photon output signal at the same incident time as a measure of time jitter. In practical applications, excessive time jitter increases inter-symbol interference (ISI) during quantum key distribution. If the output position is incorrect, there is a 50% chance of generating erroneous bits, regardless of the transmission distance. High afterpulses can severely affect the final secure key generation rate. With the rapid development of quantum key distribution, system repetition frequencies have reached over GHz, and the gating period of high-speed single-photon detectors has been compressed to the order of hundreds of ps, making the accuracy of the output time of the detection results extremely important. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide an apparatus and method for extracting avalanche diode avalanche signals. The aim is to increase the time extraction of avalanche signals, capture the time of avalanche detection results that are acceptable to the system, remove excessive jitter, and improve the secure key generation rate in the quantum key distribution process.

[0005] To achieve the above objectives, the technical solution adopted by the present invention is as follows: a device for extracting avalanche diode avalanche signals: comprising an avalanche signal preprocessing circuit, a delay unit, a first D flip-flop, a second D flip-flop, and an AND gate. The input terminal of the avalanche signal preprocessing circuit receives the original simulated avalanche signal, and its output terminal is connected to a delay unit and the first D flip-flop, respectively. The output terminal of the delay unit is connected to the second D flip-flop. The output terminals of the first D flip-flop and the second D flip-flop are respectively connected to the input terminal of the AND gate, and the output terminal of the AND gate outputs the detection result of the avalanche signal.

[0006] The avalanche signal preprocessing circuit is used to convert the original analog avalanche signal into a digital signal.

[0007] The avalanche signal preprocessing circuit includes a comparator, one end of which receives the original simulated avalanche signal and the other end receives a reference level; the output of the comparator serves as the output of the avalanche signal preprocessing circuit.

[0008] The delay unit can be set and is used to delay the preprocessed avalanche signal.

[0009] The clock signal pins CLK of the first and second D flip-flops are respectively input to the sampling clock signal, which is synchronized with the clock of the external photon to ensure that sampling is performed at each detection position.

[0010] The delay time of the delay unit is set based on the time range of the avalanche signal.

[0011] A method for extracting avalanche diode avalanche signals includes:

[0012] The collected raw simulated avalanche signals are preprocessed and converted into digital signals;

[0013] The preprocessed digital signal is input to the delay unit for delay. Then, a D flip-flop is used to sample the input and output of the delay unit simultaneously. The D flip-flop is triggered by a clock synchronized with the time of the photons incident into the avalanche diode. The two sampled signals are sent to the input of a logic AND gate and subjected to an AND operation. The result of the operation is used as the final result of extracting the avalanche signal.

[0014] The delay unit can be configured via a delay chip and an adjustable delay line, wherein the delay time of the delay unit is set based on the time range of the avalanche signal.

[0015] A comparator is used to convert analog signals into digital signals.

[0016] The advantages of this invention are as follows: By delaying the pre-processed avalanche signal and simultaneously sampling the signals before and after the delay using a D flip-flop, cases where avalanches have already occurred before reaching the input of the delay unit or have not yet occurred after passing through the delay unit are completely removed through a logical AND operation. This method ensures that the avalanche signal is only effective when it avalanches within the time range set by the delay unit. The delay unit enables selection of the avalanche signal time range, effectively reducing the time jitter of the avalanche signal caused by random avalanches. This invention proposes a device and method for extracting avalanche diode avalanche signals. The time jitter of the avalanche signal caused by the random avalanche process follows a normal distribution. Low-probability events at the edge of the jitter time can affect the judgment of the arrival time of the light pulse. By increasing the selection of the avalanche signal generation time range, signals with large avalanche time deviations are filtered out, and the detection time information corresponding to the photon is extracted more accurately. Attached Figure Description

[0017] The following is a brief explanation of the contents of each of the accompanying drawings and the markings in the drawings:

[0018] Figure 1 This is a flowchart illustrating the implementation of the present invention.

[0019] Figure 2 This is a diagram of an apparatus for implementing the present invention.

[0020] Figure 3 The delay unit of this invention

[0021] Figure 4 This is a preferred embodiment of the avalanche signal preprocessing circuit of the present invention.

[0022] Figure 5 This is a timing diagram for extracting avalanche signals according to the present invention;

[0023] Figure 6 This is a schematic diagram of the avalanche signal delay sampling and extraction results of the present invention. Detailed Implementation

[0024] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings and the description of the preferred embodiments.

[0025] Timing jitter in avalanche signals caused by random avalanche processes limits the final secure key generation rate of high-speed QKD. This invention aims to improve the timing of avalanche signal extraction, capturing the time at which acceptable avalanche detection results are generated, thus removing excessive jitter and improving the secure key generation rate in the quantum key distribution process.

[0026] This invention proposes a device for extracting avalanche diode avalanche signals, comprising:

[0027] Avalanche signal preprocessing circuit, including delay unit, D flip-flop, and AND gate. (Example) Figure 2 As shown, the connection relationship includes: the input terminal of the avalanche signal preprocessing circuit receives the original simulated avalanche signal, and its output terminal is connected to a delay unit and a first D flip-flop, respectively; the output terminal of the delay unit is connected to a second D flip-flop; the output terminals of the first and second D flip-flops are respectively connected to the input terminals of a logic AND gate, and the output terminal of the logic AND gate outputs the detection result of the avalanche signal. The first and second D flip-flops are the same components; the terms "first" and "second" are used for differentiation.

[0028] The avalanche signal preprocessing circuit is connected to the original analog avalanche signal at its input and to a delay unit and a D flip-flop at its output. After the avalanche signal preprocessing unit delays the signal, its output is connected to a D flip-flop. The positive output of one D flip-flop and the negative output of another D flip-flop are connected to an AND gate. The output of the AND gate is the detection result.

[0029] The avalanche signal preprocessing circuit converts the original analog avalanche signal into a digital signal. This can be achieved using a comparator. The comparator sets a reference voltage. When the voltage of the analog avalanche signal is greater than the reference voltage, it outputs a high level; otherwise, it outputs a low level, indicating whether the avalanche signal is present or not, thus converting it into a digital signal.

[0030] The delay of the delay unit can be set, and a signal delay is applied to the preprocessed avalanche signal; the delay time depends on the time range to be captured, which can be set.

[0031] The D flip-flop simultaneously samples the preprocessed avalanche signal from both the input and output of the delay unit. The clock signal is synchronized with the external photon clock, ensuring sampling at each detection location. An AND gate performs a logical AND operation on the sampled signal and outputs the result as the detector's output. The clock signal is synchronized with the external photon clock; the avalanche diode detects external photons, or input photons, etc.

[0032] This invention proposes a method for extracting avalanche diode avalanche signals. By delaying the pre-processed avalanche signal and simultaneously sampling the signals before and after the delay using a D flip-flop, all avalanche signals that have already avalanced before reaching the input of the delay unit or have not avalanced after passing through the delay unit are removed using a logical AND operation. This method ensures that the avalanche signal is only valid if it avalanches within the time range set by the delay unit. The delay unit enables selection of the avalanche signal's time range, effectively reducing the time jitter of the avalanche signal caused by random avalanches. The delay time is the interception time. Since the actual detection jitter index of each avalanche diode is different, the delay time must be determined according to the test values.

[0033] like Figure 1The flowchart shown is an implementation flowchart of the present invention. First, the original simulated avalanche signal is preprocessed to convert the analog signal into a digital signal. The processed digital signal then passes through a delay unit. A D flip-flop is triggered using a clock synchronized with the time of the photons incident into the avalanche diode to simultaneously sample the input and output terminals of the delay unit. A logical AND operation is performed between the positive input signal of the delay unit and the negative output signal of the delay unit. The result of the operation is the detector output, and its output result is matched with the time for use in quantum key distribution (QKD).

[0034] like Figure 2 The diagram shows an embodiment of the present invention. The original simulated avalanche signal enters the avalanche signal preprocessing circuit. The output of the avalanche signal preprocessing circuit is connected to a D flip-flop and a delay unit. The output of the delay unit is connected to a D flip-flop. The sampling clock samples the signals at the input and output of the delay unit and performs a logical AND operation. The result of the operation is used as the final result of extracting the avalanche signal.

[0035] like Figure 3 As shown, the delay unit can be configured through a delay chip and an adjustable delay line.

[0036] Figure 4 This is a preferred implementation circuit for an avalanche signal preprocessing circuit, as shown in the figure. The original simulated avalanche signal is input to one input terminal of a comparator, and the other input terminal of the comparator is set to a fixed level. When the level of the original simulated avalanche signal exceeds the set fixed level, a high level is output, indicating that the avalanche diode avalanche process is valid and the signal is then fed into the subsequent time extraction device. When the level of the original simulated avalanche signal does not exceed the set fixed level, a low level is output, indicating that the avalanche diode avalanche process is invalid and the subsequent time extraction device also does not output a valid result.

[0037] Figure 5 This is a timing diagram for extracting the avalanche signal. In (a), at clock sampling times A0=1 and B0=0, A1=1 and B1=1, so the result after the AND operation is 1, indicating that the avalanche diode signal is valid and the single-photon detector outputs a high level. In (b), at clock sampling times A0=0 and B0=0, A1=0 and B1=1, so the result after the AND operation is 0, indicating that the avalanche diode signal is invalid and the single-photon detector outputs a low level. In (c), at clock sampling times A0=1 and B0=1, A1=1 and B1=0, so the result after the AND operation is 0, indicating that the avalanche diode signal is invalid and the single-photon detector outputs a low level. This timing diagram shows that only avalanche signal edges within the delay range can be considered valid detection results.

[0038] The method for extracting avalanche diode signals implemented in this device can effectively solve the problem of excessive time jitter offset of avalanche signals by flexibly configuring the delay unit and selecting the time range of the avalanche signal to be intercepted, thereby reducing the error in detection time and position.

[0039] The following is a schematic diagram of the avalanche signal delay sampling and extraction results. Figure 6 As shown, this invention delays avalanche signals, samples avalanche signals at different times, and performs post-processing to filter out avalanche signals that are too early or too late in time, such as the avalanche signals before point B and the avalanche signals after point A in the figure. Figure 2 It can be seen that for avalanche signals before point B, the D flip-flop samples and outputs 0, which enters the AND gate. For avalanche signals after point A, the D flip-flop samples and outputs 0, which enters the AND gate. For avalanche signals generated in between, the AND gate inputs are all 1. Only then is the avalanche signal detection result valid, and the output is 1.

[0040] This invention provides a method for processing raw avalanche detection results. It truncates the output, originally recorded as the detection result, in terms of time. When t0 is greater than the gating period, a period error occurs due to time jitter in the avalanche signal. This introduces error counting in quantum key distribution. d Using time truncation shorter than the gating period can reduce error counts in quantum key distribution. d The determination of t needs to be based on the avalanche signal distribution of the actual avalanche diode, but in order to reduce the error count in quantum key distribution, t is generally used. d The time length is less than the gating period.

[0041] Obviously, the specific implementation of this invention is not limited to the above-described manner. Any non-substantial improvements made using the inventive concept and technical solution of this invention are within the protection scope of this invention.

Claims

1. A device for extracting avalanche diode avalanche signals, characterized in that: The system includes an avalanche signal preprocessing circuit, a delay unit, a first D flip-flop, a second D flip-flop, and an AND gate. The input terminal of the avalanche signal preprocessing circuit receives the original simulated avalanche signal, and its output terminal is connected to a delay unit and the first D flip-flop, respectively. The output terminal of the delay unit is connected to the second D flip-flop. The output terminals of the first and second D flip-flops are respectively connected to the input terminals of the AND gate, and the output terminal of the AND gate outputs the detection result of the avalanche signal. The delay time of the delay unit is set based on the time range of the avalanche signal.

2. The apparatus for extracting avalanche diode avalanche signals as described in claim 1, characterized in that: The avalanche signal preprocessing circuit is used to convert the original analog avalanche signal into a digital signal.

3. The apparatus for extracting avalanche diode avalanche signals as described in claim 2, characterized in that: The avalanche signal preprocessing circuit includes a comparator, one end of which receives the original simulated avalanche signal and the other end receives a reference level; the output of the comparator serves as the output of the avalanche signal preprocessing circuit.

4. The apparatus for extracting avalanche diode avalanche signals as described in any one of claims 1-3, characterized in that: The delay unit can be set and is used to delay the preprocessed avalanche signal.

5. The apparatus for extracting avalanche diode avalanche signals as described in any one of claims 1-3, characterized in that: The clock signal pins CLK of the first and second D flip-flops are respectively input to the sampling clock signal, which is synchronized with the clock of the external photon to ensure that sampling is performed at each detection position.

6. A method for extracting avalanche diode avalanche signals, characterized in that: include: The collected raw simulated avalanche signals are preprocessed and converted into digital signals; The preprocessed digital signal is input to the delay unit for delay. Then, a D flip-flop is used to sample the input and output of the delay unit simultaneously. The D flip-flop is triggered by a clock synchronized with the time of the photons incident on the avalanche diode. The two sampled signals are sent to the input of a logic AND gate and subjected to an AND operation. The result of the operation is used as the final result of extracting the avalanche signal. The delay time of the delay unit is set based on the time range of the avalanche signal.

7. The method for extracting avalanche diode avalanche signals as described in claim 6, characterized in that: The delay unit can be configured via a delay chip and an adjustable delay line.

8. The method for extracting avalanche diode avalanche signals as described in claim 6, characterized in that: A comparator is used to convert analog signals into digital signals.

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