LED power-down processing method, circuit and LED lighting device

Abstract

The application relates to an LED power-off processing method, an LED power-off processing circuit and an LED lighting device. The LED power-off processing method comprises the following steps: based on a supply voltage VCC of a controller, after the controller enters an under-voltage lock state, a feedback circuit is controlled to generate a strong pull-down current Isd applied to the supply voltage VCC end of the controller, the sum of the strong pull-down current Isd and a working current when the controller enters the under-voltage lock state is greater than a supply current provided by a peripheral power supply, a voltage stabilizing capacitor corresponding to the supply voltage VCC is discharged, so that the input voltage VCC is reduced; when the supply voltage VCC drops to a strong pull-down closing threshold voltage which is less than an under-voltage lock threshold voltage, the feedback circuit stops generating the strong pull-down current Isd; when the supply voltage VCC rises to a strong pull-down opening threshold voltage which is less than or equal to an under-voltage lock elimination threshold voltage, the feedback circuit generates the strong pull-down current Isd.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of LED power-down processing, and particularly relates to an LED power-down processing method, an LED power-down processing circuit and an LED lighting device. BACKGROUND

[0002] LED lighting devices are rapidly popularized in the lighting industry due to low energy consumption, long service life and low pollution. Some LED lighting devices have the power-down flicker problem of being re-lit after being turned off. The causes are as follows:

[0003] In the LED lighting device, an AC power supply is rectified by a bridge, and a DC line voltage VIN is generated on a bus capacitor 4 (see FIG. 1). Figure 2 After the power supply is turned off, the LED lighting control circuit enters an under-voltage lockout state due to insufficient power supply from the peripheral power supply. In this state, the LED lamp is turned off. After the LED lighting control circuit enters the under-voltage lockout state, the working current of the LED lighting control circuit decreases, the peripheral power supply causes the LED lighting control circuit to exit the under-voltage lockout state, and the LED is re-lit. The working current of the LED lighting control circuit increases, so that the peripheral power supply cannot maintain the working of the LED lighting control circuit, and the LED lighting control circuit enters the under-voltage lockout state again, and the above process is repeated to cause several times of power-down flicker until the bus capacitor 4 cannot support the start of the LED lighting control circuit.

[0004] In practical applications, the power-down flicker problem of the LED lighting device being re-lit after being turned off will bring a poor user experience. SUMMARY

[0005] Therefore, the application provides an LED power-down processing method, an LED power-down processing circuit and an LED lighting device to solve the power-down flicker problem of the LED lighting device.

[0006] To achieve the above object, the application adopts the following technical solutions:

[0007] In a first aspect, the application provides an LED power-down processing method, which comprises the following steps:

[0008] Based on the supply voltage VCC of the controller, a strong pull-down current Isd is generated by a feedback circuit after the controller enters an under-voltage lockout state, wherein the strong pull-down current Isd is applied to the supply voltage VCC of the controller, the sum of the strong pull-down current Isd and the working current when the controller enters the under-voltage lockout state is greater than the supply current provided by the peripheral power supply, and the discharge of the corresponding voltage stabilizing capacitor of the supply voltage VCC of the controller causes the supply voltage VCC to decrease.

[0009] when the supply voltage VCC falls to a strong pull-down closing threshold voltage, controlling the feedback circuit to stop generating the strong pull-down current Isd, wherein the strong pull-down closing threshold voltage is less than the under-voltage lockout threshold voltage;

[0010] when the supply voltage VCC rises to a strong pull-down opening threshold voltage, controlling the feedback circuit to generate the strong pull-down current Isd, wherein the strong pull-down opening threshold voltage is less than or equal to the under-voltage lockout elimination threshold voltage.

[0011] Further, the strong pull-down closing threshold voltage is less than the under-voltage lockout threshold voltage and greater than a power-on reset voltage.

[0012] Further, the method further comprises:

[0013] when the supply voltage VCC rises beyond the under-voltage lockout elimination threshold voltage, the controller is released from the under-voltage lockout state.

[0014] Further, the step of controlling the feedback circuit to generate the strong pull-down current Isd based on the supply voltage VCC of the controller after the controller enters the under-voltage lockout state comprises:

[0015] obtaining a plurality of timing logic signals of a preset number for the supply voltage VCC;

[0016] performing a logical operation on the plurality of timing logic signals, and when it is determined that the logical operation result represents that the controller enters the under-voltage lockout state, controlling the feedback circuit to generate the strong pull-down current Isd.

[0017] In a second aspect, the present application provides an LED power-down processing circuit, comprising: a voltage detection circuit, a timing logic signal generation circuit, a logical operation circuit and a feedback circuit connected in sequence;

[0018] The voltage detection circuit is configured to detect the supply voltage VCC of the controller.

[0019] The timing logic signal generation circuit is configured to generate a plurality of timing logic signals according to the supply voltage VCC.

[0020] The logic operation circuit is configured to perform logic operation on the multiple timing logic signals to generate a timing control signal, and the timing control signal is configured to drive the feedback circuit to generate a strong pull-down current Isd when it is indicated that the controller enters an under-voltage lock state, wherein the strong pull-down current Isd is configured to be applied to a power supply voltage VCC terminal of the controller, and the sum of the strong pull-down current Isd and an operating current of the controller when the controller enters the under-voltage lock state is greater than a power supply current provided by a peripheral power supply, and the power supply voltage VCC terminal corresponds to a discharge of a voltage stabilizing capacitor, so that the power supply voltage VCC decreases; when it is indicated that the power supply voltage VCC decreases to a strong pull-down closing threshold voltage, the timing control signal drives the feedback circuit to stop generating the strong pull-down current Isd, wherein the strong pull-down closing threshold voltage is less than an under-voltage lock threshold voltage; and when it is indicated that the power supply voltage VCC increases to a strong pull-down opening threshold voltage, the timing control signal drives the feedback circuit to generate the strong pull-down current Isd, wherein the strong pull-down opening threshold voltage is less than or equal to an under-voltage lock elimination threshold voltage.

[0021] Further, the timing logic signal generation circuit comprises a first selector, a second selector, a first comparator, a second comparator, a first inverter, a first flip-flop and a power-on reset (POR) detection circuit.

[0022] The input ends of the first selector, the second selector and the POR detection circuit are connected with the voltage detection circuit.

[0023] The output end of the first selector is connected with the positive input end of the first comparator.

[0024] The output end of the first comparator is connected with the control end of the first selector and the logic operation circuit, and the output end of the first comparator is also connected with the trigger end of the first flip-flop through the first inverter, and the output end of the first flip-flop is connected with the logic operation circuit.

[0025] The EN end of the first comparator and the CLR end of the first flip-flop are connected with the first control output end of the logic operation circuit.

[0026] The output end of the second selector is connected with the positive input end of the second comparator, and the control end of the second selector is connected with the output end of the second comparator.

[0027] The output end of the second comparator is connected with the logic operation circuit.

[0028] The output end of the POR detection circuit is connected with the EN end of the second comparator and the logic operation circuit.​

[0029] Further, the logic operation circuit comprises a first NAND gate, a second NAND gate, a second flip-flop, a second inverter and a driver.

[0030] The first NAND gate is connected with the output end of the first comparator and the output end of the first flip-flop respectively. The output end of the first NAND gate is connected with the first input end of the second NAND gate.

[0031] The second input end of the second NAND gate is connected with the output end of the second comparator and the input end of the second inverter.

[0032] The output end of the second inverter is connected with the trigger end of the second flip-flop.

[0033] The CLR end of the second flip-flop is connected with the output end of the power-on reset (POR) detection circuit, and the output end of the second flip-flop is connected with the third input end of the second NAND gate.

[0034] The Q output end of the second flip-flop is the first control output end.

[0035] The output end of the second NAND gate is connected with the input end of the driver, and the output end of the driver is the second control output end and is connected with the feedback circuit.

[0036] Further, the strong pull-down closing threshold voltage is less than the under-voltage lockout threshold voltage and greater than the power-on reset voltage.

[0037] Further, the feedback circuit comprises:

[0038] An electronic switch, the control end of the electronic switch is connected with the output end of the logic operation circuit.

[0039] A feedback generation unit connected with the electronic switch.

[0040] Further, the feedback generation unit is a current source circuit or a resistor.

[0041] In a third aspect, the present application provides an LED lighting device applying the LED power failure processing method as described in any of the above.

[0042] In a fourth aspect, the present application provides an LED lighting device comprising the LED power failure processing circuit as described in any of the above.

[0043] The present application has at least the following beneficial effects by adopting the above technical solutions:

[0044] ​Through the scheme, based on the supply voltage VCC of the controller, after the controller enters the undervoltage lockout state, the feedback circuit generates a strong pull-down current Isd, which is applied to the supply voltage VCC end of the controller. At this time, the sum of the strong pull-down current Isd and the working current when the controller enters the undervoltage lockout state is greater than the supply current provided by the peripheral power supply. The voltage stabilizing capacitor corresponding to the supply voltage VCC end of the controller is discharged, so that the supply voltage VCC decreases. When the supply voltage VCC decreases to the strong pull-down closing threshold voltage less than the undervoltage lockout threshold voltage, the feedback circuit stops generating the strong pull-down current Isd. At this time, the supply current provided by the peripheral power supply is greater than the working current of the controller in this state, that is, the voltage stabilizing capacitor corresponding to the supply voltage VCC end of the controller is charged by the peripheral power supply, so that the supply voltage VCC rises. When the supply voltage VCC rises to the strong pull-down opening threshold voltage less than or equal to the undervoltage lockout elimination threshold voltage, the feedback circuit generates the strong pull-down current Isd. At this time, the supply current provided by the peripheral power supply is less than the sum of the strong pull-down current Isd and the working current of the controller in this state. The voltage stabilizing capacitor corresponding to the supply voltage VCC end of the controller is discharged, so that the supply voltage VCC decreases. Repeating the above process several times can discharge the electric quantity in the bridge-back bus capacitor, and at the same time, the controller is always in the undervoltage lockout state. Therefore, the power-on flash problem that the LED lamp is turned off and then turned on again can be avoided, thereby helping to protect the user's LED lighting experience.

[0045] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the application. BRIEF DESCRIPTION OF DRAWINGS

[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0047] Figure 1 is a flow chart of an LED power-off processing method according to an exemplary embodiment;

[0048] Figure 2 is a block diagram of an LED power-off processing circuit according to an exemplary embodiment;

[0049] Figure 3 is a schematic diagram of implementing power-off processing by using a timing logic signal according to an exemplary embodiment;

[0050] Figure 4is a schematic diagram of an LED brown-out handling circuit implementation according to an exemplary embodiment;

[0051] Figure 5 is a schematic diagram of an LED brown-out handling circuit implementation according to another exemplary embodiment.

[0052] in the figure:

[0053] 2 - LED brown-out handling circuit; 3 - controller; 4 - bus capacitor; 5 - peripheral power supply module; 6 - voltage stabilizing capacitor;

[0054] 21 - voltage detection circuit; 22 - timing logic signal generation circuit 22; 23 - logic operation circuit; 24 - feedback circuit;

[0055] M1 - first selector; M2 - second selector; C1 - first comparator; C2 - second comparator; P1 - first inverter; D1 - first flip-flop; N1 - first NAND gate; N2 - second NAND gate; D2 - second flip-flop; P2 - second inverter; Dr - driver; T1 - electronic switch; I load - current source circuit; R load - resistance;

[0056] 201 - power-on reset (POR) detection circuit; 202 - feedback generation unit. DETAILED DESCRIPTION

[0057] In order to make the purposes, technical solutions and advantages of the present application clearer, the technical solutions of the present application will be described in detail below. Obviously, the described embodiments are only some of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of the present application.

[0058] Please refer to Figure 1 , Figure 1 is a flowchart of an LED brown-out handling method according to an exemplary embodiment, the method is applied to an LED lighting device, and the method comprises the following steps:

[0059] In step S11, based on the supply voltage VCC of the controller, after the controller enters an under-voltage lock state, a strong pull-down current Isd is generated by the feedback circuit, wherein the strong pull-down current Isd is applied to the supply voltage VCC end of the controller, the sum of the strong pull-down current Isd and the working current when the controller enters the under-voltage lock state is greater than the supply current provided by the peripheral power supply, and the voltage stabilizing capacitor 6 corresponding to the supply voltage VCC end of the controller is discharged, so that the supply voltage VCC decreases;

[0060] Step S12: When the power supply voltage VCC drops to the strong pull-down shutdown threshold voltage V SD-OPEN1 When the feedback circuit is controlled to stop generating the strong pull-down current Isd, wherein the strong pull-down shutdown threshold voltage V SD-OPEN1 Less than the undervoltage lockout threshold voltage V UVLOL ;

[0061] Step S13: When the power supply voltage VCC rises to the strong pull-down threshold voltage V SD-CLOSE When the feedback circuit is controlled to generate the strong pull-down current Isd, wherein the strong pull-down start threshold voltage V SD-CLOSE Less than or equal to the undervoltage lockout threshold voltage V UVLOH .

[0062] For details, please refer to Figure 2 and Figure 3 , Figure 2 and Figure 3 To achieve a specific application of the above method, in actual applications, when the LED lighting device is in the lighting state, the bus capacitor 4 stores electricity. After the LED lighting device enters the power-off state, the following situation occurs in the LED lighting device: the bus capacitor 4 releases electricity and supplies power to the controller 3 through the peripheral power supply. The normal working current of the controller 3 is relatively large. In this state, the peripheral power supply cannot maintain the operation of the LED lighting control circuit, causing the voltage stabilizing capacitor corresponding to the controller's power supply voltage VCC to discharge, thereby causing the controller 3's power supply voltage VCC to drop.

[0063] See also Figure 2 , when VCC drops below the undervoltage lockout threshold voltage ( Figure 3 V in UVLOL ), the controller 3 enters the under-voltage lockout state, and the control feedback circuit 24 generates a strong pull-down current Isd. After the strong pull-down current Isd is applied to the power supply voltage VCC end of the controller 3, the sum of the strong pull-down current Isd and the working current when the controller 3 enters the under-voltage lockout state is greater than the power supply current provided by the peripheral power supply, and the voltage-stabilizing capacitor 6 corresponding to the power supply voltage VCC end of the controller 3 discharges, so that the power supply voltage VCC decreases.

[0064] In this application, the strong pull-down shutdown threshold voltage ( Figure 3 V in SD-OPEN1 ) is used to indicate the release of the strong pull-down current Isd. When the supply voltage VCC drops to the strong pull-down shutdown threshold voltage V SD-OPEN1When the LED lighting control circuit enters the undervoltage lockout state, the operating current of the LED lighting control circuit decreases, and the power supply current provided by the post-bridge bus capacitor 4 through the peripheral power supply is greater than the operating current of the controller 3 in this state. At this time, the peripheral power supply charges the voltage stabilizing capacitor 6 corresponding to the supply voltage VCC end of the controller 3, causing the supply voltage VCC to rise. In actual applications, after the LED lighting control circuit enters the undervoltage lockout state, due to the decrease in the operating current of the LED lighting control circuit, the power supply current provided by the post-bridge bus capacitor 4 through the peripheral power supply is greater than the operating current of the controller 3 in this state. At this time, the peripheral power supply charges the voltage stabilizing capacitor 6 corresponding to the supply voltage VCC end of the controller 3, causing the supply voltage VCC to rise. When the supply voltage VCC rises above the undervoltage lockout elimination threshold voltage ( Figure 3 V in UVLOH ), starts working to re-light the LED, causing back flash.

[0065] In this application, the strong pull-down threshold voltage is set ( Figure 3 V in SD-CLOSE ), the strong pull-down threshold voltage V SD-CLOSE Used to indicate the re-application of the strong pull-down current Isd to ensure that the undervoltage lockout state will not be released when the supply voltage VCC rises to the strong pull-down start threshold voltage V SD-CLOSE When the power supply voltage VCC rises, the control feedback circuit 24 is triggered to generate a strong pull-down current Isd, thereby preventing the undervoltage lockout from being released due to a rise in the supply voltage VCC, which could cause a flashback problem. The present application repeats the above process several times to discharge the power in the bus capacitor 4, thereby resolving the flashback problem and helping to ensure a better user experience of LED lighting.

[0066] For the above solution, the following technical effects can also be achieved. Figure 3 In the second power-off shown in FIG, during the period when the bus capacitor 4 after the bridge supplies power to the controller 3 through the peripheral power supply, the power supply current provided by the peripheral power supply is less than the operating current of the controller 3 in the undervoltage lockout state. At this time, the voltage stabilizing capacitor 6 corresponding to the power supply voltage VCC of the controller 3 discharges, causing the power supply voltage VCC of the controller to decrease to below V POR When the circuit is powered off, it can be reset without affecting the quick power-on startup.

[0067] In one embodiment, see Figure 3 , the strong pull-down shutdown threshold voltage V SD-OPEN1 is less than the undervoltage lockout threshold voltage V UVLOL , and is greater than the power-on reset voltage V POR Under this solution, during power failure, the energy of the bus capacitor 4 after the bridge is discharged, while ensuring that the controller 3 is in a non-starting working state, thus solving the problem of flashback during power failure. Figure 3The first power-off and the subsequent hot start, through the scheme of the present application, the controller 3 can start normally. At the same time after power-off reset, the scheme does not affect the start speed of the controller 3.

[0068] In one embodiment, the method further comprises: when the supply voltage VCC rises above the undervoltage lockout elimination threshold voltage V UVLOH , the controller 3 is in an undervoltage lockout state. That is, when the supply voltage VCC is greater than the undervoltage lockout elimination threshold voltage V UVLOH , the controller 3 switches from the undervoltage lockout state to the normal working state.

[0069] In one embodiment, during power-on during power-off, the supply voltage VCC of the controller 3 can be increased by a constraint control threshold voltage (V SD_OPEN2 ). Specifically, a constraint control threshold voltage V SD-CLOSE is added between the strong pull-down enable threshold voltage V UVLOH and the undervoltage lockout elimination threshold voltage V SD_OPEN2 ; during power-on during power-off, the supply voltage VCC of the controller 3 increases to the strong pull-down enable threshold voltage V SD-CLOSE , at which point the strong pull-down is enabled, and if the supply voltage VCC of the controller 3 continues to increase to the constraint control threshold voltage V SD_OPEN2 , the strong pull-down is disabled, thereby realizing fast start-up during power-on during power-off. And during the period when the post-bridge bus capacitor 4 supplies power to the controller 3 through peripheral power supply, the supply current provided by the peripheral power supply is less than the working current of the controller 3 in the undervoltage lockout state, at this time the voltage stabilizing capacitor 6 corresponding to the supply voltage VCC of the controller is discharged, so that the supply voltage VCC of the controller decreases, and when it decreases to below V POR , the circuit realizes power-off reset and does not affect the fast start-up again.

[0070] In one embodiment, the step of controlling the feedback circuit to generate a strong pull-down current Isd based on the supply voltage VCC of the controller after the controller enters the undervoltage lockout state comprises:

[0071] For the supply voltage VCC, a plurality of timing logic signals of a predetermined number are obtained;

[0072] Logical operation is performed on the plurality of timing logic signals, and when it is determined that the logical operation result represents that the controller 3 enters the undervoltage lockout state, the feedback circuit is controlled to generate the strong pull-down current Isd.

[0073] Please refer to Figure 3 , Figure 3According to the power supply voltage VCC of the controller 3, CTR1, CTR2, FLAG and CTR3 four kinds of timing logic signals are obtained, then, the four kinds of timing logic signals are logically operated to obtain Figure 2 The logical operation result SD_CTR is shown, which is also in the form of timing logic signal, and when it represents that the controller 3 enters the undervoltage lockout state, the control signal is high, and the feedback circuit 24 is controlled to generate the strong pull-down current Isd.

[0074] In the present application, an LED lighting device is also provided to apply the LED power-down processing method of any one of the above.

[0075] For the LED lighting device, the LED power-down processing method of any one of the above is applied to solve the power-on flash problem after the light is turned off and then turned on again, and the method has been described in detail in the above embodiments, which will not be described here.

[0076] Please refer to Figure 2 , the present application also provides an LED power-down processing circuit, comprising: a voltage detection circuit 21, a timing logic signal generation circuit 22, a logic operation circuit 23 and a feedback circuit 24 connected in sequence;

[0077] The voltage detection circuit 21 is used to detect the power supply voltage VCC of the controller;

[0078] The timing logic signal generation circuit 22 is used to generate a plurality of timing logic signals according to the power supply voltage VCC;

[0079] The logic operation circuit 23 is used to logically operate the plurality of timing logic signals to generate a timing control signal, the timing control signal is used to drive the feedback circuit 24 to generate a strong pull-down current Isd when it represents that the controller enters the undervoltage lockout state, the strong pull-down current Isd is used to be applied to the power supply voltage VCC end of the controller, the sum of the strong pull-down current Isd and the working current when the controller enters the undervoltage lockout state is greater than the power supply current provided by the peripheral power supply, the discharge of the corresponding voltage stabilizing capacitor 6 of the power supply voltage VCC end of the controller makes the power supply voltage VCC decrease; then, when the power supply voltage VCC decreases to the strong pull-down closing threshold voltage V SD-OPEN1 , the timing control signal drives the feedback circuit 24 to stop generating the strong pull-down current Isd, the strong pull-down closing threshold voltage V SD-OPEN1 is less than the undervoltage lockout threshold voltage V UVLOL ; when the power supply voltage VCC rises to the strong pull-down opening threshold voltage V SD-CLOSEWhen the timing control signal drives the feedback circuit 24 to generate the strong pull-down current Isd, the strong pull-down opening threshold voltage V SD-CLOSE Less than or equal to the under-voltage lockout elimination threshold voltage V UVLOH .

[0080] Please refer to Figure 3 The AC power supply is rectified by the bridge, and a DC line voltage VIN is generated on the bus capacitor 4, which is transmitted to the peripheral power supply module 5 to supply power to the controller 3. For the functions of the timing logic signal generation circuit 22 and the logic operation circuit 23, please refer to Figure 3 The timing logic signal control is shown, Figure 3 According to the supply voltage VCC of the controller 3, CTR1, CTR2, FLAG, and CTR3 four kinds of timing logic signals are obtained, and then the four kinds of timing logic signals are logically operated to obtain Figure 2 The logic operation result SD_CTR shown is the timing control signal, which is also in the form of timing logic signal, and its high level drives the feedback circuit 24 to generate the strong pull-down current Isd. The function of the strong pull-down current Isd has been described in detail in the above related embodiments, which will not be described in detail here.

[0081] For Figure 3 The peripheral power supply module 5 shown can be realized by starting resistance, but is not limited to it, to provide the required voltage at the supply voltage VCC end of the controller 3. The voltage detection circuit 21 is used to detect the supply voltage VCC of the controller 3. For the voltage detection module 21, traditional resistance voltage division method can be used to realize it, or other traditional voltage detection methods can be used to realize it.

[0082] In one embodiment, the strong pull-down closing threshold voltage V SD-OPEN1 Less than the under-voltage lockout threshold voltage V UVLOL , and greater than the power-on reset voltage V POR .

[0083] Please refer to Figure 3 , Figure 3 According to the supply voltage VCC of the controller 3, CTR1, CTR2, FLAG, and CTR3 four kinds of timing logic signals are obtained, Figure 3 The timing control signal SD_CTR obtained under the four kinds of timing logic signals CTR1, CTR2, FLAG, and CTR3 is shown, which can represent the strong pull-down closing threshold voltage V SD-OPEN1 Less than the under-voltage lockout threshold voltage V UVLOL , and greater than the power-on reset voltage V PORThe scheme can realize the discharge of the capacitor 4 during power failure, and ensure the controller 3 in a non-starting state, and solve the problem of power failure flash. Please refer to Figure 4 The first power failure and the subsequent hot start can be normally started by the controller 3 through the scheme. Meanwhile, the scheme does not affect the starting speed of the controller 3 after power failure reset.

[0084] Further, please refer to Figure 3 In an embodiment, the timing logic signal generation circuit 22 comprises a first selector M1, a second selector M2, a first comparator C1, a second comparator C2, a first inverter P1, a first flip-flop D1, and a power-on reset POR detection circuit 201.

[0085] The input ends of the first selector M1, the second selector M2, and the power-on reset POR detection circuit 201 are respectively connected with the voltage detection circuit 21.

[0086] The output end of the first selector M1 is connected with the positive input end of the first comparator C1.

[0087] The output end of the first comparator C1 is connected with the control end of the first selector M1 and the logic operation circuit 23, and the output end of the first comparator C1 is also connected with the trigger end of the first flip-flop D1 through the first inverter P1, and the output end of the first flip-flop D1 is connected with the logic operation circuit 23.

[0088] The EN end of the first comparator C1 and the CLR end of the first flip-flop D1 are connected with the first control output end of the logic operation circuit 23.

[0089] The output end of the second selector M2 is connected with the positive input end of the second comparator C2, and the control end of the second selector M2 is connected with the output end of the second comparator C2.

[0090] The output end of the second comparator C2 is connected with the logic operation circuit 23.

[0091] The output end of the power-on reset POR detection circuit 201 is respectively connected with the EN end of the second comparator C2 and the logic operation circuit 23.

[0092] Specifically, the specific embodiment of the timing logic signal generation circuit 22 is used to generate Figure 3 ​CTR1, CTR2, FLAG and CTR3 four timing logic signals, wherein the output end of the first comparator C1 is connected with the logic operation circuit 23 to output a first timing logic signal to the logic operation circuit 23, the first timing logic signal corresponds to Figure 3 CTR3; the Q output end of the first flip-flop D1 is connected with the logic operation circuit 23 to output a second timing logic signal to the logic operation circuit 23, the second timing logic signal corresponds to FLAG shown in the figure; the output end of the second comparator C2 is connected with the logic operation circuit 23 to output a third timing logic signal to the logic operation circuit 23, the third timing logic signal corresponds to Figure 4 CTR2; the output end of the power-on reset POR detection circuit 202 is connected with the logic operation circuit 23 to output a fourth timing logic signal to the logic operation circuit 23, the fourth timing logic signal corresponds to Figure 3 CTR1.

[0093] Further, please refer to Figure 3 In an embodiment, the logic operation circuit 23 comprises: a first NAND gate N1, a second NAND gate N2, a second flip-flop D2, a second inverter P2 and a driver Dr.

[0094] The output end of the first NAND gate N1 is connected with the output end of the first comparator C1 and the output end of the first flip-flop D1 respectively, the output end of the first NAND gate N1 is connected with the first input end of the second NAND gate N2;

[0095] The second input end of the second NAND gate N2 is connected with the output end of the second comparator C2 and the input end of the second inverter P2;

[0096] The output end of the second inverter P2 is connected with the trigger end of the second flip-flop D2;

[0097] The CLR end of the second flip-flop D2 is connected with the output end of the power-on reset POR detection circuit 201, and the Q output end of the second flip-flop D2 is connected with the third input end of the second NAND gate N2;

[0098] The Q output end of the second flip-flop D2 is as the first control output end;

[0099] The output end of the second NAND gate N2 is connected with the input end of the driver Dr, and the output end of the driver Dr is as the second control output end and is connected with the feedback circuit 24.

[0100] Specifically, the specific embodiment of the above-mentioned logic operation circuit 23 is used to realize the control of Figure 4The four sequential logic signals CTR1, CTR2, FLAG and CTR3 shown in the figure are logically operated to obtain Figure 5 The logic operation result SD_CTR shown is also embodied in the form of a sequential logic signal. Its high level drives the feedback circuit 24 to generate a strong pull-down current Isd that prevents the bus capacitor 4 from supplying power to the controller 3 .

[0101] For the first flip-flop D1 and the second flip-flop D2 in the above embodiment, in practical applications, both can be but not limited to D flip-flops.

[0102] See also Figure 4 and Figure 4 In one embodiment, the feedback circuit 24 includes:

[0103] An electronic switch T1, wherein the control terminal of the electronic switch T1 is connected to the output terminal of the logic operation circuit 23;

[0104] The feedback generation unit 202 is connected to the electronic switch T1.

[0105] Specifically, the electronic switch T1 can be implemented by, but not limited to, a field effect transistor, such as Figure 5 The figure shows a field-effect transistor (FET) as the electronic switch T1. After the electronic switch T1 is turned on, the feedback circuit 24 forms a path, and the feedback generation unit 202 generates a strong pull-down current Isd. This strong pull-down current Isd is applied to the power supply voltage VCC terminal of the controller 3 to prevent the bus capacitor 4 from supplying power to the controller 3.

[0106] See also ​ , further, the feedback generating unit 202 may be a current source circuit I load .

[0107] The following is a description of the solution. In practical applications, the current source circuit I load When the LED lighting is powered normally, the electric energy can be obtained and stored. After the electronic switch T1 is turned on, the feedback circuit 24 forms a path, and the current source circuit I load The generated feedback current is applied to the power supply voltage VCC terminal of the controller 3, and the sum of the feedback current and the operating current when the controller 3 enters the undervoltage lockout state is greater than the power supply current provided by the peripheral power supply, so that the bus capacitor 4 does not supply power to the controller 3.

[0108] See also ​ , further, for the feedback generation unit 202, it can be a resistor R load .

[0109] After the electronic switch T1 is turned on, the feedback circuit 24 forms a path, and the resistor Rload The shunt is formed, and the strong pull-down current Isd is applied to the supply voltage VCC end of the controller 3, the sum of the strong pull-down current Isd and the working current when the controller 3 enters the undervoltage lock state is greater than the supply current provided by the peripheral power supply, so that the bus capacitor 4 does not supply power to the controller 3.

[0110] The present application provides an LED lighting device, comprising the LED power-down processing circuit according to any one of the above. For the LED lighting device, the LED power-down processing circuit according to any one of the above is applied to solve the problem of power-on flash after the light is turned off, and the circuit has been described in detail in the above embodiments, which will not be described here.

[0111] It can be understood that the same or similar parts in the above embodiments can be mutually referred to, and the contents not described in detail in some embodiments can be referred to the same or similar contents in other embodiments.

[0112] It should be noted that in the description of the present application, the terms "first", "second" and the like are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance. In addition, in the description of the present application, unless otherwise specified, the meaning of "a plurality of" or "multiple" is at least two.

[0113] It should be understood that when an element is referred to as "fixed to" or "disposed on" another element, it can be directly on the other element or there can be a middle element; when an element is referred to as "connected to" another element, it can be directly connected to the other element or there can be a middle element, in addition, "connected" used herein can include wireless connection; the phrase "and / or" used herein includes any unit and all combinations of the associated listed items.

[0114] Any process or method descriptions in flow charts or otherwise described herein can be understood as representing code modules, segments, or portions of code that include one or more executable instructions for implementing specific logic functions or steps, and the various embodiments of the present application can include additional implementation with additional or fewer steps, in different orders, including as an entirely sequential process, or with one or more parallel processes, as will be understood by those skilled in the art.

[0115] It should be understood that various parts of the present application can be implemented in hardware, software, firmware or a combination thereof. In the above embodiments, various steps or methods can be implemented in software or firmware that is stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any of the following technologies, known in the art, or their combinations, can be used to implement the hardware: discrete logic circuitry having logic gates for implementing logic functions on data signals, application specific integrated circuits having appropriate combinational logic gates, programmable gate arrays (PGA), field programmable gate arrays (FPGA), and the like.

[0116] Those skilled in the art can understand that all or part of the steps carried out by the above-mentioned embodiment methods can be completed by programs instructing related hardware, and the programs can be stored in a computer readable storage medium, and when the programs are executed, one or a combination of the steps of the method embodiments is included.

[0117] In addition, each functional unit in each embodiment of the present application can be integrated into one processing module, or each unit can be physically present alone, or two or more units can be integrated into one module. The above-mentioned integrated module can be realized in the form of hardware or in the form of a software function module. The integrated module, if realized in the form of a software function module and sold or used as an independent product, can also be stored in a computer readable storage medium.

[0118] The above-mentioned storage medium can be a read-only memory, a magnetic disk or an optical disk, etc.

[0119] In the description of the present specification, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example" or "some examples" means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily mean the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0120] Although the embodiments of the present application have been shown and described above, it should be understood that the above-mentioned embodiments are exemplary and cannot be understood as limiting the present application, and those skilled in the art can make changes, modifications, replacements and variations to the above-mentioned embodiments within the scope of the present application.

Claims

1. A method for processing LED power failure, characterized in that: The method comprises: Based on a supply voltage VCC of the controller, after the controller enters an under-voltage lockout state, a control feedback circuit generates a strong pull-down current Isd, wherein the strong pull-down current Isd is applied to a supply voltage VCC terminal of the controller, and the sum of the strong pull-down current Isd and an operating current of the controller when entering the under-voltage lockout state is greater than a supply current provided by a peripheral power supply. A voltage stabilizing capacitor corresponding to the supply voltage VCC terminal of the controller is discharged, thereby reducing the supply voltage VCC; When the supply voltage VCC drops to the strong pull-down shutdown threshold voltage ( ), the feedback circuit is controlled to stop generating the strong pull-down current Isd, wherein the strong pull-down shutdown threshold voltage ( ) is less than the undervoltage lockout threshold voltage ( ), and is greater than the power-on reset voltage ( ); When the supply voltage VCC rises to the strong pull-down turn-on threshold voltage ( ), the feedback circuit is controlled to generate the strong pull-down current Isd, wherein the strong pull-down start threshold voltage ( ) is less than or equal to the undervoltage lockout elimination threshold voltage ( ).

2. The method according to claim 1, characterized in that The method further comprises: When the supply voltage VCC rises above the undervoltage lockout threshold voltage ( ), the controller releases the undervoltage lockout state.

3. The method according to any one of claims 1-2, characterized in that The step of controlling the feedback circuit to generate a strong pull-down current Isd after the controller enters an undervoltage lockout state based on the supply voltage VCC of the controller includes: Obtaining a preset number of multiple sequential logic signals for the power supply voltage VCC; A logic operation is performed on the multiple sequential logic signals, and when it is determined that the logic operation result indicates that the controller has entered an undervoltage lockout state, the feedback circuit is controlled to generate the strong pull-down current Isd.

4. An LED power-off processing circuit, characterized in that: The LED power-off processing method according to any one of claims 1 to 3, wherein the LED power-off processing circuit comprises: a voltage detection circuit (21), a timing logic signal generating circuit (22), a logic operation circuit (23) and a feedback circuit (24) connected in sequence; The voltage detection circuit (21) is used to detect the power supply voltage VCC of the controller; The sequential logic signal generating circuit (22) is used to generate a plurality of sequential logic signals according to the power supply voltage VCC; The logic operation circuit (23) is used to perform logic operations on the multiple timing logic signals to generate a timing control signal. The timing control signal is used to drive the feedback circuit (24) to generate a strong pull-down current Isd when the controller enters an undervoltage lockout state. The strong pull-down current Isd is applied to the power supply voltage VCC end of the controller. The sum of the strong pull-down current Isd and the working current when the controller enters the undervoltage lockout state is greater than the power supply current provided by the peripheral power supply. The voltage stabilizing capacitor corresponding to the power supply voltage VCC end of the controller is discharged, so that the power supply voltage VCC decreases. When the power supply voltage VCC drops to the strong pull-down shutdown threshold voltage ( ), the timing control signal drives the feedback circuit (24) to stop generating the strong pull-down current Isd, wherein the strong pull-down shutdown threshold voltage ( ) is less than the undervoltage lockout threshold voltage ( ); When the power supply voltage VCC rises to the strong pull-down start threshold voltage ( ), the timing control signal drives the feedback circuit (24) to generate the strong pull-down current Isd, wherein the strong pull-down start threshold voltage ( ) is less than or equal to the undervoltage lockout elimination threshold voltage ( ).

5. The circuit according to claim 4, characterized in that The sequential logic signal generating circuit (22) comprises: a first selector (M1), a second selector (M2), a first comparator (C1), a second comparator (C2), a first inverter (P1), a first trigger (D1) and a power-on reset (POR) detection circuit (201); Input terminals of the first selector (M1), the second selector (M2) and the power-on reset (POR) detection circuit (201) are respectively connected to the voltage detection circuit (21); The output terminal of the first selector (M1) is connected to the non-inverting input terminal of the first comparator (C1); The output end of the first comparator (C1) is connected to the control end of the first selector (M1) and the logic operation circuit (23). The output end of the first comparator (C1) is also connected to the trigger end of the first trigger (D1) through the first inverter (P1). The output end is connected to the logic operation circuit (23); The EN terminal of the first comparator (C1) and the CLR terminal of the first trigger (D1) are both connected to the first control output terminal of the logic operation circuit (23); The output end of the second selector (M2) is connected to the non-inverting input end of the second comparator (C2), and the control end of the second selector (M2) is connected to the output end of the second comparator (C2); The output terminal of the second comparator (C2) is connected to the logic operation circuit (23); and The output end of the power-on reset (POR) detection circuit (201) is connected to the EN end of the second comparator (C2) and the logic operation circuit (23) respectively.

6. The circuit according to claim 5, characterized in that The logic operation circuit (23) includes: a first NAND gate (N1), a second NAND gate (N2), a second trigger (D2), a second inverter (P2) and a driver (Dr); The first NAND gate (N1) is connected to the output end of the first comparator (C1) and the output end of the first trigger (D1). The output end is connected, the output end of the first NAND gate (N1) is connected to the first input end of the second NAND gate (N2); The second input end of the second NAND gate (N2) is commonly connected to the output end of the second comparator (C2) and the input end of the second inverter (P2); The output end of the second inverter (P2) is connected to the trigger end of the second trigger (D2); The CLR terminal of the second trigger (D2) is connected to the output terminal of the power-on reset POR detection circuit (201), and the CLR terminal of the second trigger (D2) is connected to the output terminal of the power-on reset POR detection circuit (201). The output terminal is connected to the third input terminal of the second NAND gate (N2); The second flip-flop (D2) The output terminal serves as the first control output terminal; The output end of the second NAND gate (N2) is connected to the input end of the driver (Dr), and the output end of the driver (Dr) is connected to the feedback circuit (24) as a second control output end.

7. The circuit according to claim 4, characterized in that The strong pull-down shutdown threshold voltage ( ) is less than the undervoltage lockout threshold voltage ( ), and is greater than the power-on reset voltage ( ).

8. The circuit according to any one of claims 4 to 7, characterized in that: The feedback circuit (24) comprises: An electronic switch (T1), wherein a control end of the electronic switch (T1) is connected to an output end of the logic operation circuit (23); The feedback generation unit (202) is connected to the electronic switch (T1).

9. The circuit according to claim 8, characterized in that The feedback generation unit (202) is a current source circuit ( ) or resistor ( ).

10. An LED lighting device, characterized in that: Apply the LED power-off processing method according to any one of claims 1 to 3.

11. An LED lighting device, characterized in that: The LED power-off processing circuit comprises the LED power-off processing circuit according to any one of claims 4 to 9.

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